kopia lustrzana https://github.com/OpenRTX/OpenRTX
192 wiersze
5.6 KiB
C
192 wiersze
5.6 KiB
C
/***************************************************************************
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* Copyright (C) 2024 - 2025 by Silvano Seva IU2KWO *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 3 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, see <http://www.gnu.org/licenses/> *
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***************************************************************************/
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#include "interfaces/nvmem.h"
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#include "interfaces/delays.h"
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#include "calibration/calibInfo_CS7000.h"
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#include "core/nvmem_access.h"
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#include "drivers/SPI/spi_bitbang.h"
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#include "drivers/SPI/spi_stm32.h"
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#include <string.h>
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#include "wchar.h"
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#include "core/utils.h"
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#include "core/crc.h"
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#include "drivers/NVM/W25Qx.h"
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#include "drivers/NVM/eeep.h"
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static const struct W25QxCfg cfg =
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{
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.spi = (const struct spiDevice *) &flash_spi,
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.cs = { FLASH_CS }
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};
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#ifdef PLATFORM_CS7000P
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W25Qx_DEVICE_DEFINE(eflash, cfg, 0x2000000) // 32 MB, 256 Mbit
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#else
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W25Qx_DEVICE_DEFINE(eflash, cfg, 0x1000000) // 16 MB, 128 Mbit
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#endif
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EEEP_DEVICE_DEFINE(eeep)
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const struct nvmPartition memPartitions[] =
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{
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{
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.offset = 0x0000, // First partition, calibration and other OEM data
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.size = 32768 // 32kB
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},
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#ifdef PLATFORM_CS7000P
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{
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.offset = 0x1000000,// Second partition EEEP storage
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.size = 16384 // 16kB
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},
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{
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.offset = 0x1000C000,// Third partition, available memory
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.size = 0xFF4000
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}
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#else
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{
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.offset = 0x8000, // Second partition EEEP storage
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.size = 16384 // 16kB
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},
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{
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.offset = 0xC000, // Third partition, available memory
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.size = 0xFF4000
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}
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#endif
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};
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static const struct nvmDescriptor extMem[] =
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{
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{
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.name = "External flash",
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.dev = &eflash,
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.partNum = sizeof(memPartitions)/sizeof(struct nvmPartition),
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.partitions = memPartitions
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},
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{
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.name = "Virtual EEPROM",
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.dev = &eeep,
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.partNum = 0,
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.partitions = NULL
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}
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};
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static uint16_t settingsCrc;
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static uint16_t vfoCrc;
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void nvm_init()
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{
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#ifdef PLATFORM_CS7000P
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gpio_setMode(FLASH_CLK, ALTERNATE | ALTERNATE_FUNC(5));
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gpio_setMode(FLASH_SDI, ALTERNATE | ALTERNATE_FUNC(5));
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gpio_setMode(FLASH_SDO, ALTERNATE | ALTERNATE_FUNC(5));
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spiStm32_init(&flash_spi, 25000000, 0);
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#else
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spiBitbang_init(&flash_spi);
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#endif
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W25Qx_init(&eflash);
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eeep_init(&eeep, 0, 1);
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}
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void nvm_terminate()
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{
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eeep_terminate(&eeep);
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W25Qx_terminate(&eflash);
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#ifdef PLATFORM_CS7000P
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spiStm32_terminate(&flash_spi);
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#else
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spiBitbang_terminate(&flash_spi);
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#endif
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}
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const struct nvmDescriptor *nvm_getDesc(const size_t index)
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{
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if(index > 2)
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return NULL;
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return &extMem[index];
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}
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void nvm_readCalibData(void *buf)
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{
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struct CS7000Calib *calData = (struct CS7000Calib *) buf;
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nvm_read(0, 0, 0x1000, &(calData->txCalFreq), sizeof(calData->txCalFreq));
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nvm_read(0, 0, 0x1020, &(calData->rxCalFreq), sizeof(calData->rxCalFreq));
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nvm_read(0, 0, 0x1044, &(calData->rxSensitivity), sizeof(calData->rxSensitivity));
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nvm_read(0, 0, 0x106C, &(calData->txHighPwr), sizeof(calData->txHighPwr));
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nvm_read(0, 0, 0x1074, &(calData->txMiddlePwr), sizeof(calData->txMiddlePwr));
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nvm_read(0, 0, 0x10C4, &(calData->txDigitalPathQ), sizeof(calData->txDigitalPathQ));
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nvm_read(0, 0, 0x10CC, &(calData->txAnalogPathI), sizeof(calData->txAnalogPathI));
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nvm_read(0, 0, 0x10DC, &(calData->errorRate), sizeof(calData->errorRate));
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for(int i = 0; i < 8; i++)
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{
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calData->txCalFreq[i] = __builtin_bswap32(calData->txCalFreq[i]);
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calData->rxCalFreq[i] = __builtin_bswap32(calData->rxCalFreq[i]);
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}
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}
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void nvm_readHwInfo(hwInfo_t *info)
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{
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(void) info;
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}
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int nvm_readVfoChannelData(channel_t *channel)
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{
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memset(channel, 0x00, sizeof(channel_t));
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int ret = nvm_read(1, -1, 0x0001, channel, sizeof(channel_t));
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if(ret < 0)
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return -1;
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vfoCrc = crc_ccitt(channel, sizeof(channel_t));
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return 0;
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}
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int nvm_readSettings(settings_t *settings)
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{
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memset(settings, 0x00, sizeof(settings_t));
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int ret = nvm_read(1, -1, 0x0002, settings, sizeof(settings_t));
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if(ret < 0)
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return -1;
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settingsCrc = crc_ccitt(settings, sizeof(settings_t));
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return 0;
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}
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int nvm_writeSettings(const settings_t *settings)
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{
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(void) settings;
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return -1;
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}
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int nvm_writeSettingsAndVfo(const settings_t *settings, const channel_t *vfo)
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{
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uint16_t crc = crc_ccitt(vfo, sizeof(channel_t));
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if(crc != vfoCrc)
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nvm_write(1, -1, 0x0001, vfo, sizeof(channel_t));
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crc = crc_ccitt(settings, sizeof(settings_t));
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if(crc != settingsCrc)
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nvm_write(1, -1, 0x0002, settings, sizeof(settings_t));
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return 0;
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}
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