kopia lustrzana https://github.com/OpenRTX/OpenRTX
218 wiersze
8.0 KiB
C++
218 wiersze
8.0 KiB
C++
/***************************************************************************
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* Copyright (C) 2021 by Federico Amedeo Izzo IU2NUO, *
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* Niccolò Izzo IU2KIN *
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* Frederik Saraci IU2NRO *
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* Silvano Seva IU2KWO *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 3 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, see <http://www.gnu.org/licenses/> *
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**************************************************************************/
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#include <interfaces/delays.h>
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#include <I2C0.h>
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#include "AT1846S.h"
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void AT1846S::init()
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{
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i2c_writeReg16(0x30, 0x0001); // Soft reset
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delayMs(50);
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i2c_writeReg16(0x30, 0x0004); // Chip enable
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i2c_writeReg16(0x04, 0x0FD0); // 26MHz crystal frequency
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i2c_writeReg16(0x1F, 0x1000); // Gpio6 squelch output
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i2c_writeReg16(0x09, 0x03AC);
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i2c_writeReg16(0x24, 0x0001);
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i2c_writeReg16(0x31, 0x0031);
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i2c_writeReg16(0x33, 0x45F5); // AGC number
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i2c_writeReg16(0x34, 0x2B89); // RX digital gain
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i2c_writeReg16(0x3F, 0x3263); // RSSI 3 threshold
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i2c_writeReg16(0x41, 0x470F); // Tx digital gain
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i2c_writeReg16(0x42, 0x1036);
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i2c_writeReg16(0x43, 0x00BB);
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i2c_writeReg16(0x44, 0x06FF); // Tx digital gain
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i2c_writeReg16(0x47, 0x7F2F); // Soft mute
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i2c_writeReg16(0x4E, 0x0082);
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i2c_writeReg16(0x4F, 0x2C62);
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i2c_writeReg16(0x53, 0x0094);
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i2c_writeReg16(0x54, 0x2A3C);
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i2c_writeReg16(0x55, 0x0081);
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i2c_writeReg16(0x56, 0x0B02);
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i2c_writeReg16(0x57, 0x1C00); // Bypass RSSI low-pass
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i2c_writeReg16(0x5A, 0x4935); // SQ detection time
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i2c_writeReg16(0x58, 0xBCCD);
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i2c_writeReg16(0x62, 0x3263); // Modulation detect tresh
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i2c_writeReg16(0x4E, 0x2082);
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i2c_writeReg16(0x63, 0x16AD);
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i2c_writeReg16(0x30, 0x40A4);
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delayMs(50);
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i2c_writeReg16(0x30, 0x40A6); // Start calibration
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delayMs(100);
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i2c_writeReg16(0x30, 0x4006); // Stop calibration
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delayMs(100);
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i2c_writeReg16(0x58, 0xBCED);
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i2c_writeReg16(0x0A, 0x7BA0); // PGA gain
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i2c_writeReg16(0x41, 0x4731); // Tx digital gain
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i2c_writeReg16(0x44, 0x05FF); // Tx digital gain
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i2c_writeReg16(0x59, 0x09D2); // Mixer gain
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i2c_writeReg16(0x44, 0x05CF); // Tx digital gain
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i2c_writeReg16(0x44, 0x05CC); // Tx digital gain
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i2c_writeReg16(0x48, 0x1A32); // Noise 1 threshold
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i2c_writeReg16(0x60, 0x1A32); // Noise 2 threshold
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i2c_writeReg16(0x3F, 0x29D1); // RSSI 3 threshold
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i2c_writeReg16(0x0A, 0x7BA0); // PGA gain
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i2c_writeReg16(0x49, 0x0C96); // RSSI SQL thresholds
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i2c_writeReg16(0x33, 0x45F5); // AGC number
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i2c_writeReg16(0x41, 0x470F); // Tx digital gain
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i2c_writeReg16(0x42, 0x1036);
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i2c_writeReg16(0x43, 0x00BB);
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}
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void AT1846S::setBandwidth(const AT1846S_BW band)
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{
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if(band == AT1846S_BW::_25)
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{
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// 25kHz bandwidth
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i2c_writeReg16(0x15, 0x1F00); // Tuning bit
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i2c_writeReg16(0x32, 0x7564); // AGC target power
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i2c_writeReg16(0x3A, 0x44C3); // Modulation detect sel
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i2c_writeReg16(0x3F, 0x29D2); // RSSI 3 threshold
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i2c_writeReg16(0x3C, 0x0E1C); // Peak detect threshold
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i2c_writeReg16(0x48, 0x1E38); // Noise 1 threshold
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i2c_writeReg16(0x62, 0x3767); // Modulation detect tresh
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i2c_writeReg16(0x65, 0x248A);
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i2c_writeReg16(0x66, 0xFF2E); // RSSI comp and AFC range
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i2c_writeReg16(0x7F, 0x0001); // Switch to page 1
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i2c_writeReg16(0x06, 0x0024); // AGC gain table
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i2c_writeReg16(0x07, 0x0214);
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i2c_writeReg16(0x08, 0x0224);
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i2c_writeReg16(0x09, 0x0314);
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i2c_writeReg16(0x0A, 0x0324);
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i2c_writeReg16(0x0B, 0x0344);
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i2c_writeReg16(0x0D, 0x1384);
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i2c_writeReg16(0x0E, 0x1B84);
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i2c_writeReg16(0x0F, 0x3F84);
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i2c_writeReg16(0x12, 0xE0EB);
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i2c_writeReg16(0x7F, 0x0000); // Back to page 0
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maskSetRegister(0x30, 0x3000, 0x3000);
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}
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else
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{
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// 12.5kHz bandwidth
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i2c_writeReg16(0x15, 0x1100); // Tuning bit
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i2c_writeReg16(0x32, 0x4495); // AGC target power
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i2c_writeReg16(0x3A, 0x40C3); // Modulation detect sel
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i2c_writeReg16(0x3F, 0x28D0); // RSSI 3 threshold
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i2c_writeReg16(0x3C, 0x0F1E); // Peak detect threshold
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i2c_writeReg16(0x48, 0x1DB6); // Noise 1 threshold
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i2c_writeReg16(0x62, 0x1425); // Modulation detect tresh
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i2c_writeReg16(0x65, 0x2494);
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i2c_writeReg16(0x66, 0xEB2E); // RSSI comp and AFC range
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i2c_writeReg16(0x7F, 0x0001); // Switch to page 1
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i2c_writeReg16(0x06, 0x0014); // AGC gain table
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i2c_writeReg16(0x07, 0x020C);
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i2c_writeReg16(0x08, 0x0214);
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i2c_writeReg16(0x09, 0x030C);
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i2c_writeReg16(0x0A, 0x0314);
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i2c_writeReg16(0x0B, 0x0324);
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i2c_writeReg16(0x0C, 0x0344);
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i2c_writeReg16(0x0D, 0x1344);
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i2c_writeReg16(0x0E, 0x1B44);
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i2c_writeReg16(0x0F, 0x3F44);
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i2c_writeReg16(0x12, 0xE0EB); // Back to page 0
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i2c_writeReg16(0x7F, 0x0000);
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maskSetRegister(0x30, 0x3000, 0x0000);
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}
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reloadConfig();
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}
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void AT1846S::setOpMode(const AT1846S_OpMode mode)
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{
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if(mode == AT1846S_OpMode::DMR)
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{
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// DMR mode
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i2c_writeReg16(0x3A, 0x00C2);
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i2c_writeReg16(0x33, 0x45F5);
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i2c_writeReg16(0x41, 0x4731);
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i2c_writeReg16(0x42, 0x1036);
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i2c_writeReg16(0x43, 0x00BB);
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i2c_writeReg16(0x58, 0xBCFD);
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i2c_writeReg16(0x44, 0x06CC);
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i2c_writeReg16(0x40, 0x0031);
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}
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else
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{
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// FM mode
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i2c_writeReg16(0x33, 0x44A5);
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i2c_writeReg16(0x41, 0x4431);
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i2c_writeReg16(0x42, 0x10F0);
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i2c_writeReg16(0x43, 0x00A9);
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i2c_writeReg16(0x58, 0xBC05);
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i2c_writeReg16(0x44, 0x06FF);
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i2c_writeReg16(0x40, 0x0030);
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maskSetRegister(0x57, 0x0001, 0x00); // Audio feedback off
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maskSetRegister(0x3A, 0x7000, 0x4000); // Select voice channel
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}
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reloadConfig();
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}
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/*
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* Implementation of AT1846S I2C interface.
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*
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* NOTE: on GDx devices the I2C bus is shared between the EEPROM and the AT1846S,
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* so we have to acquire exclusive ownership before exchanging data
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*/
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static constexpr uint8_t devAddr = 0xE2;
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void AT1846S::i2c_init()
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{
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// I2C already init'd by platform support package
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}
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void AT1846S::i2c_writeReg16(uint8_t reg, uint16_t value)
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{
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/*
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* Beware of endianness!
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* When writing an AT1846S register, bits 15:8 must be sent first, followed
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* by bits 7:0.
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*/
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uint8_t buf[3];
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buf[0] = reg;
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buf[1] = (value >> 8) & 0xFF;
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buf[2] = value & 0xFF;
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i2c0_lockDeviceBlocking();
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i2c0_write(devAddr, buf, 3, true);
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i2c0_releaseDevice();
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}
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uint16_t AT1846S::i2c_readReg16(uint8_t reg)
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{
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uint16_t value = 0;
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i2c0_lockDeviceBlocking();
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i2c0_write(devAddr, ®, 1, false);
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i2c0_read(devAddr, &value, 2);
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i2c0_releaseDevice();
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// Correction for AT1846S sending register data in big endian format
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return __builtin_bswap16(value);
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}
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