kopia lustrzana https://github.com/OpenRTX/OpenRTX
175 wiersze
4.9 KiB
C++
175 wiersze
4.9 KiB
C++
/***************************************************************************
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* Copyright (C) 2023 by Federico Amedeo Izzo IU2NUO, *
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* Niccolò Izzo IU2KIN *
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* Frederik Saraci IU2NRO *
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* Silvano Seva IU2KWO *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 3 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, see <http://www.gnu.org/licenses/> *
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***************************************************************************/
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#include <kernel/scheduler/scheduler.h>
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#include <data_conversion.h>
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#include <DmaStream.hpp>
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#include <Timer.hpp>
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#include <miosix.h>
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#include <errno.h>
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#include "stm32_pwm.h"
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using Dma1_Stream2 = DmaStream< DMA1_BASE, 2, 1, 3 >; // DMA 1, Stream 2, channel 1, very high priority
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static const struct PwmChannelCfg *config; // Config
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static struct streamCtx *context; // Current stream context
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static StreamHandler stream(Dma1_Stream2::init(10, DataSize::_16BIT, 1)); // DMA stream handler
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static Timer tim(TIM7_BASE); // Trigger timebase
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/**
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* \internal
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* Stop an ongoing transfer, deactivating timers and DMA stream.
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*/
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static void stopTransfer()
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{
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tim.stop();
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config->stopCbk();
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context->running = 0;
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}
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/**
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* \internal
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* Actual implementation of DMA interrupt handler.
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*/
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void __attribute__((used)) DMA_Handler()
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{
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Dma1_Stream2::IRQhandleInterrupt(&stream);
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}
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void __attribute__((naked)) DMA1_Stream2_IRQHandler()
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{
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saveContext();
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asm volatile("bl _Z11DMA_Handlerv");
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restoreContext();
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}
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void stm32pwm_init()
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{
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// Enable peripherals
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RCC->APB1ENR |= RCC_APB1ENR_TIM7EN;
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__DSB();
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// Init DMA stream
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stream.setEndTransferCallback(stopTransfer);
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}
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void stm32pwm_terminate()
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{
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if(stream.running())
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stream.halt();
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RCC->APB1ENR &= ~RCC_APB1ENR_TIM7EN;
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__DSB();
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}
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static int stm32pwm_start(const uint8_t instance, const void *cfg,
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struct streamCtx *ctx)
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{
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(void) instance;
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if(ctx == NULL)
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return -EINVAL;
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if((ctx->running != 0) || stream.running())
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return -EBUSY;
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__disable_irq();
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ctx->running = 1;
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__enable_irq();
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context = ctx;
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config = reinterpret_cast< const struct PwmChannelCfg *>(cfg);
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/*
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* Convert buffer elements from int16_t to unsigned 12 bit values as required
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* by the DAC. Processing can be done in-place because the API mandates that
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* the function caller does not modify the buffer content once this function
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* has been called.
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*/
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S16toU8(ctx->buffer, ctx->bufSize);
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bool circ = false;
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if(ctx->bufMode == BUF_CIRC_DOUBLE)
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circ = true;
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stream.start(config->pwmReg, ctx->buffer, ctx->bufSize, circ);
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config->startCbk();
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// Configure trigger
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tim.setUpdateFrequency(ctx->sampleRate);
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tim.enableDmaTrigger(true);
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tim.start();
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return 0;
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}
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static int stm32pwm_idleBuf(struct streamCtx *ctx, stream_sample_t **buf)
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{
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*buf = reinterpret_cast< stream_sample_t *>(stream.idleBuf());
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return ctx->bufSize/2;
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}
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static int stm32pwm_sync(struct streamCtx *ctx, uint8_t dirty)
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{
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if((ctx->bufMode == BUF_CIRC_DOUBLE) && (dirty != 0))
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{
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void *ptr = stream.idleBuf();
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S16toU8(reinterpret_cast< int16_t *>(ptr), ctx->bufSize/2);
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}
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bool ok = stream.sync();
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if(ok) return 0;
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return -1;
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}
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static void stm32pwm_stop(struct streamCtx *ctx)
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{
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if(ctx->running == 0)
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return;
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stream.stop();
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}
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static void stm32pwm_halt(struct streamCtx *ctx)
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{
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if(ctx->running == 0)
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return;
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stream.halt();
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}
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#pragma GCC diagnostic ignored "-Wpedantic"
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const struct audioDriver stm32_pwm_audio_driver =
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{
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.start = stm32pwm_start,
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.data = stm32pwm_idleBuf,
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.sync = stm32pwm_sync,
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.stop = stm32pwm_stop,
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.terminate = stm32pwm_halt
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};
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#pragma GCC diagnostic pop
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