kopia lustrzana https://github.com/OpenRTX/OpenRTX
Audio device driver for STM32F4xx ADC peripheral
Silvano Seva
rodzic
5aed3e3316
commit
f56771734f
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/***************************************************************************
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* Copyright (C) 2023 by Federico Amedeo Izzo IU2NUO, *
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* Niccolò Izzo IU2KIN *
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* Frederik Saraci IU2NRO *
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* Silvano Seva IU2KWO *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 3 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, see <http://www.gnu.org/licenses/> *
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***************************************************************************/
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#include <kernel/scheduler/scheduler.h>
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#include <DmaStream.hpp>
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#include <Timer.hpp>
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#include <miosix.h>
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#include <errno.h>
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#include "stm32_adc.h"
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struct AdcPeriph
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{
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ADC_TypeDef *adc;
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StreamHandler *stream;
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Timer tim;
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};
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using Dma2_Stream0 = DmaStream< DMA2_BASE, 0, 0, 2 >; // DMA 2, Stream 2, channel 0, high priority (ADC1)
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using Dma2_Stream1 = DmaStream< DMA2_BASE, 1, 2, 2 >; // DMA 2, Stream 2, channel 2, high priority (ADC3)
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using Dma2_Stream2 = DmaStream< DMA2_BASE, 2, 1, 2 >; // DMA 2, Stream 2, channel 1, high priority (ADC2)
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StreamHandler Dma2_Stream0_hdl = Dma2_Stream0::init(10, DataSize::_16BIT, false);
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StreamHandler Dma2_Stream1_hdl = Dma2_Stream1::init(10, DataSize::_16BIT, false);
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StreamHandler Dma2_Stream2_hdl = Dma2_Stream2::init(10, DataSize::_16BIT, false);
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struct streamCtx *AdcContext[3];
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static constexpr AdcPeriph periph[] =
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{
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{(ADC_TypeDef *) ADC1_BASE, &Dma2_Stream0_hdl, Timer(TIM2_BASE)},
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{(ADC_TypeDef *) ADC2_BASE, &Dma2_Stream2_hdl, Timer(TIM2_BASE)},
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{(ADC_TypeDef *) ADC3_BASE, &Dma2_Stream1_hdl, Timer(TIM2_BASE)},
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};
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/**
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* \internal
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* Stop an ongoing transfer, deactivating timers and DMA stream.
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*/
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static void stopTransfer(const uint8_t instNum)
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{
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periph[instNum].tim.stop();
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periph[instNum].adc->CR2 &= ~ADC_CR2_ADON;
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AdcContext[instNum]->running = 0;
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}
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/**
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* \internal
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* Actual implementation of DMA interrupt handler.
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*/
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void __attribute__((used)) ADC_DMA_Handler(uint32_t instNum)
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{
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switch(instNum)
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{
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case 0:
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Dma2_Stream0::IRQhandleInterrupt(periph[instNum].stream);
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break;
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case 1:
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Dma2_Stream2::IRQhandleInterrupt(periph[instNum].stream);
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break;
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case 2:
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Dma2_Stream1::IRQhandleInterrupt(periph[instNum].stream);
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break;
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}
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}
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// DMA 2, Stream 0: data transfer for ADC1
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void __attribute__((used)) DMA2_Stream0_IRQHandler()
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{
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saveContext();
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asm volatile("mov r0, #0");
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asm volatile("bl _Z15ADC_DMA_Handlerm");
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restoreContext();
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}
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// DMA 2, Stream 2: data transfer for ADC2
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void __attribute__((used)) DMA2_Stream2_IRQHandler()
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{
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saveContext();
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asm volatile("mov r0, #1");
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asm volatile("bl _Z15ADC_DMA_Handlerm");
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restoreContext();
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}
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// DMA 2, Stream 1: data transfer for ADC3
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void __attribute__((used)) DMA2_Stream1_IRQHandler()
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{
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saveContext();
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asm volatile("mov r0, #2");
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asm volatile("bl _Z15ADC_DMA_Handlerm");
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restoreContext();
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}
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void stm32adc_init(const uint8_t instance)
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{
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// Enable peripherals
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switch(instance)
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{
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case 0:
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RCC->APB2ENR |= RCC_APB2ENR_ADC1EN;
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break;
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case 1:
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RCC->APB2ENR |= RCC_APB2ENR_ADC2EN;
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break;
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case 2:
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RCC->APB2ENR |= RCC_APB2ENR_ADC3EN;
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break;
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}
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/*
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* Use TIM2 as trigger source for all the ADCs.
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* TODO: change this with a dedicated timer for each ADC.
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*/
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RCC->APB1ENR |= RCC_APB1ENR_TIM2EN;
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uint32_t adcTrig = ADC_CR2_EXTSEL_1 // 0b0110 TIM2_TRGO trig. source
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| ADC_CR2_EXTSEL_2;
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__DSB();
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/*
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* ADC configuration.
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*
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* ADC clock is APB2 frequency divided by 4, giving 21MHz.
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* Channel sample time set to 84 cycles, total conversion time is 100
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* cycles: this leads to a maximum sampling frequency of 210kHz.
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* Convert one channel only, no overrun interrupt, 12-bit resolution,
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* no analog watchdog, discontinuous mode, no end of conversion interrupts.
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*/
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ADC_TypeDef *adc = periph[instance].adc;
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ADC->CCR |= ADC_CCR_ADCPRE_0;
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adc->SMPR2 = ADC_SMPR2_SMP2_2
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| ADC_SMPR2_SMP1_2;
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adc->SQR1 = 0; // Convert one channel
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adc->CR1 |= ADC_CR1_DISCEN;
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adc->CR2 |= ADC_CR2_EXTEN_0 // Trigger on rising edge
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| adcTrig // Trigger source
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| ADC_CR2_DDS // Continuous DMA requests
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| ADC_CR2_DMA; // Enable DMA data transfer
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// Register end-of-transfer callbacks
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periph[instance].stream->setEndTransferCallback(std::bind(stopTransfer, instance));
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}
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void stm32adc_terminate()
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{
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// Terminate streams before shutting of the peripherals
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for(int i = 0; i < 2; i++)
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{
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if(AdcContext[i] != NULL)
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{
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if(AdcContext[i]->running != 0)
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periph[i].stream->halt();
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}
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}
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// TODO: turn off peripherals
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RCC->APB1ENR &= ~RCC_APB1ENR_TIM2EN;
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__DSB();
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}
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static int stm32adc_start(const uint8_t instance, const void *config, struct streamCtx *ctx)
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{
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if(ctx == NULL)
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return -EINVAL;
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if((ctx->running != 0) || (periph[instance].stream->running()))
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return -EBUSY;
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__disable_irq();
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ctx->running = 1;
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__enable_irq();
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ctx->priv = (void *) &periph[instance];
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AdcContext[instance] = ctx;
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// Set conversion channel and enable the ADC
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periph[instance].adc->SQR3 = (uint32_t) config;
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periph[instance].adc->CR2 |= ADC_CR2_ADON;
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// Start DMA stream
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bool circ = false;
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if(ctx->bufMode == BUF_CIRC_DOUBLE)
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circ = true;
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periph[instance].stream->start(&(periph[instance].adc->DR), ctx->buffer,
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ctx->bufSize, circ);
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// Configure ADC trigger
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periph[instance].tim.setUpdateFrequency(ctx->sampleRate);
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periph[instance].tim.start();
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return 0;
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}
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static int stm32adc_data(struct streamCtx *ctx, stream_sample_t **buf)
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{
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AdcPeriph *p = reinterpret_cast< AdcPeriph * >(ctx->priv);
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if(ctx->bufMode == BUF_CIRC_DOUBLE)
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{
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*buf = reinterpret_cast< stream_sample_t *>(p->stream->idleBuf());
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return ctx->bufSize/2;
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}
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// Linear mode: return the full buffer
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*buf = ctx->buffer;
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return ctx->bufSize;
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}
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static int stm32adc_sync(struct streamCtx *ctx, uint8_t dirty)
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{
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(void) dirty;
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AdcPeriph *p = reinterpret_cast< AdcPeriph * >(ctx->priv);
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bool ok = p->stream->sync();
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if(ok)
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return 0;
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return -1;
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}
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static void stm32adc_stop(struct streamCtx *ctx)
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{
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if(ctx->running == 0)
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return;
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reinterpret_cast< AdcPeriph * >(ctx->priv)->stream->stop();
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}
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static void stm32adc_halt(struct streamCtx *ctx)
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{
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if(ctx->running == 0)
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return;
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reinterpret_cast< AdcPeriph * >(ctx->priv)->stream->halt();
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}
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#pragma GCC diagnostic ignored "-Wpedantic"
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const struct audioDriver stm32_adc_audio_driver =
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{
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.start = stm32adc_start,
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.data = stm32adc_data,
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.sync = stm32adc_sync,
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.stop = stm32adc_stop,
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.terminate = stm32adc_halt
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};
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#pragma GCC diagnostic pop
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@ -0,0 +1,73 @@
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/***************************************************************************
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* Copyright (C) 2023 by Federico Amedeo Izzo IU2NUO, *
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* Niccolò Izzo IU2KIN *
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* Frederik Saraci IU2NRO *
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* Silvano Seva IU2KWO *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 3 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, see <http://www.gnu.org/licenses/> *
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***************************************************************************/
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#ifndef STM32_ADC_H
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#define STM32_ADC_H
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#include <stdbool.h>
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#include <stdint.h>
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#include <stm32f4xx.h>
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#include <interfaces/audio.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* Driver for STM32F4xx ADC peripheral used as audio input stream device.
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* Output data format is signed 16-bit, hardware outputs positive-only 12-bit
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* samples.
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*
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* This driver has three instances:
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*
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* - instance 0: ADC1
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* - instance 1: ADC2
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* - instance 2: ADC3
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*
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* The configuration parameter for each instance is the ADC input number.
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*/
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enum Stm32AdcInstance
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{
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STM32_ADC_ADC1 = 0,
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STM32_ADC_ADC2,
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STM32_ADC_ADC3,
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};
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extern const struct audioDriver stm32_adc_audio_driver;
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/**
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* Initialize the driver and the peripherals.
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*/
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void stm32adc_init(const uint8_t instance);
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/**
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* Shutdown the driver and the peripherals.
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*/
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void stm32adc_terminate();
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#ifdef __cplusplus
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}
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#endif
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#endif /* STM32_DAC_H */
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