kopia lustrzana https://github.com/OpenRTX/OpenRTX
Driver for input audio stream on MDx
Silvano Seva
rodzic
c2b6bd545f
commit
f3c6e92911
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@ -99,6 +99,7 @@ mdx_src = ['platform/drivers/ADC/ADC1_MDx.c',
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'platform/drivers/GPS/GPS_MDx.cpp',
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'platform/drivers/NVM/W25Qx.c',
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'platform/drivers/audio/audio_MDx.c',
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'platform/drivers/audio/inputStream_MDx.cpp',
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'platform/drivers/baseband/HR_Cx000.cpp',
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'platform/drivers/backlight/backlight_MDx.c',
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'platform/drivers/tones/toneGenerator_MDx.cpp']
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@ -0,0 +1,283 @@
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/***************************************************************************
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* Copyright (C) 2021 by Federico Amedeo Izzo IU2NUO, *
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* Niccolò Izzo IU2KIN *
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* Frederik Saraci IU2NRO *
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* Silvano Seva IU2KWO *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 3 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, see <http://www.gnu.org/licenses/> *
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***************************************************************************/
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#include <kernel/scheduler/scheduler.h>
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#include <interfaces/audio_stream.h>
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#include <toneGenerator_MDx.h>
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#include <interfaces/gpio.h>
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#include <hwconfig.h>
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#include <stdbool.h>
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#include <miosix.h>
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using namespace miosix;
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bool inUse = false; // Flag to determine if the input stream is already open.
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Thread *sWaiting = 0; // Thread waiting on interrupt.
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uint32_t bufAddr = 0; // Start address of data buffer, fixed.
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uint32_t bufCurr = 0; // Buffer address to be returned to application.
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size_t bufLen = 0; // Buffer length.
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uint8_t bufMode = BUF_LINEAR; // Buffer management mode.
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void __attribute__((used)) DmaHandlerImpl()
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{
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if(DMA2->LISR & (DMA_LISR_TCIF2 | DMA_LISR_HTIF2))
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{
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switch(bufMode)
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{
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case BUF_LINEAR:
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// Finish, stop DMA and ADC
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DMA2_Stream2->CR &= ~DMA_SxCR_EN;
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ADC2->CR2 &= ~ADC_CR2_ADON;
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break;
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case BUF_CIRC_DOUBLE:
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// Return half of the buffer but do not stop the DMA
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if(DMA2->LISR & DMA_LISR_HTIF2)
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bufCurr = bufAddr; // Return first half
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else
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bufCurr = bufAddr + (bufLen / 2); // Return second half
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break;
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default:
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break;
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}
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// Wake up the thread
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if(sWaiting != 0)
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{
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sWaiting->IRQwakeup();
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Priority prio = sWaiting->IRQgetPriority();
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if(prio > Thread::IRQgetCurrentThread()->IRQgetPriority())
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Scheduler::IRQfindNextThread();
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sWaiting = 0;
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}
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}
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DMA2->LIFCR |= DMA_LIFCR_CTEIF2 // Clear transfer error flag (not handled)
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| DMA_LIFCR_CHTIF2 // Clear half transfer flag
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| DMA_LIFCR_CTCIF2; // Clear transfer completed flag
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}
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void __attribute__((naked)) DMA2_Stream2_IRQHandler()
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{
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saveContext();
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asm volatile("bl _Z14DmaHandlerImplv");
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restoreContext();
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}
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streamId inputStream_start(const enum AudioSource source,
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const enum AudioPriority prio,
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stream_sample_t * const buf,
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const size_t bufLength,
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const enum BufMode mode,
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const uint32_t sampleRate)
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{
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(void) prio; // TODO: input stream does not have priority
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// Check if buffer is in CCM area or not, since DMA cannot access CCM RAM
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if(reinterpret_cast< uint32_t >(buf) < 0x20000000) return -1;
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/*
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* Critical section for inUse flag management, makes the code below
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* thread-safe.
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*/
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{
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FastInterruptDisableLock dLock;
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if(inUse) return -1;
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inUse = true;
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}
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bufMode = mode;
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bufAddr = reinterpret_cast< uint32_t >(buf);
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bufLen = bufLength;
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RCC->APB2ENR |= RCC_APB2ENR_ADC2EN; // Enable ADC
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RCC->APB1ENR |= RCC_APB1ENR_TIM2EN; // Enable conv. timebase timer
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RCC->AHB1ENR |= RCC_AHB1ENR_DMA2EN; // Enable DMA
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__DSB();
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/*
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* TIM2 for conversion triggering via TIM2_TRGO, that is counter reload.
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* AP1 frequency is 42MHz but timer runs at 84MHz, tick rate is 1MHz,
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* reload register is configured based on desired sample rate.
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*/
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TIM2->PSC = 83;
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TIM2->ARR = (1000000/sampleRate) - 1;
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TIM2->CNT = 0;
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TIM2->EGR = TIM_EGR_UG;
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TIM2->CR2 = TIM_CR2_MMS_1;
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TIM2->CR1 = TIM_CR1_CEN;
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/* DMA2 Stream 2 common configuration:
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* - channel 1: ADC2
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* - high priority
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* - half-word transfer, both memory and peripheral
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* - increment memory
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* - peripheral-to-memory transfer
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*/
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DMA2_Stream2->PAR = reinterpret_cast< uint32_t >(&(ADC2->DR));
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DMA2_Stream2->M0AR = reinterpret_cast< uint32_t >(buf);
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DMA2_Stream2->NDTR = bufLength;
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DMA2_Stream2->CR = DMA_SxCR_CHSEL_0 // Channel 1
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| DMA_SxCR_MSIZE_0 // Memory size: 16 bit
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| DMA_SxCR_PSIZE_0 // Peripheral size: 16 bit
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| DMA_SxCR_PL_1 // High priority
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| DMA_SxCR_MINC; // Increment memory
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/*
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* Configure DMA and memory pointers according to buffer management mode.
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* In linear and circular mode all the buffer is returned, in double circular
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* buffer mode the buffer pointer is managed inside the DMA ISR.
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*/
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switch(mode)
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{
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case BUF_LINEAR:
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DMA2_Stream2->CR |= DMA_SxCR_TCIE; // Interrupt on transfer end
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bufCurr = bufAddr; // Return all the buffer
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break;
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case BUF_CIRC:
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DMA2_Stream2->CR |= DMA_SxCR_CIRC // Circular mode
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| DMA_SxCR_TCIE; // Interrupt on transfer end
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bufCurr = bufAddr; // Return all the buffer
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break;
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case BUF_CIRC_DOUBLE:
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DMA2_Stream2->CR |= DMA_SxCR_CIRC // Circular mode
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| DMA_SxCR_HTIE // Interrupt on half transfer
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| DMA_SxCR_TCIE; // Interrupt on transfer end
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break;
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default:
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inUse = false; // Invalid setting, release flag and return error.
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return -1;
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break;
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}
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// Configure NVIC interrupt
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NVIC_ClearPendingIRQ(DMA2_Stream2_IRQn);
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NVIC_SetPriority(DMA2_Stream2_IRQn, 10);
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NVIC_EnableIRQ(DMA2_Stream2_IRQn);
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/*
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* ADC2 configuration.
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*
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* ADC clock is APB2 frequency divided by 8, giving 10.5MHz.
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* Channel sample time set to 144 cycles, total conversion time 156 cycles.
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* Convert one channel only, no overrun interrupt, 12-bit resolution,
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* no analog watchdog, discontinuous mode, no end of conversion interrupts.
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*/
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ADC->CCR |= ADC_CCR_ADCPRE;
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ADC2->SMPR2 = ADC_SMPR2_SMP2
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| ADC_SMPR2_SMP1;
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ADC2->SQR1 = 0; // Convert one channel
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ADC2->CR1 |= ADC_CR1_DISCEN;
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ADC2->CR2 |= ADC_CR2_EXTEN_0 // Trigger on rising edge
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| ADC_CR2_EXTSEL_1
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| ADC_CR2_EXTSEL_2 // 0b0110 TIM2_TRGO trig. source
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| ADC_CR2_DDS // Enable DMA data transfer
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| ADC_CR2_DMA;
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/*
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* Select ADC channel according to signal source:
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* - CH3, mic input on PA3 (vox level)
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* - CH13, audio from RTX on PC13
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*/
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switch(source)
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{
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case SOURCE_MIC:
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gpio_setMode(GPIOA, 3, INPUT_ANALOG);
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ADC2->SQR3 = 3;
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break;
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case SOURCE_RTX:
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gpio_setMode(GPIOC, 13, INPUT_ANALOG);
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ADC2->SQR3 = 13;
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break;
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default:
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inUse = false; // Unsupported source, release flag and return error.
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return -1;
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break;
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}
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if((mode == BUF_CIRC) || (mode == BUF_CIRC_DOUBLE))
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{
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DMA2_Stream2->CR |= DMA_SxCR_EN; // Enable DMA
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ADC2->CR2 |= ADC_CR2_ADON; // Enable ADC
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}
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return 0;
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}
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dataBlock_t inputStream_getData(streamId id)
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{
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(void) id;
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if(bufMode == BUF_LINEAR)
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{
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// Reload DMA configuration then start DMA and ADC, stopped in ISR
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DMA2_Stream2->PAR = reinterpret_cast< uint32_t >(&(ADC2->DR));
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DMA2_Stream2->M0AR = bufAddr;
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DMA2_Stream2->NDTR = bufLen;
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DMA2_Stream2->CR |= DMA_SxCR_EN;
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ADC2->CR2 |= ADC_CR2_ADON;
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}
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/*
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* Put the calling thread in waiting status until data is ready.
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*/
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{
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FastInterruptDisableLock dLock;
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sWaiting = Thread::IRQgetCurrentThread();
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do
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{
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Thread::IRQwait();
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{
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FastInterruptEnableLock eLock(dLock);
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Thread::yield();
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}
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}while(sWaiting);
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}
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dataBlock_t block;
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block.data = reinterpret_cast< stream_sample_t *>(bufCurr);
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block.len = bufLen;
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if(bufMode == BUF_CIRC_DOUBLE) block.len /= 2;
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return block;
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}
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void inputStream_stop(streamId id)
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{
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(void) id;
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RCC->APB2ENR &= ~RCC_APB2ENR_ADC2EN; // Disable ADC
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RCC->APB1ENR &= ~RCC_APB1ENR_TIM2EN; // Disable conv. timebase timer
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RCC->AHB1ENR &= ~RCC_AHB1ENR_DMA2EN; // Disable DMA
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__DSB();
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// Critical section, release inUse flag
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FastInterruptDisableLock dLock;
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inUse = false;
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}
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