kopia lustrzana https://github.com/OpenRTX/OpenRTX
Drivers: SPI: added driver for STM32H7 devices
Silvano Seva
rodzic
f5012e0f63
commit
dfb24c95e8
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@ -222,7 +222,7 @@ stm32f405_src = ['platform/mcu/STM32F4xx/boot/startup.cpp',
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'platform/mcu/STM32F4xx/drivers/rcc.c',
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'platform/mcu/STM32F4xx/drivers/i2c_stm32.c',
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'platform/drivers/ADC/adc_stm32f4.c',
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'platform/drivers/SPI/spi_stm32.c',
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'platform/drivers/SPI/spi_stm32f4.c',
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'platform/drivers/GPIO/gpio_stm32.c',
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'platform/drivers/audio/stm32_dac.cpp',
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'platform/drivers/audio/stm32_adc.cpp',
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@ -285,6 +285,7 @@ stm32h743_src = ['platform/mcu/STM32H7xx/boot/startup.cpp',
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'platform/mcu/STM32H7xx/drivers/delays.cpp',
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'platform/drivers/GPIO/gpio_stm32.c',
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'platform/drivers/ADC/adc_stm32h7.c',
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'platform/drivers/SPI/spi_stm32h7.c',
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'platform/mcu/CMSIS/Device/ST/STM32H7xx/Source/system_stm32h7xx.c']
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stm32h743_inc = ['platform/mcu/CMSIS/Include',
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@ -0,0 +1,206 @@
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/***************************************************************************
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* Copyright (C) 2024 by Silvano Seva IU2KWO *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 3 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, see <http://www.gnu.org/licenses/> *
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***************************************************************************/
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#include <pll.h>
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#include <errno.h>
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#include <stm32h7xx.h>
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#include "spi_stm32.h"
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static inline uint8_t spi_sendRecv(SPI_TypeDef *spi, const uint8_t val)
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{
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// Of course, setting the SPI frame size is not enough: to actually send
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// 8 bits instead of 32, we have to access the TXDR register with an 8 bit
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// write operation. Damn ST...
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*((volatile uint8_t *) &spi->TXDR) = val;
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while((spi->SR & SPI_SR_TXC) == 0) ;
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return spi->RXDR;
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}
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int spiStm32_init(const struct spiDevice *dev, const uint32_t speed, const uint8_t flags)
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{
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SPI_TypeDef *spi = (SPI_TypeDef *) dev->priv;
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uint32_t busClk;
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// On STM32H7 the clock tree is a bit more complicated than on STM32F4:
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// - SPI1/2/3 use PLL1_Q clock for SCK generation and APB clock for reg access
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// - SPI4/5/6 use APB clock both for SCK generation and reg access
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// From PLL config PLL1_Q output is set at 100MHz
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switch((uint32_t) spi)
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{
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case SPI1_BASE:
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busClk = 100000000;
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RCC->APB2ENR |= RCC_APB2ENR_SPI1EN;
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__DSB();
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break;
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case SPI2_BASE:
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busClk = 100000000;
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RCC->APB1LENR |= RCC_APB1LENR_SPI2EN;
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__DSB();
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break;
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case SPI3_BASE:
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busClk = 100000000;
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RCC->APB1LENR |= RCC_APB1LENR_SPI3EN;
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__DSB();
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break;
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case SPI4_BASE:
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busClk = getBusClock(PERIPH_BUS_APB2);
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RCC->APB2ENR |= RCC_APB2ENR_SPI4EN;
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__DSB();
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break;
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case SPI5_BASE:
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busClk = getBusClock(PERIPH_BUS_APB2);
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RCC->APB2ENR |= RCC_APB2ENR_SPI5EN;
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__DSB();
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break;
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case SPI6_BASE:
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busClk = getBusClock(PERIPH_BUS_APB4);
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RCC->APB4ENR |= RCC_APB4ENR_SPI6EN;
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__DSB();
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break;
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default:
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return -ENODEV;
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break;
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}
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uint8_t spiDiv;
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uint32_t spiClk;
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// Find nearest clock frequency, round down
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for(spiDiv = 0; spiDiv < 7; spiDiv += 1)
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{
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spiClk = busClk / (1 << (spiDiv + 1));
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if(spiClk <= speed)
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break;
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}
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if(spiClk > speed)
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return -EINVAL;
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spi->I2SCFGR = 0;
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spi->CR2 = 0;
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spi->CFG1 = (spiDiv << SPI_CFG1_MBR_Pos) // Baud rate
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| SPI_CFG1_DSIZE_2 // SPI frame size 8-bit
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| SPI_CFG1_DSIZE_1
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| SPI_CFG1_DSIZE_0;
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spi->CR1 = SPI_CR1_SSI; // Force nCS state to active
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spi->CFG2 = SPI_CFG2_AFCNTR // Peripheral keeps control of gpio AF mode
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| SPI_CFG2_SSM // Software management of nCS
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| SPI_CFG2_MASTER;
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if((flags & SPI_FLAG_CPOL) != 0)
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spi->CFG2 |= SPI_CFG2_CPOL;
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if((flags & SPI_FLAG_CPHA) != 0)
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spi->CFG2 |= SPI_CFG2_CPHA;
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if((flags & SPI_LSB_FIRST) != 0)
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spi->CFG2 |= SPI_CFG2_LSBFRST;
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if(dev->mutex != NULL)
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pthread_mutex_init((pthread_mutex_t *) dev->mutex, NULL);
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return 0;
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}
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void spiStm32_terminate(const struct spiDevice *dev)
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{
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SPI_TypeDef *spi = (SPI_TypeDef *) dev->priv;
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switch((uint32_t) spi)
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{
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case SPI1_BASE:
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RCC->APB2ENR &= ~RCC_APB2ENR_SPI1EN;
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__DSB();
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break;
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case SPI2_BASE:
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RCC->APB1LENR &= ~RCC_APB1LENR_SPI2EN;
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__DSB();
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break;
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case SPI3_BASE:
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RCC->APB1LENR &= ~RCC_APB1LENR_SPI3EN;
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__DSB();
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break;
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case SPI4_BASE:
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RCC->APB2ENR &= ~RCC_APB2ENR_SPI4EN;
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__DSB();
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break;
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case SPI5_BASE:
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RCC->APB2ENR &= ~RCC_APB2ENR_SPI5EN;
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__DSB();
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break;
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case SPI6_BASE:
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RCC->APB4ENR &= ~RCC_APB4ENR_SPI6EN;
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__DSB();
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break;
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default:
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break;
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}
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if(dev->mutex != NULL)
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pthread_mutex_destroy((pthread_mutex_t *) dev->mutex);
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}
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int spiStm32_transfer(const struct spiDevice *dev, const void *txBuf,
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void *rxBuf, const size_t size)
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{
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SPI_TypeDef *spi = (SPI_TypeDef *) dev->priv;
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uint8_t *rxData = (uint8_t *) rxBuf;
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const uint8_t *txData = (const uint8_t *) txBuf;
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spi->CR1 |= SPI_CR1_SPE;
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spi->CR1 |= SPI_CR1_CSTART;
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// Send only
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if(rxBuf == NULL)
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{
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for(size_t i = 0; i < size; i++)
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spi_sendRecv(spi, txData[i]);
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return 0;
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}
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// Receive only
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if(txBuf == NULL)
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{
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for(size_t i = 0; i < size; i++)
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rxData[i] = spi_sendRecv(spi, 0x00);
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return 0;
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}
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// Transmit and receive
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for(size_t i = 0; i < size; i++)
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rxData[i] = spi_sendRecv(spi, txData[i]);
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spi->CR1 &= ~SPI_CR1_SPE;
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return 0;
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}
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@ -97,3 +97,12 @@ void startPll()
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RCC->CR |= RCC_CR_PLL2ON; // Start PLL2
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while((RCC->CR & RCC_CR_PLL2RDY)==0) ; // Wait until ready
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}
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uint32_t getBusClock(const uint8_t bus)
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{
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if(bus >= PERIPH_BUS_NUM)
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return 0;
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// All busses run at 200MHz
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return 200000000;
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}
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@ -29,6 +29,40 @@
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#ifndef PLL_H
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#define PLL_H
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* Enumeration type for STM32 internal busses.
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*/
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enum PeriphBus
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{
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PERIPH_BUS_AHB = 0,
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PERIPH_BUS_APB1 = 1,
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PERIPH_BUS_APB2 = 2,
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PERIPH_BUS_APB4 = 3,
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PERIPH_BUS_NUM
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};
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/**
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* Configure and start the PLL.
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*/
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void startPll();
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/**
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* Get the clock frequency of a given peripheral bus.
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*
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* @param bus: bus identifier.
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* @return bus clock frequency in Hz or zero in case of errors.
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*/
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uint32_t getBusClock(const uint8_t bus);
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#ifdef __cplusplus
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}
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#endif
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#endif //PLL_H
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