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Separated code for SPI communication from sources of external flash memory driver.

replace/93d5475c9547f28f0071478d550d487a4a83ebd7
Silvano Seva 2020-12-24 19:00:00 +01:00
rodzic 83ab86e955
commit d9f6ea31ab
6 zmienionych plików z 194 dodań i 147 usunięć
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9
meson.build
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@ -182,7 +182,8 @@ endif
## TYT MD380
md380_src = src + stm32f405_src + ['platform/drivers/display/HX83XX_MDx.c',
'platform/drivers/keyboard/keyboard_MDx.c',
'platform/drivers/NVM/extFlash_MDx.c',
'platform/drivers/NVM/W25Qx.c',
'platform/drivers/NVM/spiFlash_MDx.c',
'platform/drivers/NVM/nvmem_MD3x0.c',
'platform/drivers/ADC/ADC1_MDx.c',
'platform/drivers/tones/toneGenerator_MDx.c',
@ -198,7 +199,8 @@ md380_def = def + stm32f405_def + {'PLATFORM_MD380': ''}
## TYT MD390
md390_src = src + stm32f405_src + ['platform/drivers/display/HX83XX_MDx.c',
'platform/drivers/keyboard/keyboard_MDx.c',
'platform/drivers/NVM/extFlash_MDx.c',
'platform/drivers/NVM/W25Qx.c',
'platform/drivers/NVM/spiFlash_MDx.c',
'platform/drivers/NVM/nvmem_MD3x0.c',
'platform/drivers/ADC/ADC1_MDx.c',
'platform/drivers/tones/toneGenerator_MDx.c',
@ -214,7 +216,8 @@ md390_def = def + stm32f405_def + {'PLATFORM_MD390': ''}
## TYT MD-UV380
mduv380_src = src + stm32f405_src + ['platform/drivers/display/HX83XX_MDx.c',
'platform/drivers/keyboard/keyboard_MDx.c',
'platform/drivers/NVM/extFlash_MDx.c',
'platform/drivers/NVM/W25Qx.c',
'platform/drivers/NVM/spiFlash_MDx.c',
'platform/drivers/NVM/nvmem_MDUV3x0.c',
'platform/drivers/ADC/ADC1_MDx.c',
'platform/drivers/baseband/rtx_UV3x0.c',

82
platform/drivers/NVM/extFlash_MDx.c → platform/drivers/NVM/W25Qx.c
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@ -18,76 +18,58 @@
* along with this program; if not, see <http://www.gnu.org/licenses/> *
***************************************************************************/
#include "extFlash_MDx.h"
#include <interfaces/gpio.h>
#include "W25Qx.h"
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <hwconfig.h>
#include <interfaces/gpio.h>
#define CMD_READ 0x03 /* Read data */
#define CMD_RSEC 0x48 /* Read security register */
#define CMD_WKUP 0xAB /* Release power down */
#define CMD_PDWN 0xB9 /* Power down */
/*
* Target-specific SPI interface functions, their implementation can be found
* in source files "spiFlash_xxx.c"
*/
extern uint8_t spiFlash_SendRecv(uint8_t val);
extern void spiFlash_init();
extern void spiFlash_terminate();
uint8_t _spi1SendRecv(uint8_t val)
void W25Qx_init()
{
SPI1->DR = val;
while((SPI1->SR & SPI_SR_RXNE) == 0) ;
return SPI1->DR;
}
void extFlash_init()
{
gpio_setMode(FLASH_CLK, ALTERNATE);
gpio_setMode(FLASH_SDO, ALTERNATE);
gpio_setMode(FLASH_SDI, ALTERNATE);
gpio_setAlternateFunction(FLASH_CLK, 5); /* SPI1 is on AF5 */
gpio_setAlternateFunction(FLASH_SDO, 5);
gpio_setAlternateFunction(FLASH_SDI, 5);
gpio_setMode(FLASH_CS, OUTPUT);
gpio_setPin(FLASH_CS);
RCC->APB2ENR |= RCC_APB2ENR_SPI1EN;
__DSB();
SPI1->CR1 = SPI_CR1_SSM /* Software managment of nCS */
| SPI_CR1_SSI /* Force internal nCS */
| SPI_CR1_BR_2 /* Fclock: 84MHz/64 = 1.3MHz */
| SPI_CR1_BR_0
| SPI_CR1_MSTR /* Master mode */
| SPI_CR1_SPE; /* Enable peripheral */
spiFlash_init();
}
void extFlash_terminate()
void W25Qx_terminate()
{
extFlash_sleep();
W25Qx_sleep();
RCC->APB2ENR &= ~RCC_APB2ENR_SPI1EN;
__DSB();
gpio_setMode(FLASH_CLK, INPUT);
gpio_setMode(FLASH_SDO, INPUT);
gpio_setMode(FLASH_SDI, INPUT);
gpio_setMode(FLASH_CS, INPUT);
spiFlash_terminate();
}
void extFlash_wakeup()
void W25Qx_wakeup()
{
gpio_clearPin(FLASH_CS);
(void) _spi1SendRecv(CMD_WKUP);
(void) spiFlash_SendRecv(CMD_WKUP);
gpio_setPin(FLASH_CS);
}
void extFlash_sleep()
void W25Qx_sleep()
{
gpio_clearPin(FLASH_CS);
(void) _spi1SendRecv(CMD_PDWN);
(void) spiFlash_SendRecv(CMD_PDWN);
gpio_setPin(FLASH_CS);
}
ssize_t extFlash_readSecurityRegister(uint32_t addr, uint8_t* buf, size_t len)
ssize_t W25Qx_readSecurityRegister(uint32_t addr, uint8_t* buf, size_t len)
{
uint32_t addrBase = addr & 0x3000;
uint32_t addrRange = addr & 0xCFFF;
@ -102,15 +84,15 @@ ssize_t extFlash_readSecurityRegister(uint32_t addr, uint8_t* buf, size_t len)
}
gpio_clearPin(FLASH_CS);
(void) _spi1SendRecv(CMD_RSEC); /* Command */
(void) _spi1SendRecv((addr >> 16) & 0xFF); /* Address high */
(void) _spi1SendRecv((addr >> 8) & 0xFF); /* Address middle */
(void) _spi1SendRecv(addr & 0xFF); /* Address low */
(void) _spi1SendRecv(0x00); /* Dummy byte */
(void) spiFlash_SendRecv(CMD_RSEC); /* Command */
(void) spiFlash_SendRecv((addr >> 16) & 0xFF); /* Address high */
(void) spiFlash_SendRecv((addr >> 8) & 0xFF); /* Address middle */
(void) spiFlash_SendRecv(addr & 0xFF); /* Address low */
(void) spiFlash_SendRecv(0x00); /* Dummy byte */
for(size_t i = 0; i < readLen; i++)
{
buf[i] = _spi1SendRecv(0x00);
buf[i] = spiFlash_SendRecv(0x00);
}
gpio_setPin(FLASH_CS);
@ -118,17 +100,17 @@ ssize_t extFlash_readSecurityRegister(uint32_t addr, uint8_t* buf, size_t len)
return ((ssize_t) readLen);
}
void extFlash_readData(uint32_t addr, uint8_t* buf, size_t len)
void W25Qx_readData(uint32_t addr, uint8_t* buf, size_t len)
{
gpio_clearPin(FLASH_CS);
(void) _spi1SendRecv(CMD_READ); /* Command */
(void) _spi1SendRecv((addr >> 16) & 0xFF); /* Address high */
(void) _spi1SendRecv((addr >> 8) & 0xFF); /* Address middle */
(void) _spi1SendRecv(addr & 0xFF); /* Address low */
(void) spiFlash_SendRecv(CMD_READ); /* Command */
(void) spiFlash_SendRecv((addr >> 16) & 0xFF); /* Address high */
(void) spiFlash_SendRecv((addr >> 8) & 0xFF); /* Address middle */
(void) spiFlash_SendRecv(addr & 0xFF); /* Address low */
for(size_t i = 0; i < len; i++)
{
buf[i] = _spi1SendRecv(0x00);
buf[i] = spiFlash_SendRecv(0x00);
}
gpio_setPin(FLASH_CS);

24
platform/drivers/NVM/extFlash_MDx.h → platform/drivers/NVM/W25Qx.h
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@ -18,28 +18,26 @@
* along with this program; if not, see <http://www.gnu.org/licenses/> *
***************************************************************************/
#ifndef EXTFLASH_MDx_H
#define EXTFLASH_MDx_H
#ifndef W25Qx_H
#define W25Qx_H
#include <stdint.h>
#include <sys/types.h>
/**
* Driver for external non volatile memory on MDx family devices, containing
* both calibration and contact data.
* For this family non volatile storage hardware is a Winbond W25Q128FV SPI flash
* connected to SPI1 peripheral.
* Driver for Winbond W25Qx family of SPI flash devices, used as external non
* volatile memory on various radios to store both calibration and contact data.
*/
/**
* Initialise driver for external flash.
*/
void extFlash_init();
void W25Qx_init();
/**
* Terminate driver for external flash.
*/
void extFlash_terminate();
void W25Qx_terminate();
/**
* Release flash chip from power down mode, this function should be called at
@ -48,12 +46,12 @@ void extFlash_terminate();
* Application code must wait at least 3us before issuing any other command
* after this one.
*/
void extFlash_wakeup();
void W25Qx_wakeup();
/**
* Put flash chip in low power mode.
*/
void extFlash_sleep();
void W25Qx_sleep();
/**
* Read data from one of the flash security registers, located at addresses
@ -67,7 +65,7 @@ void extFlash_sleep();
* @return: -1 if address is not whithin security registers address range, the
* number of bytes effectively read otherwise.
*/
ssize_t extFlash_readSecurityRegister(uint32_t addr, uint8_t *buf, size_t len);
ssize_t W25Qx_readSecurityRegister(uint32_t addr, uint8_t *buf, size_t len);
/**
* Read data from flash memory.
@ -76,6 +74,6 @@ ssize_t extFlash_readSecurityRegister(uint32_t addr, uint8_t *buf, size_t len);
* @param buf: pointer to a buffer where data is written to.
* @param len: number of bytes to read.
*/
void extFlash_readData(uint32_t addr, uint8_t *buf, size_t len);
void W25Qx_readData(uint32_t addr, uint8_t *buf, size_t len);
#endif /* EXTFLASH_MDx_H */
#endif /* W25Qx_H */

70
platform/drivers/NVM/nvmem_MD3x0.c
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@ -20,8 +20,8 @@
#include <interfaces/nvmem.h>
#include <interfaces/delays.h>
#include "extFlash_MDx.h"
#include "calibInfo_MDx.h"
#include <calibInfo_MDx.h>
#include "W25Qx.h"
/**
* \internal Data structure matching the one used by original MD3x0 firmware to
@ -133,51 +133,51 @@ uint32_t _bcd2bin(uint32_t bcd)
void nvm_init()
{
extFlash_init();
W25Qx_init();
}
void nvm_terminate()
{
extFlash_terminate();
W25Qx_terminate();
}
void nvm_readCalibData(void *buf)
{
extFlash_wakeup();
W25Qx_wakeup();
delayUs(5);
md3x0Calib_t *calib = ((md3x0Calib_t *) buf);
(void) extFlash_readSecurityRegister(0x1000, &(calib->vox1), 11);
(void) extFlash_readSecurityRegister(0x1010, calib->txHighPower, 9);
(void) extFlash_readSecurityRegister(0x1020, calib->txLowPower, 9);
(void) extFlash_readSecurityRegister(0x1030, calib->rxSensitivity, 9);
(void) extFlash_readSecurityRegister(0x1040, calib->openSql9, 9);
(void) extFlash_readSecurityRegister(0x1050, calib->closeSql9, 9);
(void) extFlash_readSecurityRegister(0x1060, calib->openSql1, 9);
(void) extFlash_readSecurityRegister(0x1070, calib->closeSql1, 9);
(void) extFlash_readSecurityRegister(0x1080, calib->maxVolume, 9);
(void) extFlash_readSecurityRegister(0x1090, calib->ctcss67Hz, 9);
(void) extFlash_readSecurityRegister(0x10a0, calib->ctcss151Hz, 9);
(void) extFlash_readSecurityRegister(0x10b0, calib->ctcss254Hz, 9);
(void) extFlash_readSecurityRegister(0x10c0, calib->dcsMod2, 9);
(void) extFlash_readSecurityRegister(0x10d0, calib->dcsMod1, 9);
(void) extFlash_readSecurityRegister(0x10e0, calib->mod1Partial, 9);
(void) extFlash_readSecurityRegister(0x10f0, calib->analogVoiceAdjust, 9);
(void) W25Qx_readSecurityRegister(0x1000, &(calib->vox1), 11);
(void) W25Qx_readSecurityRegister(0x1010, calib->txHighPower, 9);
(void) W25Qx_readSecurityRegister(0x1020, calib->txLowPower, 9);
(void) W25Qx_readSecurityRegister(0x1030, calib->rxSensitivity, 9);
(void) W25Qx_readSecurityRegister(0x1040, calib->openSql9, 9);
(void) W25Qx_readSecurityRegister(0x1050, calib->closeSql9, 9);
(void) W25Qx_readSecurityRegister(0x1060, calib->openSql1, 9);
(void) W25Qx_readSecurityRegister(0x1070, calib->closeSql1, 9);
(void) W25Qx_readSecurityRegister(0x1080, calib->maxVolume, 9);
(void) W25Qx_readSecurityRegister(0x1090, calib->ctcss67Hz, 9);
(void) W25Qx_readSecurityRegister(0x10a0, calib->ctcss151Hz, 9);
(void) W25Qx_readSecurityRegister(0x10b0, calib->ctcss254Hz, 9);
(void) W25Qx_readSecurityRegister(0x10c0, calib->dcsMod2, 9);
(void) W25Qx_readSecurityRegister(0x10d0, calib->dcsMod1, 9);
(void) W25Qx_readSecurityRegister(0x10e0, calib->mod1Partial, 9);
(void) W25Qx_readSecurityRegister(0x10f0, calib->analogVoiceAdjust, 9);
(void) extFlash_readSecurityRegister(0x2000, calib->lockVoltagePartial, 9);
(void) extFlash_readSecurityRegister(0x2010, calib->sendIpartial, 9);
(void) extFlash_readSecurityRegister(0x2020, calib->sendQpartial, 9);
(void) extFlash_readSecurityRegister(0x2030, calib->sendIrange, 9);
(void) extFlash_readSecurityRegister(0x2040, calib->sendQrange, 9);
(void) extFlash_readSecurityRegister(0x2050, calib->rxIpartial, 9);
(void) extFlash_readSecurityRegister(0x2060, calib->rxQpartial, 9);
(void) extFlash_readSecurityRegister(0x2070, calib->analogSendIrange, 9);
(void) extFlash_readSecurityRegister(0x2080, calib->analogSendQrange, 9);
(void) W25Qx_readSecurityRegister(0x2000, calib->lockVoltagePartial, 9);
(void) W25Qx_readSecurityRegister(0x2010, calib->sendIpartial, 9);
(void) W25Qx_readSecurityRegister(0x2020, calib->sendQpartial, 9);
(void) W25Qx_readSecurityRegister(0x2030, calib->sendIrange, 9);
(void) W25Qx_readSecurityRegister(0x2040, calib->sendQrange, 9);
(void) W25Qx_readSecurityRegister(0x2050, calib->rxIpartial, 9);
(void) W25Qx_readSecurityRegister(0x2060, calib->rxQpartial, 9);
(void) W25Qx_readSecurityRegister(0x2070, calib->analogSendIrange, 9);
(void) W25Qx_readSecurityRegister(0x2080, calib->analogSendQrange, 9);
uint32_t freqs[18];
(void) extFlash_readSecurityRegister(0x20b0, ((uint8_t *) &freqs), 72);
extFlash_sleep();
(void) W25Qx_readSecurityRegister(0x20b0, ((uint8_t *) &freqs), 72);
W25Qx_sleep();
/*
* Ugly quirk: frequency stored in calibration data is divided by ten, so,
@ -195,13 +195,13 @@ int nvm_readChannelData(channel_t *channel, uint16_t pos)
{
if(pos > maxNumChannels) return -1;
extFlash_wakeup();
W25Qx_wakeup();
delayUs(5);
md3x0Channel_t chData;
uint32_t readAddr = chDataBaseAddr + pos * sizeof(md3x0Channel_t);
extFlash_readData(readAddr, ((uint8_t *) &chData), sizeof(md3x0Channel_t));
extFlash_sleep();
W25Qx_readData(readAddr, ((uint8_t *) &chData), sizeof(md3x0Channel_t));
W25Qx_sleep();
channel->mode = chData.channel_mode - 1;
channel->bandwidth = chData.bandwidth;

92
platform/drivers/NVM/nvmem_MDUV3x0.c
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@ -20,8 +20,8 @@
#include <interfaces/nvmem.h>
#include <interfaces/delays.h>
#include "calibInfo_MDx.h"
#include "extFlash_MDx.h"
#include <calibInfo_MDx.h>
#include "W25Qx.h"
/**
* \internal Data structure matching the one used by original MD3x0 firmware to
@ -137,45 +137,45 @@ uint32_t _bcd2bin(uint32_t bcd)
void nvm_init()
{
extFlash_init();
W25Qx_init();
}
void nvm_terminate()
{
extFlash_terminate();
W25Qx_terminate();
}
void nvm_readCalibData(void *buf)
{
extFlash_wakeup();
W25Qx_wakeup();
delayUs(5);
mduv3x0Calib_t *calib = ((mduv3x0Calib_t *) buf);
/* Common calibration data */
(void) extFlash_readSecurityRegister(0x1000, (&calib->vox1), 6);
(void) W25Qx_readSecurityRegister(0x1000, (&calib->vox1), 6);
/* UHF-band calibration data */
(void) extFlash_readSecurityRegister(0x1009, (&calib->uhfCal.freqAdjustMid), 1);
(void) extFlash_readSecurityRegister(0x1010, calib->uhfCal.txHighPower, 9);
(void) extFlash_readSecurityRegister(0x2090, calib->uhfCal.txMidPower, 9);
(void) extFlash_readSecurityRegister(0x1020, calib->uhfCal.txLowPower, 9);
(void) extFlash_readSecurityRegister(0x1030, calib->uhfCal.rxSensitivity, 9);
(void) extFlash_readSecurityRegister(0x1040, calib->uhfCal.openSql9, 9);
(void) extFlash_readSecurityRegister(0x1050, calib->uhfCal.closeSql9, 9);
(void) extFlash_readSecurityRegister(0x1070, calib->uhfCal.closeSql1, 9);
(void) extFlash_readSecurityRegister(0x1060, calib->uhfCal.openSql1, 9);
(void) extFlash_readSecurityRegister(0x1090, calib->uhfCal.ctcss67Hz, 9);
(void) extFlash_readSecurityRegister(0x10a0, calib->uhfCal.ctcss151Hz, 9);
(void) extFlash_readSecurityRegister(0x10b0, calib->uhfCal.ctcss254Hz, 9);
(void) extFlash_readSecurityRegister(0x10d0, calib->uhfCal.dcsMod1, 9);
(void) extFlash_readSecurityRegister(0x2030, calib->uhfCal.sendIrange, 9);
(void) extFlash_readSecurityRegister(0x2040, calib->uhfCal.sendQrange, 9);
(void) extFlash_readSecurityRegister(0x2070, calib->uhfCal.analogSendIrange, 9);
(void) extFlash_readSecurityRegister(0x2080, calib->uhfCal.analogSendQrange, 9);
(void) W25Qx_readSecurityRegister(0x1009, (&calib->uhfCal.freqAdjustMid), 1);
(void) W25Qx_readSecurityRegister(0x1010, calib->uhfCal.txHighPower, 9);
(void) W25Qx_readSecurityRegister(0x2090, calib->uhfCal.txMidPower, 9);
(void) W25Qx_readSecurityRegister(0x1020, calib->uhfCal.txLowPower, 9);
(void) W25Qx_readSecurityRegister(0x1030, calib->uhfCal.rxSensitivity, 9);
(void) W25Qx_readSecurityRegister(0x1040, calib->uhfCal.openSql9, 9);
(void) W25Qx_readSecurityRegister(0x1050, calib->uhfCal.closeSql9, 9);
(void) W25Qx_readSecurityRegister(0x1070, calib->uhfCal.closeSql1, 9);
(void) W25Qx_readSecurityRegister(0x1060, calib->uhfCal.openSql1, 9);
(void) W25Qx_readSecurityRegister(0x1090, calib->uhfCal.ctcss67Hz, 9);
(void) W25Qx_readSecurityRegister(0x10a0, calib->uhfCal.ctcss151Hz, 9);
(void) W25Qx_readSecurityRegister(0x10b0, calib->uhfCal.ctcss254Hz, 9);
(void) W25Qx_readSecurityRegister(0x10d0, calib->uhfCal.dcsMod1, 9);
(void) W25Qx_readSecurityRegister(0x2030, calib->uhfCal.sendIrange, 9);
(void) W25Qx_readSecurityRegister(0x2040, calib->uhfCal.sendQrange, 9);
(void) W25Qx_readSecurityRegister(0x2070, calib->uhfCal.analogSendIrange, 9);
(void) W25Qx_readSecurityRegister(0x2080, calib->uhfCal.analogSendQrange, 9);
uint32_t freqs[18];
(void) extFlash_readSecurityRegister(0x20b0, ((uint8_t *) &freqs), 72);
(void) W25Qx_readSecurityRegister(0x20b0, ((uint8_t *) &freqs), 72);
for(uint8_t i = 0; i < 9; i++)
{
@ -184,26 +184,26 @@ void nvm_readCalibData(void *buf)
}
/* VHF-band calibration data */
(void) extFlash_readSecurityRegister(0x100c, (&calib->vhfCal.freqAdjustMid), 1);
(void) extFlash_readSecurityRegister(0x1019, calib->vhfCal.txHighPower, 5);
(void) extFlash_readSecurityRegister(0x2099, calib->vhfCal.txMidPower, 5);
(void) extFlash_readSecurityRegister(0x1029, calib->vhfCal.txLowPower, 5);
(void) extFlash_readSecurityRegister(0x1039, calib->vhfCal.rxSensitivity, 5);
(void) extFlash_readSecurityRegister(0x109b, calib->vhfCal.ctcss67Hz, 5);
(void) extFlash_readSecurityRegister(0x10ab, calib->vhfCal.ctcss151Hz, 5);
(void) extFlash_readSecurityRegister(0x10bb, calib->vhfCal.ctcss254Hz, 5);
(void) extFlash_readSecurityRegister(0x10e0, calib->vhfCal.openSql9, 5);
(void) extFlash_readSecurityRegister(0x10e5, calib->vhfCal.closeSql9, 5);
(void) extFlash_readSecurityRegister(0x10ea, calib->vhfCal.closeSql1, 5);
(void) extFlash_readSecurityRegister(0x10ef, calib->vhfCal.openSql1, 5);
(void) extFlash_readSecurityRegister(0x10db, calib->vhfCal.dcsMod1, 5);
(void) extFlash_readSecurityRegister(0x2039, calib->vhfCal.sendIrange, 5);
(void) extFlash_readSecurityRegister(0x2049, calib->vhfCal.sendQrange, 5);
(void) extFlash_readSecurityRegister(0x2079, calib->uhfCal.analogSendIrange, 5);
(void) extFlash_readSecurityRegister(0x2089, calib->vhfCal.analogSendQrange, 5);
(void) W25Qx_readSecurityRegister(0x100c, (&calib->vhfCal.freqAdjustMid), 1);
(void) W25Qx_readSecurityRegister(0x1019, calib->vhfCal.txHighPower, 5);
(void) W25Qx_readSecurityRegister(0x2099, calib->vhfCal.txMidPower, 5);
(void) W25Qx_readSecurityRegister(0x1029, calib->vhfCal.txLowPower, 5);
(void) W25Qx_readSecurityRegister(0x1039, calib->vhfCal.rxSensitivity, 5);
(void) W25Qx_readSecurityRegister(0x109b, calib->vhfCal.ctcss67Hz, 5);
(void) W25Qx_readSecurityRegister(0x10ab, calib->vhfCal.ctcss151Hz, 5);
(void) W25Qx_readSecurityRegister(0x10bb, calib->vhfCal.ctcss254Hz, 5);
(void) W25Qx_readSecurityRegister(0x10e0, calib->vhfCal.openSql9, 5);
(void) W25Qx_readSecurityRegister(0x10e5, calib->vhfCal.closeSql9, 5);
(void) W25Qx_readSecurityRegister(0x10ea, calib->vhfCal.closeSql1, 5);
(void) W25Qx_readSecurityRegister(0x10ef, calib->vhfCal.openSql1, 5);
(void) W25Qx_readSecurityRegister(0x10db, calib->vhfCal.dcsMod1, 5);
(void) W25Qx_readSecurityRegister(0x2039, calib->vhfCal.sendIrange, 5);
(void) W25Qx_readSecurityRegister(0x2049, calib->vhfCal.sendQrange, 5);
(void) W25Qx_readSecurityRegister(0x2079, calib->uhfCal.analogSendIrange, 5);
(void) W25Qx_readSecurityRegister(0x2089, calib->vhfCal.analogSendQrange, 5);
(void) extFlash_readSecurityRegister(0x2000, ((uint8_t *) &freqs), 40);
extFlash_sleep();
(void) W25Qx_readSecurityRegister(0x2000, ((uint8_t *) &freqs), 40);
W25Qx_sleep();
for(uint8_t i = 0; i < 5; i++)
{
@ -216,13 +216,13 @@ int nvm_readChannelData(channel_t *channel, uint16_t pos)
{
if(pos > maxNumChannels) return -1;
extFlash_wakeup();
W25Qx_wakeup();
delayUs(5);
mduv3x0Channel_t chData;
uint32_t readAddr = chDataBaseAddr + pos * sizeof(mduv3x0Channel_t);
extFlash_readData(readAddr, ((uint8_t *) &chData), sizeof(mduv3x0Channel_t));
extFlash_sleep();
W25Qx_readData(readAddr, ((uint8_t *) &chData), sizeof(mduv3x0Channel_t));
W25Qx_sleep();
channel->mode = chData.channel_mode - 1;
channel->bandwidth = chData.bandwidth;

64
platform/drivers/NVM/spiFlash_MDx.c 100644
Wyświetl plik

@ -0,0 +1,64 @@
/***************************************************************************
* Copyright (C) 2020 by Federico Amedeo Izzo IU2NUO, *
* Niccolò Izzo IU2KIN *
* Frederik Saraci IU2NRO *
* Silvano Seva IU2KWO *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 3 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, see <http://www.gnu.org/licenses/> *
***************************************************************************/
#include <gpio.h>
#include <stdint.h>
#include <hwconfig.h>
/*
* Implementation of external flash SPI interface for MDx devices.
*/
uint8_t spiFlash_SendRecv(uint8_t val)
{
SPI1->DR = val;
while((SPI1->SR & SPI_SR_RXNE) == 0) ;
return SPI1->DR;
}
void spiFlash_init()
{
gpio_setMode(FLASH_CLK, ALTERNATE);
gpio_setMode(FLASH_SDO, ALTERNATE);
gpio_setMode(FLASH_SDI, ALTERNATE);
gpio_setAlternateFunction(FLASH_CLK, 5); /* SPI1 is on AF5 */
gpio_setAlternateFunction(FLASH_SDO, 5);
gpio_setAlternateFunction(FLASH_SDI, 5);
RCC->APB2ENR |= RCC_APB2ENR_SPI1EN;
__DSB();
SPI1->CR1 = SPI_CR1_SSM /* Software managment of nCS */
| SPI_CR1_SSI /* Force internal nCS */
| SPI_CR1_BR_2 /* Fclock: 84MHz/64 = 1.3MHz */
| SPI_CR1_BR_0
| SPI_CR1_MSTR /* Master mode */
| SPI_CR1_SPE; /* Enable peripheral */
}
void spiFlash_terminate()
{
RCC->APB2ENR &= ~RCC_APB2ENR_SPI1EN;
__DSB();
gpio_setMode(FLASH_CLK, INPUT);
gpio_setMode(FLASH_SDO, INPUT);
gpio_setMode(FLASH_SDI, INPUT);
}