kopia lustrzana https://github.com/OpenRTX/OpenRTX
Boot code for AT32F421
Silvano Seva
rodzic
20a7a842b5
commit
d8e22e0b11
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#ifndef ARCH_REGISTERS_IMPL_H
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#define ARCH_REGISTERS_IMPL_H
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#include "at32f421.h"
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#include "core_cm4.h"
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#include "system_at32f421.h"
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#define RCC_SYNC() //Workaround for a bug in stm32f42x
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#endif //ARCH_REGISTERS_IMPL_H
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/***************************************************************************
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* Copyright (C) 2023 by Federico Amedeo Izzo IU2NUO, *
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* Niccolò Izzo IU2KIN *
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* Frederik Saraci IU2NRO *
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* Silvano Seva IU2KWO, *
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* Federico Terraneo *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 3 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, see <http://www.gnu.org/licenses/> *
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***************************************************************************/
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/***********************************************************************
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* bsp.cpp Part of the Miosix Embedded OS.
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* Board support package, this file initializes hardware.
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************************************************************************/
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#include <interfaces/bsp.h>
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#include <kernel/kernel.h>
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#include <kernel/sync.h>
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namespace miosix
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{
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//
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// Initialization
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//
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void IRQbspInit()
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{
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CRM->ahben |= (1 << 17) // Enable GPIOA
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| (1 << 18) // Enable GPIOB
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| (1 << 19) // Enable GPIOC
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| (1 << 22); // Enable GPIOF
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// Configure SysTick
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SysTick->LOAD = SystemCoreClock / miosix::TICK_FREQ;
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}
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void bspInit2()
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{
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}
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//
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// Shutdown and reboot
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//
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void shutdown()
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{
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reboot();
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}
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void reboot()
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{
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disableInterrupts();
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miosix_private::IRQsystemReboot();
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}
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} //namespace miosix
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/***************************************************************************
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* Copyright (C) 2023 by Silvano Seva IU2KWO *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 3 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, see <http://www.gnu.org/licenses/> *
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***************************************************************************/
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#include <stdio.h>
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#include <reent.h>
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#include <filesystem/file_access.h>
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using namespace std;
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* \internal
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* _write_r, write to a file
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*/
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int _write_r(struct _reent *ptr, int fd, const void *buf, size_t cnt)
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{
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(void) ptr;
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(void) fd;
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(void) buf;
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(void) cnt;
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/* If fd is not stdout or stderr */
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ptr->_errno = EBADF;
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return -1;
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}
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/**
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* \internal
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* _read_r, read from a file.
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*/
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int _read_r(struct _reent *ptr, int fd, void *buf, size_t cnt)
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{
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(void) ptr;
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(void) fd;
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(void) buf;
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(void) cnt;
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ptr->_errno = EBADF;
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return -1;
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}
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#ifdef __cplusplus
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}
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#endif
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/***************************************************************************
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* Copyright (C) 2023 by Federico Amedeo Izzo IU2NUO, *
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* Niccolò Izzo IU2KIN *
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* Frederik Saraci IU2NRO *
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* Silvano Seva IU2KWO, *
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* Federico Terraneo *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 3 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, see <http://www.gnu.org/licenses/> *
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***************************************************************************/
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/*
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* startup.cpp
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* STM32 C++ startup.
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* NOTE: for stm32f4 devices ONLY.
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* Supports interrupt handlers in C++ without extern "C"
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* Developed by Terraneo Federico, based on ST startup code.
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* Additionally modified to boot Miosix.
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*/
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#include "interfaces/arch_registers.h"
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#include "kernel/stage_2_boot.h"
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#include "core/interrupts.h" //For the unexpected interrupt call
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#include <string.h>
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/**
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* Called by Reset_Handler, performs initialization and calls main.
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* Never returns.
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*/
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void program_startup() __attribute__((noreturn));
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void program_startup()
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{
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//Cortex M3 core appears to get out of reset with interrupts already enabled
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__disable_irq();
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//SystemInit() is called *before* initializing .data and zeroing .bss
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//Despite all startup files provided by ST do the opposite, there are three
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//good reasons to do so:
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//First, the CMSIS specifications say that SystemInit() must not access
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//global variables, so it is actually possible to call it before
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//Second, when running Miosix with the xram linker scripts .data and .bss
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//are placed in the external RAM, so we *must* call SystemInit(), which
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//enables xram, before touching .data and .bss
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//Third, this is a performance improvement since the loops that initialize
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//.data and zeros .bss now run with the CPU at full speed instead of 8MHz
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SystemInit();
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//These are defined in the linker script
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extern unsigned char _etext asm("_etext");
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extern unsigned char _data asm("_data");
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extern unsigned char _edata asm("_edata");
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extern unsigned char _bss_start asm("_bss_start");
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extern unsigned char _bss_end asm("_bss_end");
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//Initialize .data section, clear .bss section
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unsigned char *etext=&_etext;
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unsigned char *data=&_data;
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unsigned char *edata=&_edata;
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unsigned char *bss_start=&_bss_start;
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unsigned char *bss_end=&_bss_end;
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memcpy(data, etext, edata-data);
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memset(bss_start, 0, bss_end-bss_start);
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//Move on to stage 2
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_init();
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//If main returns, reboot
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NVIC_SystemReset();
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for(;;) ;
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}
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/**
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* Reset handler, called by hardware immediately after reset
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*/
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void Reset_Handler() __attribute__((__interrupt__, noreturn));
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void Reset_Handler()
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{
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/*
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* Initialize process stack and switch to it.
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* This is required for booting Miosix, a small portion of the top of the
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* heap area will be used as stack until the first thread starts. After,
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* this stack will be abandoned and the process stack will point to the
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* current thread's stack.
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*/
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asm volatile("ldr r0, =_heap_end \n\t"
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"msr psp, r0 \n\t"
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"movw r0, #2 \n\n" //Privileged, process stack
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"msr control, r0 \n\t"
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"isb \n\t":::"r0");
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program_startup();
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}
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/**
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* All unused interrupts call this function.
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*/
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extern "C" void Default_Handler()
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{
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unexpectedInterrupt();
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}
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//System handlers
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void /*__attribute__((weak))*/ Reset_Handler(); //These interrupts are not
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void /*__attribute__((weak))*/ NMI_Handler(); //weak because they are
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void /*__attribute__((weak))*/ HardFault_Handler(); //surely defined by Miosix
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void /*__attribute__((weak))*/ MemManage_Handler();
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void /*__attribute__((weak))*/ BusFault_Handler();
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void /*__attribute__((weak))*/ UsageFault_Handler();
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void /*__attribute__((weak))*/ SVC_Handler();
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void /*__attribute__((weak))*/ DebugMon_Handler();
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void /*__attribute__((weak))*/ PendSV_Handler();
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void /*__attribute__((weak))*/ SysTick_Handler();
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//Interrupt handlers
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void __attribute__((weak)) WWDT_IRQHandler();
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void __attribute__((weak)) PVM_IRQHandler();
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void __attribute__((weak)) ERTC_IRQHandler();
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void __attribute__((weak)) FLASH_IRQHandler();
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void __attribute__((weak)) CRM_IRQHandler();
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void __attribute__((weak)) EXINT1_0_IRQHandler();
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void __attribute__((weak)) EXINT3_2_IRQHandler();
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void __attribute__((weak)) EXINT15_4_IRQHandler();
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void __attribute__((weak)) DMA1_Channel1_IRQHandler();
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void __attribute__((weak)) DMA1_Channel3_2_IRQHandler();
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void __attribute__((weak)) DMA1_Channel5_4_IRQHandler();
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void __attribute__((weak)) ADC1_CMP_IRQHandler();
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void __attribute__((weak)) TMR1_BRK_OVF_TRG_HALL_IRQHandler();
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void __attribute__((weak)) TMR1_CH_IRQHandler();
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void __attribute__((weak)) TMR3_GLOBAL_IRQHandler();
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void __attribute__((weak)) TMR6_GLOBAL_IRQHandler();
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void __attribute__((weak)) TMR14_GLOBAL_IRQHandler();
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void __attribute__((weak)) TMR15_GLOBAL_IRQHandler();
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void __attribute__((weak)) TMR16_GLOBAL_IRQHandler();
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void __attribute__((weak)) TMR17_GLOBAL_IRQHandler();
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void __attribute__((weak)) I2C1_EVT_IRQHandler();
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void __attribute__((weak)) I2C2_EVT_IRQHandler();
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void __attribute__((weak)) SPI1_IRQHandler();
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void __attribute__((weak)) SPI2_IRQHandler();
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void __attribute__((weak)) USART1_IRQHandler();
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void __attribute__((weak)) USART2_IRQHandler();
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void __attribute__((weak)) I2C1_ERR_IRQHandler();
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void __attribute__((weak)) I2C2_ERR_IRQHandler();
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//Stack top, defined in the linker script
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extern char _main_stack_top asm("_main_stack_top");
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//Interrupt vectors, must be placed @ address 0x00000000
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//The extern declaration is required otherwise g++ optimizes it out
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extern void (* const __Vectors[])();
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void (* const __Vectors[])() __attribute__ ((section(".isr_vector"))) =
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{
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reinterpret_cast<void (*)()>(&_main_stack_top),/* Stack pointer*/
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Reset_Handler,
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NMI_Handler,
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HardFault_Handler,
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MemManage_Handler,
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BusFault_Handler,
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UsageFault_Handler,
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0,
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0,
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0,
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0,
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SVC_Handler,
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DebugMon_Handler,
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0,
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PendSV_Handler,
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SysTick_Handler,
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WWDT_IRQHandler, /* Window Watchdog Timer */
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PVM_IRQHandler, /* PVM through EXINT Line detect */
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ERTC_IRQHandler, /* ERTC */
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FLASH_IRQHandler, /* Flash */
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CRM_IRQHandler, /* CRM */
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EXINT1_0_IRQHandler, /* EXINT Line 1 & 0 */
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EXINT3_2_IRQHandler, /* EXINT Line 3 & 2 */
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EXINT15_4_IRQHandler, /* EXINT Line 15 ~ 4 */
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0, /* Reserved */
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DMA1_Channel1_IRQHandler, /* DMA1 Channel 1 */
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DMA1_Channel3_2_IRQHandler, /* DMA1 Channel 3 & 2 */
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DMA1_Channel5_4_IRQHandler, /* DMA1 Channel 5 & 4 */
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ADC1_CMP_IRQHandler, /* ADC1 & Comparator */
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TMR1_BRK_OVF_TRG_HALL_IRQHandler, /* TMR1 brake overflow trigger and hall */
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TMR1_CH_IRQHandler, /* TMR1 channel */
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0, /* Reserved */
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TMR3_GLOBAL_IRQHandler, /* TMR3 */
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TMR6_GLOBAL_IRQHandler, /* TMR6 */
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0, /* Reserved */
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TMR14_GLOBAL_IRQHandler, /* TMR14 */
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TMR15_GLOBAL_IRQHandler, /* TMR15 */
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TMR16_GLOBAL_IRQHandler, /* TMR16 */
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TMR17_GLOBAL_IRQHandler, /* TMR17 */
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I2C1_EVT_IRQHandler, /* I2C1 Event */
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I2C2_EVT_IRQHandler, /* I2C2 Event */
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SPI1_IRQHandler, /* SPI1 */
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SPI2_IRQHandler, /* SPI2 */
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USART1_IRQHandler, /* USART1 */
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USART2_IRQHandler, /* USART2 */
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0, /* Reserved */
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0, /* Reserved */
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0, /* Reserved */
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I2C1_ERR_IRQHandler, /* I2C1 Error */
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0, /* Reserved */
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I2C2_ERR_IRQHandler /* I2C2 Error */
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};
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#pragma weak WWDT_IRQHandler = Default_Handler
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#pragma weak PVM_IRQHandler = Default_Handler
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#pragma weak ERTC_IRQHandler = Default_Handler
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#pragma weak FLASH_IRQHandler = Default_Handler
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#pragma weak CRM_IRQHandler = Default_Handler
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#pragma weak EXINT1_0_IRQHandler = Default_Handler
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#pragma weak EXINT3_2_IRQHandler = Default_Handler
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#pragma weak EXINT15_4_IRQHandler = Default_Handler
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#pragma weak DMA1_Channel1_IRQHandler = Default_Handler
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#pragma weak DMA1_Channel3_2_IRQHandler = Default_Handler
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#pragma weak DMA1_Channel5_4_IRQHandler = Default_Handler
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#pragma weak ADC1_CMP_IRQHandler = Default_Handler
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#pragma weak TMR1_BRK_OVF_TRG_HALL_IRQHandler = Default_Handler
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#pragma weak TMR1_CH_IRQHandler = Default_Handler
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#pragma weak TMR3_GLOBAL_IRQHandler = Default_Handler
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#pragma weak TMR6_GLOBAL_IRQHandler = Default_Handler
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#pragma weak TMR14_GLOBAL_IRQHandler = Default_Handler
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#pragma weak TMR15_GLOBAL_IRQHandler = Default_Handler
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#pragma weak TMR16_GLOBAL_IRQHandler = Default_Handler
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#pragma weak TMR17_GLOBAL_IRQHandler = Default_Handler
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#pragma weak I2C1_EVT_IRQHandler = Default_Handler
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#pragma weak I2C2_EVT_IRQHandler = Default_Handler
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#pragma weak SPI1_IRQHandler = Default_Handler
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#pragma weak SPI2_IRQHandler = Default_Handler
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#pragma weak USART1_IRQHandler = Default_Handler
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#pragma weak USART2_IRQHandler = Default_Handler
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#pragma weak I2C1_ERR_IRQHandler = Default_Handler
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#pragma weak I2C2_ERR_IRQHandler = Default_Handler
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@ -0,0 +1,165 @@
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/*
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* C++ enabled linker script
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* Developed by TFT: Terraneo Federico Technologies
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* Optimized for use with the Miosix kernel
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*/
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/*
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* This linker script puts:
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* - read only data and code (.text, .rodata, .eh_*) in flash
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* - stacks, heap and sections .data and .bss in the internal ram
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* - the external ram (if available) is not used.
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*/
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/*
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* The main stack is used for interrupt handling by the kernel.
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*
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* *** Readme ***
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* This linker script places the main stack (used by the kernel for interrupts)
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* at the bottom of the ram, instead of the top. This is done for two reasons:
|
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*
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* - as an optimization for microcontrollers with little ram memory. In fact
|
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* the implementation of malloc from newlib requests memory to the OS in 4KB
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* block (except the first block that can be smaller). This is probably done
|
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* for compatibility with OSes with an MMU and paged memory. To see why this
|
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* is bad, consider a microcontroller with 8KB of ram: when malloc finishes
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* up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will
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* fail because the top part of the ram is used by the main stack. As a
|
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* result, the top part of the memory will not be used by malloc, even if
|
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* available (and it is nearly *half* the ram on an 8KB mcu). By placing the
|
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* main stack at the bottom of the ram, the upper 4KB block will be entirely
|
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* free and available as heap space.
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*
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* - In case of main stack overflow the cpu will fault because access to memory
|
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* before the beginning of the ram faults. Instead with the default stack
|
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* placement the main stack will silently collide with the heap.
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* Note: if increasing the main stack size also increase the ORIGIN value in
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* the MEMORY definitions below accordingly.
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*/
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_main_stack_size = 0x00000200; /* main stack = 512Bytes */
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_main_stack_top = 0x20000000 + _main_stack_size;
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ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error");
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_heap_end = 0x20004000; /* end of available ram */
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/* identify the Entry Point */
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ENTRY(_Z13Reset_Handlerv)
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/* specify the memory areas */
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MEMORY
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{
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flash(rx) : ORIGIN = 0x08001400, LENGTH = 59K
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ram(wx) : ORIGIN = 0x20000200, LENGTH = 16K - 0x200
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}
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/* now define the output sections */
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SECTIONS
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{
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. = 0;
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/* .text section: code goes to flash */
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.text :
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{
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/* Startup code must go at address 0 */
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KEEP(*(.isr_vector))
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|
||||
*(.text)
|
||||
*(.text.*)
|
||||
*(.gnu.linkonce.t.*)
|
||||
/* these sections for thumb interwork? */
|
||||
*(.glue_7)
|
||||
*(.glue_7t)
|
||||
/* these sections for C++? */
|
||||
*(.gcc_except_table)
|
||||
*(.gcc_except_table.*)
|
||||
*(.ARM.extab*)
|
||||
*(.gnu.linkonce.armextab.*)
|
||||
|
||||
. = ALIGN(4);
|
||||
/* .rodata: constant data */
|
||||
*(.rodata)
|
||||
*(.rodata.*)
|
||||
*(.gnu.linkonce.r.*)
|
||||
|
||||
/* C++ Static constructors/destructors (eabi) */
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.init))
|
||||
|
||||
. = ALIGN(4);
|
||||
__miosix_init_array_start = .;
|
||||
KEEP (*(SORT(.miosix_init_array.*)))
|
||||
KEEP (*(.miosix_init_array))
|
||||
__miosix_init_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__preinit_array_start = .;
|
||||
KEEP (*(.preinit_array))
|
||||
__preinit_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__init_array_start = .;
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array))
|
||||
__init_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
__fini_array_start = .;
|
||||
KEEP (*(.fini_array))
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
__fini_array_end = .;
|
||||
|
||||
/* C++ Static constructors/destructors (elf) */
|
||||
. = ALIGN(4);
|
||||
_ctor_start = .;
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*crtend.o(.ctors))
|
||||
_ctor_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*crtend.o(.dtors))
|
||||
} > flash
|
||||
|
||||
/* .ARM.exidx is sorted, so has to go in its own output section. */
|
||||
__exidx_start = .;
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > flash
|
||||
__exidx_end = .;
|
||||
|
||||
/* .data section: global variables go to ram, but also store a copy to
|
||||
flash to initialize them */
|
||||
.data : ALIGN(8)
|
||||
{
|
||||
_data = .;
|
||||
*(.data)
|
||||
*(.data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
. = ALIGN(8);
|
||||
_edata = .;
|
||||
} > ram AT > flash
|
||||
|
||||
_etext = LOADADDR(.data);
|
||||
|
||||
/* .bss section: uninitialized global variables go to ram */
|
||||
_bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
*(.bss)
|
||||
*(.bss.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
. = ALIGN(8);
|
||||
} > ram
|
||||
_bss_end = .;
|
||||
|
||||
_end = .;
|
||||
PROVIDE(end = .);
|
||||
}
|
||||
Ładowanie…
Reference in New Issue