kopia lustrzana https://github.com/OpenRTX/OpenRTX
Implementation of audio output stream driver for Module 17
Silvano Seva
rodzic
cc00cce982
commit
83b0182057
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@ -314,6 +314,7 @@ mod17_src = src + stm32f405_src + ['platform/targets/Module17/platform.c',
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'platform/drivers/NVM/nvmem_Mod17.c',
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'platform/drivers/baseband/radio_Mod17.cpp',
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'platform/drivers/audio/inputStream_Mod17.cpp',
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'platform/drivers/audio/outputStream_Mod17.c',
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'platform/drivers/audio/audio_Mod17.c']
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mod17_inc = inc + stm32f405_inc + ['platform/targets/Module17']
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@ -0,0 +1,198 @@
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/***************************************************************************
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* Copyright (C) 2021 by Federico Amedeo Izzo IU2NUO, *
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* Niccolò Izzo IU2KIN *
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* Frederik Saraci IU2NRO *
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* Silvano Seva IU2KWO *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 3 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, see <http://www.gnu.org/licenses/> *
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***************************************************************************/
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#include <interfaces/audio_stream.h>
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#include <interfaces/gpio.h>
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#include <hwconfig.h>
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#include <stdbool.h>
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int priority = PRIO_BEEP;
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bool running = false;
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void stopTransfer()
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{
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/* Shutdown timer */
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TIM7->CR1 &= ~TIM_CR1_CEN;
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/* Disable DAC channels and clear underrun flags */
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DAC->CR &= ~(DAC_CR_EN1 | DAC_CR_EN2);
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DAC->SR |= DAC_SR_DMAUDR1 | DAC_SR_DMAUDR2;
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/* Stop DMA transfers */
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DMA1_Stream5->CR &= ~DMA_SxCR_EN;
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DMA1_Stream6->CR &= ~DMA_SxCR_EN;
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running = false;
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}
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/*
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* DMA 1, Stream 5: data transfer for RTX sink
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*/
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void __attribute__((used)) DMA1_Stream5_IRQHandler()
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{
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stopTransfer();
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DMA1->HIFCR |= DMA_HIFCR_CTCIF5
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| DMA_HIFCR_CTEIF5;
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NVIC_DisableIRQ(DMA1_Stream5_IRQn);
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}
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/*
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* DMA 1, Stream 6: data transfer for speaker sink
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*/
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void __attribute__((used)) DMA1_Stream6_IRQHandler()
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{
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stopTransfer();
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DMA1->HIFCR |= DMA_HIFCR_CTCIF6
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| DMA_HIFCR_CTEIF6;
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NVIC_DisableIRQ(DMA1_Stream6_IRQn);
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}
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streamId outputStream_start(const enum AudioSink destination,
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const enum AudioPriority prio,
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stream_sample_t * const buf,
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const size_t length,
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const uint32_t sampleRate)
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{
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if(destination == SINK_MCU) return -1; /* This device cannot sink to buffer */
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if(running) /* Check if a stream is already running */
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{
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if(prio < priority) return -1; /* Requested priority is lower than current */
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if(prio > priority) stopTransfer(); /* Stop an ongoing stream with lower priority */
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while(running) ; /* Same priority, wait for current stream to end */
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}
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/* This assigment must be thread-safe */
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__disable_irq();
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priority = prio;
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running = true;
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__enable_irq();
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/*
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* Convert buffer elements from int16_t to unsigned 16 bit values ranging
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* from 0 to 4096, as required by DAC. Processing can be done in-place
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* because the API mandates that the function caller does not modify the
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* buffer content once this function has been called. Code below exploits
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* Cortex M4 SIMD instructions for fast execution.
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*/
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uint32_t *data = ((uint32_t *) buf);
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for(size_t i = 0; i < length/2; i++)
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{
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uint32_t value = __SADD16(data[i], 0x80008000);
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data[i] = (value >> 4) & 0x0FFF0FFF;
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}
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/* Handle last element in case of odd buffer length */
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if((length % 2) != 0)
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{
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int16_t value = buf[length - 1] + 32768;
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buf[length - 1] = ((uint16_t) value) >> 4;
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}
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/* Configure GPIOs */
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gpio_setMode(GPIOA, 4, INPUT_ANALOG); /* Baseband TX */
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gpio_setMode(GPIOA, 5, INPUT_ANALOG); /* Spk output */
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/*
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* Enable peripherals
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*/
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RCC->AHB1ENR |= RCC_AHB1ENR_DMA1EN;
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RCC->APB1ENR |= RCC_APB1ENR_DACEN
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| RCC_APB1ENR_TIM7EN;
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__DSB();
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/*
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* Configure DAC and DMA stream
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*/
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if(destination == SINK_RTX)
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{
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DAC->CR = DAC_CR_DMAEN1 /* Enable DMA mode */
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| DAC_CR_TSEL1_1 /* TIM7 TRGO as trigger source */
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| DAC_CR_TEN1 /* Enable trigger input */
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| DAC_CR_EN1; /* Enable DAC */
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DMA1_Stream5->NDTR = length;
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DMA1_Stream5->PAR = ((uint32_t) &(DAC->DHR12R1));
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DMA1_Stream5->M0AR = ((uint32_t) buf);
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DMA1_Stream5->CR = DMA_SxCR_CHSEL /* Channel 7 */
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| DMA_SxCR_PL /* Very high priority */
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| DMA_SxCR_MSIZE_0 /* 16 bit source size */
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| DMA_SxCR_PSIZE_0 /* 16 bit destination size */
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| DMA_SxCR_MINC /* Increment source pointer */
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| DMA_SxCR_TCIE /* Transfer complete interrupt */
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| DMA_SxCR_TEIE /* Transfer error interrupt */
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| DMA_SxCR_DIR_0 /* Memory to peripheral */
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| DMA_SxCR_EN; /* Start transfer */
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NVIC_ClearPendingIRQ(DMA1_Stream5_IRQn);
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NVIC_SetPriority(DMA1_Stream5_IRQn, 10);
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NVIC_EnableIRQ(DMA1_Stream5_IRQn);
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}
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else
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{
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DAC->CR = DAC_CR_DMAEN2 /* Enable DMA mode */
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| DAC_CR_TSEL2_1 /* TIM7 TRGO as trigger source */
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| DAC_CR_TEN2 /* Enable trigger input */
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| DAC_CR_EN2; /* Enable DAC */
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DMA1_Stream6->NDTR = length;
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DMA1_Stream6->PAR = ((uint32_t) &(DAC->DHR12R2));
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DMA1_Stream6->M0AR = ((uint32_t) buf);
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DMA1_Stream6->CR = DMA_SxCR_CHSEL /* Channel 7 */
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| DMA_SxCR_PL /* Very high priority */
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| DMA_SxCR_MSIZE_0 /* 16 bit source size */
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| DMA_SxCR_PSIZE_0 /* 16 bit destination size */
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| DMA_SxCR_MINC /* Increment source pointer */
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| DMA_SxCR_TCIE /* Transfer complete interrupt */
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| DMA_SxCR_TEIE /* Transfer error interrupt */
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| DMA_SxCR_DIR_0 /* Memory to peripheral */
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| DMA_SxCR_EN; /* Start transfer */
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NVIC_ClearPendingIRQ(DMA1_Stream6_IRQn);
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NVIC_SetPriority(DMA1_Stream6_IRQn, 10);
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NVIC_EnableIRQ(DMA1_Stream6_IRQn);
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}
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/*
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* TIM7 for conversion triggering via TIM7_TRGO, that is counter reload.
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* AP1 frequency is 42MHz but timer runs at 84MHz, tick rate is 1MHz,
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* reload register is configured based on desired sample rate.
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*/
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TIM7->PSC = 83;
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TIM7->ARR = (1000000/sampleRate) - 1;
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TIM7->CNT = 0;
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TIM7->EGR = TIM_EGR_UG;
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TIM7->CR2 = TIM_CR2_MMS_1;
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TIM7->CR1 = TIM_CR1_CEN;
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return 0;
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}
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void outputStream_stop(streamId id)
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{
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(void) id;
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if(!running) return;
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stopTransfer();
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}
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