kopia lustrzana https://github.com/OpenRTX/OpenRTX
Initial implementation of rtx driver for TYT MD-380 radio, by now supporting only analog FM reception
Silvano Seva
rodzic
17376b819a
commit
55b182406d
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@ -11,7 +11,6 @@ project('OpenRTX', 'c',
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## OpenRTX
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openrtx_src = ['openrtx/src/bootstrap.c',
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'openrtx/src/state.c',
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'openrtx/src/ui.c',
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@ -32,6 +31,8 @@ openrtx_inc = ['openrtx/include/interfaces',
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'platform/drivers/NVM',
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'platform/drivers/tones',
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'openrtx/include/fonts/adafruit']
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'platform/drivers/tones',
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'platform/drivers/baseband']
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## RTOS
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rtos_src = ['rtos/uC-OS3/Source/__dbg_uCOS-III.c',
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@ -174,6 +175,8 @@ md380_src = src + stm32f405_src + ['platform/drivers/display/HX83XX_MDx.c',
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'platform/drivers/NVM/extFlash_MDx.c',
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'platform/drivers/NVM/nvmem_MD3x0.c',
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'platform/drivers/tones/toneGenerator_MDx.c',
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'platform/drivers/baseband/pll_MD3x0.c',
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'platform/drivers/baseband/rtx_MD3x0.c',
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'platform/targets/MD-380/platform.c',
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'openrtx/src/graphics/graphics_rgb565.c']
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@ -22,23 +22,23 @@
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#include <stdint.h>
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/**
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* \brief CTCSS and DCS type definition.
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*
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* Continuous Tone Controlled Squelch System (CTCSS)
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* sub-audible tone frequency are expressed in \em tenth of Hz.
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* For example, the subaudible tone of 88.5 Hz is represented within
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* Hamlib by 885.
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*
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* Digitally-Coded Squelch codes are simple direct integers.
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*/
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/**
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* \brief CTCSS and DCS type definition.
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*
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* Continuous Tone Controlled Squelch System (CTCSS)
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* sub-audible tone frequency are expressed in \em tenth of Hz.
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* For example, the subaudible tone of 88.5 Hz is represented within Hamlib by
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* 885.
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*
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* Digitally-Coded Squelch codes are simple direct integers.
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*/
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typedef unsigned int tone_t;
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/**
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* \brief Frequency type,
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*
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* Frequency type unit in Hz, able to hold SHF frequencies.
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*/
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/**
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* \brief Frequency type.
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*
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* Frequency type unit in Hz, able to hold SHF frequencies.
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*/
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typedef uint32_t freq_t;
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#endif /* DATATYPES_H */
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@ -0,0 +1,74 @@
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/***************************************************************************
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* Copyright (C) 2020 by Federico Amedeo Izzo IU2NUO, *
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* Niccolò Izzo IU2KIN *
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* Frederik Saraci IU2NRO *
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* Silvano Seva IU2KWO *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 3 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, see <http://www.gnu.org/licenses/> *
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***************************************************************************/
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#ifndef RTX_H
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#define RTX_H
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#include <stdint.h>
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#include <datatypes.h>
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enum funcmode
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{
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OFF,
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RX,
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TX
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};
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enum tone
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{
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NONE,
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CTCSS_67_0,
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CTCSS_71_9,
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CTCSS_81_5
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};
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enum bw
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{
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BW_12_5,
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BW_25
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};
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enum opmode
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{
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FM,
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DMR
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};
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void rtx_init();
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void rtx_terminate();
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void rtx_setTxFreq(freq_t freq);
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void rtx_setRxFreq(freq_t freq);
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void rtx_setFuncmode(enum funcmode mode);
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void rtx_setToneRx(enum tone t);
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void rtx_setToneTx(enum tone t);
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void rtx_setBandwidth(enum bw b);
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float rtx_getRssi();
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void rtx_setOpmode(enum opmode mode);
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#endif /* RTX_H */
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@ -0,0 +1,111 @@
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/***************************************************************************
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* Copyright (C) 2020 by Silvano Seva IU2KWO and Niccolò Izzo IU2KIN *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 3 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, see <http://www.gnu.org/licenses/> *
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***************************************************************************/
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#include "pll_MD3x0.h"
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#include <math.h>
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#include "gpio.h"
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#include "delays.h"
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#include "hwconfig.h"
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#define REF_CLK 16800000.0F /* Reference clock: 16.8MHz */
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#define PHD_GAIN 0x1F /* Phase detector gain: hex value, max 0x1F */
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void _spiSend(uint16_t value)
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{
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uint16_t temp = value;
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gpio_clearPin(PLL_CS);
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delayUs(10);
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for(uint8_t i = 0; i < 16; i++)
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{
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gpio_setPin(PLL_CLK);
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delayUs(1);
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if(temp & 0x8000)
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{
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gpio_setPin(PLL_DAT);
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}
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else
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{
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gpio_clearPin(PLL_DAT);
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}
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temp <<= 1;
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delayUs(1);
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gpio_clearPin(PLL_CLK);
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delayUs(1);
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}
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gpio_setPin(PLL_CLK);
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delayUs(10);
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gpio_setPin(PLL_CS);
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}
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void pll_init()
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{
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gpio_setMode(PLL_CLK, OUTPUT);
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gpio_setMode(PLL_DAT, OUTPUT);
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gpio_setMode(PLL_CS, OUTPUT);
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gpio_setPin(PLL_CS);
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gpio_setMode(PLL_LD, INPUT);
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_spiSend(0x6000 | ((uint16_t) PHD_GAIN)); /* Phase detector gain */
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_spiSend(0x73D0); /* Power down/multiplexer control register */
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_spiSend(0x8000); /* Modulation control register */
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_spiSend(0x9000); /* Modulation data register */
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}
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void pll_terminate()
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{
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gpio_setMode(PLL_CLK, INPUT);
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gpio_setMode(PLL_DAT, INPUT);
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gpio_setMode(PLL_CS, INPUT);
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}
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void pll_setFrequency(float freq, uint8_t clkDiv)
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{
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/* Maximum allowable value for reference clock divider is 32 */
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if (clkDiv > 32) clkDiv = 32;
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float K = freq/(REF_CLK/((float) clkDiv));
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float Ndiv = floor(K) - 32.0;
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float Ndnd = round(262144*(K - Ndiv - 32.0));
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uint32_t dnd = ((uint32_t) Ndnd);
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uint16_t dndMsb = dnd >> 8;
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uint16_t dndLsb = dnd & 0x00FF;
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_spiSend((uint16_t) Ndiv); /* Divider register */
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_spiSend(0x2000 | dndLsb); /* Dividend LSB register */
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_spiSend(0x1000 | dndMsb); /* Dividend MSB register */
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_spiSend(0x5000 | ((uint16_t)clkDiv - 1)); /* Reference clock divider */
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}
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bool pll_locked()
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{
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return (gpio_readPin(PLL_LD) == 1) ? true : false;
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}
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bool pll_spiInUse()
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{
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/* If PLL chip select is low, SPI is being used by this driver. */
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return (gpio_readPin(PLL_CS) == 1) ? false : true;
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}
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@ -0,0 +1,64 @@
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/***************************************************************************
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* Copyright (C) 2020 by Silvano Seva IU2KWO and Niccolò Izzo IU2KIN *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 3 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, see <http://www.gnu.org/licenses/> *
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***************************************************************************/
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#ifndef PLL_MD3x0_H
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#define PLL_MD3x0_H
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#include <stdint.h>
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#include <stdbool.h>
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/**
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* Driver for PLL in MD3x0 radios (MD380 and MD380), which is SKY73210.
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*
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* WARNING: the PLL and DMR chips share the SPI MOSI line, thus particular care
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* has to be put to avoid them stomping reciprocally. This driver does not make
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* any check if a SPI transfer is already in progress, deferring the correct bus
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* management to higher level modules. However, a function returning true if the
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* bus is currently in use by this driver is provided.
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*/
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/**
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* Initialise the PLL.
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*/
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void pll_init();
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/**
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* Terminate PLL driver, bringing GPIOs back to reset state.
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*/
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void pll_terminate();
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/**
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* Change VCO frequency.
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* @param freq: new VCO frequency, in Hz.
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* @param clkDiv: reference clock division factor.
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*/
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void pll_setFrequency(float freq, uint8_t clkDiv);
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/**
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* Check if PLL is locked.
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* @return true if PLL is locked.
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*/
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bool pll_locked();
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/**
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* Check if the SPI bus in common between PLL and DMR chips is in use by this
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* driver.
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* @return true if this driver is using the SPI bus.
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*/
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bool pll_spiInUse();
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#endif /* PLL_H */
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@ -0,0 +1,194 @@
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/***************************************************************************
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* Copyright (C) 2020 by Federico Amedeo Izzo IU2NUO, *
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* Niccolò Izzo IU2KIN *
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* Frederik Saraci IU2NRO *
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* Silvano Seva IU2KWO *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 3 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, see <http://www.gnu.org/licenses/> *
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***************************************************************************/
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#include <hwconfig.h>
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#include <datatypes.h>
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#include <gpio.h>
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#include "rtx.h"
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#include "pll_MD3x0.h"
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#include "ADC1_MDxx380.h"
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const freq_t IF_FREQ = 49950000.0f; /* Intermediate frequency: 49.95MHz */
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freq_t rxFreq = 430000000.0f;
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freq_t txFreq = 430000000.0f;
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void _setMod2Bias(uint16_t value)
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{
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DAC->DHR12R2 = value;
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}
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void _setApcTv(uint16_t value)
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{
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DAC->DHR12R1 = value;
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}
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void rtx_init()
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{
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/*
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* Configure GPIOs
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*/
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gpio_setMode(PLL_PWR, OUTPUT);
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gpio_setMode(VCOVCC_SW, OUTPUT);
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gpio_setMode(DMR_SW, OUTPUT);
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gpio_setMode(WN_SW, OUTPUT);
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gpio_setMode(FM_SW, OUTPUT);
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// gpio_setMode(V_CS, OUTPUT);
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gpio_setMode(RF_APC_SW, OUTPUT);
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gpio_setMode(TX_STG_EN, OUTPUT);
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gpio_setMode(RX_STG_EN, OUTPUT);
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gpio_clearPin(PLL_PWR); /* PLL off */
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gpio_setPin(VCOVCC_SW); /* VCOVCC high enables RX VCO, TX VCO if low */
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gpio_clearPin(WN_SW); /* 25kHz band (?) */
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gpio_clearPin(DMR_SW); /* Disconnect HR_C5000 input IF signal and audio out */
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gpio_clearPin(FM_SW); /* Disconnect analog FM audio path */
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// gpio_setPin(V_CS);
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gpio_clearPin(RF_APC_SW); /* Disable RF power control */
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gpio_clearPin(TX_STG_EN); /* Disable TX power stage */
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gpio_clearPin(RX_STG_EN); /* Disable RX input stage */
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/*
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* Configure and enble DAC
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*/
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gpio_setMode(APC_TV, INPUT_ANALOG);
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gpio_setMode(MOD2_BIAS, INPUT_ANALOG);
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RCC->APB1ENR |= RCC_APB1ENR_DACEN;
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DAC->CR = DAC_CR_EN2 | DAC_CR_EN1;
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DAC->DHR12R2 = 0;
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DAC->DHR12R1 = 0;
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/*
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* Enable and configure PLL
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*/
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gpio_setPin(PLL_PWR);
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pll_init();
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}
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void rtx_terminate()
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{
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pll_terminate();
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gpio_clearPin(PLL_PWR); /* PLL off */
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gpio_clearPin(DMR_SW); /* Disconnect HR_C5000 input IF signal and audio out */
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gpio_clearPin(FM_SW); /* Disconnect analog FM audio path */
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gpio_clearPin(RF_APC_SW); /* Disable RF power control */
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gpio_clearPin(TX_STG_EN); /* Disable TX power stage */
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gpio_clearPin(RX_STG_EN); /* Disable RX input stage */
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DAC->DHR12R2 = 0;
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DAC->DHR12R1 = 0;
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RCC->APB1ENR &= ~RCC_APB1ENR_DACEN;
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}
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void rtx_setTxFreq(freq_t freq)
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{
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txFreq = freq;
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}
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void rtx_setRxFreq(freq_t freq)
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{
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rxFreq = freq;
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}
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void rtx_setFuncmode(enum funcmode mode)
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{
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switch(mode)
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{
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case OFF:
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gpio_clearPin(TX_STG_EN);
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gpio_clearPin(RX_STG_EN);
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break;
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case RX:
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gpio_clearPin(TX_STG_EN);
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gpio_clearPin(RF_APC_SW);
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gpio_setPin(VCOVCC_SW);
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pll_setFrequency(rxFreq - IF_FREQ, 5);
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_setMod2Bias(0x3c0); /* TODO use calibration */
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_setApcTv(0x956); /* TODO use calibration */
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gpio_setPin(RX_STG_EN);
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break;
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case TX:
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/* TODO */
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break;
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default:
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/* TODO */
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break;
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}
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}
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void rtx_setToneRx(enum tone t)
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{
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/* TODO */
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}
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void rtx_setToneTx(enum tone t)
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{
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/* TODO */
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}
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void rtx_setBandwidth(enum bw b)
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{
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switch(b)
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{
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case BW_25:
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gpio_clearPin(WN_SW);
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break;
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case BW_12_5:
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gpio_setPin(WN_SW);
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break;
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default:
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/* TODO */
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break;
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}
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}
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float rtx_getRssi()
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{
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return adc1_getMeasurement(1);
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}
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||||
void rtx_setOpmode(enum opmode mode)
|
||||
{
|
||||
switch(mode)
|
||||
{
|
||||
case FM:
|
||||
gpio_clearPin(DMR_SW);
|
||||
gpio_setPin(FM_SW);
|
||||
break;
|
||||
|
||||
case DMR:
|
||||
gpio_clearPin(FM_SW);
|
||||
gpio_setPin(DMR_SW);
|
||||
break;
|
||||
|
||||
default:
|
||||
/* TODO */
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
|
@ -87,4 +87,35 @@
|
|||
#define FLASH_SDO GPIOB,4
|
||||
#define FLASH_SDI GPIOB,5
|
||||
|
||||
/* PLL */
|
||||
#define PLL_CS GPIOD,11
|
||||
#define PLL_CLK GPIOE,4
|
||||
#define PLL_DAT GPIOE,5 /* WARNING: this line is also HR_C5000 MOSI */
|
||||
#define PLL_LD GPIOD,10
|
||||
|
||||
/* HR_C5000 */
|
||||
#define DMR_CS GPIOE,2
|
||||
#define DMR_CLK GPIOC,13
|
||||
#define DMR_MOSI PLL_DAT
|
||||
#define DMR_MISO GPIOE,3
|
||||
#define DMR_SLEEP GPIOE,6
|
||||
#define V_CS GPIOB,12
|
||||
|
||||
/* RTX control */
|
||||
#define PLL_PWR GPIOA,8
|
||||
#define VCOVCC_SW GPIOA,9
|
||||
#define DMR_SW GPIOA,10
|
||||
#define FM_SW GPIOB,2
|
||||
#define WN_SW GPIOA,13
|
||||
#define RF_APC_SW GPIOC,4
|
||||
#define TX_STG_EN GPIOC,5
|
||||
#define RX_STG_EN GPIOC,9
|
||||
#define APC_TV GPIOA,4
|
||||
#define MOD2_BIAS GPIOA,5
|
||||
|
||||
/* Audio control */
|
||||
#define AMP_EN GPIOB,9
|
||||
#define SPK_MUTE GPIOB,8
|
||||
#define FM_MUTE GPIOE,13
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Ładowanie…
Reference in New Issue