kopia lustrzana https://github.com/OpenRTX/OpenRTX
Fixed compilation warnings and code refactoring pass
rodzic
1846fde270
commit
1cd0efdee1
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@ -163,21 +163,24 @@ inline void gfx_setPixel(point_t pos, color_t color)
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#ifdef PIX_FMT_RGB565
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#ifdef PIX_FMT_RGB565
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// Blend old pixel value and new one
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// Blend old pixel value and new one
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if (color.alpha < 255) {
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if (color.alpha < 255)
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{
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uint8_t alpha = color.alpha;
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uint8_t alpha = color.alpha;
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rgb565_t new_pixel = _true2highColor(color);
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rgb565_t new_pixel = _true2highColor(color);
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uint16_t raw_pixel = *((uint16_t *)buf + pos.x + pos.y*SCREEN_WIDTH);
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rgb565_t old_pixel = buf[pos.x + pos.y*SCREEN_WIDTH];
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rgb565_t old_pixel = *((rgb565_t*) &raw_pixel);
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rgb565_t pixel = {((255-alpha)*old_pixel.b+alpha*new_pixel.b)/255,
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rgb565_t pixel = {((255-alpha)*old_pixel.b+alpha*new_pixel.b)/255,
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((255-alpha)*old_pixel.g+alpha*new_pixel.g)/255,
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((255-alpha)*old_pixel.g+alpha*new_pixel.g)/255,
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((255-alpha)*old_pixel.r+alpha*new_pixel.r)/255};
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((255-alpha)*old_pixel.r+alpha*new_pixel.r)/255};
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buf[pos.x + pos.y*SCREEN_WIDTH] = pixel;
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buf[pos.x + pos.y*SCREEN_WIDTH] = pixel;
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} else {
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}
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else
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{
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buf[pos.x + pos.y*SCREEN_WIDTH] = _true2highColor(color);
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buf[pos.x + pos.y*SCREEN_WIDTH] = _true2highColor(color);
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}
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}
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#elif defined PIX_FMT_BW
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#elif defined PIX_FMT_BW
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// Ignore more than half transparent pixels
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// Ignore more than half transparent pixels
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if (color.alpha >= 128) {
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if (color.alpha >= 128)
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{
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uint16_t cell = (pos.x + pos.y*SCREEN_WIDTH) / 8;
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uint16_t cell = (pos.x + pos.y*SCREEN_WIDTH) / 8;
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uint16_t elem = (pos.x + pos.y*SCREEN_WIDTH) % 8;
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uint16_t elem = (pos.x + pos.y*SCREEN_WIDTH) % 8;
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buf[cell] &= ~(1 << elem);
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buf[cell] &= ~(1 << elem);
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@ -243,19 +246,18 @@ void gfx_drawVLine(uint16_t x, uint16_t width, color_t color)
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* @param text: the input text
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* @param text: the input text
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* @param length: the length of the input text, used for boundary checking
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* @param length: the length of the input text, used for boundary checking
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*/
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*/
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static inline uint16_t get_line_size(GFXfont f,
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static inline uint16_t get_line_size(GFXfont f, const char *text, uint16_t length)
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const char *text,
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{
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uint16_t length) {
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uint16_t line_size = 0;
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uint16_t line_size = 0;
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for(unsigned i = 0;
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for(unsigned i = 0; i < length && text[i] != '\n' && text[i] != '\r'; i++)
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i < length && text[i] != '\n' && text[i] != '\r';
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{
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i++) {
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GFXglyph glyph = f.glyph[text[i] - f.first];
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GFXglyph glyph = f.glyph[text[i] - f.first];
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if (line_size + glyph.xAdvance < SCREEN_WIDTH)
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if (line_size + glyph.xAdvance < SCREEN_WIDTH)
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line_size += glyph.xAdvance;
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line_size += glyph.xAdvance;
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else
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else
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break;
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break;
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}
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}
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return line_size;
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return line_size;
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}
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}
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@ -264,9 +266,9 @@ static inline uint16_t get_line_size(GFXfont f,
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* @param alinment: enum representing the text alignment
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* @param alinment: enum representing the text alignment
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* @param line_size: the size of the current text line in pixels
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* @param line_size: the size of the current text line in pixels
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*/
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*/
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static inline uint16_t get_reset_x(textAlign_t alignment,
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static inline uint16_t get_reset_x(textAlign_t alignment, uint16_t line_size,
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uint16_t line_size,
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uint16_t startx)
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uint16_t startx) {
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{
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switch(alignment)
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switch(alignment)
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{
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{
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case TEXT_ALIGN_LEFT:
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case TEXT_ALIGN_LEFT:
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@ -276,10 +278,13 @@ static inline uint16_t get_reset_x(textAlign_t alignment,
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case TEXT_ALIGN_RIGHT:
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case TEXT_ALIGN_RIGHT:
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return SCREEN_WIDTH - line_size - startx;
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return SCREEN_WIDTH - line_size - startx;
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}
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}
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return 0;
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return 0;
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}
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}
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point_t gfx_print(point_t start, const char *text, fontSize_t size, textAlign_t alignment, color_t color) {
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point_t gfx_print(point_t start, const char *text, fontSize_t size,
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textAlign_t alignment, color_t color)
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{
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GFXfont f = fonts[size];
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GFXfont f = fonts[size];
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@ -289,13 +294,14 @@ point_t gfx_print(point_t start, const char *text, fontSize_t size, textAlign_t
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uint16_t line_size = get_line_size(f, text, len);
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uint16_t line_size = get_line_size(f, text, len);
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uint16_t reset_x = get_reset_x(alignment, line_size, start.x);
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uint16_t reset_x = get_reset_x(alignment, line_size, start.x);
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start.x = reset_x;
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start.x = reset_x;
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// Save initial start.y value to calculate vertical size
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// Save initial start.y value to calculate vertical size
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uint16_t saved_start_y = start.y;
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uint16_t saved_start_y = start.y;
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uint16_t line_h = 0;
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uint16_t line_h = 0;
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/* For each char in the string */
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/* For each char in the string */
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for(unsigned i = 0; i < len; i++) {
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for(unsigned i = 0; i < len; i++)
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{
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char c = text[i];
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char c = text[i];
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GFXglyph glyph = f.glyph[c - f.first];
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GFXglyph glyph = f.glyph[c - f.first];
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uint8_t *bitmap = f.bitmap;
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uint8_t *bitmap = f.bitmap;
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@ -308,17 +314,21 @@ point_t gfx_print(point_t start, const char *text, fontSize_t size, textAlign_t
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line_h = h;
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line_h = h;
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// Handle newline and carriage return
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// Handle newline and carriage return
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if (c == '\n') {
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if (c == '\n')
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{
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start.x = reset_x;
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start.x = reset_x;
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start.y += f.yAdvance;
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start.y += f.yAdvance;
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continue;
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continue;
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} else if (c == '\r') {
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}
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else if (c == '\r')
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{
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start.x = reset_x;
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start.x = reset_x;
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continue;
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continue;
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}
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}
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// Handle wrap around
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// Handle wrap around
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if (start.x + glyph.xAdvance > SCREEN_WIDTH) {
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if (start.x + glyph.xAdvance > SCREEN_WIDTH)
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{
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// Compute size of the first row in pixels
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// Compute size of the first row in pixels
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line_size = get_line_size(f, text, len);
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line_size = get_line_size(f, text, len);
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start.x = reset_x = get_reset_x(alignment, line_size, start.x);
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start.x = reset_x = get_reset_x(alignment, line_size, start.x);
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@ -326,12 +336,17 @@ point_t gfx_print(point_t start, const char *text, fontSize_t size, textAlign_t
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}
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}
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// Draw bitmap
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// Draw bitmap
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for (yy = 0; yy < h; yy++) {
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for (yy = 0; yy < h; yy++)
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for (xx = 0; xx < w; xx++) {
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{
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if (!(bit++ & 7)) {
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for (xx = 0; xx < w; xx++)
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{
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if (!(bit++ & 7))
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{
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bits = bitmap[bo++];
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bits = bitmap[bo++];
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}
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}
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if (bits & 0x80) {
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if (bits & 0x80)
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{
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if (start.y + yo + yy < SCREEN_HEIGHT &&
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if (start.y + yo + yy < SCREEN_HEIGHT &&
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start.x + xo + xx < SCREEN_WIDTH &&
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start.x + xo + xx < SCREEN_WIDTH &&
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start.y + yo + yy > 0 &&
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start.y + yo + yy > 0 &&
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@ -342,9 +357,11 @@ point_t gfx_print(point_t start, const char *text, fontSize_t size, textAlign_t
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}
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}
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}
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}
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bits <<= 1;
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bits <<= 1;
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}
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}
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}
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}
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start.x += glyph.xAdvance;
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start.x += glyph.xAdvance;
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}
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}
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// Calculate text size
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// Calculate text size
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@ -355,7 +372,8 @@ point_t gfx_print(point_t start, const char *text, fontSize_t size, textAlign_t
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}
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}
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// Print an error message to the center of the screen, surronded by a red (when possible) box
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// Print an error message to the center of the screen, surronded by a red (when possible) box
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void gfx_printError(const char *text, fontSize_t size) {
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void gfx_printError(const char *text, fontSize_t size)
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{
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// 3 px box padding
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// 3 px box padding
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uint16_t box_padding = 16;
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uint16_t box_padding = 16;
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color_t white = {255, 255, 255, 255};
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color_t white = {255, 255, 255, 255};
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@ -382,8 +400,8 @@ void gfx_printError(const char *text, fontSize_t size) {
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* * ******* * |
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* * ******* * |
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* * ******* ** |
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* * ******* ** |
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* * ******* ** | <-- Height (px)
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* * ******* ** | <-- Height (px)
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* * ******* * |
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* * ******* * |
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* * * |
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* * * |
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* **************** |
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* **************** |
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*
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*
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* __________________
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* __________________
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@ -394,7 +412,9 @@ void gfx_printError(const char *text, fontSize_t size) {
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* Width (px)
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* Width (px)
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*
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*
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*/
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*/
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void gfx_drawBattery(point_t start, uint16_t width, uint16_t height, float percentage) {
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void gfx_drawBattery(point_t start, uint16_t width, uint16_t height,
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float percentage)
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{
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color_t white = {255, 255, 255, 255};
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color_t white = {255, 255, 255, 255};
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color_t black = {0, 0, 0 , 255};
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color_t black = {0, 0, 0 , 255};
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@ -421,7 +441,8 @@ void gfx_drawBattery(point_t start, uint16_t width, uint16_t height, float perce
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// Draw the battery fill
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// Draw the battery fill
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point_t fill_start = {start.x + 2, start.y + 2};
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point_t fill_start = {start.x + 2, start.y + 2};
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gfx_drawRect(fill_start, (int)(((float)(width - 4)) * percentage), height - 4, bat_color, true);
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gfx_drawRect(fill_start, (int)(((float)(width - 4)) * percentage),
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height - 4, bat_color, true);
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// Round corners
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// Round corners
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point_t top_left = start;
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point_t top_left = start;
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@ -459,13 +480,16 @@ void gfx_drawBattery(point_t start, uint16_t width, uint16_t height, float perce
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* Width (px)
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* Width (px)
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*
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*
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*/
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*/
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void gfx_drawSmeter(point_t start, uint16_t width, uint16_t height, float rssi, float squelch, color_t color) {
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void gfx_drawSmeter(point_t start, uint16_t width, uint16_t height, float rssi,
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float squelch, color_t color)
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{
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color_t white = {255, 255, 255, 255};
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color_t white = {255, 255, 255, 255};
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color_t yellow = {250, 180, 19 , 255};
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color_t yellow = {250, 180, 19 , 255};
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color_t red = {255, 0, 0 , 255};
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color_t red = {255, 0, 0 , 255};
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// S-level dots
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// S-level dots
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for(int i = 0; i < 11; i++) {
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for(int i = 0; i < 11; i++)
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{
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color_t color = (i % 3 == 0) ? yellow : white;
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color_t color = (i % 3 == 0) ? yellow : white;
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color = (i > 9) ? red : color;
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color = (i > 9) ? red : color;
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point_t pixel_pos = {i * (width - 1) / 11, start.y};
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point_t pixel_pos = {i * (width - 1) / 11, start.y};
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@ -473,6 +497,7 @@ void gfx_drawSmeter(point_t start, uint16_t width, uint16_t height, float rssi,
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pixel_pos.y += height;
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pixel_pos.y += height;
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gfx_setPixel(pixel_pos, color);
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gfx_setPixel(pixel_pos, color);
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}
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}
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point_t pixel_pos = {width - 1, start.y};
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point_t pixel_pos = {width - 1, start.y};
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gfx_setPixel(pixel_pos, red);
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gfx_setPixel(pixel_pos, red);
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pixel_pos.y += height;
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pixel_pos.y += height;
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@ -67,7 +67,7 @@ void _ui_drawMainTop()
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void _ui_drawZoneChannel()
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void _ui_drawZoneChannel()
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{
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{
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char zone_buf[20] = "";
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char zone_buf[20] = "";
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char channel_buf[20] = "";
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char channel_buf[25] = "";
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if(!last_state.zone_enabled)
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if(!last_state.zone_enabled)
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snprintf(zone_buf, sizeof(zone_buf), "zone: %.13s", "All channels");
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snprintf(zone_buf, sizeof(zone_buf), "zone: %.13s", "All channels");
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else
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else
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@ -83,7 +83,7 @@ void _ui_drawZoneChannel()
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void _ui_drawFrequency()
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void _ui_drawFrequency()
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{
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{
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// Print big numbers frequency
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// Print big numbers frequency
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char freq_buf[10] = "";
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char freq_buf[15] = "";
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snprintf(freq_buf, sizeof(freq_buf), "%03lu.%05lu",
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snprintf(freq_buf, sizeof(freq_buf), "%03lu.%05lu",
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(unsigned long)last_state.channel.rx_frequency/1000000,
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(unsigned long)last_state.channel.rx_frequency/1000000,
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(unsigned long)last_state.channel.rx_frequency%1000000/10);
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(unsigned long)last_state.channel.rx_frequency%1000000/10);
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@ -241,15 +241,21 @@ void nvm_loadHwInfo(hwInfo_t *info)
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int nvm_readChannelData(channel_t *channel, uint16_t pos)
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int nvm_readChannelData(channel_t *channel, uint16_t pos)
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{
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{
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(void) channel;
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(void) pos;
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return -1;
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return -1;
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}
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}
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int nvm_readZoneData(zone_t *zone, uint16_t pos)
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int nvm_readZoneData(zone_t *zone, uint16_t pos)
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{
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{
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(void) zone;
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(void) pos;
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return -1;
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return -1;
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}
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}
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int nvm_readContactData(contact_t *contact, uint16_t pos)
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int nvm_readContactData(contact_t *contact, uint16_t pos)
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{
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{
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(void) contact;
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(void) pos;
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return -1;
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return -1;
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}
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}
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|
Plik diff jest za duży
Load Diff
|
@ -16,8 +16,8 @@
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*
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*
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* http://www.st.com/software_license_agreement_liberty_v2
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* http://www.st.com/software_license_agreement_liberty_v2
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*
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*
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||||||
* Unless required by applicable law or agreed to in writing, software
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* See the License for the specific language governing permissions and
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||||||
* limitations under the License.
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* limitations under the License.
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@ -31,7 +31,7 @@
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* @{
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* @{
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*/
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*/
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/** @defgroup USB_DCD_INT
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/** @defgroup USB_DCD_INT
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* @brief This file contains the interrupt subroutines for the Device mode.
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* @brief This file contains the interrupt subroutines for the Device mode.
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* @{
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* @{
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*/
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*/
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@ -39,40 +39,40 @@
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/** @defgroup USB_DCD_INT_Private_Defines
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/** @defgroup USB_DCD_INT_Private_Defines
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* @{
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* @{
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*/
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*/
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/**
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/**
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* @}
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* @}
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*/
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*/
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/** @defgroup USB_DCD_INT_Private_TypesDefinitions
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/** @defgroup USB_DCD_INT_Private_TypesDefinitions
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* @{
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* @{
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*/
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*/
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/**
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/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
/** @defgroup USB_DCD_INT_Private_Macros
|
/** @defgroup USB_DCD_INT_Private_Macros
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
|
||||||
/** @defgroup USB_DCD_INT_Private_Variables
|
/** @defgroup USB_DCD_INT_Private_Variables
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
|
||||||
/** @defgroup USB_DCD_INT_Private_FunctionPrototypes
|
/** @defgroup USB_DCD_INT_Private_FunctionPrototypes
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
/* static functions */
|
/* static functions */
|
||||||
static uint32_t DCD_ReadDevInEP (USB_OTG_CORE_HANDLE *pdev, uint8_t epnum);
|
static uint32_t DCD_ReadDevInEP (USB_OTG_CORE_HANDLE *pdev, uint8_t epnum);
|
||||||
|
|
||||||
|
@ -98,15 +98,15 @@ static uint32_t DCD_OTG_ISR(USB_OTG_CORE_HANDLE *pdev);
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
|
||||||
/** @defgroup USB_DCD_INT_Private_Functions
|
/** @defgroup USB_DCD_INT_Private_Functions
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
|
||||||
#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED
|
#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED
|
||||||
/**
|
/**
|
||||||
* @brief USBD_OTG_EP1OUT_ISR_Handler
|
* @brief USBD_OTG_EP1OUT_ISR_Handler
|
||||||
* handles all USB Interrupts
|
* handles all USB Interrupts
|
||||||
|
@ -115,13 +115,13 @@ static uint32_t DCD_OTG_ISR(USB_OTG_CORE_HANDLE *pdev);
|
||||||
*/
|
*/
|
||||||
uint32_t USBD_OTG_EP1OUT_ISR_Handler (USB_OTG_CORE_HANDLE *pdev)
|
uint32_t USBD_OTG_EP1OUT_ISR_Handler (USB_OTG_CORE_HANDLE *pdev)
|
||||||
{
|
{
|
||||||
|
|
||||||
USB_OTG_DOEPINTn_TypeDef doepint;
|
USB_OTG_DOEPINTn_TypeDef doepint;
|
||||||
USB_OTG_DEPXFRSIZ_TypeDef deptsiz;
|
USB_OTG_DEPXFRSIZ_TypeDef deptsiz;
|
||||||
|
|
||||||
doepint.d32 = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[1]->DOEPINT);
|
doepint.d32 = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[1]->DOEPINT);
|
||||||
doepint.d32&= USB_OTG_READ_REG32(&pdev->regs.DREGS->DOUTEP1MSK);
|
doepint.d32&= USB_OTG_READ_REG32(&pdev->regs.DREGS->DOUTEP1MSK);
|
||||||
|
|
||||||
/* Transfer complete */
|
/* Transfer complete */
|
||||||
if ( doepint.b.xfercompl )
|
if ( doepint.b.xfercompl )
|
||||||
{
|
{
|
||||||
|
@ -133,13 +133,13 @@ uint32_t USBD_OTG_EP1OUT_ISR_Handler (USB_OTG_CORE_HANDLE *pdev)
|
||||||
/*ToDo : handle more than one single MPS size packet */
|
/*ToDo : handle more than one single MPS size packet */
|
||||||
pdev->dev.out_ep[1].xfer_count = pdev->dev.out_ep[1].maxpacket - \
|
pdev->dev.out_ep[1].xfer_count = pdev->dev.out_ep[1].maxpacket - \
|
||||||
deptsiz.b.xfersize;
|
deptsiz.b.xfersize;
|
||||||
}
|
}
|
||||||
/* Inform upper layer: data ready */
|
/* Inform upper layer: data ready */
|
||||||
/* RX COMPLETE */
|
/* RX COMPLETE */
|
||||||
USBD_DCD_INT_fops->DataOutStage(pdev , 1);
|
USBD_DCD_INT_fops->DataOutStage(pdev , 1);
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Endpoint disable */
|
/* Endpoint disable */
|
||||||
if ( doepint.b.epdisabled )
|
if ( doepint.b.epdisabled )
|
||||||
{
|
{
|
||||||
|
@ -158,15 +158,15 @@ uint32_t USBD_OTG_EP1OUT_ISR_Handler (USB_OTG_CORE_HANDLE *pdev)
|
||||||
*/
|
*/
|
||||||
uint32_t USBD_OTG_EP1IN_ISR_Handler (USB_OTG_CORE_HANDLE *pdev)
|
uint32_t USBD_OTG_EP1IN_ISR_Handler (USB_OTG_CORE_HANDLE *pdev)
|
||||||
{
|
{
|
||||||
|
|
||||||
USB_OTG_DIEPINTn_TypeDef diepint;
|
USB_OTG_DIEPINTn_TypeDef diepint;
|
||||||
uint32_t fifoemptymsk, msk, emp;
|
uint32_t fifoemptymsk, msk, emp;
|
||||||
|
|
||||||
msk = USB_OTG_READ_REG32(&pdev->regs.DREGS->DINEP1MSK);
|
msk = USB_OTG_READ_REG32(&pdev->regs.DREGS->DINEP1MSK);
|
||||||
emp = USB_OTG_READ_REG32(&pdev->regs.DREGS->DIEPEMPMSK);
|
emp = USB_OTG_READ_REG32(&pdev->regs.DREGS->DIEPEMPMSK);
|
||||||
msk |= ((emp >> 1 ) & 0x1) << 7;
|
msk |= ((emp >> 1 ) & 0x1) << 7;
|
||||||
diepint.d32 = USB_OTG_READ_REG32(&pdev->regs.INEP_REGS[1]->DIEPINT) & msk;
|
diepint.d32 = USB_OTG_READ_REG32(&pdev->regs.INEP_REGS[1]->DIEPINT) & msk;
|
||||||
|
|
||||||
if ( diepint.b.xfercompl )
|
if ( diepint.b.xfercompl )
|
||||||
{
|
{
|
||||||
fifoemptymsk = 0x1 << 1;
|
fifoemptymsk = 0x1 << 1;
|
||||||
|
@ -178,7 +178,7 @@ uint32_t USBD_OTG_EP1IN_ISR_Handler (USB_OTG_CORE_HANDLE *pdev)
|
||||||
if ( diepint.b.epdisabled )
|
if ( diepint.b.epdisabled )
|
||||||
{
|
{
|
||||||
CLEAR_IN_EP_INTR(1, epdisabled);
|
CLEAR_IN_EP_INTR(1, epdisabled);
|
||||||
}
|
}
|
||||||
if ( diepint.b.timeout )
|
if ( diepint.b.timeout )
|
||||||
{
|
{
|
||||||
CLEAR_IN_EP_INTR(1, timeout);
|
CLEAR_IN_EP_INTR(1, timeout);
|
||||||
|
@ -210,7 +210,7 @@ uint32_t USBD_OTG_ISR_Handler (USB_OTG_CORE_HANDLE *pdev)
|
||||||
{
|
{
|
||||||
USB_OTG_GINTSTS_TypeDef gintr_status;
|
USB_OTG_GINTSTS_TypeDef gintr_status;
|
||||||
uint32_t retval = 0;
|
uint32_t retval = 0;
|
||||||
|
|
||||||
if (USB_OTG_IsDeviceMode(pdev)) /* ensure that we are in device mode */
|
if (USB_OTG_IsDeviceMode(pdev)) /* ensure that we are in device mode */
|
||||||
{
|
{
|
||||||
gintr_status.d32 = USB_OTG_ReadCoreItr(pdev);
|
gintr_status.d32 = USB_OTG_ReadCoreItr(pdev);
|
||||||
|
@ -218,32 +218,32 @@ uint32_t USBD_OTG_ISR_Handler (USB_OTG_CORE_HANDLE *pdev)
|
||||||
{
|
{
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
if (gintr_status.b.outepintr)
|
if (gintr_status.b.outepintr)
|
||||||
{
|
{
|
||||||
retval |= DCD_HandleOutEP_ISR(pdev);
|
retval |= DCD_HandleOutEP_ISR(pdev);
|
||||||
}
|
}
|
||||||
|
|
||||||
if (gintr_status.b.inepint)
|
if (gintr_status.b.inepint)
|
||||||
{
|
{
|
||||||
retval |= DCD_HandleInEP_ISR(pdev);
|
retval |= DCD_HandleInEP_ISR(pdev);
|
||||||
}
|
}
|
||||||
|
|
||||||
if (gintr_status.b.modemismatch)
|
if (gintr_status.b.modemismatch)
|
||||||
{
|
{
|
||||||
USB_OTG_GINTSTS_TypeDef gintsts;
|
USB_OTG_GINTSTS_TypeDef gintsts;
|
||||||
|
|
||||||
/* Clear interrupt */
|
/* Clear interrupt */
|
||||||
gintsts.d32 = 0;
|
gintsts.d32 = 0;
|
||||||
gintsts.b.modemismatch = 1;
|
gintsts.b.modemismatch = 1;
|
||||||
USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32);
|
USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32);
|
||||||
}
|
}
|
||||||
|
|
||||||
if (gintr_status.b.wkupintr)
|
if (gintr_status.b.wkupintr)
|
||||||
{
|
{
|
||||||
retval |= DCD_HandleResume_ISR(pdev);
|
retval |= DCD_HandleResume_ISR(pdev);
|
||||||
}
|
}
|
||||||
|
|
||||||
if (gintr_status.b.usbsuspend)
|
if (gintr_status.b.usbsuspend)
|
||||||
{
|
{
|
||||||
retval |= DCD_HandleUSBSuspend_ISR(pdev);
|
retval |= DCD_HandleUSBSuspend_ISR(pdev);
|
||||||
|
@ -251,25 +251,25 @@ uint32_t USBD_OTG_ISR_Handler (USB_OTG_CORE_HANDLE *pdev)
|
||||||
if (gintr_status.b.sofintr)
|
if (gintr_status.b.sofintr)
|
||||||
{
|
{
|
||||||
retval |= DCD_HandleSof_ISR(pdev);
|
retval |= DCD_HandleSof_ISR(pdev);
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
if (gintr_status.b.rxstsqlvl)
|
if (gintr_status.b.rxstsqlvl)
|
||||||
{
|
{
|
||||||
retval |= DCD_HandleRxStatusQueueLevel_ISR(pdev);
|
retval |= DCD_HandleRxStatusQueueLevel_ISR(pdev);
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
if (gintr_status.b.usbreset)
|
if (gintr_status.b.usbreset)
|
||||||
{
|
{
|
||||||
retval |= DCD_HandleUsbReset_ISR(pdev);
|
retval |= DCD_HandleUsbReset_ISR(pdev);
|
||||||
|
|
||||||
}
|
}
|
||||||
if (gintr_status.b.enumdone)
|
if (gintr_status.b.enumdone)
|
||||||
{
|
{
|
||||||
retval |= DCD_HandleEnumDone_ISR(pdev);
|
retval |= DCD_HandleEnumDone_ISR(pdev);
|
||||||
}
|
}
|
||||||
|
|
||||||
if (gintr_status.b.incomplisoin)
|
if (gintr_status.b.incomplisoin)
|
||||||
{
|
{
|
||||||
retval |= DCD_IsoINIncomplete_ISR(pdev);
|
retval |= DCD_IsoINIncomplete_ISR(pdev);
|
||||||
|
@ -278,7 +278,7 @@ uint32_t USBD_OTG_ISR_Handler (USB_OTG_CORE_HANDLE *pdev)
|
||||||
if (gintr_status.b.incomplisoout)
|
if (gintr_status.b.incomplisoout)
|
||||||
{
|
{
|
||||||
retval |= DCD_IsoOUTIncomplete_ISR(pdev);
|
retval |= DCD_IsoOUTIncomplete_ISR(pdev);
|
||||||
}
|
}
|
||||||
#ifdef VBUS_SENSING_ENABLED
|
#ifdef VBUS_SENSING_ENABLED
|
||||||
if (gintr_status.b.sessreqintr)
|
if (gintr_status.b.sessreqintr)
|
||||||
{
|
{
|
||||||
|
@ -288,8 +288,8 @@ uint32_t USBD_OTG_ISR_Handler (USB_OTG_CORE_HANDLE *pdev)
|
||||||
if (gintr_status.b.otgintr)
|
if (gintr_status.b.otgintr)
|
||||||
{
|
{
|
||||||
retval |= DCD_OTG_ISR(pdev);
|
retval |= DCD_OTG_ISR(pdev);
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
return retval;
|
return retval;
|
||||||
}
|
}
|
||||||
|
@ -303,13 +303,13 @@ uint32_t USBD_OTG_ISR_Handler (USB_OTG_CORE_HANDLE *pdev)
|
||||||
*/
|
*/
|
||||||
static uint32_t DCD_SessionRequest_ISR(USB_OTG_CORE_HANDLE *pdev)
|
static uint32_t DCD_SessionRequest_ISR(USB_OTG_CORE_HANDLE *pdev)
|
||||||
{
|
{
|
||||||
USB_OTG_GINTSTS_TypeDef gintsts;
|
USB_OTG_GINTSTS_TypeDef gintsts;
|
||||||
USBD_DCD_INT_fops->DevConnected (pdev);
|
USBD_DCD_INT_fops->DevConnected (pdev);
|
||||||
|
|
||||||
/* Clear interrupt */
|
/* Clear interrupt */
|
||||||
gintsts.d32 = 0;
|
gintsts.d32 = 0;
|
||||||
gintsts.b.sessreqintr = 1;
|
gintsts.b.sessreqintr = 1;
|
||||||
USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GINTSTS, gintsts.d32);
|
USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GINTSTS, gintsts.d32);
|
||||||
return 1;
|
return 1;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -326,13 +326,13 @@ static uint32_t DCD_OTG_ISR(USB_OTG_CORE_HANDLE *pdev)
|
||||||
USB_OTG_GOTGINT_TypeDef gotgint;
|
USB_OTG_GOTGINT_TypeDef gotgint;
|
||||||
|
|
||||||
gotgint.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GOTGINT);
|
gotgint.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GOTGINT);
|
||||||
|
|
||||||
if (gotgint.b.sesenddet)
|
if (gotgint.b.sesenddet)
|
||||||
{
|
{
|
||||||
USBD_DCD_INT_fops->DevDisconnected (pdev);
|
USBD_DCD_INT_fops->DevDisconnected (pdev);
|
||||||
}
|
}
|
||||||
/* Clear OTG interrupt */
|
/* Clear OTG interrupt */
|
||||||
USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GOTGINT, gotgint.d32);
|
USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GOTGINT, gotgint.d32);
|
||||||
return 1;
|
return 1;
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
@ -348,24 +348,26 @@ static uint32_t DCD_HandleResume_ISR(USB_OTG_CORE_HANDLE *pdev)
|
||||||
USB_OTG_GINTSTS_TypeDef gintsts;
|
USB_OTG_GINTSTS_TypeDef gintsts;
|
||||||
USB_OTG_DCTL_TypeDef devctl;
|
USB_OTG_DCTL_TypeDef devctl;
|
||||||
USB_OTG_PCGCCTL_TypeDef power;
|
USB_OTG_PCGCCTL_TypeDef power;
|
||||||
|
|
||||||
if(pdev->cfg.low_power)
|
if(pdev->cfg.low_power)
|
||||||
{
|
{
|
||||||
/* un-gate USB Core clock */
|
/* un-gate USB Core clock */
|
||||||
|
#pragma GCC diagnostic ignored "-Wstrict-aliasing"
|
||||||
power.d32 = USB_OTG_READ_REG32(&pdev->regs.PCGCCTL);
|
power.d32 = USB_OTG_READ_REG32(&pdev->regs.PCGCCTL);
|
||||||
power.b.gatehclk = 0;
|
power.b.gatehclk = 0;
|
||||||
power.b.stoppclk = 0;
|
power.b.stoppclk = 0;
|
||||||
USB_OTG_WRITE_REG32(pdev->regs.PCGCCTL, power.d32);
|
USB_OTG_WRITE_REG32(pdev->regs.PCGCCTL, power.d32);
|
||||||
|
#pragma GCC diagnostic pop
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Clear the Remote Wake-up Signaling */
|
/* Clear the Remote Wake-up Signaling */
|
||||||
devctl.d32 = 0;
|
devctl.d32 = 0;
|
||||||
devctl.b.rmtwkupsig = 1;
|
devctl.b.rmtwkupsig = 1;
|
||||||
USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DCTL, devctl.d32, 0);
|
USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DCTL, devctl.d32, 0);
|
||||||
|
|
||||||
/* Inform upper layer by the Resume Event */
|
/* Inform upper layer by the Resume Event */
|
||||||
USBD_DCD_INT_fops->Resume (pdev);
|
USBD_DCD_INT_fops->Resume (pdev);
|
||||||
|
|
||||||
/* Clear interrupt */
|
/* Clear interrupt */
|
||||||
gintsts.d32 = 0;
|
gintsts.d32 = 0;
|
||||||
gintsts.b.wkupintr = 1;
|
gintsts.b.wkupintr = 1;
|
||||||
|
@ -385,29 +387,29 @@ static uint32_t DCD_HandleUSBSuspend_ISR(USB_OTG_CORE_HANDLE *pdev)
|
||||||
USB_OTG_PCGCCTL_TypeDef power;
|
USB_OTG_PCGCCTL_TypeDef power;
|
||||||
USB_OTG_DSTS_TypeDef dsts;
|
USB_OTG_DSTS_TypeDef dsts;
|
||||||
__IO uint8_t prev_status = 0;
|
__IO uint8_t prev_status = 0;
|
||||||
|
|
||||||
prev_status = pdev->dev.device_status;
|
prev_status = pdev->dev.device_status;
|
||||||
USBD_DCD_INT_fops->Suspend (pdev);
|
USBD_DCD_INT_fops->Suspend (pdev);
|
||||||
|
|
||||||
dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS);
|
dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS);
|
||||||
|
|
||||||
/* Clear interrupt */
|
/* Clear interrupt */
|
||||||
gintsts.d32 = 0;
|
gintsts.d32 = 0;
|
||||||
gintsts.b.usbsuspend = 1;
|
gintsts.b.usbsuspend = 1;
|
||||||
USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32);
|
USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32);
|
||||||
|
|
||||||
if((pdev->cfg.low_power) && (dsts.b.suspsts == 1) &&
|
if((pdev->cfg.low_power) && (dsts.b.suspsts == 1) &&
|
||||||
(pdev->dev.connection_status == 1) &&
|
(pdev->dev.connection_status == 1) &&
|
||||||
(prev_status == USB_OTG_CONFIGURED))
|
(prev_status == USB_OTG_CONFIGURED))
|
||||||
{
|
{
|
||||||
/* switch-off the clocks */
|
/* switch-off the clocks */
|
||||||
power.d32 = 0;
|
power.d32 = 0;
|
||||||
power.b.stoppclk = 1;
|
power.b.stoppclk = 1;
|
||||||
USB_OTG_MODIFY_REG32(pdev->regs.PCGCCTL, 0, power.d32);
|
USB_OTG_MODIFY_REG32(pdev->regs.PCGCCTL, 0, power.d32);
|
||||||
|
|
||||||
power.b.gatehclk = 1;
|
power.b.gatehclk = 1;
|
||||||
USB_OTG_MODIFY_REG32(pdev->regs.PCGCCTL, 0, power.d32);
|
USB_OTG_MODIFY_REG32(pdev->regs.PCGCCTL, 0, power.d32);
|
||||||
|
|
||||||
/* Request to enter Sleep mode after exit from current ISR */
|
/* Request to enter Sleep mode after exit from current ISR */
|
||||||
SCB->SCR |= (SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk);
|
SCB->SCR |= (SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk);
|
||||||
}
|
}
|
||||||
|
@ -423,13 +425,13 @@ static uint32_t DCD_HandleUSBSuspend_ISR(USB_OTG_CORE_HANDLE *pdev)
|
||||||
static uint32_t DCD_HandleInEP_ISR(USB_OTG_CORE_HANDLE *pdev)
|
static uint32_t DCD_HandleInEP_ISR(USB_OTG_CORE_HANDLE *pdev)
|
||||||
{
|
{
|
||||||
USB_OTG_DIEPINTn_TypeDef diepint;
|
USB_OTG_DIEPINTn_TypeDef diepint;
|
||||||
|
|
||||||
uint32_t ep_intr;
|
uint32_t ep_intr;
|
||||||
uint32_t epnum = 0;
|
uint32_t epnum = 0;
|
||||||
uint32_t fifoemptymsk;
|
uint32_t fifoemptymsk;
|
||||||
diepint.d32 = 0;
|
diepint.d32 = 0;
|
||||||
ep_intr = USB_OTG_ReadDevAllInEPItr(pdev);
|
ep_intr = USB_OTG_ReadDevAllInEPItr(pdev);
|
||||||
|
|
||||||
while ( ep_intr )
|
while ( ep_intr )
|
||||||
{
|
{
|
||||||
if (ep_intr&0x1) /* In ITR */
|
if (ep_intr&0x1) /* In ITR */
|
||||||
|
@ -442,7 +444,7 @@ static uint32_t DCD_HandleInEP_ISR(USB_OTG_CORE_HANDLE *pdev)
|
||||||
CLEAR_IN_EP_INTR(epnum, xfercompl);
|
CLEAR_IN_EP_INTR(epnum, xfercompl);
|
||||||
/* TX COMPLETE */
|
/* TX COMPLETE */
|
||||||
USBD_DCD_INT_fops->DataInStage(pdev , epnum);
|
USBD_DCD_INT_fops->DataInStage(pdev , epnum);
|
||||||
|
|
||||||
if (pdev->cfg.dma_enable == 1)
|
if (pdev->cfg.dma_enable == 1)
|
||||||
{
|
{
|
||||||
if((epnum == 0) && (pdev->dev.device_state == USB_OTG_EP0_STATUS_IN))
|
if((epnum == 0) && (pdev->dev.device_state == USB_OTG_EP0_STATUS_IN))
|
||||||
|
@ -450,7 +452,7 @@ static uint32_t DCD_HandleInEP_ISR(USB_OTG_CORE_HANDLE *pdev)
|
||||||
/* prepare to rx more setup packets */
|
/* prepare to rx more setup packets */
|
||||||
USB_OTG_EP0_OutStart(pdev);
|
USB_OTG_EP0_OutStart(pdev);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
if ( diepint.b.timeout )
|
if ( diepint.b.timeout )
|
||||||
{
|
{
|
||||||
|
@ -467,19 +469,19 @@ static uint32_t DCD_HandleInEP_ISR(USB_OTG_CORE_HANDLE *pdev)
|
||||||
if ( diepint.b.epdisabled )
|
if ( diepint.b.epdisabled )
|
||||||
{
|
{
|
||||||
CLEAR_IN_EP_INTR(epnum, epdisabled);
|
CLEAR_IN_EP_INTR(epnum, epdisabled);
|
||||||
}
|
}
|
||||||
if (diepint.b.emptyintr)
|
if (diepint.b.emptyintr)
|
||||||
{
|
{
|
||||||
|
|
||||||
DCD_WriteEmptyTxFifo(pdev , epnum);
|
DCD_WriteEmptyTxFifo(pdev , epnum);
|
||||||
|
|
||||||
CLEAR_IN_EP_INTR(epnum, emptyintr);
|
CLEAR_IN_EP_INTR(epnum, emptyintr);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
epnum++;
|
epnum++;
|
||||||
ep_intr >>= 1;
|
ep_intr >>= 1;
|
||||||
}
|
}
|
||||||
|
|
||||||
return 1;
|
return 1;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -495,19 +497,19 @@ static uint32_t DCD_HandleOutEP_ISR(USB_OTG_CORE_HANDLE *pdev)
|
||||||
USB_OTG_DOEPINTn_TypeDef doepint;
|
USB_OTG_DOEPINTn_TypeDef doepint;
|
||||||
USB_OTG_DEPXFRSIZ_TypeDef deptsiz;
|
USB_OTG_DEPXFRSIZ_TypeDef deptsiz;
|
||||||
uint32_t epnum = 0;
|
uint32_t epnum = 0;
|
||||||
|
|
||||||
doepint.d32 = 0;
|
doepint.d32 = 0;
|
||||||
|
|
||||||
/* Read in the device interrupt bits */
|
/* Read in the device interrupt bits */
|
||||||
ep_intr = USB_OTG_ReadDevAllOutEp_itr(pdev);
|
ep_intr = USB_OTG_ReadDevAllOutEp_itr(pdev);
|
||||||
|
|
||||||
while ( ep_intr )
|
while ( ep_intr )
|
||||||
{
|
{
|
||||||
if (ep_intr&0x1)
|
if (ep_intr&0x1)
|
||||||
{
|
{
|
||||||
|
|
||||||
doepint.d32 = USB_OTG_ReadDevOutEP_itr(pdev, epnum);
|
doepint.d32 = USB_OTG_ReadDevOutEP_itr(pdev, epnum);
|
||||||
|
|
||||||
/* Transfer complete */
|
/* Transfer complete */
|
||||||
if ( doepint.b.xfercompl )
|
if ( doepint.b.xfercompl )
|
||||||
{
|
{
|
||||||
|
@ -523,7 +525,7 @@ static uint32_t DCD_HandleOutEP_ISR(USB_OTG_CORE_HANDLE *pdev)
|
||||||
/* Inform upper layer: data ready */
|
/* Inform upper layer: data ready */
|
||||||
/* RX COMPLETE */
|
/* RX COMPLETE */
|
||||||
USBD_DCD_INT_fops->DataOutStage(pdev , epnum);
|
USBD_DCD_INT_fops->DataOutStage(pdev , epnum);
|
||||||
|
|
||||||
if (pdev->cfg.dma_enable == 1)
|
if (pdev->cfg.dma_enable == 1)
|
||||||
{
|
{
|
||||||
if((epnum == 0) && (pdev->dev.device_state == USB_OTG_EP0_STATUS_OUT))
|
if((epnum == 0) && (pdev->dev.device_state == USB_OTG_EP0_STATUS_OUT))
|
||||||
|
@ -531,7 +533,7 @@ static uint32_t DCD_HandleOutEP_ISR(USB_OTG_CORE_HANDLE *pdev)
|
||||||
/* prepare to rx more setup packets */
|
/* prepare to rx more setup packets */
|
||||||
USB_OTG_EP0_OutStart(pdev);
|
USB_OTG_EP0_OutStart(pdev);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
/* Endpoint disable */
|
/* Endpoint disable */
|
||||||
if ( doepint.b.epdisabled )
|
if ( doepint.b.epdisabled )
|
||||||
|
@ -542,7 +544,7 @@ static uint32_t DCD_HandleOutEP_ISR(USB_OTG_CORE_HANDLE *pdev)
|
||||||
/* Setup Phase Done (control EPs) */
|
/* Setup Phase Done (control EPs) */
|
||||||
if ( doepint.b.setup )
|
if ( doepint.b.setup )
|
||||||
{
|
{
|
||||||
|
|
||||||
/* inform the upper layer that a setup packet is available */
|
/* inform the upper layer that a setup packet is available */
|
||||||
/* SETUP COMPLETE */
|
/* SETUP COMPLETE */
|
||||||
USBD_DCD_INT_fops->SetupStage(pdev);
|
USBD_DCD_INT_fops->SetupStage(pdev);
|
||||||
|
@ -564,15 +566,15 @@ static uint32_t DCD_HandleOutEP_ISR(USB_OTG_CORE_HANDLE *pdev)
|
||||||
static uint32_t DCD_HandleSof_ISR(USB_OTG_CORE_HANDLE *pdev)
|
static uint32_t DCD_HandleSof_ISR(USB_OTG_CORE_HANDLE *pdev)
|
||||||
{
|
{
|
||||||
USB_OTG_GINTSTS_TypeDef GINTSTS;
|
USB_OTG_GINTSTS_TypeDef GINTSTS;
|
||||||
|
|
||||||
|
|
||||||
USBD_DCD_INT_fops->SOF(pdev);
|
USBD_DCD_INT_fops->SOF(pdev);
|
||||||
|
|
||||||
/* Clear interrupt */
|
/* Clear interrupt */
|
||||||
GINTSTS.d32 = 0;
|
GINTSTS.d32 = 0;
|
||||||
GINTSTS.b.sofintr = 1;
|
GINTSTS.b.sofintr = 1;
|
||||||
USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GINTSTS, GINTSTS.d32);
|
USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GINTSTS, GINTSTS.d32);
|
||||||
|
|
||||||
return 1;
|
return 1;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -587,17 +589,17 @@ static uint32_t DCD_HandleRxStatusQueueLevel_ISR(USB_OTG_CORE_HANDLE *pdev)
|
||||||
USB_OTG_GINTMSK_TypeDef int_mask;
|
USB_OTG_GINTMSK_TypeDef int_mask;
|
||||||
USB_OTG_DRXSTS_TypeDef status;
|
USB_OTG_DRXSTS_TypeDef status;
|
||||||
USB_OTG_EP *ep;
|
USB_OTG_EP *ep;
|
||||||
|
|
||||||
/* Disable the Rx Status Queue Level interrupt */
|
/* Disable the Rx Status Queue Level interrupt */
|
||||||
int_mask.d32 = 0;
|
int_mask.d32 = 0;
|
||||||
int_mask.b.rxstsqlvl = 1;
|
int_mask.b.rxstsqlvl = 1;
|
||||||
USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, int_mask.d32, 0);
|
USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, int_mask.d32, 0);
|
||||||
|
|
||||||
/* Get the Status from the top of the FIFO */
|
/* Get the Status from the top of the FIFO */
|
||||||
status.d32 = USB_OTG_READ_REG32( &pdev->regs.GREGS->GRXSTSP );
|
status.d32 = USB_OTG_READ_REG32( &pdev->regs.GREGS->GRXSTSP );
|
||||||
|
|
||||||
ep = &pdev->dev.out_ep[status.b.epnum];
|
ep = &pdev->dev.out_ep[status.b.epnum];
|
||||||
|
|
||||||
switch (status.b.pktsts)
|
switch (status.b.pktsts)
|
||||||
{
|
{
|
||||||
case STS_GOUT_NAK:
|
case STS_GOUT_NAK:
|
||||||
|
@ -622,10 +624,10 @@ static uint32_t DCD_HandleRxStatusQueueLevel_ISR(USB_OTG_CORE_HANDLE *pdev)
|
||||||
default:
|
default:
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Enable the Rx Status Queue Level interrupt */
|
/* Enable the Rx Status Queue Level interrupt */
|
||||||
USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, 0, int_mask.d32);
|
USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, 0, int_mask.d32);
|
||||||
|
|
||||||
return 1;
|
return 1;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -642,42 +644,42 @@ static uint32_t DCD_WriteEmptyTxFifo(USB_OTG_CORE_HANDLE *pdev, uint32_t epnum)
|
||||||
uint32_t len = 0;
|
uint32_t len = 0;
|
||||||
uint32_t len32b;
|
uint32_t len32b;
|
||||||
txstatus.d32 = 0;
|
txstatus.d32 = 0;
|
||||||
|
|
||||||
ep = &pdev->dev.in_ep[epnum];
|
ep = &pdev->dev.in_ep[epnum];
|
||||||
|
|
||||||
len = ep->xfer_len - ep->xfer_count;
|
len = ep->xfer_len - ep->xfer_count;
|
||||||
|
|
||||||
if (len > ep->maxpacket)
|
if (len > ep->maxpacket)
|
||||||
{
|
{
|
||||||
len = ep->maxpacket;
|
len = ep->maxpacket;
|
||||||
}
|
}
|
||||||
|
|
||||||
len32b = (len + 3) / 4;
|
len32b = (len + 3) / 4;
|
||||||
txstatus.d32 = USB_OTG_READ_REG32( &pdev->regs.INEP_REGS[epnum]->DTXFSTS);
|
txstatus.d32 = USB_OTG_READ_REG32( &pdev->regs.INEP_REGS[epnum]->DTXFSTS);
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
while (txstatus.b.txfspcavail > len32b &&
|
while (txstatus.b.txfspcavail > len32b &&
|
||||||
ep->xfer_count < ep->xfer_len &&
|
ep->xfer_count < ep->xfer_len &&
|
||||||
ep->xfer_len != 0)
|
ep->xfer_len != 0)
|
||||||
{
|
{
|
||||||
/* Write the FIFO */
|
/* Write the FIFO */
|
||||||
len = ep->xfer_len - ep->xfer_count;
|
len = ep->xfer_len - ep->xfer_count;
|
||||||
|
|
||||||
if (len > ep->maxpacket)
|
if (len > ep->maxpacket)
|
||||||
{
|
{
|
||||||
len = ep->maxpacket;
|
len = ep->maxpacket;
|
||||||
}
|
}
|
||||||
len32b = (len + 3) / 4;
|
len32b = (len + 3) / 4;
|
||||||
|
|
||||||
USB_OTG_WritePacket (pdev , ep->xfer_buff, epnum, len);
|
USB_OTG_WritePacket (pdev , ep->xfer_buff, epnum, len);
|
||||||
|
|
||||||
ep->xfer_buff += len;
|
ep->xfer_buff += len;
|
||||||
ep->xfer_count += len;
|
ep->xfer_count += len;
|
||||||
|
|
||||||
txstatus.d32 = USB_OTG_READ_REG32(&pdev->regs.INEP_REGS[epnum]->DTXFSTS);
|
txstatus.d32 = USB_OTG_READ_REG32(&pdev->regs.INEP_REGS[epnum]->DTXFSTS);
|
||||||
}
|
}
|
||||||
|
|
||||||
return 1;
|
return 1;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -696,37 +698,37 @@ static uint32_t DCD_HandleUsbReset_ISR(USB_OTG_CORE_HANDLE *pdev)
|
||||||
USB_OTG_DCTL_TypeDef dctl;
|
USB_OTG_DCTL_TypeDef dctl;
|
||||||
USB_OTG_GINTSTS_TypeDef gintsts;
|
USB_OTG_GINTSTS_TypeDef gintsts;
|
||||||
uint32_t i;
|
uint32_t i;
|
||||||
|
|
||||||
dctl.d32 = 0;
|
dctl.d32 = 0;
|
||||||
daintmsk.d32 = 0;
|
daintmsk.d32 = 0;
|
||||||
doepmsk.d32 = 0;
|
doepmsk.d32 = 0;
|
||||||
diepmsk.d32 = 0;
|
diepmsk.d32 = 0;
|
||||||
dcfg.d32 = 0;
|
dcfg.d32 = 0;
|
||||||
gintsts.d32 = 0;
|
gintsts.d32 = 0;
|
||||||
|
|
||||||
/* Clear the Remote Wake-up Signaling */
|
/* Clear the Remote Wake-up Signaling */
|
||||||
dctl.b.rmtwkupsig = 1;
|
dctl.b.rmtwkupsig = 1;
|
||||||
USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DCTL, dctl.d32, 0 );
|
USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DCTL, dctl.d32, 0 );
|
||||||
|
|
||||||
/* Flush the Tx FIFO */
|
/* Flush the Tx FIFO */
|
||||||
USB_OTG_FlushTxFifo(pdev , 0 );
|
USB_OTG_FlushTxFifo(pdev , 0 );
|
||||||
|
|
||||||
for (i = 0; i < pdev->cfg.dev_endpoints ; i++)
|
for (i = 0; i < pdev->cfg.dev_endpoints ; i++)
|
||||||
{
|
{
|
||||||
USB_OTG_WRITE_REG32( &pdev->regs.INEP_REGS[i]->DIEPINT, 0xFF);
|
USB_OTG_WRITE_REG32( &pdev->regs.INEP_REGS[i]->DIEPINT, 0xFF);
|
||||||
USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[i]->DOEPINT, 0xFF);
|
USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[i]->DOEPINT, 0xFF);
|
||||||
}
|
}
|
||||||
USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINT, 0xFFFFFFFF );
|
USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINT, 0xFFFFFFFF );
|
||||||
|
|
||||||
daintmsk.ep.in = 1;
|
daintmsk.ep.in = 1;
|
||||||
daintmsk.ep.out = 1;
|
daintmsk.ep.out = 1;
|
||||||
USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINTMSK, daintmsk.d32 );
|
USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINTMSK, daintmsk.d32 );
|
||||||
|
|
||||||
doepmsk.b.setup = 1;
|
doepmsk.b.setup = 1;
|
||||||
doepmsk.b.xfercompl = 1;
|
doepmsk.b.xfercompl = 1;
|
||||||
doepmsk.b.epdisabled = 1;
|
doepmsk.b.epdisabled = 1;
|
||||||
USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DOEPMSK, doepmsk.d32 );
|
USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DOEPMSK, doepmsk.d32 );
|
||||||
#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED
|
#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED
|
||||||
USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DOUTEP1MSK, doepmsk.d32 );
|
USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DOUTEP1MSK, doepmsk.d32 );
|
||||||
#endif
|
#endif
|
||||||
diepmsk.b.xfercompl = 1;
|
diepmsk.b.xfercompl = 1;
|
||||||
|
@ -734,23 +736,23 @@ static uint32_t DCD_HandleUsbReset_ISR(USB_OTG_CORE_HANDLE *pdev)
|
||||||
diepmsk.b.epdisabled = 1;
|
diepmsk.b.epdisabled = 1;
|
||||||
|
|
||||||
USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DIEPMSK, diepmsk.d32 );
|
USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DIEPMSK, diepmsk.d32 );
|
||||||
#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED
|
#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED
|
||||||
USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DINEP1MSK, diepmsk.d32 );
|
USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DINEP1MSK, diepmsk.d32 );
|
||||||
#endif
|
#endif
|
||||||
/* Reset Device Address */
|
/* Reset Device Address */
|
||||||
dcfg.d32 = USB_OTG_READ_REG32( &pdev->regs.DREGS->DCFG);
|
dcfg.d32 = USB_OTG_READ_REG32( &pdev->regs.DREGS->DCFG);
|
||||||
dcfg.b.devaddr = 0;
|
dcfg.b.devaddr = 0;
|
||||||
USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DCFG, dcfg.d32);
|
USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DCFG, dcfg.d32);
|
||||||
|
|
||||||
|
|
||||||
/* setup EP0 to receive SETUP packets */
|
/* setup EP0 to receive SETUP packets */
|
||||||
USB_OTG_EP0_OutStart(pdev);
|
USB_OTG_EP0_OutStart(pdev);
|
||||||
|
|
||||||
/* Clear interrupt */
|
/* Clear interrupt */
|
||||||
gintsts.d32 = 0;
|
gintsts.d32 = 0;
|
||||||
gintsts.b.usbreset = 1;
|
gintsts.b.usbreset = 1;
|
||||||
USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GINTSTS, gintsts.d32);
|
USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GINTSTS, gintsts.d32);
|
||||||
|
|
||||||
/*Reset internal state machine */
|
/*Reset internal state machine */
|
||||||
USBD_DCD_INT_fops->Reset(pdev);
|
USBD_DCD_INT_fops->Reset(pdev);
|
||||||
return 1;
|
return 1;
|
||||||
|
@ -766,28 +768,28 @@ static uint32_t DCD_HandleEnumDone_ISR(USB_OTG_CORE_HANDLE *pdev)
|
||||||
{
|
{
|
||||||
USB_OTG_GINTSTS_TypeDef gintsts;
|
USB_OTG_GINTSTS_TypeDef gintsts;
|
||||||
USB_OTG_GUSBCFG_TypeDef gusbcfg;
|
USB_OTG_GUSBCFG_TypeDef gusbcfg;
|
||||||
|
|
||||||
USB_OTG_EP0Activate(pdev);
|
USB_OTG_EP0Activate(pdev);
|
||||||
|
|
||||||
/* Set USB turn-around time based on device speed and PHY interface. */
|
/* Set USB turn-around time based on device speed and PHY interface. */
|
||||||
gusbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG);
|
gusbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG);
|
||||||
|
|
||||||
/* Full or High speed */
|
/* Full or High speed */
|
||||||
if ( USB_OTG_GetDeviceSpeed(pdev) == USB_SPEED_HIGH)
|
if ( USB_OTG_GetDeviceSpeed(pdev) == USB_SPEED_HIGH)
|
||||||
{
|
{
|
||||||
pdev->cfg.speed = USB_OTG_SPEED_HIGH;
|
pdev->cfg.speed = USB_OTG_SPEED_HIGH;
|
||||||
pdev->cfg.mps = USB_OTG_HS_MAX_PACKET_SIZE ;
|
pdev->cfg.mps = USB_OTG_HS_MAX_PACKET_SIZE ;
|
||||||
gusbcfg.b.usbtrdtim = 9;
|
gusbcfg.b.usbtrdtim = 9;
|
||||||
}
|
}
|
||||||
else
|
else
|
||||||
{
|
{
|
||||||
pdev->cfg.speed = USB_OTG_SPEED_FULL;
|
pdev->cfg.speed = USB_OTG_SPEED_FULL;
|
||||||
pdev->cfg.mps = USB_OTG_FS_MAX_PACKET_SIZE ;
|
pdev->cfg.mps = USB_OTG_FS_MAX_PACKET_SIZE ;
|
||||||
gusbcfg.b.usbtrdtim = 5;
|
gusbcfg.b.usbtrdtim = 5;
|
||||||
}
|
}
|
||||||
|
|
||||||
USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GUSBCFG, gusbcfg.d32);
|
USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GUSBCFG, gusbcfg.d32);
|
||||||
|
|
||||||
/* Clear interrupt */
|
/* Clear interrupt */
|
||||||
gintsts.d32 = 0;
|
gintsts.d32 = 0;
|
||||||
gintsts.b.enumdone = 1;
|
gintsts.b.enumdone = 1;
|
||||||
|
@ -804,16 +806,16 @@ static uint32_t DCD_HandleEnumDone_ISR(USB_OTG_CORE_HANDLE *pdev)
|
||||||
*/
|
*/
|
||||||
static uint32_t DCD_IsoINIncomplete_ISR(USB_OTG_CORE_HANDLE *pdev)
|
static uint32_t DCD_IsoINIncomplete_ISR(USB_OTG_CORE_HANDLE *pdev)
|
||||||
{
|
{
|
||||||
USB_OTG_GINTSTS_TypeDef gintsts;
|
USB_OTG_GINTSTS_TypeDef gintsts;
|
||||||
|
|
||||||
gintsts.d32 = 0;
|
gintsts.d32 = 0;
|
||||||
|
|
||||||
USBD_DCD_INT_fops->IsoINIncomplete (pdev);
|
USBD_DCD_INT_fops->IsoINIncomplete (pdev);
|
||||||
|
|
||||||
/* Clear interrupt */
|
/* Clear interrupt */
|
||||||
gintsts.b.incomplisoin = 1;
|
gintsts.b.incomplisoin = 1;
|
||||||
USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32);
|
USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32);
|
||||||
|
|
||||||
return 1;
|
return 1;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -825,12 +827,12 @@ static uint32_t DCD_IsoINIncomplete_ISR(USB_OTG_CORE_HANDLE *pdev)
|
||||||
*/
|
*/
|
||||||
static uint32_t DCD_IsoOUTIncomplete_ISR(USB_OTG_CORE_HANDLE *pdev)
|
static uint32_t DCD_IsoOUTIncomplete_ISR(USB_OTG_CORE_HANDLE *pdev)
|
||||||
{
|
{
|
||||||
USB_OTG_GINTSTS_TypeDef gintsts;
|
USB_OTG_GINTSTS_TypeDef gintsts;
|
||||||
|
|
||||||
gintsts.d32 = 0;
|
gintsts.d32 = 0;
|
||||||
|
|
||||||
USBD_DCD_INT_fops->IsoOUTIncomplete (pdev);
|
USBD_DCD_INT_fops->IsoOUTIncomplete (pdev);
|
||||||
|
|
||||||
/* Clear interrupt */
|
/* Clear interrupt */
|
||||||
gintsts.b.incomplisoout = 1;
|
gintsts.b.incomplisoout = 1;
|
||||||
USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32);
|
USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32);
|
||||||
|
@ -856,11 +858,11 @@ static uint32_t DCD_ReadDevInEP (USB_OTG_CORE_HANDLE *pdev, uint8_t epnum)
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
|
|
|
@ -12,7 +12,7 @@
|
||||||
/* stack top in large ram, at an address which, masked with 0x2FFE0000,
|
/* stack top in large ram, at an address which, masked with 0x2FFE0000,
|
||||||
gives 0x20000000
|
gives 0x20000000
|
||||||
*/
|
*/
|
||||||
_stack_top = 0x2001FFFF;
|
_stack_top = 0x2001FFFC;
|
||||||
|
|
||||||
/* temporary set heap end equal to stack top */
|
/* temporary set heap end equal to stack top */
|
||||||
_heap_end = _stack_top;
|
_heap_end = _stack_top;
|
||||||
|
@ -33,13 +33,13 @@ MEMORY
|
||||||
SECTIONS
|
SECTIONS
|
||||||
{
|
{
|
||||||
. = 0;
|
. = 0;
|
||||||
|
|
||||||
/* .text section: code goes to flash */
|
/* .text section: code goes to flash */
|
||||||
.text :
|
.text :
|
||||||
{
|
{
|
||||||
/* Startup code must go at address 0 */
|
/* Startup code must go at address 0 */
|
||||||
KEEP(*(.isr_vector))
|
KEEP(*(.isr_vector))
|
||||||
|
|
||||||
*(.text)
|
*(.text)
|
||||||
*(.text.*)
|
*(.text.*)
|
||||||
*(.gnu.linkonce.t.*)
|
*(.gnu.linkonce.t.*)
|
||||||
|
@ -61,7 +61,7 @@ SECTIONS
|
||||||
/* C++ Static constructors/destructors (eabi) */
|
/* C++ Static constructors/destructors (eabi) */
|
||||||
. = ALIGN(4);
|
. = ALIGN(4);
|
||||||
KEEP(*(.init))
|
KEEP(*(.init))
|
||||||
|
|
||||||
. = ALIGN(4);
|
. = ALIGN(4);
|
||||||
__preinit_array_start = .;
|
__preinit_array_start = .;
|
||||||
KEEP (*(.preinit_array))
|
KEEP (*(.preinit_array))
|
||||||
|
|
Ładowanie…
Reference in New Issue