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Moved to C++ and refactored HR_C5000/HR_C6000 drivers, grouping common code. A C-callable wrapper is also provided. TG-37

replace/6ddbdd5fefeb5d29aae396380c5a1239e16df198
Silvano Seva 2021-04-15 22:33:58 +02:00
rodzic d95e36f43b
commit 11161fa64a
13 zmienionych plików z 1139 dodań i 1332 usunięć
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264
platform/drivers/baseband/HR_C5000.c
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@ -1,264 +0,0 @@
/***************************************************************************
* Copyright (C) 2020 by Federico Amedeo Izzo IU2NUO, *
* Niccolò Izzo IU2KIN *
* Frederik Saraci IU2NRO *
* Silvano Seva IU2KWO *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 3 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, see <http://www.gnu.org/licenses/> *
***************************************************************************/
#include <hwconfig.h>
#include <interfaces/gpio.h>
#include <interfaces/delays.h>
#include <hwconfig.h>
#include "HR_C5000.h"
const uint8_t initSeq1[] = {0x00, 0x00, 0xFF, 0xB0, 0x00, 0x00, 0x00, 0x00};
const uint8_t initSeq2[] =
{
0x00, 0x11, 0x80, 0x0A, 0x22, 0x01, 0x00, 0x00, 0x33, 0xEF, 0x00, 0xFF, 0xFF,
0xFF, 0xF0, 0xF0, 0x10, 0x00, 0x00, 0x07, 0x3B, 0xF8, 0x0E, 0xFD, 0x40, 0xFF,
0x00, 0x0B, 0x00, 0x00, 0x00, 0x04, 0x0B, 0x00, 0x17, 0x02, 0xFF, 0xE0, 0x28,
0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
};
const uint8_t initSeq3[] =
{
0x01, 0x10, 0x69, 0x69, 0x96, 0x96, 0x96, 0x99, 0x99, 0x99, 0xA5, 0xA5, 0xAA,
0xAA, 0xCC, 0xCC, 0x00, 0xF0, 0x01, 0xFF, 0x01, 0x0F
};
const uint8_t initSeq4[] = {0x01, 0x30, 0x30, 0x4E, 0x14, 0x1E, 0x1A, 0x30, 0x3D,
0x50, 0x07, 0x60};
const uint8_t initSeq5[] = {0x01, 0x40, 0x90, 0x03, 0x01, 0x02, 0x05, 0x07, 0xF0};
const uint8_t initSeq6[] = {0x01, 0x50, 0x00, 0x00, 0x00, 0x00, 0x00};
uint8_t _spiSendRecv(uint8_t value)
{
gpio_clearPin(DMR_CLK);
uint8_t incoming = 0;
uint8_t cnt = 0;
for(; cnt < 8; cnt++)
{
gpio_setPin(DMR_CLK);
if(value & (0x80 >> cnt))
{
gpio_setPin(DMR_MOSI);
}
else
{
gpio_clearPin(DMR_MOSI);
}
delayUs(1);
gpio_clearPin(DMR_CLK);
incoming = (incoming << 1) | gpio_readPin(DMR_MISO);
delayUs(1);
}
return incoming;
}
void _writeReg(uint8_t type, uint8_t reg, uint8_t val)
{
gpio_clearPin(DMR_CS);
(void) _spiSendRecv(type);
(void) _spiSendRecv(reg);
(void) _spiSendRecv(val);
gpio_setPin(DMR_CS);
}
void _sendSequence(const uint8_t *seq, uint8_t len)
{
gpio_clearPin(DMR_CS);
uint8_t i = 0;
for(; i < len; i++)
{
(void) _spiSendRecv(seq[i]);
}
gpio_setPin(DMR_CS);
}
void C5000_init()
{
gpio_setMode(DMR_CS, OUTPUT);
gpio_setMode(DMR_CLK, OUTPUT);
gpio_setMode(DMR_MOSI, OUTPUT);
gpio_setMode(DMR_MISO, OUTPUT);
gpio_setMode(DMR_SLEEP, OUTPUT);
gpio_setPin(DMR_CS);
gpio_clearPin(DMR_SLEEP); // Exit from sleep pulling down DMR_SLEEP
_writeReg(0x00, 0x0A, 0x80); // Internal clock connected to crystal
_writeReg(0x00, 0x0B, 0x28); // PLL M register (multiplier)
_writeReg(0x00, 0x0C, 0x33); // PLL input and output dividers
delayMs(1);
_writeReg(0x00, 0x0A, 0x00); // Internal clock connected to PLL
_writeReg(0x00, 0xBA, 0x22); // Built-in codec clock freq. (HR_C6000)
_writeReg(0x00, 0xBB, 0x11); // Output clock operating freq. (HR_C6000)
}
void C5000_terminate()
{
gpio_setPin(DMR_SLEEP);
gpio_setMode(DMR_CS, INPUT);
gpio_setMode(DMR_CLK, INPUT);
gpio_setMode(DMR_MOSI, INPUT);
gpio_setMode(DMR_MISO, INPUT);
gpio_setMode(DMR_SLEEP, INPUT);
}
void C5000_setModOffset(uint8_t offset)
{
/*
* Original TYT MD-380 code does this, both for DMR and FM.
*
* References: functions @0x0803fda8 and @0x0804005c
*/
uint8_t offUpper = (offset < 0x80) ? 0x00 : 0x03;
uint8_t offLower = 0x7F - offset;
_writeReg(0x00, 0x48, offUpper); // Two-point bias, upper value
_writeReg(0x00, 0x47, offLower); // Two-point bias, lower value
_writeReg(0x00, 0x04, offLower); // Bias value for TX, Q-channel
}
void C5000_setModAmplitude(uint8_t iAmp, uint8_t qAmp)
{
_writeReg(0x00, 0x45, iAmp); // Mod2 magnitude (HR_C6000)
_writeReg(0x00, 0x46, qAmp); // Mod1 magnitude (HR_C6000)
}
void C5000_setModFactor(uint8_t mf)
{
_writeReg(0x00, 0x35, mf); // FM modulation factor
_writeReg(0x00, 0x3F, 0x04); // FM Limiting modulation factor (HR_C6000)
}
void C5000_dmrMode()
{
// _writeReg(0x00, 0x0A, 0x80);
// _writeReg(0x00, 0x0B, 0x28);
// _writeReg(0x00, 0x0C, 0x33);
// OSTimeDly(1, OS_OPT_TIME_DLY, &e);
// _writeReg(0x00, 0x0A, 0x00);
_writeReg(0x00, 0xB9, 0x32);
// _writeReg(0x00, 0xBA, 0x22);
// _writeReg(0x00, 0xBB, 0x11);
_writeReg(0x00, 0x10, 0x4F);
_writeReg(0x00, 0x40, 0x43);
_writeReg(0x00, 0x41, 0x40);
_writeReg(0x00, 0x07, 0x0B);
_writeReg(0x00, 0x08, 0xB8);
_writeReg(0x00, 0x09, 0x00);
_writeReg(0x00, 0x06, 0x21);
_sendSequence(initSeq1, sizeof(initSeq1));
// _writeReg(0x00, 0x48, 0x00);
// _writeReg(0x00, 0x47, 0x1F); // This is 0x7F - freq_adj_mid */
_sendSequence(initSeq2, sizeof(initSeq2));
_writeReg(0x00, 0x00, 0x28);
delayMs(1);
_writeReg(0x00, 0x14, 0x59);
_writeReg(0x00, 0x15, 0xF5);
_writeReg(0x00, 0x16, 0x21);
_sendSequence(initSeq3, sizeof(initSeq3));
_sendSequence(initSeq4, sizeof(initSeq4));
_sendSequence(initSeq5, sizeof(initSeq5));
_sendSequence(initSeq6, sizeof(initSeq6));
_writeReg(0x01, 0x52, 0x08);
_writeReg(0x01, 0x53, 0xEB);
_writeReg(0x01, 0x54, 0x78);
_writeReg(0x01, 0x45, 0x1E);
_writeReg(0x01, 0x37, 0x50);
_writeReg(0x01, 0x35, 0xFF);
_writeReg(0x00, 0x39, 0x02);
_writeReg(0x00, 0x3D, 0x0A);
_writeReg(0x00, 0x83, 0xFF);
_writeReg(0x00, 0x87, 0x00);
_writeReg(0x00, 0x65, 0x0A);
_writeReg(0x00, 0x1D, 0xFF);
_writeReg(0x00, 0x1E, 0xF1);
_writeReg(0x00, 0x1F, 0x10);
_writeReg(0x00, 0x0D, 0x8C);
_writeReg(0x00, 0x0E, 0x44);
_writeReg(0x00, 0x0F, 0xC8);
_writeReg(0x00, 0x37, 0xC2);
_writeReg(0x00, 0x25, 0x0E);
_writeReg(0x00, 0x26, 0xFD);
_writeReg(0x00, 0x64, 0x00);
_writeReg(0x01, 0x24, 0x00);
_writeReg(0x01, 0x25, 0x00);
_writeReg(0x01, 0x26, 0x00);
_writeReg(0x01, 0x27, 0x00);
_writeReg(0x00, 0x81, 0x19);
_writeReg(0x00, 0x85, 0x00);
}
void C5000_fmMode()
{
_writeReg(0x00, 0xB9, 0x33); // System clock frequency (HR_C6000)
_writeReg(0x00, 0x10, 0x80); // FM modulator mode
_writeReg(0x00, 0x07, 0x0E); // IF frequency - upper 8 bits
_writeReg(0x00, 0x08, 0x10); // IF frequency - middle 8 bits
_writeReg(0x00, 0x09, 0x00); // IF frequency - lower 8 bits
_sendSequence(initSeq1, sizeof(initSeq1));
_writeReg(0x00, 0x06, 0x00); // VoCoder control
_sendSequence(initSeq2, sizeof(initSeq2));
_writeReg(0x00, 0x0D, 0x8C); // Codec control
_writeReg(0x00, 0x0E, 0x44); // Mute HPout and enable MIC 1
_writeReg(0x00, 0x0F, 0xC8); // ADLinVol, mic volume
// _writeReg(0x00, 0x25, 0x0E);
// _writeReg(0x00, 0x26, 0xFE);
_writeReg(0x00, 0x83, 0xFF); // Clear all interrupt flags
_writeReg(0x00, 0x87, 0x00); // Disable "stop" interrupts
_writeReg(0x00, 0x81, 0x00); // Mask other interrupts
_writeReg(0x00, 0x60, 0x00); // Disable both analog and DMR transmission
_writeReg(0x00, 0x00, 0x28); // Reset register
}
void C5000_startAnalogTx()
{
_writeReg(0x00, 0x0D, 0x8C); // Codec control
_writeReg(0x00, 0x0E, 0x44); // Mute HPout and enable MIC 1
_writeReg(0x00, 0x0F, 0xC8); // ADLinVol, mic volume
// _writeReg(0x00, 0x25, 0x0E);
// _writeReg(0x00, 0x26, 0xFE);
_writeReg(0x00, 0x34, 0x3C); // Enable pre-emphasis, 25kHz bandwidth
_writeReg(0x00, 0x3E, 0x08); // "FM Modulation frequency deviation coefficient at the receiving end" (HR_C6000)
_writeReg(0x00, 0x37, 0xC2); // Unknown register
// _writeReg(0x01, 0x50, 0x00);
// _writeReg(0x01, 0x51, 0x00);
_writeReg(0x00, 0x60, 0x80); // Enable analog voice transmission
}
void C5000_stopAnalogTx()
{
_writeReg(0x00, 0x60, 0x00); // Disable both analog and DMR transmission
}
bool C5000_spiInUse()
{
return (gpio_readPin(DMR_CS) == 0) ? true : false;
}

82
platform/drivers/baseband/HR_C5000.h
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@ -1,5 +1,5 @@
/***************************************************************************
* Copyright (C) 2020 by Federico Amedeo Izzo IU2NUO, *
* Copyright (C) 2021 by Federico Amedeo Izzo IU2NUO, *
* Niccolò Izzo IU2KIN *
* Frederik Saraci IU2NRO *
* Silvano Seva IU2KWO *
@ -21,74 +21,18 @@
#ifndef HRC5000_H
#define HRC5000_H
#include <stdint.h>
#include <stdbool.h>
#include "HR_Cx000.h"
/**
* Driver for HR_C5000 "baseband" chip.
*
* WARNING: on MD3x0 devices the PLL and DMR chips share the SPI MOSI line,
* thus particular care has to be put to avoid them stomping reciprocally.
* This driver does not make any check if a SPI transfer is already in progress,
* deferring the correct bus management to higher level modules. However,
* a function returning true if the bus is currently in use by this driver is
* provided.
*/
enum class C5000_SpiOpModes : uint8_t
{
CONFIG = 0, ///< Main configuration registers.
AUX = 1, ///< Auxiliary configuration registers.
DATA = 2, ///< Data register.
SOUND = 3, ///< Voice prompt sample register.
CMX638 = 4, ///< CMX638 configuration register.
AMBE3K = 5 ///< AMBE3000 configuration register.
};
/**
* Initialise the HR_C5000 driver.
*/
void C5000_init();
using HR_C5000 = HR_Cx000 < C5000_SpiOpModes >;
/**
* Terminate the HR_C5000 driver.
*/
void C5000_terminate();
/**
* Set value for two-point modulation offset adjustment. This value usually is
* stored in radio calibration data.
* @param offset: value for modulation offset adjustment.
*/
void C5000_setModOffset(uint8_t offset);
/**
* Set values for two-point modulation amplitude adjustment. These values
* usually are stored in radio calibration data.
* @param iMag: value for modulation offset adjustment.
*/
void C5000_setModAmplitude(uint8_t iAmp, uint8_t qAmp);
/**
* Set value for FM-mode modulation factor, a value dependent on bandwidth.
* @param mf: value for FM modulation factor.
*/
void C5000_setModFactor(uint8_t mf);
/**
* Configure chipset for DMR operation.
*/
void C5000_dmrMode();
/**
* Configure chipset for analog FM operation.
*/
void C5000_fmMode();
/**
* Start analog FM transmission.
*/
void C5000_startAnalogTx();
/**
* Stop analog FM transmission.
*/
void C5000_stopAnalogTx();
/**
* Check if SPI common to HR_C5000 and PLL is in use by this driver.
* @retur true if SPI lines are being used by this driver.
*/
bool C5000_spiInUse();
#endif /* HRC5000_H */
#endif // HRC5000_H

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platform/drivers/baseband/HR_C5000_MDx.cpp 100644
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/***************************************************************************
* Copyright (C) 2020 by Federico Amedeo Izzo IU2NUO, *
* Niccolò Izzo IU2KIN *
* Frederik Saraci IU2NRO *
* Silvano Seva IU2KWO *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 3 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, see <http://www.gnu.org/licenses/> *
***************************************************************************/
#include <interfaces/delays.h>
#include <interfaces/gpio.h>
#include <hwconfig.h>
#include "HR_C5000.h"
static const uint8_t initSeq1[] = {0x00, 0x00, 0xFF, 0xB0, 0x00, 0x00, 0x00, 0x00};
static const uint8_t initSeq2[] =
{
0x00, 0x11, 0x80, 0x0A, 0x22, 0x01, 0x00, 0x00, 0x33, 0xEF, 0x00, 0xFF, 0xFF,
0xFF, 0xF0, 0xF0, 0x10, 0x00, 0x00, 0x07, 0x3B, 0xF8, 0x0E, 0xFD, 0x40, 0xFF,
0x00, 0x0B, 0x00, 0x00, 0x00, 0x04, 0x0B, 0x00, 0x17, 0x02, 0xFF, 0xE0, 0x28,
0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
};
static const uint8_t initSeq3[] =
{
0x01, 0x10, 0x69, 0x69, 0x96, 0x96, 0x96, 0x99, 0x99, 0x99, 0xA5, 0xA5, 0xAA,
0xAA, 0xCC, 0xCC, 0x00, 0xF0, 0x01, 0xFF, 0x01, 0x0F
};
static const uint8_t initSeq4[] = {0x01, 0x30, 0x30, 0x4E, 0x14, 0x1E, 0x1A, 0x30, 0x3D,
0x50, 0x07, 0x60};
static const uint8_t initSeq5[] = {0x01, 0x40, 0x90, 0x03, 0x01, 0x02, 0x05, 0x07, 0xF0};
static const uint8_t initSeq6[] = {0x01, 0x50, 0x00, 0x00, 0x00, 0x00, 0x00};
template class HR_Cx000 < C5000_SpiOpModes >;
template< class M >
void HR_Cx000< M >::init()
{
gpio_setMode(DMR_SLEEP, OUTPUT);
gpio_clearPin(DMR_SLEEP); // Exit from sleep pulling down DMR_SLEEP
writeReg(M::CONFIG, 0x0A, 0x80); // Internal clock connected to crystal
writeReg(M::CONFIG, 0x0B, 0x28); // PLL M register (multiplier)
writeReg(M::CONFIG, 0x0C, 0x33); // PLL input and output dividers
delayMs(1);
writeReg(M::CONFIG, 0x0A, 0x00); // Internal clock connected to PLL
writeReg(M::CONFIG, 0xBA, 0x22); // Built-in codec clock freq. (HR_C6000)
writeReg(M::CONFIG, 0xBB, 0x11); // Output clock operating freq. (HR_C6000)
}
template< class M >
void HR_Cx000< M >::terminate()
{
gpio_setPin(DMR_SLEEP);
gpio_setMode(DMR_CS, INPUT);
gpio_setMode(DMR_CLK, INPUT);
gpio_setMode(DMR_MOSI, INPUT);
gpio_setMode(DMR_MISO, INPUT);
gpio_setMode(DMR_SLEEP, INPUT);
}
template< class M >
void HR_Cx000< M >::setModOffset(const uint16_t offset)
{
/*
* Original TYT MD-380 code does this, both for DMR and FM.
* References: functions @0x0803fda8 and @0x0804005c
*
* Cast to uint8_t to have the exact situation of the original firmware.
*/
uint8_t value = static_cast< uint8_t>(offset);
uint8_t offUpper = (value < 0x80) ? 0x00 : 0x03;
uint8_t offLower = 0x7F - value;
writeReg(M::CONFIG, 0x48, offUpper); // Two-point bias, upper value
writeReg(M::CONFIG, 0x47, offLower); // Two-point bias, lower value
writeReg(M::CONFIG, 0x04, offLower); // Bias value for TX, Q-channel
}
template< class M >
void HR_Cx000< M >::dmrMode()
{
writeReg(M::CONFIG, 0xB9, 0x32);
// writeReg(M::CONFIG, 0xBA, 0x22);
// writeReg(M::CONFIG, 0xBB, 0x11);
writeReg(M::CONFIG, 0x10, 0x4F);
writeReg(M::CONFIG, 0x40, 0x43);
writeReg(M::CONFIG, 0x41, 0x40);
writeReg(M::CONFIG, 0x07, 0x0B);
writeReg(M::CONFIG, 0x08, 0xB8);
writeReg(M::CONFIG, 0x09, 0x00);
writeReg(M::CONFIG, 0x06, 0x21);
sendSequence(initSeq1, sizeof(initSeq1));
sendSequence(initSeq2, sizeof(initSeq2));
writeReg(M::CONFIG, 0x00, 0x28);
delayMs(1);
writeReg(M::CONFIG, 0x14, 0x59);
writeReg(M::CONFIG, 0x15, 0xF5);
writeReg(M::CONFIG, 0x16, 0x21);
sendSequence(initSeq3, sizeof(initSeq3));
sendSequence(initSeq4, sizeof(initSeq4));
sendSequence(initSeq5, sizeof(initSeq5));
sendSequence(initSeq6, sizeof(initSeq6));
writeReg(M::AUX, 0x52, 0x08);
writeReg(M::AUX, 0x53, 0xEB);
writeReg(M::AUX, 0x54, 0x78);
writeReg(M::AUX, 0x45, 0x1E);
writeReg(M::AUX, 0x37, 0x50);
writeReg(M::AUX, 0x35, 0xFF);
writeReg(M::CONFIG, 0x39, 0x02);
writeReg(M::CONFIG, 0x3D, 0x0A);
writeReg(M::CONFIG, 0x83, 0xFF);
writeReg(M::CONFIG, 0x87, 0x00);
writeReg(M::CONFIG, 0x65, 0x0A);
writeReg(M::CONFIG, 0x1D, 0xFF);
writeReg(M::CONFIG, 0x1E, 0xF1);
writeReg(M::CONFIG, 0x1F, 0x10);
writeReg(M::CONFIG, 0x0D, 0x8C);
writeReg(M::CONFIG, 0x0E, 0x44);
writeReg(M::CONFIG, 0x0F, 0xC8);
writeReg(M::CONFIG, 0x37, 0xC2);
writeReg(M::CONFIG, 0x25, 0x0E);
writeReg(M::CONFIG, 0x26, 0xFD);
writeReg(M::CONFIG, 0x64, 0x00);
writeReg(M::AUX, 0x24, 0x00);
writeReg(M::AUX, 0x25, 0x00);
writeReg(M::AUX, 0x26, 0x00);
writeReg(M::AUX, 0x27, 0x00);
writeReg(M::CONFIG, 0x81, 0x19);
writeReg(M::CONFIG, 0x85, 0x00);
}
template< class M >
void HR_Cx000< M >::fmMode()
{
writeReg(M::CONFIG, 0xB9, 0x33); // System clock frequency (HR_C6000)
writeReg(M::CONFIG, 0x10, 0x80); // FM modulator mode
writeReg(M::CONFIG, 0x07, 0x0E); // IF frequency - upper 8 bits
writeReg(M::CONFIG, 0x08, 0x10); // IF frequency - middle 8 bits
writeReg(M::CONFIG, 0x09, 0x00); // IF frequency - lower 8 bits
sendSequence(initSeq1, sizeof(initSeq1));
writeReg(M::CONFIG, 0x06, 0x00); // VoCoder control
sendSequence(initSeq2, sizeof(initSeq2));
writeReg(M::CONFIG, 0x0D, 0x8C); // Codec control
writeReg(M::CONFIG, 0x0E, 0x44); // Mute HPout and enable MIC 1
writeReg(M::CONFIG, 0x0F, 0xC8); // ADLinVol, mic volume
// writeReg(M::CONFIG, 0x25, 0x0E);
// writeReg(M::CONFIG, 0x26, 0xFE);
writeReg(M::CONFIG, 0x83, 0xFF); // Clear all interrupt flags
writeReg(M::CONFIG, 0x87, 0x00); // Disable "stop" interrupts
writeReg(M::CONFIG, 0x81, 0x00); // Mask other interrupts
writeReg(M::CONFIG, 0x60, 0x00); // Disable both analog and DMR transmission
writeReg(M::CONFIG, 0x00, 0x28); // Reset register
}
template< class M>
void HR_Cx000<M>::startAnalogTx(const TxAudioSource source, const FmConfig cfg)
{
uint8_t audioCfg = 0x40; // Mute HPout
if(source == TxAudioSource::MIC) audioCfg |= 0x04; // Mic1En
if(source == TxAudioSource::LINE_IN) audioCfg |= 0x02; // Mic2En
writeReg(M::CONFIG, 0x0D, 0x8C); // Codec control
writeReg(M::CONFIG, 0x0E, audioCfg);
writeReg(M::CONFIG, 0x0F, 0xC8); // ADLinVol, mic volume
// writeReg(M::CONFIG, 0x25, 0x0E);
// writeReg(M::CONFIG, 0x26, 0xFE);
writeReg(M::CONFIG, 0x34, static_cast< uint8_t >(cfg));
writeReg(M::CONFIG, 0x3E, 0x08); // "FM Modulation frequency deviation coefficient at the receiving end" (HR_C6000)
writeReg(M::CONFIG, 0x37, 0xC2); // Unknown register
// writeReg(M::AUX, 0x50, 0x00);
// writeReg(M::AUX, 0x51, 0x00);
writeReg(M::CONFIG, 0x60, 0x80); // Enable analog voice transmission
}
template< class M >
void HR_Cx000< M >::stopAnalogTx()
{
writeReg(M::CONFIG, 0x60, 0x00); // Disable both analog and DMR transmission
}
/*
* SPI interface driver
*/
template<class M>
void HR_Cx000<M>::uSpi_init()
{
gpio_setMode(DMR_CS, OUTPUT);
gpio_setMode(DMR_CLK, OUTPUT);
gpio_setMode(DMR_MOSI, OUTPUT);
gpio_setMode(DMR_MISO, OUTPUT);
// Deselect HR_C5000, idle state of the CS line.
gpio_setPin(DMR_CS);
}
template< class M >
uint8_t HR_Cx000< M >::uSpi_sendRecv(const uint8_t value)
{
gpio_clearPin(DMR_CLK);
uint8_t incoming = 0;
for(uint8_t cnt = 0; cnt < 8; cnt++)
{
gpio_setPin(DMR_CLK);
if(value & (0x80 >> cnt))
{
gpio_setPin(DMR_MOSI);
}
else
{
gpio_clearPin(DMR_MOSI);
}
delayUs(1);
gpio_clearPin(DMR_CLK);
incoming = (incoming << 1) | gpio_readPin(DMR_MISO);
delayUs(1);
}
return incoming;
}

304
platform/drivers/baseband/HR_C6000.c
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@ -1,304 +0,0 @@
/***************************************************************************
* Copyright (C) 2020 by Federico Amedeo Izzo IU2NUO, *
* Niccolò Izzo IU2KIN *
* Frederik Saraci IU2NRO *
* Silvano Seva IU2KWO *
* *
* Based on the original work from Kai Ludwig, DG4KLU, and *
* Roger Clark, VK3KYY/G4KYF. *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 3 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, see <http://www.gnu.org/licenses/> *
***************************************************************************/
#include "HR_C6000.h"
#include "interfaces.h"
#include <hwconfig.h>
#include <interfaces/gpio.h>
#include <interfaces/delays.h>
#include <hwconfig.h>
#include <calibUtils.h>
#include <stdio.h>
static const uint8_t initSeq1[] = { 0x01, 0x04, 0xD5, 0xD7, 0xF7, 0x7F, 0xD7, 0x57 };
static const uint8_t initSeq2[] =
{
0x01, 0x10, 0x69, 0x69, 0x96, 0x96, 0x96, 0x99, 0x99, 0x99, 0xA5, 0xA5, 0xAA,
0xAA, 0xCC, 0xCC, 0x00, 0xF0, 0x01, 0xFF, 0x01, 0x0F, 0x00, 0x00, 0x00, 0x00,
0x10, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
};
static const uint8_t initSeq3[] =
{
0x01, 0x30, 0x00, 0x00, 0x14, 0x1E, 0x1A, 0xFF, 0x3D, 0x50, 0x07, 0x60, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00
};
static const uint8_t initSeq4[] = { 0x01, 0x40, 0x00, 0x03, 0x01, 0x02, 0x05, 0x1E, 0xF0 };
static const uint8_t initSeq5[] = { 0x01, 0x51, 0x00, 0x00, 0xEB, 0x78, 0x67 };
static const uint8_t initSeq6[] =
{
0x01, 0x60, 0x32, 0xEF, 0x00, 0x31, 0xEF, 0x00, 0x12, 0xEF, 0x00, 0x13, 0xEF,
0x00, 0x14, 0xEF, 0x00, 0x15, 0xEF, 0x00, 0x16, 0xEF, 0x00, 0x17, 0xEF, 0x00,
0x18, 0xEF, 0x00, 0x19, 0xEF, 0x00, 0x1A, 0xEF, 0x00, 0x1B, 0xEF, 0x00, 0x1C,
0xEF, 0x00, 0x1D, 0xEF, 0x00, 0x1E, 0xEF, 0x00, 0x1F, 0xEF, 0x00, 0x20, 0xEF,
0x00, 0x21, 0xEF, 0x00, 0x22, 0xEF, 0x00, 0x23, 0xEF, 0x00, 0x24, 0xEF, 0x00,
0x25, 0xEF, 0x00, 0x26, 0xEF, 0x00, 0x27, 0xEF, 0x00, 0x28, 0xEF, 0x00, 0x29,
0xEF, 0x00, 0x2A, 0xEF, 0x00, 0x2B, 0xEF, 0x00, 0x2C, 0xEF, 0x00, 0x2D, 0xEF,
0x00, 0x2E, 0xEF, 0x00, 0x2F, 0xEF, 0x00
};
void _writeReg(uint8_t type, uint8_t reg, uint8_t val)
{
gpio_clearPin(DMR_CS);
(void) uSpi_sendRecv(type);
(void) uSpi_sendRecv(reg);
(void) uSpi_sendRecv(val);
delayUs(2);
gpio_setPin(DMR_CS);
delayUs(2);
}
uint8_t _readReg(uint8_t type, uint8_t reg)
{
gpio_clearPin(DMR_CS);
(void) uSpi_sendRecv(type);
(void) uSpi_sendRecv(reg);
uint8_t val = uSpi_sendRecv(0xFF);
delayUs(2);
gpio_setPin(DMR_CS);
delayUs(2);
return val;
}
void _sendSequence(const uint8_t *seq, uint8_t len)
{
gpio_clearPin(DMR_CS);
uint8_t i = 0;
for(; i < len; i++)
{
(void) uSpi_sendRecv(seq[i]);
}
delayUs(2);
gpio_setPin(DMR_CS);
delayUs(2);
}
void C6000_init()
{
uSpi_init();
gpio_setMode(DMR_CS, OUTPUT);
gpio_setMode(DMR_SLEEP, OUTPUT);
gpio_setMode(DMR_RESET, OUTPUT);
gpio_setPin(DMR_RESET);
gpio_setPin(DMR_SLEEP);
delayMs(10);
gpio_clearPin(DMR_SLEEP); // Exit from sleep pulling down DMR_SLEEP
delayMs(10);
_writeReg(0x04, 0x0a, 0x81); //Clock connected to crystal
_writeReg(0x04, 0x0b, 0x40); //Set PLL M Register
_writeReg(0x04, 0x0c, 0x32); //Set PLL Dividers
_writeReg(0x04, 0xb9, 0x05);
_writeReg(0x04, 0x0a, 0x01); //Clock connected to PLL, set Clock Source Enable CLKOUT Pin
//*
_sendSequence(initSeq1, sizeof(initSeq1));
_sendSequence(initSeq2, sizeof(initSeq2));
_sendSequence(initSeq3, sizeof(initSeq3));
_sendSequence(initSeq4, sizeof(initSeq4));
_sendSequence(initSeq5, sizeof(initSeq5));
_sendSequence(initSeq6, sizeof(initSeq6));
_writeReg(0x04, 0x00, 0x00); //Clear all Reset Bits which forces a reset of all internal systems
_writeReg(0x04, 0x10, 0x6E); //Set DMR,Tier2,Timeslot Mode, Layer 2, Repeater, Aligned, Slot1
_writeReg(0x04, 0x11, 0x80); //Set LocalChanMode to Default Value
_writeReg(0x04, 0x13, 0x00); //Zero Cend_Band Timing advance
_writeReg(0x04, 0x1F, 0x10); //Set LocalEMB DMR Colour code in upper 4 bits - defaulted to 1, and is updated elsewhere in the code
_writeReg(0x04, 0x20, 0x00); //Set LocalAccessPolicy to Impolite
_writeReg(0x04, 0x21, 0xA0); //Set LocalAccessPolicy1 to Polite to Color Code (unsure why there are two registers for this)
_writeReg(0x04, 0x22, 0x26); //Start Vocoder Decode, I2S mode
_writeReg(0x04, 0x22, 0x86); //Start Vocoder Encode, I2S mode
_writeReg(0x04, 0x25, 0x0E); //Undocumented Register
_writeReg(0x04, 0x26, 0x7D); //Undocumented Register
_writeReg(0x04, 0x27, 0x40); //Undocumented Register
_writeReg(0x04, 0x28, 0x7D); //Undocumented Register
_writeReg(0x04, 0x29, 0x40); //Undocumented Register
_writeReg(0x04, 0x2A, 0x0B); //Set spi_clk_cnt to default value
_writeReg(0x04, 0x2B, 0x0B); //According to Datasheet this is a Read only register For FM Squelch
_writeReg(0x04, 0x2C, 0x17); //According to Datasheet this is a Read only register For FM Squelch
_writeReg(0x04, 0x2D, 0x05); //Set FM Compression and Decompression points (?)
_writeReg(0x04, 0x2E, 0x04); //Set tx_pre_on (DMR Transmission advance) to 400us
_writeReg(0x04, 0x2F, 0x0B); //Set I2S Clock Frequency
_writeReg(0x04, 0x32, 0x02); //Set LRCK_CNT_H CODEC Operating Frequency to default value
_writeReg(0x04, 0x33, 0xFF); //Set LRCK_CNT_L CODEC Operating Frequency to default value
_writeReg(0x04, 0x34, 0xF0); //Set FM Filters on and bandwidth to 12.5Khz
_writeReg(0x04, 0x35, 0x28); //Set FM Modulation Coefficient
_writeReg(0x04, 0x3E, 0x28); //Set FM Modulation Offset
_writeReg(0x04, 0x3F, 0x10); //Set FM Modulation Limiter
_writeReg(0x04, 0x36, 0x00); //Enable all clocks
_writeReg(0x04, 0x37, 0x00); //Set mcu_control_shift to default. (codec under HRC-6000 control)
_writeReg(0x04, 0x4B, 0x1B); //Set Data packet types to defaults
_writeReg(0x04, 0x4C, 0x00); //Set Data packet types to defaults
_writeReg(0x04, 0x56, 0x00); //Undocumented Register
_writeReg(0x04, 0x5F, 0xC0); //Enable Sync detection for MS or BS orignated signals
_writeReg(0x04, 0x81, 0xFF); //Enable all Interrupts
_writeReg(0x04, 0xD1, 0xC4); //According to Datasheet this register is for FM DTMF (?)
_writeReg(0x04, 0x01, 0x70); //set 2 point Mod, swap receive I and Q, receive mode IF (?) (Presumably changed elsewhere)
_writeReg(0x04, 0x03, 0x00); //zero Receive I Offset
_writeReg(0x04, 0x05, 0x00); //Zero Receive Q Offset
_writeReg(0x04, 0x12, 0x15); //Set rf_pre_on Receive to transmit switching advance
_writeReg(0x04, 0xA1, 0x80); //According to Datasheet this register is for FM Modulation Setting (?)
_writeReg(0x04, 0xC0, 0x0A); //Set RF Signal Advance to 1ms (10x100us)
_writeReg(0x04, 0x06, 0x21); //Use SPI vocoder under MCU control
_writeReg(0x04, 0x07, 0x0B); //Set IF Frequency H to default 450KHz
_writeReg(0x04, 0x08, 0xB8); //Set IF Frequency M to default 450KHz
_writeReg(0x04, 0x09, 0x00); //Set IF Frequency L to default 450KHz
_writeReg(0x04, 0x0D, 0x10); //Set Voice Superframe timeout value
_writeReg(0x04, 0x0E, 0x8E); //Register Documented as Reserved
_writeReg(0x04, 0x0F, 0xB8); //FSK Error Count
_writeReg(0x04, 0xC2, 0x00); //Disable Mic Gain AGC
_writeReg(0x04, 0xE0, 0x8B); //CODEC under MCU Control, LineOut2 Enabled, Mic_p Enabled, I2S Slave Mode
_writeReg(0x04, 0xE1, 0x0F); //Undocumented Register (Probably associated with CODEC)
_writeReg(0x04, 0xE2, 0x06); //CODEC Anti Pop Enabled, DAC Output Enabled
_writeReg(0x04, 0xE3, 0x52); //CODEC Default Settings
_writeReg(0x04, 0xE4, 0x4A); //CODEC LineOut Gain 2dB, Mic Stage 1 Gain 0dB, Mic Stage 2 Gain 30dB
_writeReg(0x04, 0xE5, 0x1A); //CODEC Default Setting
_writeReg(0x04, 0x40, 0xC3); //Enable DMR Tx, DMR Rx, Passive Timing, Normal mode
_writeReg(0x04, 0x41, 0x40); //Receive during next timeslot
_writeReg(0x04, 0x06, 0x23); // SET OpenMusic bit (play Boot sound and Call Prompts)
gpio_clearPin(DMR_CS);
(void) uSpi_sendRecv(0x03);
(void) uSpi_sendRecv(0x00);
for(uint8_t i = 0; i < 128; i++) uSpi_sendRecv(0xAA);
delayUs(2);
gpio_setPin(DMR_CS);
delayUs(2);
_writeReg(0x04, 0x06, 0x21); // CLEAR OpenMusic bit (play Boot sound and Call Prompts)
_writeReg(0x04, 0x37, 0x9E); // MCU take control of CODEC
_writeReg(0x04, 0xE4, 0x0A);
// SPI0SeClearPageRegByteWithMask(0x04, 0xE4, 0x3F, 0x00); // Set CODEC LineOut Gain to 0dB
// dmrMonitorCapturedTimeout = nonVolatileSettings.dmrCaptureTimeout * 1000;
_writeReg(0x04, 0x04, 0xE8); //Set Mod2 output offset
_writeReg(0x04, 0x46, 0x37); //Set Mod1 Amplitude
_writeReg(0x04, 0x48, 0x03); //Set 2 Point Mod Bias
_writeReg(0x04, 0x47, 0xE8); //Set 2 Point Mod Bias
_writeReg(0x04, 0x41, 0x20); //set sync fail bit (reset?)
_writeReg(0x04, 0x40, 0x03); //Disable DMR Tx and Rx
_writeReg(0x04, 0x41, 0x00); //Reset all bits.
_writeReg(0x04, 0x00, 0x3F); //Reset DMR Protocol and Physical layer modules.
_sendSequence(initSeq1, sizeof(initSeq1));
_writeReg(0x04, 0x10, 0x6E); //Set DMR, Tier2, Timeslot mode, Layer2, Repeater, Aligned, Slot 1
_writeReg(0x04, 0x1F, 0x10); // Set Local EMB. DMR Colour code in upper 4 bits - defaulted to 1, and is updated elsewhere in the code
_writeReg(0x04, 0x26, 0x7D); //Undocumented Register
_writeReg(0x04, 0x27, 0x40); //Undocumented Register
_writeReg(0x04, 0x28, 0x7D); //Undocumented Register
_writeReg(0x04, 0x29, 0x40); //Undocumented Register
_writeReg(0x04, 0x2A, 0x0B); //Set SPI Clock to default value
_writeReg(0x04, 0x2B, 0x0B); //According to Datasheet this is a Read only register For FM Squelch
_writeReg(0x04, 0x2C, 0x17); //According to Datasheet this is a Read only register For FM Squelch
_writeReg(0x04, 0x2D, 0x05); //Set FM Compression and Decompression points (?)
_writeReg(0x04, 0x56, 0x00); //Undocumented Register
_writeReg(0x04, 0x5F, 0xC0); //Enable Sync detection for MS or BS orignated signals
_writeReg(0x04, 0x81, 0xFF); //Enable all Interrupts
_writeReg(0x04, 0x01, 0x70); //Set 2 Point Mod, Swap Rx I and Q, Rx Mode IF
_writeReg(0x04, 0x03, 0x00); //Zero Receive I Offset
_writeReg(0x04, 0x05, 0x00); //Zero Receive Q Offset
_writeReg(0x04, 0x12, 0x15); //Set RF Switching Receive to Transmit Advance
_writeReg(0x04, 0xA1, 0x80); //According to Datasheet this register is for FM Modulation Setting (?)
_writeReg(0x04, 0xC0, 0x0A); //Set RF Signal Advance to 1ms (10x100us)
_writeReg(0x04, 0x06, 0x21); //Use SPI vocoder under MCU control
_writeReg(0x04, 0x07, 0x0B); //Set IF Frequency H to default 450KHz
_writeReg(0x04, 0x08, 0xB8); //Set IF Frequency M to default 450KHz
_writeReg(0x04, 0x09, 0x00); //Set IF Frequency l to default 450KHz
_writeReg(0x04, 0x0D, 0x10); //Set Voice Superframe timeout value
_writeReg(0x04, 0x0E, 0x8E); //Register Documented as Reserved
_writeReg(0x04, 0x0F, 0xB8); //FSK Error Count
_writeReg(0x04, 0xC2, 0x00); //Disable Mic Gain AGC
_writeReg(0x04, 0xE0, 0x8B); //CODEC under MCU Control, LineOut2 Enabled, Mic_p Enabled, I2S Slave Mode
_writeReg(0x04, 0xE1, 0x0F); //Undocumented Register (Probably associated with CODEC)
_writeReg(0x04, 0xE2, 0x06); //CODEC Anti Pop Enabled, DAC Output Enabled
_writeReg(0x04, 0xE3, 0x52); //CODEC Default Settings
_writeReg(0x04, 0xE5, 0x1A); //CODEC Default Setting
_writeReg(0x04, 0x26, 0x7D); //Undocumented Register
_writeReg(0x04, 0x27, 0x40); //Undocumented Register
_writeReg(0x04, 0x28, 0x7D); //Undocumented Register
_writeReg(0x04, 0x29, 0x40); //Undocumented Register
_writeReg(0x04, 0x41, 0x20); //Set Sync Fail Bit (Reset?)
_writeReg(0x04, 0x40, 0xC3); //Enable DMR Tx and Rx, Passive Timing
_writeReg(0x04, 0x41, 0x40); //Set Receive During Next Slot Bit
_writeReg(0x04, 0x01, 0x70); //Set 2 Point Mod, Swap Rx I and Q, Rx Mode IF
_writeReg(0x04, 0x10, 0x6E); //Set DMR, Tier2, Timeslot mode, Layer2, Repeater, Aligned, Slot 1
_writeReg(0x04, 0x00, 0x3F); //Reset DMR Protocol and Physical layer modules.
_writeReg(0x04, 0xE4, 0xCB); //CODEC LineOut Gain 6dB, Mic Stage 1 Gain 0dB, Mic Stage 2 Gain default is 11 = 33dB
_writeReg(0x04, 0x06, 0x23);
//*/
}
void C6000_terminate()
{
gpio_setPin(DMR_SLEEP);
gpio_setMode(DMR_CS, INPUT);
}
void C6000_setModOffset(uint16_t offset)
{
uint8_t offUpper = (offset >> 8) & 0x03;
uint8_t offLower = offset & 0xFF;
_writeReg(0x04, 0x48, offUpper);
_writeReg(0x04, 0x47, offLower);
}
void C6000_setModAmplitude(uint8_t iAmp, uint8_t qAmp)
{
_writeReg(0x04, 0x45, iAmp); // Mod2 magnitude (HR_C6000)
_writeReg(0x04, 0x46, qAmp); // Mod1 magnitude (HR_C6000)
}
void C6000_setMod2Bias(uint8_t bias)
{
_writeReg(0x04, 0x04, bias);
}
void C6000_setDacGain(uint8_t value)
{
uint8_t dacData = value + 1;
if(dacData > 31) dacData = 31;
_writeReg(0x04, 0x37, dacData);
}
bool C6000_spiInUse()
{
return (gpio_readPin(DMR_CS) == 0) ? true : false;
}

84
platform/drivers/baseband/HR_C6000.h
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@ -1,5 +1,5 @@
/***************************************************************************
* Copyright (C) 2020 by Federico Amedeo Izzo IU2NUO, *
* Copyright (C) 2021 by Federico Amedeo Izzo IU2NUO, *
* Niccolò Izzo IU2KIN *
* Frederik Saraci IU2NRO *
* Silvano Seva IU2KWO *
@ -21,77 +21,19 @@
#ifndef HRC6000_H
#define HRC6000_H
#include <stdint.h>
#include <stdbool.h>
#include "HR_Cx000.h"
#include <calibInfo_GDx.h>
enum class C6000_SpiOpModes : uint8_t
{
AUX = 1, ///< Auxiliary configuration registers.
DATA = 2, ///< Write TX data register and read RX data register.
SOUND = 3, ///< Voice prompt sample register.
CONFIG = 4, ///< Main configuration registers.
AMBE3K = 5, ///< AMBE3000 configuration register.
DATA_R = 6, ///< Write RX data register and read TX data register.
AMBE1K = 7 ///< AMBE1000 configuration register.
};
/**
* Initialise the HR_C6000 driver.
*/
void C6000_init();
/**
* Terminate the HR_C6000 driver.
*/
void C6000_terminate();
/**
* Set value for two-point modulation offset adjustment. This value usually is
* stored in radio calibration data.
* @param offset: value for modulation offset adjustment.
*/
void C6000_setModOffset(uint16_t offset);
/**
* Set values for two-point modulation amplitude adjustment. These values
* usually are stored in radio calibration data.
* @param iMag: value for modulation offset adjustment.
*/
void C6000_setModAmplitude(uint8_t iAmp, uint8_t qAmp);
/**
*
*/
void C6000_setMod2Bias(uint8_t bias);
/**
* Set value for FM-mode modulation factor, a value dependent on bandwidth.
* @param mf: value for FM modulation factor.
*/
void C6000_setModFactor(uint8_t mf);
/**
* Configure the gain of lineout DAC stage. Allowed range is 1 - 31 and each
* step corresponds to a variation of 1.5dB.
* @param value: gain for the DAC stage.
*/
void C6000_setDacGain(uint8_t value);
/**
* Configure chipset for DMR operation.
*/
void C6000_dmrMode();
/**
* Configure chipset for analog FM operation.
*/
void C6000_fmMode();
/**
* Start analog FM transmission.
*/
void C6000_startAnalogTx();
/**
* Stop analog FM transmission.
*/
void C6000_stopAnalogTx();
/**
* Check if SPI common to HR_C6000 and PLL is in use by this driver.
* @return true if SPI lines are being used by this driver.
*/
bool C6000_spiInUse();
using HR_C6000 = HR_Cx000 < C6000_SpiOpModes >;
#endif /* HRC6000_H */

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platform/drivers/baseband/HR_C6000_GDx.cpp 100644
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/***************************************************************************
* Copyright (C) 2021 by Federico Amedeo Izzo IU2NUO, *
* Niccolò Izzo IU2KIN *
* Frederik Saraci IU2NRO *
* Silvano Seva IU2KWO *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 3 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, see <http://www.gnu.org/licenses/> *
***************************************************************************/
#include <interfaces/gpio.h>
#include <interfaces/delays.h>
#include <hwconfig.h>
#include "HR_C6000.h"
static const uint8_t initSeq1[] = { 0x01, 0x04, 0xD5, 0xD7, 0xF7, 0x7F, 0xD7, 0x57 };
static const uint8_t initSeq2[] =
{
0x01, 0x10, 0x69, 0x69, 0x96, 0x96, 0x96, 0x99, 0x99, 0x99, 0xA5, 0xA5, 0xAA,
0xAA, 0xCC, 0xCC, 0x00, 0xF0, 0x01, 0xFF, 0x01, 0x0F, 0x00, 0x00, 0x00, 0x00,
0x10, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
};
static const uint8_t initSeq3[] =
{
0x01, 0x30, 0x00, 0x00, 0x14, 0x1E, 0x1A, 0xFF, 0x3D, 0x50, 0x07, 0x60, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00
};
static const uint8_t initSeq4[] = { 0x01, 0x40, 0x00, 0x03, 0x01, 0x02, 0x05, 0x1E, 0xF0 };
static const uint8_t initSeq5[] = { 0x01, 0x51, 0x00, 0x00, 0xEB, 0x78, 0x67 };
static const uint8_t initSeq6[] =
{
0x01, 0x60, 0x32, 0xEF, 0x00, 0x31, 0xEF, 0x00, 0x12, 0xEF, 0x00, 0x13, 0xEF,
0x00, 0x14, 0xEF, 0x00, 0x15, 0xEF, 0x00, 0x16, 0xEF, 0x00, 0x17, 0xEF, 0x00,
0x18, 0xEF, 0x00, 0x19, 0xEF, 0x00, 0x1A, 0xEF, 0x00, 0x1B, 0xEF, 0x00, 0x1C,
0xEF, 0x00, 0x1D, 0xEF, 0x00, 0x1E, 0xEF, 0x00, 0x1F, 0xEF, 0x00, 0x20, 0xEF,
0x00, 0x21, 0xEF, 0x00, 0x22, 0xEF, 0x00, 0x23, 0xEF, 0x00, 0x24, 0xEF, 0x00,
0x25, 0xEF, 0x00, 0x26, 0xEF, 0x00, 0x27, 0xEF, 0x00, 0x28, 0xEF, 0x00, 0x29,
0xEF, 0x00, 0x2A, 0xEF, 0x00, 0x2B, 0xEF, 0x00, 0x2C, 0xEF, 0x00, 0x2D, 0xEF,
0x00, 0x2E, 0xEF, 0x00, 0x2F, 0xEF, 0x00
};
template class HR_Cx000 < C6000_SpiOpModes >;
template< class M >
void HR_Cx000< M >::init()
{
gpio_setMode(DMR_SLEEP, OUTPUT);
gpio_setMode(DMR_RESET, OUTPUT);
gpio_setPin(DMR_RESET);
gpio_setPin(DMR_SLEEP);
delayMs(10);
gpio_clearPin(DMR_SLEEP); //Exit from sleep pulling down DMR_SLEEP
delayMs(10);
writeReg(M::CONFIG, 0x0A, 0x81); //Clock connected to crystal
writeReg(M::CONFIG, 0x0B, 0x40); //Set PLL M Register
writeReg(M::CONFIG, 0x0C, 0x32); //Set PLL Dividers
writeReg(M::CONFIG, 0xB9, 0x05);
writeReg(M::CONFIG, 0x0A, 0x01); //Clock connected to PLL, set Clock Source Enable CLKOUT Pin
sendSequence(initSeq1, sizeof(initSeq1));
sendSequence(initSeq2, sizeof(initSeq2));
sendSequence(initSeq3, sizeof(initSeq3));
sendSequence(initSeq4, sizeof(initSeq4));
sendSequence(initSeq5, sizeof(initSeq5));
sendSequence(initSeq6, sizeof(initSeq6));
writeReg(M::CONFIG, 0x00, 0x00); //Clear all Reset Bits which forces a reset of all internal systems
writeReg(M::CONFIG, 0x10, 0x6E); //Set DMR,Tier2,Timeslot Mode, Layer 2, Repeater, Aligned, Slot1
writeReg(M::CONFIG, 0x11, 0x80); //Set LocalChanMode to Default Value
writeReg(M::CONFIG, 0x13, 0x00); //Zero Cend_Band Timing advance
writeReg(M::CONFIG, 0x1F, 0x10); //Set LocalEMB DMR Colour code in upper 4 bits - defaulted to 1, and is updated elsewhere in the code
writeReg(M::CONFIG, 0x20, 0x00); //Set LocalAccessPolicy to Impolite
writeReg(M::CONFIG, 0x21, 0xA0); //Set LocalAccessPolicy1 to Polite to Color Code (unsure why there are two registers for this)
writeReg(M::CONFIG, 0x22, 0x26); //Start Vocoder Decode, I2S mode
writeReg(M::CONFIG, 0x22, 0x86); //Start Vocoder Encode, I2S mode
writeReg(M::CONFIG, 0x25, 0x0E); //Undocumented Register
writeReg(M::CONFIG, 0x26, 0x7D); //Undocumented Register
writeReg(M::CONFIG, 0x27, 0x40); //Undocumented Register
writeReg(M::CONFIG, 0x28, 0x7D); //Undocumented Register
writeReg(M::CONFIG, 0x29, 0x40); //Undocumented Register
writeReg(M::CONFIG, 0x2A, 0x0B); //Set spi_clk_cnt to default value
writeReg(M::CONFIG, 0x2B, 0x0B); //According to Datasheet this is a Read only register For FM Squelch
writeReg(M::CONFIG, 0x2C, 0x17); //According to Datasheet this is a Read only register For FM Squelch
writeReg(M::CONFIG, 0x2D, 0x05); //Set FM Compression and Decompression points (?)
writeReg(M::CONFIG, 0x2E, 0x04); //Set tx_pre_on (DMR Transmission advance) to 400us
writeReg(M::CONFIG, 0x2F, 0x0B); //Set I2S Clock Frequency
writeReg(M::CONFIG, 0x32, 0x02); //Set LRCK_CNT_H CODEC Operating Frequency to default value
writeReg(M::CONFIG, 0x33, 0xFF); //Set LRCK_CNT_L CODEC Operating Frequency to default value
writeReg(M::CONFIG, 0x34, 0xF0); //Set FM Filters on and bandwidth to 12.5Khz
writeReg(M::CONFIG, 0x35, 0x28); //Set FM Modulation Coefficient
writeReg(M::CONFIG, 0x3E, 0x28); //Set FM Modulation Offset
writeReg(M::CONFIG, 0x3F, 0x10); //Set FM Modulation Limiter
writeReg(M::CONFIG, 0x36, 0x00); //Enable all clocks
writeReg(M::CONFIG, 0x37, 0x00); //Set mcu_control_shift to default. (codec under HRC-6000 control)
writeReg(M::CONFIG, 0x4B, 0x1B); //Set Data packet types to defaults
writeReg(M::CONFIG, 0x4C, 0x00); //Set Data packet types to defaults
writeReg(M::CONFIG, 0x56, 0x00); //Undocumented Register
writeReg(M::CONFIG, 0x5F, 0xC0); //Enable Sync detection for MS or BS orignated signals
writeReg(M::CONFIG, 0x81, 0xFF); //Enable all Interrupts
writeReg(M::CONFIG, 0xD1, 0xC4); //According to Datasheet this register is for FM DTMF (?)
writeReg(M::CONFIG, 0x01, 0x70); //set 2 point Mod, swap receive I and Q, receive mode IF (?) (Presumably changed elsewhere)
writeReg(M::CONFIG, 0x03, 0x00); //zero Receive I Offset
writeReg(M::CONFIG, 0x05, 0x00); //Zero Receive Q Offset
writeReg(M::CONFIG, 0x12, 0x15); //Set rf_pre_on Receive to transmit switching advance
writeReg(M::CONFIG, 0xA1, 0x80); //According to Datasheet this register is for FM Modulation Setting (?)
writeReg(M::CONFIG, 0xC0, 0x0A); //Set RF Signal Advance to 1ms (10x100us)
writeReg(M::CONFIG, 0x06, 0x21); //Use SPI vocoder under MCU control
writeReg(M::CONFIG, 0x07, 0x0B); //Set IF Frequency H to default 450KHz
writeReg(M::CONFIG, 0x08, 0xB8); //Set IF Frequency M to default 450KHz
writeReg(M::CONFIG, 0x09, 0x00); //Set IF Frequency L to default 450KHz
writeReg(M::CONFIG, 0x0D, 0x10); //Set Voice Superframe timeout value
writeReg(M::CONFIG, 0x0E, 0x8E); //Register Documented as Reserved
writeReg(M::CONFIG, 0x0F, 0xB8); //FSK Error Count
writeReg(M::CONFIG, 0xC2, 0x00); //Disable Mic Gain AGC
writeReg(M::CONFIG, 0xE0, 0x8B); //CODEC under MCU Control, LineOut2 Enabled, Mic_p Enabled, I2S Slave Mode
writeReg(M::CONFIG, 0xE1, 0x0F); //Undocumented Register (Probably associated with CODEC)
writeReg(M::CONFIG, 0xE2, 0x06); //CODEC Anti Pop Enabled, DAC Output Enabled
writeReg(M::CONFIG, 0xE3, 0x52); //CODEC Default Settings
writeReg(M::CONFIG, 0xE4, 0x4A); //CODEC LineOut Gain 2dB, Mic Stage 1 Gain 0dB, Mic Stage 2 Gain 30dB
writeReg(M::CONFIG, 0xE5, 0x1A); //CODEC Default Setting
writeReg(M::CONFIG, 0x40, 0xC3); //Enable DMR Tx, DMR Rx, Passive Timing, Normal mode
writeReg(M::CONFIG, 0x41, 0x40); //Receive during next timeslot
}
template< class M >
void HR_Cx000< M >::terminate()
{
gpio_setPin(DMR_SLEEP);
gpio_setMode(DMR_CS, INPUT);
}
template< class M >
void HR_Cx000< M >::setModOffset(const uint16_t offset)
{
uint8_t offUpper = (offset >> 8) & 0x03;
uint8_t offLower = offset & 0xFF;
writeReg(M::CONFIG, 0x48, offUpper);
writeReg(M::CONFIG, 0x47, offLower);
}
// Unused functionalities on GDx
template< class M > void HR_Cx000< M >::dmrMode() { }
template< class M > void HR_Cx000< M >::fmMode() { }
template< class M >
void HR_Cx000< M >::startAnalogTx(const TxAudioSource source, const FmConfig cfg)
{
(void) source;
(void) cfg;
}
template< class M > void HR_Cx000< M >::stopAnalogTx() { }
/*
* SPI interface driver
*/
template< class M >
void HR_Cx000< M >::uSpi_init()
{
gpio_setMode(DMR_CS, OUTPUT);
gpio_setMode(DMR_CLK, OUTPUT);
gpio_setMode(DMR_MOSI, OUTPUT);
gpio_setMode(DMR_MISO, INPUT);
gpio_setAlternateFunction(DMR_CLK, 0);
gpio_setAlternateFunction(DMR_MOSI, 0);
gpio_setAlternateFunction(DMR_MISO, 0);
SIM->SCGC6 |= SIM_SCGC6_SPI0_MASK;
SPI0->MCR &= ~SPI_MCR_MDIS_MASK; // Enable the SPI0 module
SPI0->MCR |= SPI_MCR_MSTR_MASK // Master mode
| SPI_MCR_PCSIS_MASK // CS high when inactive
| SPI_MCR_DIS_RXF_MASK // Disable RX FIFO
| SPI_MCR_DIS_TXF_MASK // Disable TX FIFO
| SPI_MCR_HALT_MASK; // Stop transfers
SPI0->CTAR[0] = SPI_CTAR_FMSZ(7) // 8bit frame size
| SPI_CTAR_CPHA_MASK // CPHA = 1
| SPI_CTAR_PBR(2) // CLK prescaler divide by 5
| SPI_CTAR_BR(3) // CLK scaler divide by 8
| SPI_CTAR_PCSSCK(1)
| SPI_CTAR_PASC(1)
| SPI_CTAR_CSSCK(4)
| SPI_CTAR_ASC(4);
}
template< class M >
uint8_t HR_Cx000< M >::uSpi_sendRecv(const uint8_t value)
{
SPI0->MCR &= ~SPI_MCR_HALT_MASK; // Start transfer
SPI0->MCR |= SPI_MCR_CLR_TXF_MASK | SPI_MCR_CLR_RXF_MASK;
while((SPI0->SR & SPI_SR_TFFF_MASK) == 0) ;
SPI0->PUSHR = SPI_PUSHR_EOQ_MASK | value;
SPI0->SR |= SPI_SR_TFFF_MASK;
while((SPI0->SR & SPI_SR_RFDF_MASK) == 0) ;
SPI0->SR |= SPI_SR_RFDF_MASK;
SPI0->MCR |= SPI_MCR_HALT_MASK; // Start transfer
return SPI0->POPR;
}

298
platform/drivers/baseband/HR_C6000_UV3x0.c
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@ -1,298 +0,0 @@
/***************************************************************************
* Copyright (C) 2020 by Federico Amedeo Izzo IU2NUO, *
* Niccolò Izzo IU2KIN *
* Frederik Saraci IU2NRO *
* Silvano Seva IU2KWO *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 3 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, see <http://www.gnu.org/licenses/> *
***************************************************************************/
#include "HR_C6000.h"
#include "interfaces.h"
#include <hwconfig.h>
#include <interfaces/gpio.h>
#include <interfaces/delays.h>
#include <hwconfig.h>
#include <calibUtils.h>
#include <stdio.h>
static const uint8_t initSeq1[] = { 0x01, 0x04, 0xD5, 0xD7, 0xF7, 0x7F, 0xD7, 0x57 };
static const uint8_t initSeq2[] =
{
0x04, 0x11, 0x80, 0x0C, 0x22, 0x01, 0x00, 0x00, 0x33, 0xEF, 0x00, 0xFF, 0xFF,
0xFF, 0xF0, 0xF0, 0x10, 0x00, 0x00, 0x06, 0x3B, 0xF8, 0x0E, 0xFD, 0x40, 0xFF,
0x00, 0x0B, 0x00, 0x00, 0x00, 0x06, 0x0B, 0x00, 0x17, 0x02, 0xFF, 0xE0, 0x14,
0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
};
static const uint8_t initSeq3[] =
{
0x01, 0x10, 0x69, 0x69, 0x96, 0x96, 0x96, 0x99, 0x99, 0x99, 0xA5, 0xA5, 0xAA,
0xAA, 0xCC, 0xCC, 0x00, 0xF0, 0x01, 0xFF, 0x01, 0x0F, 0x00, 0x00, 0x00, 0x00,
0x0D, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
};
static const uint8_t initSeq4[] =
{
0x01, 0x30, 0x00, 0x00, 0x20, 0x3C, 0xFF, 0xFF, 0x3F, 0x50, 0x07, 0x60, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00
};
static const uint8_t initSeq5[] = { 0x01, 0x40, 0x00, 0x01, 0x01, 0x02, 0x01, 0x1E, 0xF0 };
static const uint8_t initSeq6[] = { 0x01, 0x50, 0x00, 0x08, 0xEB, 0x78, 0x67 };
static const uint8_t initSeq7[] = { 0x01, 0x04, 0xD5, 0xD7, 0xF7, 0x7F, 0xD7, 0x57 };
void _writeReg(uint8_t type, uint8_t reg, uint8_t val)
{
gpio_clearPin(DMR_CS);
(void) uSpi_sendRecv(type);
(void) uSpi_sendRecv(reg);
(void) uSpi_sendRecv(val);
delayUs(2);
gpio_setPin(DMR_CS);
delayUs(2);
}
uint8_t _readReg(uint8_t type, uint8_t reg)
{
gpio_clearPin(DMR_CS);
(void) uSpi_sendRecv(type);
(void) uSpi_sendRecv(reg);
uint8_t val = uSpi_sendRecv(0xFF);
delayUs(2);
gpio_setPin(DMR_CS);
delayUs(2);
return val;
}
void _sendSequence(const uint8_t *seq, uint8_t len)
{
gpio_clearPin(DMR_CS);
uint8_t i = 0;
for(; i < len; i++)
{
(void) uSpi_sendRecv(seq[i]);
}
delayUs(2);
gpio_setPin(DMR_CS);
delayUs(2);
}
void C6000_init()
{
uSpi_init();
gpio_setMode(DMR_CS, OUTPUT);
gpio_setMode(DMR_SLEEP, OUTPUT);
gpio_setPin(DMR_SLEEP);
delayMs(10);
gpio_clearPin(DMR_SLEEP); // Exit from sleep pulling down DMR_SLEEP
delayMs(10);
_writeReg(0x04, 0x0A, 0x80); //Clock connected to crystal
_writeReg(0x04, 0x0B, 0x28); //Set PLL M Register
_writeReg(0x04, 0x0C, 0x33); //Set PLL Dividers
delayMs(250);
_writeReg(0x04, 0x0A, 0x00);
_writeReg(0x04, 0xB9, 0x05);
_writeReg(0x04, 0xBA, 0x04);
_writeReg(0x04, 0xBB, 0x02);
_writeReg(0x04, 0xA1, 0x80);
_writeReg(0x04, 0x10, 0xF3);
_writeReg(0x04, 0x40, 0x43);
_writeReg(0x04, 0x07, 0x0B);
_writeReg(0x04, 0x08, 0xB8);
_writeReg(0x04, 0x09, 0x00);
_writeReg(0x04, 0x06, 0x21);
_sendSequence(initSeq1, sizeof(initSeq1));
_writeReg(0x04, 0x01, 0xF8);
_sendSequence(initSeq2, sizeof(initSeq2));
_writeReg(0x04, 0x00, 0x2A);
_writeReg(0x04, 0x06, 0x22);
gpio_clearPin(DMR_CS);
(void) uSpi_sendRecv(0x03);
(void) uSpi_sendRecv(0x00);
for(uint8_t i = 0; i < 128; i++) uSpi_sendRecv(0xAA);
delayUs(2);
gpio_setPin(DMR_CS);
delayUs(2);
_writeReg(0x04, 0x06, 0x20);
_writeReg(0x04, 0x14, 0x59);
_writeReg(0x04, 0x15, 0xF5);
_writeReg(0x04, 0x16, 0x21);
_sendSequence(initSeq3, sizeof(initSeq3));
_sendSequence(initSeq4, sizeof(initSeq4));
_sendSequence(initSeq5, sizeof(initSeq5));
_sendSequence(initSeq6, sizeof(initSeq6));
_writeReg(0x01, 0x52, 0x08);
_writeReg(0x01, 0x53, 0xEB);
_writeReg(0x01, 0x54, 0x78);
_writeReg(0x01, 0x45, 0x1E);
_writeReg(0x01, 0x37, 0x50);
_writeReg(0x01, 0x35, 0xFF);
_writeReg(0x04, 0x39, 0x02);
_writeReg(0x04, 0x3D, 0x0A);
_writeReg(0x04, 0x83, 0xFF);
_writeReg(0x04, 0x87, 0x00);
_writeReg(0x04, 0x65, 0x0A);
_writeReg(0x04, 0x1D, 0xFF);
_writeReg(0x04, 0x1E, 0xF1);
_writeReg(0x04, 0xE2, 0x06);
_writeReg(0x04, 0xE4, 0x27);
_writeReg(0x04, 0xE3, 0x52);
_writeReg(0x04, 0xE5, 0x1A);
_writeReg(0x04, 0xE1, 0x0F);
_writeReg(0x04, 0xD1, 0xC4);
_writeReg(0x04, 0x25, 0x0E);
_writeReg(0x04, 0x26, 0xFD);
_writeReg(0x04, 0x64, 0x00);
}
void C6000_terminate()
{
gpio_setPin(DMR_SLEEP);
gpio_setMode(DMR_CS, INPUT);
}
void C6000_setModOffset(uint16_t offset)
{
/*
* Same as original TYT firmware.
* Reference: functions @0802e7d4 and @080546cc in S18.16 binary image
*/
uint8_t offUpper = (offset < 0x80) ? 0x03 : 0x00;
uint8_t offLower = offset + 0x80;
_writeReg(0x04, 0x48, offUpper); // Two-point bias, upper value
_writeReg(0x04, 0x47, offLower); // Two-point bias, lower value
_writeReg(0x04, 0x04, offLower); // Bias value for TX, Q-channel
}
void C6000_setModAmplitude(uint8_t iAmp, uint8_t qAmp)
{
_writeReg(0x04, 0x45, iAmp); // Mod2 magnitude (HR_C6000)
_writeReg(0x04, 0x46, qAmp); // Mod1 magnitude (HR_C6000)
}
void C6000_setMod2Bias(uint8_t bias)
{
_writeReg(0x04, 0x04, bias);
}
void C6000_setDacGain(uint8_t value)
{
if(value < 1) value = 1;
if(value > 31) value = 31;
_writeReg(0x04, 0x37, (0x80 | value));
}
void C6000_dmrMode()
{
_writeReg(0x04, 0x10, 0x4F);
_writeReg(0x04, 0x81, 0x19);
_writeReg(0x04, 0x01, 0xF0);
_writeReg(0x04, 0xE4, 0x27);
_writeReg(0x04, 0xE5, 0x1A);
_writeReg(0x04, 0x25, 0x0E);
_writeReg(0x04, 0x26, 0xFD);
_writeReg(0x01, 0x54, 0x78);
// _writeReg(0x04, 0x48, 0x00);
// _writeReg(0x04, 0x47, 0x25);
_writeReg(0x04, 0x1F, 0x10);
_writeReg(0x01, 0x24, 0x00);
_writeReg(0x01, 0x25, 0x00);
_writeReg(0x01, 0x26, 0x00);
_writeReg(0x01, 0x27, 0x00);
_writeReg(0x04, 0x41, 0x40);
_writeReg(0x04, 0x56, 0x00);
_writeReg(0x04, 0x41, 0x40);
_writeReg(0x04, 0x5C, 0x09);
_writeReg(0x04, 0x5F, 0xC0);
_sendSequence(initSeq7, sizeof(initSeq7));
_writeReg(0x04, 0x11, 0x80);
}
void C6000_fmMode()
{
_writeReg(0x04, 0x10, 0xF3);
_writeReg(0x04, 0x01, 0xB0);
_writeReg(0x04, 0x81, 0x04);
_writeReg(0x04, 0xE5, 0x1A);
_writeReg(0x04, 0x36, 0x02);
_writeReg(0x04, 0xE4, 0x27);
_writeReg(0x04, 0xE2, 0x06);
_writeReg(0x04, 0x34, 0x98);
_writeReg(0x04, 0x60, 0x00);
_writeReg(0x04, 0x1F, 0x00);
_writeReg(0x01, 0x24, 0x00);
_writeReg(0x01, 0x25, 0x00);
_writeReg(0x01, 0x26, 0x00);
_writeReg(0x01, 0x27, 0x00);
_writeReg(0x04, 0x56, 0x00);
_writeReg(0x04, 0x41, 0x40);
_writeReg(0x04, 0x5C, 0x09);
_writeReg(0x04, 0x5F, 0xC0);
_sendSequence(initSeq7, sizeof(initSeq7));
_writeReg(0x04, 0x11, 0x80);
_writeReg(0x04, 0xE0, 0xC9);
_writeReg(0x04, 0x37, 0x81);
}
void C6000_startAnalogTx()
{
_writeReg(0x04, 0xE2, 0x00);
_writeReg(0x04, 0xE4, 0x23);
_writeReg(0x04, 0xC2, 0x00);
_writeReg(0x04, 0xA1, 0x80);
// _writeReg(0x04, 0x25, 0x0E);
// _writeReg(0x04, 0x26, 0xFE);
_writeReg(0x04, 0x83, 0xFF);
_writeReg(0x04, 0x87, 0x00);
_writeReg(0x04, 0x04, 0x24);
_writeReg(0x04, 0x35, 0x40);
_writeReg(0x04, 0x3F, 0x04);
_writeReg(0x04, 0x34, 0xBC);
_writeReg(0x04, 0x3E, 0x08);
_writeReg(0x01, 0x50, 0x00);
_writeReg(0x01, 0x51, 0x00);
_writeReg(0x04, 0x60, 0x80);
_writeReg(0x04, 0x10, 0xF3);
_writeReg(0x04, 0xE0, 0xC1);
_writeReg(0x04, 0x37, 0x8C);
}
void C6000_stopAnalogTx()
{
_writeReg(0x04, 0x60, 0x00);
_writeReg(0x04, 0xE0, 0xC9);
_writeReg(0x04, 0xE2, 0x06);
_writeReg(0x04, 0x34, 0x98);
_writeReg(0x04, 0x37, 0x81);
}
bool C6000_spiInUse()
{
return (gpio_readPin(DMR_CS) == 0) ? true : false;
}

281
platform/drivers/baseband/HR_C6000_UV3x0.cpp 100644
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@ -0,0 +1,281 @@
/***************************************************************************
* Copyright (C) 2021 by Federico Amedeo Izzo IU2NUO, *
* Niccolò Izzo IU2KIN *
* Frederik Saraci IU2NRO *
* Silvano Seva IU2KWO *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 3 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, see <http://www.gnu.org/licenses/> *
***************************************************************************/
#include <interfaces/gpio.h>
#include <interfaces/delays.h>
#include <hwconfig.h>
#include "HR_C6000.h"
static const uint8_t initSeq1[] = { 0x01, 0x04, 0xD5, 0xD7, 0xF7, 0x7F, 0xD7, 0x57 };
static const uint8_t initSeq2[] =
{
0x04, 0x11, 0x80, 0x0C, 0x22, 0x01, 0x00, 0x00, 0x33, 0xEF, 0x00, 0xFF, 0xFF,
0xFF, 0xF0, 0xF0, 0x10, 0x00, 0x00, 0x06, 0x3B, 0xF8, 0x0E, 0xFD, 0x40, 0xFF,
0x00, 0x0B, 0x00, 0x00, 0x00, 0x06, 0x0B, 0x00, 0x17, 0x02, 0xFF, 0xE0, 0x14,
0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
};
static const uint8_t initSeq3[] =
{
0x01, 0x10, 0x69, 0x69, 0x96, 0x96, 0x96, 0x99, 0x99, 0x99, 0xA5, 0xA5, 0xAA,
0xAA, 0xCC, 0xCC, 0x00, 0xF0, 0x01, 0xFF, 0x01, 0x0F, 0x00, 0x00, 0x00, 0x00,
0x0D, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
};
static const uint8_t initSeq4[] =
{
0x01, 0x30, 0x00, 0x00, 0x20, 0x3C, 0xFF, 0xFF, 0x3F, 0x50, 0x07, 0x60, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00
};
static const uint8_t initSeq5[] = { 0x01, 0x40, 0x00, 0x01, 0x01, 0x02, 0x01, 0x1E, 0xF0 };
static const uint8_t initSeq6[] = { 0x01, 0x50, 0x00, 0x08, 0xEB, 0x78, 0x67 };
static const uint8_t initSeq7[] = { 0x01, 0x04, 0xD5, 0xD7, 0xF7, 0x7F, 0xD7, 0x57 };
template class HR_Cx000 < C6000_SpiOpModes >;
template< class M >
void HR_Cx000< M >::init()
{
gpio_setMode(DMR_CS, OUTPUT);
gpio_setMode(DMR_SLEEP, OUTPUT);
gpio_setPin(DMR_SLEEP);
delayMs(10);
gpio_clearPin(DMR_SLEEP); // Exit from sleep pulling down DMR_SLEEP
delayMs(10);
writeReg(M::CONFIG, 0x0A, 0x80); //Clock connected to crystal
writeReg(M::CONFIG, 0x0B, 0x28); //Set PLL M Register
writeReg(M::CONFIG, 0x0C, 0x33); //Set PLL Dividers
delayMs(250);
writeReg(M::CONFIG, 0x0A, 0x00);
writeReg(M::CONFIG, 0xB9, 0x05);
writeReg(M::CONFIG, 0xBA, 0x04);
writeReg(M::CONFIG, 0xBB, 0x02);
writeReg(M::CONFIG, 0xA1, 0x80);
writeReg(M::CONFIG, 0x10, 0xF3);
writeReg(M::CONFIG, 0x40, 0x43);
writeReg(M::CONFIG, 0x07, 0x0B);
writeReg(M::CONFIG, 0x08, 0xB8);
writeReg(M::CONFIG, 0x09, 0x00);
sendSequence(initSeq1, sizeof(initSeq1));
writeReg(M::CONFIG, 0x01, 0xF8);
sendSequence(initSeq2, sizeof(initSeq2));
writeReg(M::CONFIG, 0x00, 0x2A);
writeReg(M::CONFIG, 0x06, 0x20);
writeReg(M::CONFIG, 0x14, 0x59);
writeReg(M::CONFIG, 0x15, 0xF5);
writeReg(M::CONFIG, 0x16, 0x21);
sendSequence(initSeq3, sizeof(initSeq3));
sendSequence(initSeq4, sizeof(initSeq4));
sendSequence(initSeq5, sizeof(initSeq5));
sendSequence(initSeq6, sizeof(initSeq6));
writeReg(M::AUX, 0x52, 0x08);
writeReg(M::AUX, 0x53, 0xEB);
writeReg(M::AUX, 0x54, 0x78);
writeReg(M::AUX, 0x45, 0x1E);
writeReg(M::AUX, 0x37, 0x50);
writeReg(M::AUX, 0x35, 0xFF);
writeReg(M::CONFIG, 0x39, 0x02);
writeReg(M::CONFIG, 0x3D, 0x0A);
writeReg(M::CONFIG, 0x83, 0xFF);
writeReg(M::CONFIG, 0x87, 0x00);
writeReg(M::CONFIG, 0x65, 0x0A);
writeReg(M::CONFIG, 0x1D, 0xFF);
writeReg(M::CONFIG, 0x1E, 0xF1);
writeReg(M::CONFIG, 0xE2, 0x06);
writeReg(M::CONFIG, 0xE4, 0x27);
writeReg(M::CONFIG, 0xE3, 0x52);
writeReg(M::CONFIG, 0xE5, 0x1A);
writeReg(M::CONFIG, 0xE1, 0x0F);
writeReg(M::CONFIG, 0xD1, 0xC4);
writeReg(M::CONFIG, 0x25, 0x0E);
writeReg(M::CONFIG, 0x26, 0xFD);
writeReg(M::CONFIG, 0x64, 0x00);
}
template< class M >
void HR_Cx000< M >::terminate()
{
gpio_setPin(DMR_SLEEP);
gpio_setMode(DMR_CS, INPUT);
}
template< class M >
void HR_Cx000< M >::setModOffset(const uint16_t offset)
{
/*
* Same as original TYT firmware.
* Reference: functions @0802e7d4 and @080546cc in S18.16 binary image.
*
* Cast to uint8_t to have the exact situation of the original firmware.
*/
uint8_t value = static_cast< uint8_t>(offset);
uint8_t offUpper = (value < 0x80) ? 0x03 : 0x00;
uint8_t offLower = value + 0x80;
writeReg(M::CONFIG, 0x48, offUpper); // Two-point bias, upper value
writeReg(M::CONFIG, 0x47, offLower); // Two-point bias, lower value
writeReg(M::CONFIG, 0x04, offLower); // Bias value for TX, Q-channel
}
template< class M >
void HR_Cx000< M >::dmrMode()
{
writeReg(M::CONFIG, 0x10, 0x4F);
writeReg(M::CONFIG, 0x81, 0x19);
writeReg(M::CONFIG, 0x01, 0xF0);
writeReg(M::CONFIG, 0xE4, 0x27);
writeReg(M::CONFIG, 0xE5, 0x1A);
writeReg(M::CONFIG, 0x25, 0x0E);
writeReg(M::CONFIG, 0x26, 0xFD);
writeReg(M::AUX, 0x54, 0x78);
writeReg(M::CONFIG, 0x1F, 0x10);
writeReg(M::AUX, 0x24, 0x00);
writeReg(M::AUX, 0x25, 0x00);
writeReg(M::AUX, 0x26, 0x00);
writeReg(M::AUX, 0x27, 0x00);
writeReg(M::CONFIG, 0x41, 0x40);
writeReg(M::CONFIG, 0x56, 0x00);
writeReg(M::CONFIG, 0x41, 0x40);
writeReg(M::CONFIG, 0x5C, 0x09);
writeReg(M::CONFIG, 0x5F, 0xC0);
sendSequence(initSeq7, sizeof(initSeq7));
writeReg(M::CONFIG, 0x11, 0x80);
}
template< class M >
void HR_Cx000< M >::fmMode()
{
writeReg(M::CONFIG, 0x10, 0xF3);
writeReg(M::CONFIG, 0x01, 0xB0);
writeReg(M::CONFIG, 0x81, 0x04);
writeReg(M::CONFIG, 0xE5, 0x1A);
writeReg(M::CONFIG, 0x36, 0x02);
writeReg(M::CONFIG, 0xE4, 0x27);
writeReg(M::CONFIG, 0xE2, 0x06);
writeReg(M::CONFIG, 0x34, 0x98);
writeReg(M::CONFIG, 0x60, 0x00);
writeReg(M::CONFIG, 0x1F, 0x00);
writeReg(M::AUX, 0x24, 0x00);
writeReg(M::AUX, 0x25, 0x00);
writeReg(M::AUX, 0x26, 0x00);
writeReg(M::AUX, 0x27, 0x00);
writeReg(M::CONFIG, 0x56, 0x00);
writeReg(M::CONFIG, 0x41, 0x40);
writeReg(M::CONFIG, 0x5C, 0x09);
writeReg(M::CONFIG, 0x5F, 0xC0);
sendSequence(initSeq7, sizeof(initSeq7));
writeReg(M::CONFIG, 0x11, 0x80);
writeReg(M::CONFIG, 0xE0, 0xC9);
writeReg(M::CONFIG, 0x37, 0x81);
}
template< class M >
void HR_Cx000< M >::startAnalogTx(const TxAudioSource source, const FmConfig cfg)
{
/*
* NOTE: on MD-UV3x0 the incoming audio from the microphone is connected to
* "Linein1" input, while signal coming from the tone generator is connected
* to "Mic_p".
*/
uint8_t audioCfg = 0x81;
if(source == TxAudioSource::MIC) audioCfg |= 0x40;
if(source == TxAudioSource::LINE_IN) audioCfg |= 0x02;
writeReg(M::CONFIG, 0xE2, 0x00);
writeReg(M::CONFIG, 0xE4, 0x23);
writeReg(M::CONFIG, 0xC2, 0x00);
writeReg(M::CONFIG, 0xA1, 0x80);
// writeReg(M::CONFIG, 0x25, 0x0E);
// writeReg(M::CONFIG, 0x26, 0xFE);
writeReg(M::CONFIG, 0x83, 0xFF);
writeReg(M::CONFIG, 0x87, 0x00);
writeReg(M::CONFIG, 0x04, 0x24);
writeReg(M::CONFIG, 0x35, 0x40);
writeReg(M::CONFIG, 0x3F, 0x04);
writeReg(M::CONFIG, 0x34, static_cast< uint8_t >(cfg));
writeReg(M::CONFIG, 0x3E, 0x08);
writeReg(M::AUX, 0x50, 0x00);
writeReg(M::AUX, 0x51, 0x00);
writeReg(M::CONFIG, 0x60, 0x80);
writeReg(M::CONFIG, 0x10, 0xF3);
writeReg(M::CONFIG, 0xE0, audioCfg);
writeReg(M::CONFIG, 0x37, 0x8C);
}
template< class M >
void HR_Cx000< M >::stopAnalogTx()
{
writeReg(M::CONFIG, 0x60, 0x00);
writeReg(M::CONFIG, 0xE0, 0xC9);
writeReg(M::CONFIG, 0xE2, 0x06);
writeReg(M::CONFIG, 0x34, 0x98);
writeReg(M::CONFIG, 0x37, 0x81);
}
/*
* SPI interface driver
*/
template< class M >
void HR_Cx000<M>::uSpi_init()
{
gpio_setMode(DMR_CS, OUTPUT);
gpio_setMode(DMR_CLK, OUTPUT);
gpio_setMode(DMR_MOSI, OUTPUT);
gpio_setMode(DMR_MISO, OUTPUT);
// Deselect HR_C6000, idle state of the CS line.
gpio_setPin(DMR_CS);
}
template< class M >
uint8_t HR_Cx000<M>::uSpi_sendRecv(const uint8_t value)
{
gpio_clearPin(DMR_CLK);
uint8_t incoming = 0;
for(uint8_t cnt = 0; cnt < 8; cnt++)
{
gpio_setPin(DMR_CLK);
if(value & (0x80 >> cnt))
{
gpio_setPin(DMR_MOSI);
}
else
{
gpio_clearPin(DMR_MOSI);
}
delayUs(1);
gpio_clearPin(DMR_CLK);
incoming = (incoming << 1) | gpio_readPin(DMR_MISO);
delayUs(1);
}
return incoming;
}

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platform/drivers/baseband/HR_Cx000.cpp 100644
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/***************************************************************************
* Copyright (C) 2021 by Federico Amedeo Izzo IU2NUO, *
* Niccolò Izzo IU2KIN *
* Frederik Saraci IU2NRO *
* Silvano Seva IU2KWO *
* *
* Mhis program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 3 of the License, or *
* (at your option) any later version. *
* *
* Mhis program is distributed in the hope that it will be useful, *
* but WIMHOUM ANY WARRANMY; without even the implied warranty of *
* MERCHANMABILIMY or FIMNESS FOR A PARMICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, see <http://www.gnu.org/licenses/> *
***************************************************************************/
#include <interfaces/delays.h>
#include <interfaces/gpio.h>
#include <type_traits>
#include <hwconfig.h>
#include "HR_Cx000.h"
#include "HR_C5000.h"
#include "HR_C6000.h"
bool Cx000_uSpiBusy()
{
return (gpio_readPin(DMR_CS) == 0) ? true : false;
}
template <>
void HR_Cx000< C5000_SpiOpModes >::setDacGain(uint8_t value)
{
// TODO: "DALin" register for HR_C5000 is not documented.
(void) value;
}
template <>
void HR_Cx000< C6000_SpiOpModes >::setDacGain(uint8_t value)
{
if(value < 1) value = 1;
if(value > 31) value = 31;
writeReg(C6000_SpiOpModes::CONFIG, 0x37, (0x80 | value));
}
ScopedChipSelect::ScopedChipSelect()
{
gpio_clearPin(DMR_CS);
}
ScopedChipSelect::~ScopedChipSelect()
{
delayUs(2);
gpio_setPin(DMR_CS);
delayUs(2);
}
FmConfig operator |(FmConfig lhs, FmConfig rhs)
{
return static_cast< FmConfig >
(
static_cast< std::underlying_type< FmConfig >::type >(lhs) |
static_cast< std::underlying_type< FmConfig >::type >(rhs)
);
}

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platform/drivers/baseband/HR_Cx000.h 100644
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/***************************************************************************
* Copyright (C) 2021 by Federico Amedeo Izzo IU2NUO, *
* Niccolò Izzo IU2KIN *
* Frederik Saraci IU2NRO *
* Silvano Seva IU2KWO *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 3 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, see <http://www.gnu.org/licenses/> *
***************************************************************************/
#ifndef HRCx000_H
#define HRCx000_H
#include <stdbool.h>
#include <stdint.h>
#include <stddef.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* Check if "user" SPI bus, on some platforms shared between the baseband and
* other chips, is in use by the HR_Cx000 driver. This function is callable
* either from C or C++ sources.
*
* WARNING: this function is NOT thread safe! A proper critical section has to
* be set up to ensure it is accessed by one task at a time.
*
* @return true if SPI lines are being used by this driver.
*/
bool Cx000_uSpiBusy();
#ifdef __cplusplus
}
/**
* Configuration options for analog FM mode.
* Each option is tied to a particular bit of the Configuration register 0x34.
*/
enum class FmConfig : uint8_t
{
BPF_EN = 1 << 7, ///< Enable band-pass filter.
COMP_EN = 1 << 6, ///< Enable compression.
PREEMPH_EN = 1 << 5, ///< Enable preemphasis.
BW_25kHz = 1 << 4, ///< 25kHz TX bandwidth.
BW_12p5kHz = 0 ///< 12.5kHz TX bandwidth.
};
/**
* Audio input selection for both DMR and FM operation.
*/
enum class TxAudioSource
{
MIC, ///< Audio source is microphone.
LINE_IN ///< Audio source is "line in", e.g. tone generator.
};
/**
* Generic driver for HR_C5000/HR_C6000 "baseband" chip.
*
*
* WARNING: on some MDx devices the PLL and DMR chips share the SPI MOSI line,
* thus particular care has to be put to avoid them stomping reciprocally.
* This driver does not make any check if a SPI transfer is already in progress,
* deferring the correct bus management to higher level modules. However,
* a function returning true if the bus is currently in use by this driver is
* provided.
*/
class ScopedChipSelect;
template< class M >
class HR_Cx000
{
public:
/**
* \return a reference to the instance of the AT1846S class (singleton).
*/
static HR_Cx000& instance()
{
static HR_Cx000< M > Cx000;
return Cx000;
}
/**
* Destructor.
* When called it shuts down the baseband chip.
*/
~HR_Cx000()
{
terminate();
}
/**
* Initialise the baseband chip.
*/
void init();
/**
* Shutdown the baseband chip.
*/
void terminate();
/**
* Set value for two-point modulation offset adjustment. This value usually
* is stored in radio calibration data.
*
* @param offset: value for modulation offset adjustment.
*/
void setModOffset(const uint16_t offset);
/**
* Set values for two-point modulation amplitude adjustment. These values
* usually are stored in radio calibration data.
*
* @param iAmp: value for modulation offset adjustment.
* @param qAmp: value for modulation offset adjustment.
*/
inline void setModAmplitude(const uint8_t iAmp, const uint8_t qAmp)
{
writeReg(M::CONFIG, 0x45, iAmp); // Mod2 magnitude
writeReg(M::CONFIG, 0x46, qAmp); // Mod1 magnitude
}
/**
* Set value for FM-mode modulation factor, a value dependent on bandwidth.
*
* @param mf: value for FM modulation factor.
*/
inline void setModFactor(const uint8_t mf)
{
writeReg(M::CONFIG, 0x35, mf); // FM modulation factor
writeReg(M::CONFIG, 0x3F, 0x04); // FM Limiting modulation factor (HR_C6000)
}
/**
* Set the gain of the audio DAC stage. This value affects the sound volume
* in RX mode.
*
* @param value: gain value. Allowed range is 1-31.
*/
void setDacGain(uint8_t value);
/**
* Configure chipset for DMR operation.
*/
void dmrMode();
/**
* Configure chipset for analog FM operation.
*/
void fmMode();
/**
* Start analog FM transmission.
*
* @param source: audio source for TX.
* @param cfg: TX configuration parameters, e.g. bandwidth.
*/
void startAnalogTx(const TxAudioSource source, const FmConfig cfg);
/**
* Stop analog FM transmission.
*/
void stopAnalogTx();
/**
* Set the value of a configuration register.
*
* @param reg: register number.
* @param value: new register value.
*/
inline void writeCfgRegister(const uint8_t reg, const uint8_t value)
{
writeReg(M::CONFIG, reg, value);
}
/**
* Get the current value of a configuration register.
*
* @param reg: register number.
* \return current value of the register.
*/
inline uint8_t readCfgRegister(const uint8_t reg)
{
return readReg(M::CONFIG, reg);
}
private:
/**
* Constructor.
*/
HR_Cx000()
{
// Being a singleton class, uSPI is initialised only once.
uSpi_init();
}
/**
* Helper function for register writing.
*
* @param opMode: "operating mode" specifier, see datasheet for details.
* @param addr: register number.
* @param value: value to be written.
*/
void writeReg(const M opMode, const uint8_t addr, const uint8_t value)
{
ScopedChipSelect cs;
(void) uSpi_sendRecv(static_cast< uint8_t >(opMode));
(void) uSpi_sendRecv(addr);
(void) uSpi_sendRecv(value);
}
/**
* Helper function for register reading.
*
* @param opMode: "operating mode" specifier, see datasheet for details.
* @param addr: register number.
* @return current value of the addressed register.
*/
uint8_t readReg(const M opMode, const uint8_t addr)
{
ScopedChipSelect cs;
(void) uSpi_sendRecv(static_cast< uint8_t >(opMode) | 0x80);
(void) uSpi_sendRecv(addr);
return uSpi_sendRecv(0x00);
}
/**
* Send a configuration sequence to the chipset. Configuration sequences are
* blocks of data sent contiguously.
*
* @param seq: pointer to the configuration sequence to be sent.
* @param len: length of the configuration sequence.
*/
void sendSequence(const uint8_t *seq, const size_t len)
{
ScopedChipSelect cs;
for(size_t i = 0; i < len; i++)
{
(void) uSpi_sendRecv(seq[i]);
}
}
/**
* Initialise the low-level driver which manages "user" SPI interface, that
* is the one used to configure the chipset functionalities.
*/
void uSpi_init();
/**
* Transfer one byte across the "user" SPI interface.
*
* @param value: value to be sent.
* @return incoming byte from the baseband chip.
*/
uint8_t uSpi_sendRecv(const uint8_t value);
};
/**
* \internal
* Specialisation of logical OR operator to allow composition of FmConfig fields.
* This allows to have code like: "FmConfig::BPF_EN | FmConfig::WB_MODE"
*/
FmConfig operator |(FmConfig lhs, FmConfig rhs);
/**
* \internal
* RAII class for chip select management.
*/
class ScopedChipSelect
{
public:
/**
* Constructor.
* When called it brings the HR_C5000/HR_C6000 chip select to logical low,
* selecting it.
*/
ScopedChipSelect();
/**
* Destructor.
* When called it brings the HR_C5000/HR_C6000 chip select to logical high,
* deselecting it.
*/
~ScopedChipSelect();
};
#endif // __cplusplus
#endif // HRCx000_H

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platform/drivers/baseband/interfaces.h
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/***************************************************************************
* Copyright (C) 2020 by Federico Amedeo Izzo IU2NUO, *
* Niccolò Izzo IU2KIN *
* Frederik Saraci IU2NRO *
* Silvano Seva IU2KWO *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 3 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, see <http://www.gnu.org/licenses/> *
***************************************************************************/
#ifndef INTERFACES_H
#define INTERFACES_H
#include <stdint.h>
/*
* This file provides a standard interface for low-level data exchange with the
* baseband chipset (HR_C6000, AT1846S, ...).
* Its aim is to provide a decoupling layer between the chipset drivers, written
* to be platform-agnostic, and the platform-specific communication busses.
*/
/**
* HR_C5000 and HR_C6000: initialise "user" SPI interface, the one for chip
* configuration.
*/
void uSpi_init();
/**
* HR_C5000 and HR_C6000: transfer one byte over the "user" SPI interface.
*/
uint8_t uSpi_sendRecv(uint8_t val);
#endif /* INTERFACES_H */

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platform/drivers/baseband/interfaces_GDx.c
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/***************************************************************************
* Copyright (C) 2020 by Federico Amedeo Izzo IU2NUO, *
* Niccolò Izzo IU2KIN *
* Frederik Saraci IU2NRO *
* Silvano Seva IU2KWO *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 3 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, see <http://www.gnu.org/licenses/> *
***************************************************************************/
#include <hwconfig.h>
#include <interfaces/gpio.h>
#include <interfaces/delays.h>
#include <interfaces/platform.h>
#include <stdint.h>
#include <string.h>
#include <I2C0.h>
#include "interfaces.h"
/*
* Implementation of HR_C6000 "user" SPI interface.
*/
void uSpi_init()
{
gpio_setMode(DMR_CLK, OUTPUT);
gpio_setMode(DMR_MOSI, OUTPUT);
gpio_setMode(DMR_MISO, INPUT);
gpio_setAlternateFunction(DMR_CLK, 0);
gpio_setAlternateFunction(DMR_MOSI, 0);
gpio_setAlternateFunction(DMR_MISO, 0);
SIM->SCGC6 |= SIM_SCGC6_SPI0_MASK;
SPI0->MCR &= ~SPI_MCR_MDIS_MASK; /* Enable the SPI0 module */
SPI0->MCR |= SPI_MCR_MSTR_MASK /* Master mode */
| SPI_MCR_PCSIS_MASK /* CS high when inactive */
| SPI_MCR_DIS_RXF_MASK /* Disable RX FIFO */
| SPI_MCR_DIS_TXF_MASK /* Disable TX FIFO */
| SPI_MCR_HALT_MASK; /* Stop transfers */
SPI0->CTAR[0] = SPI_CTAR_FMSZ(7) /* 8bit frame size */
| SPI_CTAR_CPHA_MASK /* CPHA = 1 */
| SPI_CTAR_PBR(2) /* CLK prescaler divide by 5 */
| SPI_CTAR_BR(3) /* CLK scaler divide by 8 */
| SPI_CTAR_PCSSCK(1)
| SPI_CTAR_PASC(1)
| SPI_CTAR_CSSCK(4)
| SPI_CTAR_ASC(4);
}
uint8_t uSpi_sendRecv(uint8_t val)
{
SPI0->MCR &= ~SPI_MCR_HALT_MASK; /* Start transfer */
SPI0->MCR |= SPI_MCR_CLR_TXF_MASK | SPI_MCR_CLR_RXF_MASK;
while((SPI0->SR & SPI_SR_TFFF_MASK) == 0) ;
SPI0->PUSHR = SPI_PUSHR_EOQ_MASK | val;
SPI0->SR |= SPI_SR_TFFF_MASK;
while((SPI0->SR & SPI_SR_RFDF_MASK) == 0) ;
SPI0->SR |= SPI_SR_RFDF_MASK;
SPI0->MCR |= SPI_MCR_HALT_MASK; /* Start transfer */
return SPI0->POPR;
}

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platform/drivers/baseband/interfaces_UV3x0.c
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/***************************************************************************
* Copyright (C) 2020 by Federico Amedeo Izzo IU2NUO, *
* Niccolò Izzo IU2KIN *
* Frederik Saraci IU2NRO *
* Silvano Seva IU2KWO *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 3 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, see <http://www.gnu.org/licenses/> *
***************************************************************************/
#include <hwconfig.h>
#include <interfaces/gpio.h>
#include <interfaces/delays.h>
#include <interfaces/platform.h>
#include <stdint.h>
#include <string.h>
#include <stdbool.h>
#include "interfaces.h"
/*
* Implementation of HR_C6000 "user" SPI interface.
*/
void uSpi_init()
{
gpio_setMode(DMR_CS, OUTPUT);
gpio_setMode(DMR_CLK, OUTPUT);
gpio_setMode(DMR_MOSI, OUTPUT);
gpio_setMode(DMR_MISO, OUTPUT);
}
uint8_t uSpi_sendRecv(uint8_t val)
{
gpio_clearPin(DMR_CLK);
uint8_t incoming = 0;
uint8_t cnt = 0;
for(; cnt < 8; cnt++)
{
gpio_setPin(DMR_CLK);
if(val & (0x80 >> cnt))
{
gpio_setPin(DMR_MOSI);
}
else
{
gpio_clearPin(DMR_MOSI);
}
delayUs(1);
gpio_clearPin(DMR_CLK);
incoming = (incoming << 1) | gpio_readPin(DMR_MISO);
delayUs(1);
}
return incoming;
}
/*
* Software I2C routine
*/
void _i2c_start()
{
gpio_setMode(I2C_SDA, OUTPUT);
/*
* Lines commented to keep SCL high when idle
*
gpio_clearPin(I2C_SCL);
delayUs(2);
*/
gpio_setPin(I2C_SDA);
delayUs(2);
gpio_setPin(I2C_SCL);
delayUs(2);
gpio_clearPin(I2C_SDA);
delayUs(2);
gpio_clearPin(I2C_SCL);
delayUs(6);
}
void _i2c_stop()
{
gpio_setMode(I2C_SDA, OUTPUT);
gpio_clearPin(I2C_SCL);
delayUs(2);
gpio_clearPin(I2C_SDA);
delayUs(2);
gpio_setPin(I2C_SCL);
delayUs(2);
gpio_setPin(I2C_SDA);
delayUs(2);
/*
* Lines commented to keep SCL high when idle
*
gpio_clearPin(I2C_SCL);
delayUs(2);
*/
}
void _i2c_write(uint8_t val)
{
gpio_setMode(I2C_SDA, OUTPUT);
for(uint8_t i = 0; i < 8; i++)
{
gpio_clearPin(I2C_SCL);
delayUs(1);
if(val & 0x80)
{
gpio_setPin(I2C_SDA);
}
else
{
gpio_clearPin(I2C_SDA);
}
val <<= 1;
delayUs(1);
gpio_setPin(I2C_SCL);
delayUs(2);
}
/* Ensure SCL is low before releasing SDA */
gpio_clearPin(I2C_SCL);
/* Clock cycle for slave ACK/NACK */
gpio_setMode(I2C_SDA, INPUT_PULL_UP);
delayUs(2);
gpio_setPin(I2C_SCL);
delayUs(2);
gpio_clearPin(I2C_SCL);
delayUs(1);
/* Asserting SDA pin allows to fastly bring the line to idle state */
gpio_setPin(I2C_SDA);
gpio_setMode(I2C_SDA, OUTPUT);
delayUs(6);
}
uint8_t _i2c_read(bool ack)
{
gpio_setMode(I2C_SDA, INPUT_PULL_UP);
gpio_clearPin(I2C_SCL);
uint8_t value = 0;
for(uint8_t i = 0; i < 8; i++)
{
delayUs(2);
gpio_setPin(I2C_SCL);
delayUs(2);
value <<= 1;
value |= gpio_readPin(I2C_SDA);
gpio_clearPin(I2C_SCL);
}
/*
* Set ACK/NACK state BEFORE putting SDA gpio to output mode.
* This avoids spurious spikes which can be interpreted as NACKs
*/
gpio_clearPin(I2C_SDA);
gpio_setMode(I2C_SDA, OUTPUT);
delayUs(2);
if(!ack) gpio_setPin(I2C_SDA);
/* Clock cycle for ACK/NACK */
delayUs(2);
gpio_setPin(I2C_SCL);
delayUs(2);
gpio_clearPin(I2C_SCL);
delayUs(2);
return value;
}