kopia lustrzana https://github.com/OpenRTX/OpenRTX
Reorganized MDx nonvolatile memory devices
Silvano Seva
rodzic
e0c3623d11
commit
0aa2818d4a
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@ -279,14 +279,6 @@ int W25Qx_writeData(uint32_t addr, const void *buf, size_t len)
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return 0;
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}
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static const struct nvmParams W25Qx_params =
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{
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.write_size = 1,
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.erase_size = SECT_SIZE,
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.erase_cycles = 100000,
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.type = NVM_FLASH
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};
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static int nvm_api_readSecReg(const struct nvmDevice *dev, uint32_t offset, void *data, size_t len)
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{
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(void) dev;
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@ -315,27 +307,34 @@ static int nvm_api_erase(const struct nvmDevice *dev, uint32_t offset, size_t si
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return W25Qx_erase(offset, size);
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}
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static const struct nvmParams *nvm_api_params(const struct nvmDevice *dev)
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{
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(void) dev;
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return &W25Qx_params;
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}
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const struct nvmApi W25Qx_api =
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const struct nvmOps W25Qx_ops =
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{
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.read = nvm_api_read,
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.write = nvm_api_write,
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.erase = nvm_api_erase,
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.sync = NULL,
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.params = nvm_api_params
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};
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const struct nvmApi W25Qx_secReg_api =
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const struct nvmOps W25Qx_secReg_ops =
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{
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.read = nvm_api_readSecReg,
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.write = NULL,
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.erase = NULL,
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.sync = NULL,
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.params = nvm_api_params
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};
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const struct nvmInfo W25Qx_info =
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{
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.write_size = 1,
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.erase_size = SECT_SIZE,
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.erase_cycles = 100000,
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.device_info = NVM_FLASH | NVM_WRITE | NVM_BITWRITE | NVM_ERASE
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};
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const struct nvmInfo W25Qx_secReg_info =
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{
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.write_size = 0,
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.erase_size = 0,
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.erase_cycles = 0,
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.device_info = NVM_FLASH
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};
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@ -32,28 +32,56 @@
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*/
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/**
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* Device driver API for W25Qx main memory.
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* Driver data structure for W25Qx security registers.
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*/
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extern const struct nvmApi W25Qx_api;
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struct w25qSecRegDevice
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{
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const struct nvmOps *ops; ///< Device operations
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const struct nvmInfo *info; ///< Device info
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const size_t size; ///< Device size
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const uint32_t baseAddr; ///< Register base address
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};
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/**
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* Device driver API for W25Qx security registers.
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* Device driver and information block for W25Qx main memory.
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*/
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extern const struct nvmApi W25Qx_secReg_api;
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extern const struct nvmOps W25Qx_ops;
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extern const struct nvmInfo W25Qx_info;
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/**
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* Instantiate an W25Qx nonvolatile memory device.
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*
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* @param name: device name.
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* @param driver: device driver API.
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* @param sz: memory size, in bytes.
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*/
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#define W25Qx_DEVICE_DEFINE(name, driver) \
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struct nvmDevice name = \
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{ \
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.config = NULL, \
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.priv = NULL, \
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.api = &driver \
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#define W25Qx_DEVICE_DEFINE(name, sz) \
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struct nvmDevice name = \
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{ \
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.ops = &W25Qx_ops, \
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.info = &W25Qx_info, \
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.size = sz \
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};
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/**
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* Device driver and information block for W25Qx security registers area.
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*/
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extern const struct nvmOps W25Qx_secReg_ops;
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extern const struct nvmInfo W25Qx_secReg_info;
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/**
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* Instantiate an W25Qx security register memory device.
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*
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* @param name: device name.
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* @param base: security register base address.
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* @param sz: memory size, in bytes.
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*/
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#define W25Qx_SECREG_DEFINE(name, base, sz) \
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struct w25qSecRegDevice name = \
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{ \
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.ops = &W25Qx_secReg_ops, \
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.info = &W25Qx_secReg_info, \
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.size = sz, \
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.baseAddr = base \
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};
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/**
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@ -26,30 +26,28 @@
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#include <utils.h>
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#include "W25Qx.h"
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W25Qx_DEVICE_DEFINE(W25Q128_main, W25Qx_api)
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W25Qx_DEVICE_DEFINE(W25Q128_secr, W25Qx_secReg_api)
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W25Qx_DEVICE_DEFINE(eflash, 0x1000000) // 16 MB, 128 Mbit
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W25Qx_SECREG_DEFINE(cal1, 0x1000, 0x100) // 256 byte
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W25Qx_SECREG_DEFINE(cal2, 0x2000, 0x100) // 256 byte
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static const struct nvmArea areas[] =
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static const struct nvmDescriptor nvmDevices[] =
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{
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{
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.name = "External flash",
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.dev = &W25Q128_main,
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.startAddr = 0x0000,
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.size = 0x1000000, // 16 MB, 128 Mbit
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.dev = &eflash,
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.partNum = 0,
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.partitions = NULL
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},
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{
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.name = "Cal. data 1",
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.dev = &W25Q128_secr,
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.startAddr = 0x1000,
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.size = 0x100, // 256 byte
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.dev = (const struct nvmDevice *) &cal1,
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.partNum = 0,
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.partitions = NULL
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},
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{
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.name = "Cal. data 2",
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.dev = &W25Q128_secr,
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.startAddr = 0x2000,
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.size = 0x100, // 256 byte
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.dev = (const struct nvmDevice *) &cal2,
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.partNum = 0,
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.partitions = NULL
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}
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};
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@ -65,11 +63,12 @@ void nvm_terminate()
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W25Qx_terminate();
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}
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size_t nvm_getMemoryAreas(const struct nvmArea **list)
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const struct nvmDescriptor *nvm_getDesc(const size_t index)
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{
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*list = &areas[0];
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if(index > 3)
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return NULL;
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return (sizeof(areas) / sizeof(struct nvmArea));
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return &nvmDevices[index];
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}
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void nvm_readCalibData(void *buf)
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@ -26,30 +26,28 @@
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#include <utils.h>
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#include "W25Qx.h"
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W25Qx_DEVICE_DEFINE(W25Q128_main, W25Qx_api)
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W25Qx_DEVICE_DEFINE(W25Q128_secr, W25Qx_secReg_api)
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W25Qx_DEVICE_DEFINE(eflash, 0x1000000) // 16 MB, 128 Mbit
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W25Qx_SECREG_DEFINE(cal1, 0x1000, 0x100) // 256 byte
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W25Qx_SECREG_DEFINE(cal2, 0x2000, 0x100) // 256 byte
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static const struct nvmArea areas[] =
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static const struct nvmDescriptor nvmDevices[] =
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{
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{
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.name = "External flash",
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.dev = &W25Q128_main,
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.startAddr = 0x0000,
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.size = 0x1000000, // 16 MB, 128 Mbit
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.dev = &eflash,
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.partNum = 0,
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.partitions = NULL
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},
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{
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.name = "Cal. data 1",
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.dev = &W25Q128_secr,
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.startAddr = 0x1000,
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.size = 0x100, // 256 byte
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.dev = (const struct nvmDevice *) &cal1,
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.partNum = 0,
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.partitions = NULL
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},
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{
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.name = "Cal. data 2",
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.dev = &W25Q128_secr,
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.startAddr = 0x2000,
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.size = 0x100, // 256 byte
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.dev = (const struct nvmDevice *) &cal2,
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.partNum = 0,
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.partitions = NULL
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}
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};
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@ -65,11 +63,12 @@ void nvm_terminate()
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W25Qx_terminate();
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}
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size_t nvm_getMemoryAreas(const struct nvmArea **list)
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const struct nvmDescriptor *nvm_getDesc(const size_t index)
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{
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*list = &areas[0];
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if(index > 3)
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return NULL;
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return (sizeof(areas) / sizeof(struct nvmArea));
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return &nvmDevices[index];
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}
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void nvm_readCalibData(void *buf)
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@ -26,30 +26,28 @@
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#include <utils.h>
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#include "W25Qx.h"
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W25Qx_DEVICE_DEFINE(W25Q128_main, W25Qx_api)
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W25Qx_DEVICE_DEFINE(W25Q128_secr, W25Qx_secReg_api)
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W25Qx_DEVICE_DEFINE(eflash, 0x1000000) // 16 MB, 128 Mbit
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W25Qx_SECREG_DEFINE(cal1, 0x1000, 0x100) // 256 byte
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W25Qx_SECREG_DEFINE(cal2, 0x2000, 0x100) // 256 byte
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static const struct nvmArea areas[] =
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static const struct nvmDescriptor nvmDevices[] =
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{
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{
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.name = "External flash",
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.dev = &W25Q128_main,
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.startAddr = 0x0000,
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.size = 0x1000000, // 16 MB, 128 Mbit
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.dev = &eflash,
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.partNum = 0,
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.partitions = NULL
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},
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{
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.name = "Cal. data 1",
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.dev = &W25Q128_secr,
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.startAddr = 0x1000,
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.size = 0x100, // 256 byte
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.dev = (const struct nvmDevice *) &cal1,
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.partNum = 0,
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.partitions = NULL
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},
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{
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.name = "Cal. data 2",
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.dev = &W25Q128_secr,
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.startAddr = 0x2000,
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.size = 0x100, // 256 byte
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.dev = (const struct nvmDevice *) &cal2,
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.partNum = 0,
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.partitions = NULL
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}
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};
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@ -65,11 +63,12 @@ void nvm_terminate()
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W25Qx_terminate();
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}
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size_t nvm_getMemoryAreas(const struct nvmArea **list)
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const struct nvmDescriptor *nvm_getDesc(const size_t index)
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{
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*list = &areas[0];
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if(index > 3)
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return NULL;
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return (sizeof(areas) / sizeof(struct nvmArea));
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return &nvmDevices[index];
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}
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void nvm_readCalibData(void *buf)
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