kopia lustrzana https://github.com/Jean-MarcHarvengt/MCUME
1044 wiersze
37 KiB
C
1044 wiersze
37 KiB
C
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static char *disass_cc(unsigned char cc)
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{
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switch(cc) {
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case 0:
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return "T ";
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case 1:
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return "F ";
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case 2:
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return "HI";
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case 3:
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return "LS";
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case 4:
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return "CC";
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case 5:
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return "CS";
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case 6:
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return "NE";
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case 7:
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return "EQ";
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case 8:
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return "VC";
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case 9:
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return "VS";
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case 0xa:
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return "PL";
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case 0xb:
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return "MI";
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case 0xc:
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return "GE";
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case 0xd:
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return "LT";
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case 0xe:
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return "GT";
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case 0xf:
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return "LE";
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default:
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return "??";
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}
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}
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static char *disass_areg(unsigned char spec)
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{
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switch (spec) {
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case 0: return "A0";
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case 1: return "A1";
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case 2: return "A2";
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case 3: return "A3";
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case 4: return "A4";
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case 5: return "A5";
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case 6: return "A6";
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case 7: return "A7";
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default: return "??";
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}
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}
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static char *disass_dreg(unsigned char spec)
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{
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switch (spec) {
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case 0: return "D0";
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case 1: return "D1";
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case 2: return "D2";
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case 3: return "D3";
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case 4: return "D4";
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case 5: return "D5";
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case 6: return "D6";
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case 7: return "D7";
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default: return "??";
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}
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}
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static char *disass_reg(unsigned char spec)
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{
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if (spec >= 8) return disass_areg(spec & 0x7);
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else return disass_dreg(spec);
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}
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static void disass_reglist(char *buf, unsigned short reglist, int predecrement)
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{
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int index = 0, len;
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*buf = 0;
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if (!predecrement) {
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while (reglist) {
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if (reglist & 0x1) {
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strcat(buf, disass_reg(index));
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strcat(buf, "/");
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}
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index++;
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reglist = reglist >> 1;
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}
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} else {
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while (reglist) {
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if (reglist & 0x8000) {
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strcat(buf, disass_reg(index));
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strcat(buf, "/");
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}
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index++;
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reglist = reglist << 1;
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}
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}
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/* remove trailing / */
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len = strlen(buf);
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if (len > 0) *(buf + len - 1) = 0;
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}
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static int disass_count(unsigned char spec)
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{
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if (spec == 0) return 8;
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else return spec;
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}
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/*
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* return # of extension words used for addressing
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*/
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static int disass_displacement(char *buf, unsigned short *inst_stream, char displacement)
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{
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if (displacement == 0) {
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sprintf(buf, "%04x", inst_stream[1]);
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return 1;
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} else if (displacement == -1) {
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sprintf(buf, "%04x%04x", inst_stream[1], inst_stream[2]);
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return 2;
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} else {
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sprintf(buf, "%02x", displacement);
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return 0;
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}
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}
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/*
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* return # of extension words used for addressing
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*/
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static int disass_ea(char *buf, unsigned short *inst_stream, unsigned char mode, unsigned char spec, unsigned char size)
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{
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switch(mode) {
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case 0:
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strcpy(buf, disass_dreg(spec));
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return 0;
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case 1:
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strcpy(buf, disass_areg(spec));
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return 0;
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case 2:
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sprintf(buf, "(%s)", disass_areg(spec));
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return 0;
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case 3:
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sprintf(buf, "(%s)+", disass_areg(spec));
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return 0;
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case 4:
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sprintf(buf, "-(%s)", disass_areg(spec));
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return 0;
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case 5:
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sprintf(buf, "%04x(%s)", inst_stream[1], disass_areg(spec));
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return 1;
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case 6: // TODO: 680x0 full extension format
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sprintf(buf, "(%02x(%s,%s.%c*%x)",
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(char) inst_stream[1], disass_areg(spec),
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disass_reg(inst_stream[1] >> 12),
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(inst_stream[1] & 0x0800)?'L':'W',
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1 << ((inst_stream[1] & 0x0600) >> 9));
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return 1;
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case 7:
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switch(spec) {
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case 0:
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sprintf(buf, "%04x", inst_stream[1]);
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return 1;
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case 1:
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sprintf(buf, "%04x%04x", inst_stream[1], inst_stream[2]);
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return 2;
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case 2:
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sprintf(buf, "%04x(PC)", inst_stream[1]);
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return 1;
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case 3: // TODO: 680x0 full extension format
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sprintf(buf, "(%02x(PC,%s.%c*%x)",
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(char) inst_stream[1],
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disass_reg(inst_stream[1] >> 12),
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(inst_stream[1] & 0x0800)?'L':'W',
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1 << ((inst_stream[1] & 0x0600) >> 9));
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return 1;
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case 4:
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switch(size) {
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case 0:
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case 1:
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sprintf(buf, "#%04x", inst_stream[1]);
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return 1;
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case 2:
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sprintf(buf, "#%04x%04x", inst_stream[1], inst_stream[2]);
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return 2;
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case 3:
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sprintf(buf, "???");
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return 0;
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}
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}
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}
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sprintf (buf, "???");
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return 0;
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}
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void disassemble68k(char *buf, unsigned short *inst_stream)
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{
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char src_ea_buf[80];
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char tgt_ea_buf[80];
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unsigned char src_mode = (inst_stream[0] & 0x0038) >> 3;
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unsigned char src_spec = (inst_stream[0] & 0x0007);
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unsigned char src_size = (inst_stream[0] & 0x00c0) >> 6;
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unsigned char tgt_mode = (inst_stream[0] & 0x01c0) >> 6;
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unsigned char tgt_spec = (inst_stream[0] & 0x0e00) >> 9;
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unsigned char condition = (inst_stream[0] & 0x0f00) >> 8;
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int wc;
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switch (inst_stream[0] & 0xf000) {
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case 0x0000:
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// TODO: CAS2, CAS
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disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, src_size);
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switch (inst_stream[0]) {
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case 0x003c:
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sprintf(buf, "ORI.B #%02x,CCR", (char) inst_stream[1]);
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return;
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case 0x007c:
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sprintf(buf, "ORI.W #%04x,SR", inst_stream[1]);
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return;
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case 0x013c:
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sprintf(buf, "ANDI.B #%02x,CCR", (char) inst_stream[1]);
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return;
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case 0x017c:
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sprintf(buf, "ANDI.W #%04x,SR", inst_stream[1]);
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return;
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case 0x0a3c:
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sprintf(buf, "EORI.B #%02x,CCR", (char) inst_stream[1]);
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return;
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case 0x0a7c:
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sprintf(buf, "EORI.W #%04x,SR", inst_stream[1]);
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return;
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}
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switch (inst_stream[0] & 0x0fc0) {
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case 0x0000:
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sprintf(buf, "ORI.B #%02x,%s", (char) inst_stream[1], src_ea_buf);
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return;
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case 0x0040:
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sprintf(buf, "ORI.W #%04x,%s", inst_stream[1], src_ea_buf);
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return;
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case 0x0080:
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sprintf(buf, "ORI.L #%04x%04x,%s", inst_stream[1], inst_stream[2], src_ea_buf);
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return;
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case 0x0200:
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sprintf(buf, "ANDI.B #%02x,%s", (char) inst_stream[1], src_ea_buf);
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return;
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case 0x0240:
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sprintf(buf, "ANDI.W #%04x,%s", inst_stream[1], src_ea_buf);
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return;
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case 0x0280:
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sprintf(buf, "ANDI.L #%04x%04x,%s", inst_stream[1], inst_stream[2], src_ea_buf);
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return;
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case 0x0400:
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sprintf(buf, "SUBI.B #%02x,%s", (char) inst_stream[1], src_ea_buf);
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return;
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case 0x0440:
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sprintf(buf, "SUBI.W #%04x,%s", inst_stream[1], src_ea_buf);
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return;
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case 0x0480:
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sprintf(buf, "SUBI.L #%04x%04x,%s", inst_stream[1], inst_stream[2], src_ea_buf);
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return;
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case 0x0600:
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sprintf(buf, "ADDI.B #%02x,%s", (char) inst_stream[1], src_ea_buf);
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return;
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case 0x0640:
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sprintf(buf, "ADDI.W #%04x,%s", inst_stream[1], src_ea_buf);
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return;
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case 0x0680:
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sprintf(buf, "ADDI.L #%04x%04x,%s", inst_stream[1], inst_stream[2], src_ea_buf);
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return;
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case 0x0800:
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sprintf(buf, "BTST #%02x,%s", (char) inst_stream[1], src_ea_buf);
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return;
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case 0x0840:
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sprintf(buf, "BCHG #%02x,%s", (char) inst_stream[1], src_ea_buf);
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return;
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case 0x0880:
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sprintf(buf, "BCLR #%02x,%s", (char) inst_stream[1], src_ea_buf);
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return;
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case 0x08c0:
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sprintf(buf, "BSET #%02x,%s", (char) inst_stream[1], src_ea_buf);
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return;
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case 0x0a00:
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sprintf(buf, "EORI.B #%02x,%s", (char) inst_stream[1], src_ea_buf);
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return;
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case 0x0a40:
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sprintf(buf, "EORI.W #%04x,%s", inst_stream[1], src_ea_buf);
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return;
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case 0x0a80:
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sprintf(buf, "EORI.L #%04x%04x,%s", inst_stream[1], inst_stream[2], src_ea_buf);
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return;
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case 0x0c00:
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sprintf(buf, "CMPI.B #%02x,%s", (char) inst_stream[1], src_ea_buf);
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return;
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case 0x0c40:
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sprintf(buf, "CMPI.W #%04x,%s", inst_stream[1], src_ea_buf);
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return;
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case 0x0c80:
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sprintf(buf, "CMPI.L #%04x%04x,%s", inst_stream[1], inst_stream[2], src_ea_buf);
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return;
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case 0x0e00:
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switch (inst_stream[1] & 0x0800) {
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case 0x0000: sprintf(buf, "MOVES.B %s,%s", src_ea_buf, disass_reg((inst_stream[1] >> 12) & 0xf));
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return;
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case 0x0800: sprintf(buf, "MOVES.B %s,%s", disass_reg((inst_stream[1] >> 12) & 0xf), src_ea_buf);
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return;
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}
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case 0x0e40:
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switch (inst_stream[1] & 0x0800) {
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case 0x0000: sprintf(buf, "MOVES.W %s,%s", src_ea_buf, disass_reg((inst_stream[1] >> 12) & 0xf));
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return;
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case 0x0800: sprintf(buf, "MOVES.W %s,%s", disass_reg((inst_stream[1] >> 12) & 0xf), src_ea_buf);
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return;
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}
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case 0x0e80:
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switch (inst_stream[1] & 0x0800) {
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case 0x0000: sprintf(buf, "MOVES.L %s,%s", src_ea_buf, disass_reg((inst_stream[1] >> 12) & 0xf));
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return;
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case 0x0800: sprintf(buf, "MOVES.L %s,%s", disass_reg((inst_stream[1] >> 12) & 0xf), src_ea_buf);
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return;
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}
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case 0x06c0:
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switch (inst_stream[0] & 0x0030) {
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case 0x0000: sprintf(buf, "RTM %s", disass_reg(inst_stream[0] & 0xf));
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return;
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case 0x0030: sprintf(buf, "CALLM %s", src_ea_buf);
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return;
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}
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case 0x00c0:
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disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, 0);
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switch (inst_stream[1] & 0x0800) {
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case 0x0000: sprintf(buf, "CMP2.B %s,%s", src_ea_buf, disass_reg((inst_stream[1] >> 12) & 0xf));
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return;
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case 0x0800: sprintf(buf, "CHK2.B %s,%s", src_ea_buf, disass_reg((inst_stream[1] >> 12) & 0xf));
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return;
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}
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case 0x02c0:
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disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, 1);
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switch (inst_stream[1] & 0x0800) {
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case 0x0000: sprintf(buf, "CMP2.W %s,%s", src_ea_buf, disass_reg((inst_stream[1] >> 12) & 0xf));
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return;
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case 0x0800: sprintf(buf, "CHK2.W %s,%s", src_ea_buf, disass_reg((inst_stream[1] >> 12) & 0xf));
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return;
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}
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case 0x04c0:
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disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, 2);
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switch (inst_stream[1] & 0x0800) {
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case 0x0000: sprintf(buf, "CMP2.L %s,%s", src_ea_buf, disass_reg((inst_stream[1] >> 12) & 0xf));
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return;
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case 0x0800: sprintf(buf, "CHK2.L %s,%s", src_ea_buf, disass_reg((inst_stream[1] >> 12) & 0xf));
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return;
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}
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}
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if (inst_stream[0] & 0x0100) {
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if (src_mode == 1) {
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switch (tgt_mode) {
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case 0x0100: sprintf(buf, "MOVEP.W #%04x(%s),%s", inst_stream[1], disass_areg(src_spec), disass_dreg(tgt_spec));
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return;
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case 0x0140: sprintf(buf, "MOVEP.L #%04x(%s),%s", inst_stream[1], disass_areg(src_spec), disass_dreg(tgt_spec));
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return;
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case 0x0180: sprintf(buf, "MOVEP.W %s,#%04x(%s)", disass_dreg(tgt_spec), inst_stream[1], disass_areg(src_spec));
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return;
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case 0x01c0: sprintf(buf, "MOVEP.L %s,#%04x(%s)", disass_dreg(tgt_spec), inst_stream[1], disass_areg(src_spec));
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return;
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}
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}
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switch (inst_stream[0] & 0x0030) {
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case 0x0000: sprintf(buf, "BTST %s,%s", disass_dreg(tgt_spec), src_ea_buf);
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return;
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case 0x0010: sprintf(buf, "BCHG %s,%s", disass_dreg(tgt_spec), src_ea_buf);
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return;
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case 0x0020: sprintf(buf, "BCLR %s,%s", disass_dreg(tgt_spec), src_ea_buf);
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return;
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case 0x0030: sprintf(buf, "BSET %s,%s", disass_dreg(tgt_spec), src_ea_buf);
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return;
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}
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}
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case 0x1000: /* Move Byte */
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wc = disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, 0);
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disass_ea(tgt_ea_buf, inst_stream + wc, tgt_mode, tgt_spec, 0);
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sprintf(buf, "MOVE.B %s,%s", src_ea_buf, tgt_ea_buf);
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return;
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case 0x2000: /* Move Long */
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wc = disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, 2);
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disass_ea(tgt_ea_buf, inst_stream + wc, tgt_mode, tgt_spec, 2);
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sprintf(buf, "MOVE.L %s,%s", src_ea_buf, tgt_ea_buf);
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return;
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case 0x3000: /* Move Word */
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wc = disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, 1);
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disass_ea(tgt_ea_buf, inst_stream + wc, tgt_mode, tgt_spec, 1);
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sprintf(buf, "MOVE.W %s,%s", src_ea_buf, tgt_ea_buf);
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return;
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case 0x4000: /* Miscellaneous */
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// TODO: MULU.L, MULS.L, DIVU.L, DIVS.L, EXTB.L
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disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, src_size);
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switch (inst_stream[0] & 0xffc0) {
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case 0x4000:
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sprintf(buf, "NEGX.B %s", src_ea_buf);
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return;
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case 0x4040:
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sprintf(buf, "NEGX.W %s", src_ea_buf);
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return;
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case 0x4080:
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sprintf(buf, "NEGX.L %s", src_ea_buf);
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return;
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case 0x40c0:
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disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, 1);
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sprintf(buf, "MOVE.W SR,%s", src_ea_buf);
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return;
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case 0x4200:
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sprintf(buf, "CLR.B %s", src_ea_buf);
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return;
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case 0x4240:
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sprintf(buf, "CLR.W %s", src_ea_buf);
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return;
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case 0x4280:
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sprintf(buf, "CLR.L %s", src_ea_buf);
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return;
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case 0x42c0:
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disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, 1);
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sprintf(buf, "MOVE.W CCR,%s", src_ea_buf);
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return;
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case 0x4400:
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sprintf(buf, "NEG.B %s", src_ea_buf);
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return;
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case 0x4440:
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sprintf(buf, "NEG.W %s", src_ea_buf);
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return;
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case 0x4480:
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sprintf(buf, "NEG.L %s", src_ea_buf);
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return;
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case 0x44c0:
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disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, 1);
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sprintf(buf, "MOVE.W %s,CCR", src_ea_buf);
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return;
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case 0x4600:
|
|
disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, 1);
|
|
sprintf(buf, "NOT.B %s", src_ea_buf);
|
|
return;
|
|
case 0x4640:
|
|
sprintf(buf, "NOT.W %s", src_ea_buf);
|
|
return;
|
|
case 0x4680:
|
|
sprintf(buf, "NOT.L %s", src_ea_buf);
|
|
return;
|
|
case 0x46c0:
|
|
disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, 1);
|
|
sprintf(buf, "MOVE.W %s,SR", src_ea_buf);
|
|
return;
|
|
case 0x4800:
|
|
if (src_mode == 1) {
|
|
sprintf(buf, "LINK.L #%04x%04x,%s",
|
|
inst_stream[1], inst_stream[2], disass_areg(src_spec));
|
|
} else {
|
|
sprintf(buf, "NBCD %s", src_ea_buf);
|
|
}
|
|
return;
|
|
case 0x4840:
|
|
if (src_mode == 0) {
|
|
sprintf(buf, "SWAP.W %s", disass_dreg(src_spec));
|
|
} else if (src_mode == 1) {
|
|
sprintf(buf, "BKPT #%x", src_spec);
|
|
} else {
|
|
sprintf(buf, "PEA %s", src_ea_buf);
|
|
}
|
|
return;
|
|
case 0x4880:
|
|
if (src_mode == 0) {
|
|
sprintf(buf, "EXT.W %s", disass_dreg(src_spec));
|
|
} else {
|
|
disass_reglist(tgt_ea_buf, inst_stream[1], src_mode == 6);
|
|
disass_ea(src_ea_buf, inst_stream + 1, src_mode, src_spec, src_size);
|
|
sprintf(buf, "MOVEM.W %s,%s", tgt_ea_buf, src_ea_buf);
|
|
}
|
|
return;
|
|
case 0x48c0:
|
|
if (src_mode == 0) {
|
|
sprintf(buf, "EXT.L %s", disass_dreg(src_spec));
|
|
} else {
|
|
disass_reglist(tgt_ea_buf, inst_stream[1], src_mode == 6);
|
|
disass_ea(src_ea_buf, inst_stream + 1, src_mode, src_spec, src_size);
|
|
sprintf(buf, "MOVEM.L %s,%s", tgt_ea_buf, src_ea_buf);
|
|
}
|
|
return;
|
|
case 0x4a00:
|
|
sprintf(buf, "TST.B %s", src_ea_buf);
|
|
return;
|
|
case 0x4a40:
|
|
sprintf(buf, "TST.W %s", src_ea_buf);
|
|
return;
|
|
case 0x4a80:
|
|
sprintf(buf, "TST.L %s", src_ea_buf);
|
|
return;
|
|
case 0x4ac0:
|
|
switch (inst_stream[0] & 0x003f) {
|
|
case 0x003a:
|
|
sprintf(buf, "BGND ");
|
|
return;
|
|
case 0x003c:
|
|
sprintf(buf, "ILLEGAL");
|
|
return;
|
|
default:
|
|
disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, 0);
|
|
sprintf(buf, "TAS %s", src_ea_buf);
|
|
return;
|
|
}
|
|
case 0x4c80:
|
|
if (src_mode == 0) {
|
|
} else {
|
|
disass_reglist(tgt_ea_buf, inst_stream[1], src_mode == 6);
|
|
disass_ea(src_ea_buf, inst_stream + 1, src_mode, src_spec, src_size);
|
|
sprintf(buf, "MOVEM.W %s,%s", src_ea_buf, tgt_ea_buf);
|
|
}
|
|
return;
|
|
case 0x4cc0:
|
|
if (src_mode == 0) {
|
|
} else {
|
|
disass_reglist(tgt_ea_buf, inst_stream[1], src_mode == 6);
|
|
disass_ea(src_ea_buf, inst_stream + 1, src_mode, src_spec, 2);
|
|
sprintf(buf, "MOVEM.L %s,%s", src_ea_buf, tgt_ea_buf);
|
|
}
|
|
return;
|
|
case 0x4e40:
|
|
switch(src_mode) {
|
|
case 0:
|
|
case 1:
|
|
sprintf(buf, "TRAP #%x", inst_stream[0] & 0xf);
|
|
return;
|
|
case 2:
|
|
sprintf(buf, "LINK #%4x,%s", inst_stream[1], disass_areg(src_spec));
|
|
return;
|
|
case 3:
|
|
sprintf(buf, "UNLK %s", disass_areg(src_spec));
|
|
return;
|
|
case 4:
|
|
sprintf(buf, "MOVE.L %s,USP", disass_areg(src_spec));
|
|
return;
|
|
case 5:
|
|
sprintf(buf, "MOVE.L USP,%s", disass_areg(src_spec));
|
|
return;
|
|
case 6:
|
|
switch(inst_stream[0]) {
|
|
case 0x4e70:
|
|
sprintf(buf, "RESET ");
|
|
return;
|
|
case 0x4e71:
|
|
sprintf(buf, "NOP ");
|
|
return;
|
|
case 0x4e72:
|
|
sprintf(buf, "STOP ");
|
|
return;
|
|
case 0x4e73:
|
|
sprintf(buf, "RTE ");
|
|
return;
|
|
case 0x4e74:
|
|
sprintf(buf, "RTD ");
|
|
return;
|
|
case 0x4e75:
|
|
sprintf(buf, "RTS ");
|
|
return;
|
|
case 0x4e76:
|
|
sprintf(buf, "TRAPV ");
|
|
return;
|
|
case 0x4e77:
|
|
sprintf(buf, "RTR ");
|
|
return;
|
|
}
|
|
case 7:
|
|
switch(inst_stream[0]) {
|
|
case 0x4e7a:
|
|
sprintf(buf, "MOVEC #%04x,%s", inst_stream[1] & 0xfff, disass_reg(inst_stream[1] >> 12));
|
|
return;
|
|
case 0x4e7b:
|
|
sprintf(buf, "MOVEC #%s,%04x", disass_reg(inst_stream[1] >> 12), inst_stream[1] & 0xfff);
|
|
return;
|
|
}
|
|
}
|
|
sprintf(buf, "??? ");
|
|
return;
|
|
case 0x4e80:
|
|
sprintf(buf, "JSR %s", src_ea_buf);
|
|
return;
|
|
case 0x4ec0:
|
|
disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, 2);
|
|
sprintf(buf, "JMP %s", src_ea_buf);
|
|
return;
|
|
}
|
|
switch (tgt_mode) {
|
|
case 4:
|
|
sprintf(buf, "CHK.L %s,%s", src_ea_buf, disass_dreg(tgt_spec));
|
|
return;
|
|
case 6:
|
|
sprintf(buf, "CHK.W %s,%s", src_ea_buf, disass_dreg(tgt_spec));
|
|
return;
|
|
case 7:
|
|
sprintf(buf, "LEA %s,%s", src_ea_buf, disass_areg(tgt_spec));
|
|
return;
|
|
}
|
|
case 0x5000: /* ADDQ/SUBQ/Scc/DBcc/TRAPcc */
|
|
// TODO: TRAPcc
|
|
wc = disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, src_size);
|
|
switch (inst_stream[0] & 0x00c0) {
|
|
case 0x0000:
|
|
if (inst_stream[0] & 0x0100) {
|
|
sprintf(buf, "SUBQ.B #%x,%s", disass_count(tgt_spec), src_ea_buf);
|
|
} else {
|
|
sprintf(buf, "ADDQ.B #%x,%s", disass_count(tgt_spec), src_ea_buf);
|
|
}
|
|
return;
|
|
case 0x0040:
|
|
if (inst_stream[0] & 0x0100) {
|
|
sprintf(buf, "SUBQ.W #%x,%s", disass_count(tgt_spec), src_ea_buf);
|
|
} else {
|
|
sprintf(buf, "ADDQ.W #%x,%s", disass_count(tgt_spec), src_ea_buf);
|
|
}
|
|
return;
|
|
case 0x0080:
|
|
if (inst_stream[0] & 0x0100) {
|
|
sprintf(buf, "SUBQ.L #%x,%s", disass_count(tgt_spec), src_ea_buf);
|
|
} else {
|
|
sprintf(buf, "ADDQ.L #%x,%s", disass_count(tgt_spec), src_ea_buf);
|
|
}
|
|
return;
|
|
case 0x00c0:
|
|
if (src_mode == 1) {
|
|
disass_displacement(tgt_ea_buf, inst_stream + wc, 0);
|
|
sprintf(buf, "DB%s %s,%s", disass_cc(condition), tgt_ea_buf, disass_dreg(src_spec));
|
|
} else {
|
|
sprintf(buf, "S%s %s", disass_cc(condition), src_ea_buf);
|
|
}
|
|
return;
|
|
}
|
|
case 0x6000: /* Bcc/BSR/BRA */
|
|
disass_displacement(tgt_ea_buf, inst_stream, inst_stream[0]);
|
|
if ((inst_stream[0] & 0xff00) == 0x6000) {
|
|
sprintf(buf, "BRA %s", tgt_ea_buf);
|
|
} else if ((inst_stream[0] & 0xff00) == 0x6100) {
|
|
sprintf(buf, "BSR %s", tgt_ea_buf);
|
|
} else {
|
|
sprintf(buf, "B%s %s",disass_cc(condition), tgt_ea_buf);
|
|
}
|
|
return;
|
|
case 0x7000: /* MOVEQ */
|
|
sprintf(buf, "MOVEQ.L #%02x,%s", (char) inst_stream[0], disass_dreg(tgt_spec));
|
|
return;
|
|
case 0x8000: /* OR/DIV/SBCD */
|
|
// TODO: PACK, UNPK
|
|
disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, src_size);
|
|
switch (inst_stream[0] & 0x01c0) {
|
|
case 0x0000:
|
|
sprintf(buf, "OR.B %s,%s", src_ea_buf, disass_dreg(tgt_spec));
|
|
return;
|
|
case 0x0040:
|
|
sprintf(buf, "OR.W %s,%s", src_ea_buf, disass_dreg(tgt_spec));
|
|
return;
|
|
case 0x0080:
|
|
sprintf(buf, "OR.L %s,%s", src_ea_buf, disass_dreg(tgt_spec));
|
|
return;
|
|
case 0x00c0:
|
|
disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, 1);
|
|
sprintf(buf, "DIVU.W %s,%s", src_ea_buf, disass_dreg(tgt_spec));
|
|
return;
|
|
case 0x0100:
|
|
if (src_mode == 0) {
|
|
sprintf(buf, "SBCD %s,%s", disass_dreg(src_spec), disass_dreg(tgt_spec));
|
|
} else if (src_mode == 1) {
|
|
sprintf(buf, "SBCD -(%s),-(%s)", disass_areg(src_spec), disass_areg(tgt_spec));
|
|
} else {
|
|
sprintf(buf, "OR.B %s,%s", disass_dreg(tgt_spec), src_ea_buf);
|
|
}
|
|
return;
|
|
case 0x0140:
|
|
sprintf(buf, "OR.W %s,%s", disass_reg(tgt_spec), src_ea_buf);
|
|
return;
|
|
case 0x0180:
|
|
sprintf(buf, "OR.L %s,%s", disass_reg(tgt_spec), src_ea_buf);
|
|
return;
|
|
case 0x01c0:
|
|
disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, 1);
|
|
sprintf(buf, "DIVS.W %s,%s", src_ea_buf, disass_reg(tgt_spec));
|
|
return;
|
|
}
|
|
case 0x9000:
|
|
disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, src_size);
|
|
switch (inst_stream[0] & 0x01c0) {
|
|
case 0x0000:
|
|
sprintf(buf, "SUB.B %s,%s", src_ea_buf, disass_dreg(tgt_spec));
|
|
return;
|
|
case 0x0040:
|
|
sprintf(buf, "SUB.W %s,%s", src_ea_buf, disass_dreg(tgt_spec));
|
|
return;
|
|
case 0x0080:
|
|
sprintf(buf, "SUB.L %s,%s", src_ea_buf, disass_dreg(tgt_spec));
|
|
return;
|
|
case 0x00c0:
|
|
disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, 1);
|
|
sprintf(buf, "SUBA.W %s,%s", src_ea_buf, disass_areg(tgt_spec));
|
|
return;
|
|
case 0x0100:
|
|
if (src_mode == 0) {
|
|
sprintf(buf, "SUBX.B %s,%s", disass_dreg(src_spec), disass_dreg(tgt_spec));
|
|
} else if (src_mode == 1) {
|
|
sprintf(buf, "SUBX.B -(%s),-(%s)", disass_areg(src_spec), disass_areg(tgt_spec));
|
|
} else {
|
|
sprintf(buf, "SUB.B %s,%s", disass_dreg(tgt_spec), src_ea_buf);
|
|
}
|
|
return;
|
|
case 0x0140:
|
|
if (src_mode == 0) {
|
|
sprintf(buf, "SUBX.W %s,%s", disass_dreg(src_spec), disass_dreg(tgt_spec));
|
|
} else if (src_mode == 1) {
|
|
sprintf(buf, "SUBX.W -(%s),-(%s)", disass_areg(src_spec), disass_areg(tgt_spec));
|
|
} else {
|
|
sprintf(buf, "SUB.W %s,%s", disass_dreg(tgt_spec), src_ea_buf);
|
|
}
|
|
return;
|
|
case 0x0180:
|
|
if (src_mode == 0) {
|
|
sprintf(buf, "SUBX.L %s,%s", disass_dreg(src_spec), disass_dreg(tgt_spec));
|
|
} else if (src_mode == 1) {
|
|
sprintf(buf, "SUBX.L -(%s),-(%s)", disass_areg(src_spec), disass_areg(tgt_spec));
|
|
} else {
|
|
sprintf(buf, "SUB.L %s,%s", disass_dreg(tgt_spec), src_ea_buf);
|
|
}
|
|
return;
|
|
case 0x01c0:
|
|
disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, 2);
|
|
sprintf(buf, "SUBA.L %s,%s", src_ea_buf, disass_areg(tgt_spec));
|
|
return;
|
|
}
|
|
case 0xb000:
|
|
disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, src_size);
|
|
switch (inst_stream[0] & 0x01c0) {
|
|
case 0x0000:
|
|
sprintf(buf, "CMP.B %s,%s", src_ea_buf, disass_dreg(tgt_spec));
|
|
return;
|
|
case 0x0040:
|
|
sprintf(buf, "CMP.W %s,%s", src_ea_buf, disass_dreg(tgt_spec));
|
|
return;
|
|
case 0x0080:
|
|
sprintf(buf, "CMP.L %s,%s", src_ea_buf, disass_dreg(tgt_spec));
|
|
return;
|
|
case 0x00c0:
|
|
disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, 1);
|
|
sprintf(buf, "CMPA.W %s,%s", src_ea_buf, disass_areg(tgt_spec));
|
|
return;
|
|
case 0x0100:
|
|
if (src_mode == 1) {
|
|
sprintf(buf, "CMPM.B (%s)+,(%s)+", disass_areg(src_spec), disass_areg(tgt_spec));
|
|
} else {
|
|
sprintf(buf, "EOR.B %s,%s", disass_dreg(tgt_spec), src_ea_buf);
|
|
}
|
|
return;
|
|
case 0x0140:
|
|
if (src_mode == 1) {
|
|
sprintf(buf, "CMPM.W (%s)+,(%s)+", disass_areg(src_spec), disass_areg(tgt_spec));
|
|
} else {
|
|
sprintf(buf, "EOR.W %s,%s", disass_dreg(tgt_spec), src_ea_buf);
|
|
}
|
|
return;
|
|
case 0x0180:
|
|
if (src_mode == 1) {
|
|
sprintf(buf, "CMPM.L (%s)+,(%s)+", disass_areg(src_spec), disass_areg(tgt_spec));
|
|
} else {
|
|
sprintf(buf, "EOR.L %s,%s", disass_dreg(tgt_spec), src_ea_buf);
|
|
}
|
|
return;
|
|
case 0x01c0:
|
|
disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, 2);
|
|
sprintf(buf, "CMPA.L %s,%s", src_ea_buf, disass_areg(tgt_spec));
|
|
return;
|
|
}
|
|
case 0xc000:
|
|
disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, src_size);
|
|
switch (inst_stream[0] & 0x01c0) {
|
|
case 0x0000:
|
|
sprintf(buf, "AND.B %s,%s", src_ea_buf, disass_dreg(tgt_spec));
|
|
return;
|
|
case 0x0040:
|
|
sprintf(buf, "AND.W %s,%s", src_ea_buf, disass_dreg(tgt_spec));
|
|
return;
|
|
case 0x0080:
|
|
sprintf(buf, "AND.L %s,%s", src_ea_buf, disass_dreg(tgt_spec));
|
|
return;
|
|
case 0x00c0:
|
|
disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, 1);
|
|
sprintf(buf, "MULU.W %s,%s", src_ea_buf, disass_dreg(tgt_spec));
|
|
return;
|
|
case 0x0100:
|
|
if (src_mode == 0) {
|
|
sprintf(buf, "ABCD %s,%s", disass_dreg(src_spec), disass_dreg(tgt_spec));
|
|
} else if (src_mode == 1) {
|
|
sprintf(buf, "ABCD -(%s),-(%s)", disass_areg(src_spec), disass_reg(tgt_spec));
|
|
} else {
|
|
sprintf(buf, "AND.B %s,%s", disass_dreg(tgt_spec), src_ea_buf);
|
|
}
|
|
return;
|
|
case 0x0140:
|
|
if (src_mode == 0) {
|
|
sprintf(buf, "EXG %s,%s", disass_dreg(src_spec), disass_dreg(tgt_spec));
|
|
} else if (src_mode == 1) {
|
|
sprintf(buf, "EXG %s,%s", disass_areg(src_spec), disass_areg(tgt_spec));
|
|
} else {
|
|
sprintf(buf, "AND.W %s,%s", disass_reg(tgt_spec), src_ea_buf);
|
|
}
|
|
return;
|
|
case 0x0180:
|
|
if (src_mode == 1) {
|
|
sprintf(buf, "EXG %s,%s", disass_dreg(src_spec), disass_areg(tgt_spec));
|
|
} else {
|
|
sprintf(buf, "AND.L %s,%s", disass_dreg(tgt_spec), src_ea_buf);
|
|
}
|
|
return;
|
|
case 0x01c0:
|
|
disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, 1);
|
|
sprintf(buf, "MULS.W %s,%s", src_ea_buf, disass_dreg(tgt_spec));
|
|
return;
|
|
}
|
|
case 0xd000:
|
|
disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, src_size);
|
|
switch (inst_stream[0] & 0x01c0) {
|
|
case 0x0000:
|
|
sprintf(buf, "ADD.B %s,%s", src_ea_buf, disass_dreg(tgt_spec));
|
|
return;
|
|
case 0x0040:
|
|
sprintf(buf, "ADD.W %s,%s", src_ea_buf, disass_dreg(tgt_spec));
|
|
return;
|
|
case 0x0080:
|
|
sprintf(buf, "ADD.L %s,%s", src_ea_buf, disass_dreg(tgt_spec));
|
|
return;
|
|
case 0x00c0:
|
|
disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, 1);
|
|
sprintf(buf, "ADDA.W %s,%s", src_ea_buf, disass_areg(tgt_spec));
|
|
return;
|
|
case 0x0100:
|
|
if (src_mode == 0) {
|
|
sprintf(buf, "ADDX.B %s,%s", disass_dreg(src_spec), disass_dreg(tgt_spec));
|
|
} else if (src_mode == 0x0008) {
|
|
sprintf(buf, "ADDX.B -(%s),-(%s)", disass_areg(src_spec), disass_areg(tgt_spec));
|
|
} else {
|
|
sprintf(buf, "ADD.B %s,%s", disass_dreg(tgt_spec), src_ea_buf);
|
|
}
|
|
return;
|
|
case 0x0140:
|
|
if (src_mode == 0) {
|
|
sprintf(buf, "ADDX.W %s,%s", disass_dreg(src_spec), disass_dreg(tgt_spec));
|
|
} else if (src_mode == 1) {
|
|
sprintf(buf, "ADDX.W -(%s),-(%s)", disass_areg(src_spec), disass_areg(tgt_spec));
|
|
} else {
|
|
sprintf(buf, "ADD.W %s,%s", disass_dreg(tgt_spec), src_ea_buf);
|
|
}
|
|
return;
|
|
case 0x0180:
|
|
if (src_mode == 0) {
|
|
sprintf(buf, "ADDX.L %s,%s", disass_dreg(src_spec), disass_dreg(tgt_spec));
|
|
} else if (src_mode == 1) {
|
|
sprintf(buf, "ADDX.L -(%s),-(%s)", disass_areg(src_spec), disass_areg(tgt_spec));
|
|
} else {
|
|
sprintf(buf, "ADD.L %s,%s", disass_dreg(tgt_spec), src_ea_buf);
|
|
}
|
|
return;
|
|
case 0x01c0:
|
|
disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, 2);
|
|
sprintf(buf, "ADDA.L %s,%s", src_ea_buf, disass_areg(tgt_spec));
|
|
return;
|
|
}
|
|
case 0xe000:
|
|
// TODO: BFTST, BFEXTU, BFCHG, BFEXTS, BFCLR, BFFFO, BFSET, BFINS
|
|
disass_ea(src_ea_buf, inst_stream, src_mode, src_spec, src_size);
|
|
switch (inst_stream[0] & 0x07c0) {
|
|
case 0x00c0:
|
|
sprintf(buf, "ASR.B #1,%s", src_ea_buf);
|
|
return;
|
|
case 0x01c0:
|
|
sprintf(buf, "ASL.B #1,%s", src_ea_buf);
|
|
return;
|
|
case 0x02c0:
|
|
sprintf(buf, "LSR.B #1,%s", src_ea_buf);
|
|
return;
|
|
case 0x03c0:
|
|
sprintf(buf, "LSL.B #1,%s", src_ea_buf);
|
|
return;
|
|
case 0x04c0:
|
|
sprintf(buf, "ROXR.B #1,%s", src_ea_buf);
|
|
return;
|
|
case 0x05c0:
|
|
sprintf(buf, "ROXL.B #1,%s", src_ea_buf);
|
|
return;
|
|
case 0x06c0:
|
|
sprintf(buf, "ROR.B #1,%s", src_ea_buf);
|
|
return;
|
|
case 0x07c0:
|
|
sprintf(buf, "ROL.B #1,%s", src_ea_buf);
|
|
return;
|
|
}
|
|
switch (inst_stream[0] & 0x01f8) {
|
|
case 0x0000:
|
|
sprintf(buf, "ASR.B #%x,%s", disass_count(tgt_spec), disass_dreg(src_spec));
|
|
return;
|
|
case 0x0008:
|
|
sprintf(buf, "LSR.B #%x,%s", disass_count(tgt_spec), disass_dreg(src_spec));
|
|
return;
|
|
case 0x0010:
|
|
sprintf(buf, "ROXR.B #%x,%s", disass_count(tgt_spec), disass_dreg(src_spec));
|
|
return;
|
|
case 0x0018:
|
|
sprintf(buf, "ROR.B #%x,%s", disass_count(tgt_spec), disass_dreg(src_spec));
|
|
return;
|
|
case 0x0020:
|
|
sprintf(buf, "ASR.B #%s,%s", disass_dreg(tgt_spec), disass_dreg(src_spec));
|
|
return;
|
|
case 0x0028:
|
|
sprintf(buf, "LSR.B #%s,%s", disass_dreg(tgt_spec), disass_dreg(src_spec));
|
|
return;
|
|
case 0x0030:
|
|
sprintf(buf, "ROXR.B #%s,%s", disass_dreg(tgt_spec), disass_dreg(src_spec));
|
|
return;
|
|
case 0x0038:
|
|
sprintf(buf, "ROR.B #%s,%s", disass_dreg(tgt_spec), disass_dreg(src_spec));
|
|
return;
|
|
case 0x0040:
|
|
sprintf(buf, "ASR.W #%x,%s", disass_count(tgt_spec), disass_dreg(src_spec));
|
|
return;
|
|
case 0x0048:
|
|
sprintf(buf, "LSR.W #%x,%s", disass_count(tgt_spec), disass_dreg(src_spec));
|
|
return;
|
|
case 0x0050:
|
|
sprintf(buf, "ROXR.W #%x,%s", disass_count(tgt_spec), disass_dreg(src_spec));
|
|
return;
|
|
case 0x0058:
|
|
sprintf(buf, "ROR.W #%x,%s", disass_count(tgt_spec), disass_dreg(src_spec));
|
|
return;
|
|
case 0x0060:
|
|
sprintf(buf, "ASR.W #%s,%s", disass_dreg(tgt_spec), disass_dreg(src_spec));
|
|
return;
|
|
case 0x0068:
|
|
sprintf(buf, "LSR.W #%s,%s", disass_dreg(tgt_spec), disass_dreg(src_spec));
|
|
return;
|
|
case 0x0070:
|
|
sprintf(buf, "ROXR.W #%s,%s", disass_dreg(tgt_spec), disass_dreg(src_spec));
|
|
return;
|
|
case 0x0078:
|
|
sprintf(buf, "ROR.W #%s,%s", disass_dreg(tgt_spec), disass_dreg(src_spec));
|
|
return;
|
|
case 0x0080:
|
|
sprintf(buf, "ASR.L #%x,%s", disass_count(tgt_spec), disass_dreg(src_spec));
|
|
return;
|
|
case 0x0088:
|
|
sprintf(buf, "LSR.L #%x,%s", disass_count(tgt_spec), disass_dreg(src_spec));
|
|
return;
|
|
case 0x0090:
|
|
sprintf(buf, "ROXR.L #%x,%s", disass_count(tgt_spec), disass_dreg(src_spec));
|
|
return;
|
|
case 0x0098:
|
|
sprintf(buf, "ROR.L #%x,%s", disass_count(tgt_spec), disass_dreg(src_spec));
|
|
return;
|
|
case 0x00a0:
|
|
sprintf(buf, "ASR.L #%s,%s", disass_dreg(tgt_spec), disass_dreg(src_spec));
|
|
return;
|
|
case 0x00a8:
|
|
sprintf(buf, "LSR.L #%s,%s", disass_dreg(tgt_spec), disass_dreg(src_spec));
|
|
return;
|
|
case 0x00b0:
|
|
sprintf(buf, "ROXR.L #%s,%s", disass_dreg(tgt_spec), disass_dreg(src_spec));
|
|
return;
|
|
case 0x00b8:
|
|
sprintf(buf, "ROR.L #%s,%s", disass_dreg(tgt_spec), disass_dreg(src_spec));
|
|
return;
|
|
case 0x0100:
|
|
sprintf(buf, "ASL.B #%x,%s", disass_count(tgt_spec), disass_dreg(src_spec));
|
|
return;
|
|
case 0x0108:
|
|
sprintf(buf, "LSL.B #%x,%s", disass_count(tgt_spec), disass_dreg(src_spec));
|
|
return;
|
|
case 0x0110:
|
|
sprintf(buf, "ROXL.B #%x,%s", disass_count(tgt_spec), disass_dreg(src_spec));
|
|
return;
|
|
case 0x0118:
|
|
sprintf(buf, "ROL.B #%x,%s", disass_count(tgt_spec), disass_dreg(src_spec));
|
|
return;
|
|
case 0x0120:
|
|
sprintf(buf, "ASL.B #%s,%s", disass_dreg(tgt_spec), disass_dreg(src_spec));
|
|
return;
|
|
case 0x0128:
|
|
sprintf(buf, "LSL.B #%s,%s", disass_dreg(tgt_spec), disass_dreg(src_spec));
|
|
return;
|
|
case 0x0130:
|
|
sprintf(buf, "ROXL.B #%s,%s", disass_dreg(tgt_spec), disass_dreg(src_spec));
|
|
return;
|
|
case 0x0138:
|
|
sprintf(buf, "ROL.B #%s,%s", disass_dreg(tgt_spec), disass_dreg(src_spec));
|
|
return;
|
|
case 0x0140:
|
|
sprintf(buf, "ASL.W #%x,%s", disass_count(tgt_spec), disass_dreg(src_spec));
|
|
return;
|
|
case 0x0148:
|
|
sprintf(buf, "LSL.W #%x,%s", disass_count(tgt_spec), disass_dreg(src_spec));
|
|
return;
|
|
case 0x0150:
|
|
sprintf(buf, "ROXL.W #%x,%s", disass_count(tgt_spec), disass_dreg(src_spec));
|
|
return;
|
|
case 0x0158:
|
|
sprintf(buf, "ROL.W #%x,%s", disass_count(tgt_spec), disass_dreg(src_spec));
|
|
return;
|
|
case 0x0160:
|
|
sprintf(buf, "ASL.W #%s,%s", disass_dreg(tgt_spec), disass_dreg(src_spec));
|
|
return;
|
|
case 0x0168:
|
|
sprintf(buf, "LSL.W #%s,%s", disass_dreg(tgt_spec), disass_dreg(src_spec));
|
|
return;
|
|
case 0x0170:
|
|
sprintf(buf, "ROXL.W #%s,%s", disass_dreg(tgt_spec), disass_dreg(src_spec));
|
|
return;
|
|
case 0x0178:
|
|
sprintf(buf, "ROL.W #%s,%s", disass_dreg(tgt_spec), disass_dreg(src_spec));
|
|
return;
|
|
case 0x0180:
|
|
sprintf(buf, "ASL.L #%x,%s", disass_count(tgt_spec), disass_dreg(src_spec));
|
|
return;
|
|
case 0x0188:
|
|
sprintf(buf, "LSL.L #%x,%s", disass_count(tgt_spec), disass_dreg(src_spec));
|
|
return;
|
|
case 0x0190:
|
|
sprintf(buf, "ROXL.L #%x,%s", disass_count(tgt_spec), disass_dreg(src_spec));
|
|
return;
|
|
case 0x0198:
|
|
sprintf(buf, "ROL.L #%x,%s", disass_count(tgt_spec), disass_dreg(src_spec));
|
|
return;
|
|
case 0x01a0:
|
|
sprintf(buf, "ASL.L #%s,%s", disass_dreg(tgt_spec), disass_dreg(src_spec));
|
|
return;
|
|
case 0x01a8:
|
|
sprintf(buf, "LSL.L #%s,%s", disass_dreg(tgt_spec), disass_dreg(src_spec));
|
|
return;
|
|
case 0x01b0:
|
|
sprintf(buf, "ROXL.L #%s,%s", disass_dreg(tgt_spec), disass_dreg(src_spec));
|
|
return;
|
|
case 0x01b8:
|
|
sprintf(buf, "ROL.L #%s,%s", disass_dreg(tgt_spec), disass_dreg(src_spec));
|
|
return;
|
|
}
|
|
}
|
|
}
|
|
|
|
|