kopia lustrzana https://github.com/Jean-MarcHarvengt/MCUME
add crtc character count
AlinTigaeru
rodzic
552f9b4ff4
commit
179fce4e9f
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@ -1,13 +1,14 @@
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#include "cpc.h"
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#include "pico.h"
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#include "pico/stdlib.h"
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#include "processor/Z80.h"
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#include "roms/rom464.h"
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extern "C" {
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#include "emuapi.h"
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#include "platform_config.h"
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}
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#include "processor/Z80.h"
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#include "roms/rom464.h"
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#include "crtc.h"
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#include "ga.h"
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@ -15,10 +16,10 @@ extern "C" {
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* Declarations of instances of the RAM, VRAM, processor and other required components.
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*/
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static byte ram[0x10000]; // 64k
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static byte RAM[0x10000]; // 64k
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static byte bitstream[0x4000]; // 16k video ram to be used by PIO.
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static Z80 cpu;
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extern struct GA_Config ga_config;
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static Z80 CPU;
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extern struct GAConfig gateArray;
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/*
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* Implementations of system-specific emuapi Init, Step etc. functions.
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@ -48,10 +49,10 @@ void cpc_Input(int bClick)
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* System-specific implementations of the Z80 instructions required by the portable Z80 emulator.
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*/
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void OutZ80(register word Port, register byte Value)
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void OutZ80(word Port, byte Value)
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{
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if(!(Port & 0x8000)) write_ga(Value); // The Gate Array is selected when bit 15 is set to 0.
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if(!(Port & 0x4000)) write_crtc(Port, Value); // The CRTC is selected when bit 14 is set to 0.
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if(!(Port & 0x8000)) writeGA(Value); // The Gate Array is selected when bit 15 is set to 0.
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if(!(Port & 0x4000)) writeCRTC(Port, Value); // The CRTC is selected when bit 14 is set to 0.
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if(!(Port & 0x2000))
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{
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// upper rom bank number. ROM banking needs to be done regardless of CPC model
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@ -64,32 +65,31 @@ void OutZ80(register word Port, register byte Value)
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}
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}
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byte InZ80(register word Port)
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byte InZ80(word Port)
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{
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if(!(Port & 0x4000)) read_crtc(Port); // The CRTC is selected when bit 14 is set to 0.
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return 0xFF;
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if(!(Port & 0x4000)) return readCRTC(Port); // The CRTC is selected when bit 14 is set to 0.
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}
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#define LOWER_ROM_END 0x4000
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#define UPPER_ROM_BEGIN 0xC000
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void WrZ80(register word Addr, register byte Value)
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void WrZ80(word Addr, byte Value)
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{
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ram[Addr] = Value;
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RAM[Addr] = Value;
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}
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byte RdZ80(register word Addr)
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byte RdZ80(word Addr)
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{
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if(Addr <= LOWER_ROM_END && ga_config.lower_rom_enable)
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if(Addr <= LOWER_ROM_END && gateArray.lowerROMEnable)
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{
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return gb_rom_464_0[Addr];
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}
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else if(Addr >= UPPER_ROM_BEGIN && ga_config.upper_rom_enable)
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else if(Addr >= UPPER_ROM_BEGIN && gateArray.upperROMEnable)
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{
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return gb_rom_464_1[Addr];
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}
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else
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{
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return ram[Addr];
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return RAM[Addr];
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}
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}
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@ -1,4 +1,9 @@
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#ifndef CPC_H_
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#define CPC_H_
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extern void cpc_Init(void);
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extern void cpc_Step(void);
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extern void cpc_Start(char* filename);
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extern void cpc_Input(int bClick);
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extern void cpc_Input(int bClick);
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#endif
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@ -1,43 +1,79 @@
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/**
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* What 6845 primarily does is to generate CRT signals such as Horizontal Sync and Vertical Sync as well as
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* video memory addresses to fetch pixel data.
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* Gate Array works together in sync with CRTC, and is responsible for converting the pixel data in memory
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* into video signals through an R2R DAC.
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*/
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#include "pico.h"
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#include "pico/stdlib.h"
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struct Registers {
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uint8_t HorizontalTotal = 63;
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uint8_t HorizontalDisplayed = 40;
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uint8_t HorizontalSyncPosition = 46;
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uint8_t HorizontalAndVerticalSyncWidths = 142;
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uint8_t VerticalTotal = 38;
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uint8_t VerticalTotalAdjust = 0;
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uint8_t VerticalDisplayed = 25;
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uint8_t VerticalSyncPosition = 30;
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uint8_t InterlaceAndSkew = 0;
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uint8_t MaximumRasterAddress = 7;
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uint8_t CursorStartRaster = 0;
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uint8_t CursorEndRaster = 0;
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uint8_t DisplayStartAddressHigh = 48;
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uint8_t DisplayStartAddressLow = 0;
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uint8_t CursorAddressHigh = 0;
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uint8_t CursorAddressLow = 0;
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uint8_t LightPenAddressHigh = 0; // Read only
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uint8_t LightPenAddressLow = 0; // Read only
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} Registers;
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#include "crtc.h"
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void write_crtc(unsigned short address, unsigned short value)
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uint8_t registers[16] = {
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63, // horizontal_total
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40, // horitzontal_displayed
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46, // horizontal_sync_position
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142, // horizontal_and_vertical_sync_widths
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38, // vertical_total
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0, // vertical_total_adjust
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25, // vertical_displayed
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30, // vertical_sync_position
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0, // interlace_and_skew
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7, // max_raster_address
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0, // cursor_start_raster
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0, // cursor_end_raster
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48, // display_start_addr_high
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0, // display_start_addr_low
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0, // cursor_addr_high
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0 // cursor_addr_low
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};
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uint8_t selectedRegister = 0;
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uint8_t horizontal_counter = 0; // C0
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uint8_t vertical_counter = 0; // C4
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uint8_t scanline_counter = 0; // C9
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uint8_t vertical_adjust_counter = 0;
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uint16_t memory_address = 0;
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void step()
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{
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return;
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horizontal_counter++;
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if(horizontal_counter == registers[0])
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{
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// horizontal counter is equal to the Horizontal Total Register.
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horizontal_counter = 0;
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scanline_counter++;
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}
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if(scanline_counter == registers[9])
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{
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// The counter for Maximum Raster Address is equal to it.
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scanline_counter = 0;
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vertical_counter++;
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}
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if(vertical_counter == registers[4])
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{
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// The vertical counter reaches the Vertical Total register.
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if(vertical_adjust_counter == registers[5])
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{
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// TODO see how the vertical adjust counter is used by GA and rest of the system.
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vertical_adjust_counter = 0;
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vertical_counter = 0;
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}
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}
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}
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void read_crtc(unsigned short address)
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// TODO hsync and vsync functions.
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void writeCRTC(unsigned short address, uint8_t value)
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{
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switch(address & 0xFF00)
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{
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case 0xBF00: break;
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case 0xBC00: selectedRegister = value & 0b11111;
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case 0xBD00: registers[selectedRegister] = value;
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}
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return;
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}
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}
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uint8_t readCRTC(unsigned short address)
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{
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switch(address & 0xFF00)
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{
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case 0xBF00: return registers[selectedRegister];
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}
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}
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@ -1,2 +1,12 @@
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void write_crtc(unsigned short address, unsigned short value);
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void read_crtc(unsigned short address);
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#ifndef CRTC_H_
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#define CRTC_H_
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#ifndef PICO_H_
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#include "pico.h"
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#include "pico/stdlib.h"
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#endif
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void writeCRTC(unsigned short address, uint8_t value);
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uint8_t readCRTC(unsigned short address);
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#endif
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@ -1,23 +1,15 @@
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/**
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* Gate Array is connected to a 16Mhz clock signal, which is then divided to 4Mhz to feed the Z80, and 1Mhz for the CRTC.
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* Gate Array's READY signal is connected to Z80's WAIT input for "memory contention".
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* This means CPU execution is halted every time Gate Array and CPU accesses the memory at the same time.
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* The reason for this is that both GA and the CPU share the same address/data bus for memory access.
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*
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* The Gate Array is responsible for the display (colour palette, resolution, horizontal and vertical sync), interrupt generation
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* and memory arrangement.
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*/
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#include "pico.h"
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#include "pico/stdlib.h"
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#include "ga.h"
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struct GA_Config ga_config;
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struct GAConfig gaConfig;
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/**
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* Some of these colours are duplicates, because select_pen_colour() uses the least significant
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* 5 bits to index into this array, so the duplicates prevent out-of-bounds read.
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*/
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struct RGB Palette[32] = {
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struct RGB palette[32] = {
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{50, 50, 50}, // White
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{50, 50, 50}, // White
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{0, 100, 50}, // Sea Green
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@ -52,45 +44,51 @@ struct RGB Palette[32] = {
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{50, 50, 100} // Pastel Blue
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};
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// TODO: Add a step() function, or something, that reads from the crtc's hsync and vsync and generates the actual
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// pixel data based on its config data.
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void step()
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{
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return;
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}
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void select_pen(register uint8_t value)
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void select_pen(uint8_t value)
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{
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switch(value >> 4)
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{
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case 0b01:
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// Select border.
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ga_config.pen_selected = 0x10;
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gaConfig.penSelected = 0x10;
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break;
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case 0b00:
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// Bits 0-3 dictate the pen number
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ga_config.pen_selected = value & 15;
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gaConfig.penSelected = value & 15;
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break;
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}
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}
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void select_pen_colour(register uint8_t value)
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void select_pen_colour(uint8_t value)
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{
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// Bits 0-4 of "value" specify the hardware colour number from the hardware colour palette.
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// (i.e. which index into the Palette array of structs.)
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ga_config.pen_colors[ga_config.pen_selected] = Palette[value & 31];
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gaConfig.penColours[gaConfig.penSelected] = palette[value & 31];
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}
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void do_rom_bank_screen_cfg(register uint8_t value)
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void do_rom_bank_screen_cfg(uint8_t value)
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{
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// Screen mode config, dictated by the least significant 2 bits.
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switch(value & 3)
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{
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case 0b00:
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// mode 0
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// ga_config.ScreenMode = 0;
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// ga_config.screen_mode = 0;
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break;
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case 0b01:
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// mode 1
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ga_config.screen_mode = 1;
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gaConfig.screenMode = 1;
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break;
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case 0b10:
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// mode 2
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// ga_config.ScreenMode = 2;
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// ga_config.screen_mode = 2;
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break;
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case 0b11:
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// mode 3, unused.
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@ -98,11 +96,11 @@ void do_rom_bank_screen_cfg(register uint8_t value)
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}
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// ROM enable flags.
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if ((value >> 2) & 0b1) ga_config.lower_rom_enable = false; else ga_config.lower_rom_enable = true;
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if ((value >> 3) & 0b1) ga_config.upper_rom_enable = false; else ga_config.upper_rom_enable = true;
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if ((value >> 2) & 0b1) gaConfig.lowerROMEnable = false; else gaConfig.lowerROMEnable = true;
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if ((value >> 3) & 0b1) gaConfig.upperROMEnable = false; else gaConfig.upperROMEnable = true;
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// Interrupt generation control.
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if ((value >> 4) & 0b1) ga_config.interrupt_delay = true; else ga_config.interrupt_delay = false;
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if ((value >> 4) & 0b1) gaConfig.interruptDelay = true; else gaConfig.interruptDelay = false;
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}
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/** Bit 7 Bit 6 Function
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@ -111,7 +109,7 @@ void do_rom_bank_screen_cfg(register uint8_t value)
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* --1-- --0-- Select screen mode, ROM configuration and interrupt control
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* --1-- --1-- RAM memory management
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*/
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void write_ga(register uint8_t value)
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void write_ga(uint8_t value)
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{
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switch(value >> 6)
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{
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@ -1,7 +1,15 @@
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extern void write_ga(register uint8_t value);
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void select_pen(register uint8_t value);
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void select_pen_colour(register uint8_t value);
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void rom_banking(register uint8_t value);
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#ifndef GA_H_
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#define GA_H_
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#ifndef PICO_H_
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#include "pico.h"
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#include "pico/stdlib.h"
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#endif
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extern void writeGA(uint8_t value);
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void selectPen(uint8_t value);
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void selectPenColour(uint8_t value);
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void romBanking(uint8_t value);
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#define PEN_NUMBER 4 // Mode 0 has 16 pens, mode 1 has 4 pens and mode 2 has 2 pens.
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@ -9,12 +17,14 @@ struct RGB {
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uint8_t R, G, B;
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};
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struct GA_Config {
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uint8_t pen_selected = 0;
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RGB pen_colors[PEN_NUMBER];
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uint8_t screen_mode = 1; // 0 -> 160x200 16c; 1 -> 320x200 4c; 2 -> 640x200 2c; 3 (undocumented) -> 160x200 4c.
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bool upper_rom_enable = false;
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bool lower_rom_enable = false;
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bool interrupt_delay = false;
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uint8_t ram_banking = 0; // unused in CPC 464
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struct GAConfig {
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uint8_t penSelected = 0;
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RGB penColours[PEN_NUMBER];
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uint8_t screenMode = 1; // 0 -> 160x200 16c; 1 -> 320x200 4c; 2 -> 640x200 2c; 3 (undocumented) -> 160x200 4c.
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bool upperROMEnable = false;
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bool lowerROMEnable = false;
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bool interruptDelay = false;
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uint8_t ramBanking = 0; // unused in CPC 464
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};
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#endif
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