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65 Commity
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Autor SHA1 Wiadomość Data
Piotr Wilkoń d308fcfde7
Update manual_pl.md 2024-05-16 09:30:48 +02:00
Piotr Wilkoń ce8c0a7d21
default uart params and backspace handling 2024-05-16 09:30:04 +02:00
Piotr Wilkoń fff395670a
default uart config, backspace handling 2024-05-16 09:26:30 +02:00
Piotr Wilkoń f2ef2339f4
Update terminal.c 
git conflict markers removal
 2024-05-16 09:11:16 +02:00
Piotr Wilkoń 0d04dac063
Merge pull request #37 from sq8vps/sq8vps-patch-4-1 
Update manual.md
 2023-11-12 12:12:58 +01:00
Piotr Wilkoń e19487284e
Merge pull request #38 from sq8vps/sq8vps-patch-4 
Update manual_pl.md
 2023-11-12 12:12:46 +01:00
Piotr Wilkoń d51b06ae6f
Update manual.md 2023-11-12 12:12:10 +01:00
Piotr Wilkoń c107998094
Update manual_pl.md 2023-11-12 12:10:01 +01:00
Piotr Wilkoń 395fe829ee
Merge pull request #36 from sq8vps/sq8vps-patch-3 
Resolve example beacon path confusion
 2023-11-07 17:47:24 +01:00
Piotr Wilkoń 475e73ac4d
Resolve example beacon path confusion in manual 2023-11-07 17:46:35 +01:00
Piotr Wilkoń cee4b6254e
Resolve example beacon path confusion in manual 2023-11-07 17:45:25 +01:00
Piotr Wilkoń 7da29cde6c
Update README_pl.md 
interpunction
 2023-10-05 20:04:38 +02:00
sq8vps 061508c6f7 kiss sanity checking 2023-10-03 17:36:14 +02:00
Piotr Wilkoń da31c81b20
Merge pull request #33 from sq8vps/sq8vps-patch-2 
Update README.md
 2023-10-03 16:27:01 +02:00
Piotr Wilkoń af9be1c420
Update README.md 2023-10-03 16:24:55 +02:00
Piotr Wilkoń db11674779
Merge pull request #32 from sq8vps/modems 
v. 2.0.0 - new modems, FX.25 etc.
 2023-10-03 16:22:33 +02:00
Piotr Wilkon d59e43c99a more conflict resolutions 2023-10-03 16:16:31 +02:00
Piotr Wilkon f4ad4a8022 conflict resolution 2023-10-03 16:13:36 +02:00
Piotr Wilkon 040ce42764 new experimental KISS handling 2023-09-12 11:16:22 +02:00
Piotr Wilkon dfb13fa356 experimental kiss double buffering 2023-09-11 10:25:08 +02:00
Piotr Wilkon eb00ad619d readme 2023-09-08 22:43:05 +02:00
Piotr Wilkon e2511c4f5d got rid of real-time operations 2023-09-08 22:40:03 +02:00
Piotr Wilkon 167a1bb30f moved to stm32cubeide, new hal version, uart bug fix 2023-09-08 16:58:49 +02:00
Piotr Wilkon 0224e40a6d low-level wrappers for easier porting 2023-09-08 10:51:54 +02:00
Piotr Wilkon 7df3b8dc3d removed unnecesary stuff 2023-09-08 08:19:03 +02:00
sq8vps 3d6b672a18 manual update 2023-09-07 09:28:42 +02:00
sq8vps 55f524509a setting uart default modes 2023-09-07 07:49:26 +02:00
sq8vps 8adf034d26 readme, manuals 2023-09-06 13:17:21 +02:00
sq8vps b4a774bb52 copyright notices, pl manual, small ax.25 change 2023-09-06 11:38:33 +02:00
Piotr Wilkon c9066cea5a non-APRS in FX.25 mode 2023-09-05 11:01:44 +02:00
Piotr Wilkon b898d05a7f fixed non-APRS RX problem 2023-09-05 10:24:53 +02:00
Piotr Wilkon 8d83ab5cfa modem frequency correction 2023-09-05 08:11:48 +02:00
sq8vps 8189de2e0f changelog 2023-09-05 07:41:29 +02:00
sq8vps 6dae655f45 KISS fixes 2023-09-05 07:38:01 +02:00
Piotr Wilkoń e9a5ebd2c6
Merge pull request #29 from sq8vps/dev 
v.1.3.3
 2023-09-04 11:33:51 +02:00
Piotr Wilkon 08baecee8a tnc2 converter bug fix 2023-09-04 11:32:41 +02:00
Piotr Wilkon 25a7125932 changelog and version number 2023-09-04 10:47:24 +02:00
sq8vps f23d89dadb concurrency handling 2023-09-04 10:25:26 +02:00
sq8vps c0d90a3793 KISS handling improvements 2023-09-04 09:54:16 +02:00
sq8vps a11eca1c28 kiss escape chars handling 2023-09-03 10:49:47 +02:00
Piotr Wilkoń e550e10d7e
Merge pull request #28 from sq8vps/dev 
duplicate protection bug
 2023-08-31 21:03:58 +02:00
Piotr Wilkon d7738a0a6f duplicate protection bug 2023-08-31 21:02:42 +02:00
Piotr Wilkon 1d923864fb duplicate protection bug 2023-08-31 20:58:59 +02:00
Piotr Wilkon 5bdc61f3bc schematic 2023-08-31 20:12:19 +02:00
Piotr Wilkon 2f894ab5a3 timer frq change, hamming distance using built-in fun 2023-08-31 20:10:16 +02:00
Piotr Wilkon 743f2d7d1d v2 2023-08-31 18:55:03 +02:00
Piotr Wilkon 3b404fb35a modems working 2023-08-31 17:48:32 +02:00
Piotr Wilkoń 995990ef1e
Merge pull request #27 from sq8vps/dev 
non-aprs config bug, pwm by default
 2023-08-30 22:58:44 +02:00
sq8vps ba0002222b non-aprs config bug, pwm by default 2023-08-30 22:57:27 +02:00
sq8vps b329dfddf4 small changes 2023-08-30 22:52:16 +02:00
Piotr Wilkon 4341ba3cec modem configuration 2023-08-30 16:52:27 +02:00
Piotr Wilkon 46334fd16d conflict resolution 2023-08-30 16:38:49 +02:00
Piotr Wilkon f1506bf732 in progress 2023-08-30 16:26:23 +02:00
sq8vps fbc2d1b1d5 ? 2023-08-30 16:25:37 +02:00
Piotr Wilkoń b27fde7fc0
Merge pull request #25 from sq8vps/dev 
v. 1.3.0
 2023-08-30 14:15:34 +02:00
Piotr Wilkoń 70f2805bb2
Merge branch 'main' into dev 2023-08-30 14:15:23 +02:00
Piotr Wilkon bd6b7f5286 changelog and readme 2023-08-29 11:06:55 +02:00
Piotr Wilkoń 7ea31b587b
Update README.md 2023-08-29 10:25:32 +02:00
Piotr Wilkon 00431f9716 beacon send bug fix and copyrights 2023-08-29 10:16:34 +02:00
Piotr Wilkon 94d5dcf3ca initial kicad files 2023-08-29 09:46:24 +02:00
sq8vps 80093c96ea working on modems 2023-08-25 11:56:06 +02:00
sq8vps bb6797b293 9600 untested 2023-08-24 07:47:22 +02:00
sq8vps e4f659d9da working on more modems 2023-08-22 13:32:07 +02:00
sq8vps 665d210683 ax25 send, removed all mallocs 2023-08-18 12:50:33 +02:00
Piotr Wilkon 5a1427ad11 major code refactoring and rewrite 2023-08-17 14:57:29 +02:00
135 zmienionych plików z 25918 dodań i 12156 usunięć
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3
.gitmodules vendored 100644
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@ -0,0 +1,3 @@
[submodule "lwfec"]
path = lwfec
url = https://github.com/sq8vps/lwfec

43
.mxproject
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File diff suppressed because one or more lines are too long

9
.project
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@ -1,6 +1,6 @@
<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>F103C8T6_DIGI_USB</name>
<name>vp-digi</name>
<comment></comment>
<projects>
</projects>
@ -19,9 +19,14 @@
</buildCommand>
</buildSpec>
<natures>
<nature>com.st.stm32cube.ide.mcu.MCUProjectNature</nature>
<nature>org.eclipse.cdt.core.cnature</nature>
<nature>com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAev2ProjectNature</nature>
<nature>com.st.stm32cube.ide.mcu.MCUCubeProjectNature</nature>
<nature>com.st.stm32cube.ide.mcu.MCUAdvancedStructureProjectNature</nature>
<nature>com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature</nature>
<nature>com.st.stm32cube.ide.mcu.MCURootProjectNature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
<nature>fr.ac6.mcu.ide.core.MCUProjectNature</nature>
</natures>
</projectDescription>

75
CHANGELOG.md
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@ -1,3 +1,67 @@
# 2.0.0 (2023-09-09)
## New features
* New modems: AFSK Bell 103 (300 Bd, 1600/1800 Hz), GFSK G3RUH (9600 Bd), AFSK V.23 (1200 Bd, 1300/2100 Hz)
* FX.25 (AX.25 with Reed-Solomon FEC) support
* Default UART/USB modes can be configured
## Bug fixes
* none
## Other
* New signal level measurement method
* Got rid of float operations for PLL adjustment
* Full documentation (English and Polish) in Markdown
* Project moved to STM32CubeIDE
* Updated HAL version used for USB
## Known bugs
* none
# 1.3.3 (2023-09-04)
## New features
* none
## Bug fixes
* RX buffer pointers bug fix
* AX.25 to TNC2 converter bug with non-UI frames
## Other
* New KISS handling method to support long and multiple frames
## Known bugs
* none
# 1.3.2 (2023-08-31)
## New features
* none
## Bug fixes
* Duplicate protection was not working properly
## Other
* none
## Known bugs
* none
# 1.3.1 (2023-08-30)
## New features
* none
## Bug fixes
* Non-APRS switch was not stored in memory
## Other
* PWM is now the default option
## Known bugs
* none
# 1.3.0 (2023-08-30)
## New features
* Callsign is now set together with SSID using ```call <call-SSID>```
* ```time``` command to show uptime
## Removed features
* ```ssid``` command is removed
* Auto-reset functionality and ```autoreset``` command is removed
## Bug fixes
* When beacon *n* delay hadn't passed yet, beacon *n+1*, *n+2*, ... were not sent regardless of their delay
* Bugs with line ending parsing
## Other
* Major code refactoring and rewrite
* Got rid of *uart_transmitStart()* routine
* USB sending is handled the same way as UART
* New way of TX and RX frame handling to improve non-APRS compatibility
* Much bigger frame buffer
* Minimized number of temporary buffers
* All *malloc()*s removed
* Added copyright notice as required by GNU GPL
## Known bugs
* none
# 1.2.6 (2023-07-29)
## New features
* Added ```nonaprs [on/off]``` command that enables reception of non-APRS frames, e.g. for full Packet Radio use
@ -43,15 +107,6 @@
* none
## Known bugs
* USB in KISS mode has problem with TX frames
# 1.2.2 (2022-06-11)
## New features
* none
## Bug fixes
* Default de-dupe time was 0, backspace was sometimes stored in config, frame length was not checked in viscous delay mode
## Other
* none
## Known bugs
* USB in KISS mode has problem with TX frames
# 1.2.1 (2021-10-13)
## New features
* none
@ -73,4 +128,4 @@ This is the very first open-source VP-Digi release.
## Other
* Code was partially rewritten (especially digipeater, modem and AX.25 layer)
## Known bugs
* none
* none

127
Core/Inc/ax25.h 100644
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@ -0,0 +1,127 @@
/*
Copyright 2020-2023 Piotr Wilkon
This file is part of VP-Digi.
VP-Digi is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
VP-Digi is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with VP-Digi. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef AX25_H_
#define AX25_H_
#include <stdint.h>
#include <stdbool.h>
#define AX25_NOT_FX25 255
//for AX.25 329 bytes is the theoretical max size assuming 2-byte Control, 1-byte PID, 256-byte info field and 8 digi address fields
#define AX25_FRAME_MAX_SIZE (329) //single frame max length
enum Ax25RxStage
{
RX_STAGE_IDLE = 0,
RX_STAGE_FLAG,
RX_STAGE_FRAME,
#ifdef ENABLE_FX25
RX_STAGE_FX25_FRAME,
#endif
};
struct Ax25ProtoConfig
{
uint16_t txDelayLength; //TXDelay length in ms
uint16_t txTailLength; //TXTail length in ms
uint16_t quietTime; //Quiet time in ms
uint8_t allowNonAprs : 1; //allow non-APRS packets
uint8_t fx25 : 1; //enable FX.25 (AX.25 + FEC)
uint8_t fx25Tx : 1; //enable TX in FX.25
};
extern struct Ax25ProtoConfig Ax25Config;
/**
* @brief Write frame to transmit buffer
* @param *data Data to transmit
* @param size Data size
* @return Pointer to internal frame handle or NULL on failure
* @attention This function will block if transmission is already in progress
*/
void *Ax25WriteTxFrame(uint8_t *data, uint16_t size);
/**
* @brief Get bitmap of "frame received" flags for each decoder. A non-zero value means that a frame was received
* @return Bitmap of decoder that received the frame
*/
uint8_t Ax25GetReceivedFrameBitmap(void);
/**
* @brief Clear bitmap of "frame received" flags
*/
void Ax25ClearReceivedFrameBitmap(void);
/**
* @brief Get next received frame (if available)
* @param **dst Pointer to internal buffer
* @param *size Actual frame size
<<<<<<< HEAD
* @param *peak Signak positive peak value in %
* @param *valley Signal negative peak value in %
* @param *level Signal level in %
* @param *corrected Number of bytes corrected in FX.25 mode. 255 is returned if not a FX.25 packet.
* @return True if frame was read, false if no more frames to read
*/
bool Ax25ReadNextRxFrame(uint8_t **dst, uint16_t *size, int8_t *peak, int8_t *valley, uint8_t *level, uint8_t *corrected);
/**
* @brief Get current RX stage
* @param[in] modemNo Modem/decoder number (0 or 1)
* @return RX_STATE_IDLE, RX_STATE_FLAG or RX_STATE_FRAME
* @warning Only for internal use
*/
enum Ax25RxStage Ax25GetRxStage(uint8_t modemNo);
/**
* @brief Parse incoming bit (not symbol!)
* @details Handles bit-stuffing, header and CRC checking, stores received frame and sets "frame received flag", multiplexes both decoders
* @param[in] bit Incoming bit
* @param[in] *dem Modem state pointer
* @warning Only for internal use
*/
void Ax25BitParse(uint8_t bit, uint8_t modemNo);
/**
* @brief Get next bit to be transmitted
* @return Bit to be transmitted
* @warning Only for internal use
*/
uint8_t Ax25GetTxBit(void);
/**
* @brief Initialize transmission and start when possible
*/
void Ax25TransmitBuffer(void);
/**
* @brief Start transmitting when possible
* @attention Must be continuously polled in main loop
*/
void Ax25TransmitCheck(void);
/**
* @brief Initialize AX25 module
*/
void Ax25Init(void);
#endif /* AX25_H_ */

22
Inc/beacon.h → Core/Inc/beacon.h
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@ -1,4 +1,6 @@
/*
Copyright 2020-2023 Piotr Wilkon
This file is part of VP-Digi.
VP-Digi is free software: you can redistribute it and/or modify
@ -21,35 +23,35 @@ along with VP-Digi. If not, see <http://www.gnu.org/licenses/>.
#include <stdint.h>
#define BEACON_MAX_PAYLOAD_SIZE 100
typedef struct
struct Beacon
{
uint8_t enable; //enable beacon
uint32_t interval; //interval in seconds
uint32_t delay; //delay in seconds
uint8_t data[101]; //information field
uint8_t data[BEACON_MAX_PAYLOAD_SIZE + 1]; //information field
uint8_t path[15]; //path, 2 parts max, e.g. WIDE1<sp>1SP2<sp><sp><sp>2<NUL>, <NUL> can be at byte 0, 7 and 14
uint32_t next; //next beacon timestamp
} Beacon;
};
Beacon beacon[8];
extern struct Beacon beacon[8];
/**
* @brief Send specified beacon
* @param[in] no Beacon number (0-7)
* @param number Beacon number (0-7)
*/
void Beacon_send(uint8_t no);
void BeaconSend(uint8_t number);
/**
* @brief Check if any beacon should be transmitted and transmit if neccessary
* @brief Check if any beacon should be transmitted and transmit if necessary
*/
void Beacon_check(void);
void BeaconCheck(void);
/**
* @brief Initialize beacon module
*/
void Beacon_init(void);
void BeaconInit(void);
#endif /* BEACON_H_ */

114
Core/Inc/common.h 100644
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@ -0,0 +1,114 @@
/*
Copyright 2020-2023 Piotr Wilkon
This file is part of VP-Digi.
VP-Digi is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
VP-Digi is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with VP-Digi. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef COMMON_H_
#define COMMON_H_
#include <stdint.h>
#include "uart.h"
#define IS_UPPERCASE_ALPHANUMERIC(x) ((((x) >= '0') && ((x) <= '9')) || (((x) >= 'A') && ((x) <= 'Z')))
#define IS_NUMBER(x) (((x) >= '0') && ((x) <= '9'))
#define ABS(x) (((x) > 0) ? (x) : (-x))
#define CRC32_INIT 0xFFFFFFFF
struct _GeneralConfig
{
uint8_t call[6]; //device callsign
uint8_t callSsid; //device ssid
uint8_t dest[7]; //destination address for own beacons. Should be APNV01-0 for VP-Digi, but can be changed. SSID MUST remain 0.
uint8_t kissMonitor;
};
extern struct _GeneralConfig GeneralConfig;
extern const char versionString[]; //version string
/**
* @brief Generate random number from min to max
* @param[in] min Lower boundary
* @param[in] max Higher boundary
* @return Generated number
*/
int16_t Random(int16_t min, int16_t max);
/**
* @brief Convert string to int
* @param[in] *str Input string
* @param[in] len String length or 0 to detect by strlen()
* @return Converted int
*/
int64_t StrToInt(const char *str, uint16_t len);
///**
// * @brief Convert AX25 frame to TNC2 (readable) format
// * @param *from Input AX25 frame
// * @param len Input frame length
// * @param *to Destination buffer, will be NULL terminated
// * @param limit Destination buffer size limit
// */
//void ConvertToTNC2(uint8_t *from, uint16_t fromlen, uint8_t *to, uint16_t limit);
/**
* @brief Convert AX25 frame to TNC2 (readable) format and send it through available ports
* @param *from Input AX25 frame
* @param len Input frame length
*/
void SendTNC2(uint8_t *from, uint16_t len);
/**
* @brief Calculate CRC32
* @param[in] crc0 Initial or current CRC value
* @param[in] *s Input data
* @param[in] n Input data length
* @return Calculated CRC32
*/
uint32_t Crc32(uint32_t crc0, uint8_t *s, uint64_t n);
/**
* @brief Check if callsign is correct and convert it to AX.25 format
* @param *in Input ASCII callsign
* @param size Input size, not bigger than 6
* @param *out Output buffer, exactly 6 bytes
* @return True if callsign is valid
*/
bool ParseCallsign(const char *in, uint16_t size, uint8_t *out);
/**
* @brief Check if callsign with SSID is correct and convert it to AX.25 format
* @param *in Input ASCII callsign with SSID
* @param size Input size
* @param *out Output buffer, exactly 6 bytes
* @param *ssid Output SSID, exactly 1 byte
* @return True if callsign is valid
*/
bool ParseCallsignWithSsid(const char *in, uint16_t size, uint8_t *out, uint8_t *ssid);
/**
* @brief Check if SSID is correct and convert it to uint8_t
* @param *in Input ASCII SSID
* @param size Input size
* @param *out Output buffer, exactly 1 byte
* @return True if SSID is valid
*/
bool ParseSsid(const char *in, uint16_t size, uint8_t *out);
#endif /* COMMON_H_ */

28
Inc/drivers/systick.h → Core/Inc/config.h
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@ -1,4 +1,6 @@
/*
Copyright 2020-2023 Piotr Wilkon
This file is part of VP-Digi.
VP-Digi is free software: you can redistribute it and/or modify
@ -15,16 +17,28 @@ You should have received a copy of the GNU General Public License
along with VP-Digi. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef SYSTICK_H_
#define SYSTICK_H_
#ifndef CONFIG_H_
#define CONFIG_H_
#include <stdint.h>
#include "stm32f1xx.h"
extern volatile uint32_t ticks;
//void SysTick_Handler(void);
void SysTick_init(void);
/**
* @brief Store configuration from RAM to Flash
*/
void ConfigWrite(void);
#endif /* SYSTICK_H_ */
/**
* @brief Erase all configuration
*/
void ConfigErase(void);
/**
* @brief Read configuration from Flash to RAM
* @return 1 if success, 0 if no configuration stored in Flash
*/
uint8_t ConfigRead(void);
#endif /* CONFIG_H_ */

26
Inc/digipeater.h → Core/Inc/digipeater.h
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@ -1,4 +1,6 @@
/*
Copyright 2020-2023 Piotr Wilkon
This file is part of VP-Digi.
VP-Digi is free software: you can redistribute it and/or modify
@ -21,9 +23,7 @@ along with VP-Digi. If not, see <http://www.gnu.org/licenses/>.
#include <stdint.h>
typedef struct
struct _DigiConfig
{
uint8_t alias[8][6]; //digi alias list
uint8_t ssid[4]; //ssid list for simple aliases
@ -38,10 +38,9 @@ typedef struct
uint8_t callFilter[20][7]; //callsign filter array
uint8_t callFilterEnable; //enable filter by call for every alias
uint8_t filterPolarity : 1; //filter polarity: 0 - blacklist, 1- whitelist
} Digi;
Digi digi; //digipeater state
};
extern struct _DigiConfig DigiConfig; //digipeater state
/**
@ -50,18 +49,19 @@ Digi digi; //digipeater state
* @param[in] len Frame length
* Decides whether the frame should be digipeated or not, processes it and pushes to TX buffer if needed
*/
void Digi_digipeat(uint8_t *frame, uint16_t len);
void DigiDigipeat(uint8_t *frame, uint16_t len);
/**
* @brief Store duplicate protection hash for the frame already pushed to TX buffer
* @param[in] idx First frame byte index in TX buffer
* @brief Store duplicate protection hash for frame
* @param *buf Frame buffer
* @param size Frame size
*/
void Digi_storeDeDupeFromXmitBuf(uint16_t idx);
void DigiStoreDeDupe(uint8_t *buf, uint16_t size);
/**
* @brief Refresh viscous-delay buffers and push frames to TX buffer if neccessary
* @attention Should be called constantly
* @brief Refresh viscous-delay buffers and push frames to TX buffer if necessary
* @attention Should be called in main loop
*/
void Digi_viscousRefresh(void);
void DigiViscousRefresh(void);
#endif /* DIGIPEATER_H_ */

196
Core/Inc/drivers/modem_ll.h 100644
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@ -0,0 +1,196 @@
/*
Copyright 2020-2023 Piotr Wilkon
This file is part of VP-Digi.
VP-Digi is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
VP-Digi is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with VP-Digi. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* This file is kind of HAL for modem
*/
#ifndef DRIVERS_MODEM_LL_H_
#define DRIVERS_MODEM_LL_H_
#include <stdint.h>
//Oversampling factor
//This is a helper value, not a setting that can be changed without further code modification!
#define MODEM_LL_OVERSAMPLING_FACTOR 4
#if defined(STM32F103xB) || defined(STM32F103x8)
#include "stm32f1xx.h"
/**
* TIM1 is used for pushing samples to DAC (R2R or PWM) (clocked at 18 MHz)
* TIM3 is the baudrate generator for TX (clocked at 18 MHz)
* TIM4 is the PWM generator with no software interrupt
* TIM2 is the RX sampling timer with no software interrupt, but it directly calls DMA
*/
#define MODEM_LL_DMA_INTERRUPT_HANDLER DMA1_Channel2_IRQHandler
#define MODEM_LL_DAC_INTERRUPT_HANDLER TIM1_UP_IRQHandler
#define MODEM_LL_BAUDRATE_TIMER_INTERRUPT_HANDLER TIM3_IRQHandler
#define MODEM_LL_DMA_IRQ DMA1_Channel2_IRQn
#define MODEM_LL_DAC_IRQ TIM1_UP_IRQn
#define MODEM_LL_BAUDRATE_TIMER_IRQ TIM3_IRQn
#define MODEM_LL_DMA_TRANSFER_COMPLETE_FLAG (DMA1->ISR & DMA_ISR_TCIF2)
#define MODEM_LL_DMA_CLEAR_TRANSFER_COMPLETE_FLAG() {DMA1->IFCR |= DMA_IFCR_CTCIF2;}
#define MODEM_LL_BAUDRATE_TIMER_CLEAR_INTERRUPT_FLAG() {TIM3->SR &= ~TIM_SR_UIF;}
#define MODEM_LL_BAUDRATE_TIMER_ENABLE() {TIM3->CR1 = TIM_CR1_CEN;}
#define MODEM_LL_BAUDRATE_TIMER_DISABLE() {TIM3->CR1 &= ~TIM_CR1_CEN;}
#define MODEM_LL_BAUDRATE_TIMER_SET_RELOAD_VALUE(val) {TIM3->ARR = (val);}
#define MODEM_LL_DAC_TIMER_CLEAR_INTERRUPT_FLAG {TIM1->SR &= ~TIM_SR_UIF;}
#define MODEM_LL_DAC_TIMER_SET_RELOAD_VALUE(val) {TIM1->ARR = (val);}
#define MODEM_LL_DAC_TIMER_SET_CURRENT_VALUE(val) {TIM1->CNT = (val);}
#define MODEM_LL_DAC_TIMER_ENABLE() {TIM1->CR1 |= TIM_CR1_CEN;}
#define MODEM_LL_DAC_TIMER_DISABLE() {TIM1->CR1 &= ~TIM_CR1_CEN;}
#define MODEM_LL_ADC_TIMER_ENABLE() {TIM2->CR1 |= TIM_CR1_CEN;}
#define MODEM_LL_ADC_TIMER_DISABLE() {TIM2->CR1 &= ~TIM_CR1_CEN;}
#define MODEM_LL_PWM_PUT_VALUE(value) {TIM4->CCR1 = (value);}
#define MODEM_LL_R2R_PUT_VALUE(value) {GPIOB->ODR &= ~0xF000; \
GPIOB->ODR |= ((uint32_t)(value) << 12); }\
#define MODEM_LL_DCD_LED_ON() { \
GPIOC->BSRR = GPIO_BSRR_BR13; \
GPIOB->BSRR = GPIO_BSRR_BS5; \
} \
#define MODEM_LL_DCD_LED_OFF() { \
GPIOC->BSRR = GPIO_BSRR_BS13; \
GPIOB->BSRR = GPIO_BSRR_BR5; \
} \
#define MODEM_LL_PTT_ON() {GPIOB->BSRR = GPIO_BSRR_BS7;}
#define MODEM_LL_PTT_OFF() {GPIOB->BSRR = GPIO_BSRR_BR7;}
#define MODEM_LL_INITIALIZE_RCC() { \
RCC->APB2ENR |= RCC_APB2ENR_IOPBEN; \
RCC->APB2ENR |= RCC_APB2ENR_IOPCEN; \
RCC->APB2ENR |= RCC_APB2ENR_IOPAEN; \
RCC->APB1ENR |= RCC_APB1ENR_TIM2EN; \
RCC->APB1ENR |= RCC_APB1ENR_TIM3EN; \
RCC->APB2ENR |= RCC_APB2ENR_TIM1EN; \
RCC->APB2ENR |= RCC_APB2ENR_ADC1EN; \
RCC->AHBENR |= RCC_AHBENR_DMA1EN; \
RCC->APB1ENR |= RCC_APB1ENR_TIM4EN; \
} \
#define MODEM_LL_INITIALIZE_OUTPUTS() { \
/* DCD LEDs: PC13 (cathode driven - built-in LED on Blue Pill) and PB5 (anode driven) */ \
GPIOC->CRH |= GPIO_CRH_MODE13_1; \
GPIOC->CRH &= ~GPIO_CRH_MODE13_0; \
GPIOC->CRH &= ~GPIO_CRH_CNF13; \
GPIOB->CRL |= GPIO_CRL_MODE5_1; \
GPIOB->CRL &= ~GPIO_CRL_MODE5_0; \
GPIOB->CRL &= ~GPIO_CRL_CNF5; \
/* PTT: PB7 */ \
GPIOB->CRL |= GPIO_CRL_MODE7_1; \
GPIOB->CRL &= ~GPIO_CRL_MODE7_0; \
GPIOB->CRL &= ~GPIO_CRL_CNF7; \
/* R2R: 4 bits, PB12-PB15 */ \
GPIOB->CRH &= ~0xFFFF0000; \
GPIOB->CRH |= 0x22220000; \
/* PWM output: PB6 */ \
GPIOB->CRL |= GPIO_CRL_CNF6_1; \
GPIOB->CRL |= GPIO_CRL_MODE6; \
GPIOB->CRL &= ~GPIO_CRL_CNF6_0; \
} \
#define MODEM_LL_INITIALIZE_ADC() { \
/* ADC input: PA0 */ \
GPIOA->CRL &= ~GPIO_CRL_CNF0; \
GPIOA->CRL &= ~GPIO_CRL_MODE0; \
/*/6 prescaler */ \
RCC->CFGR |= RCC_CFGR_ADCPRE_1; \
RCC->CFGR &= ~RCC_CFGR_ADCPRE_0; \
ADC1->CR2 |= ADC_CR2_CONT; \
ADC1->CR2 |= ADC_CR2_EXTSEL; \
ADC1->SQR1 &= ~ADC_SQR1_L; \
/* 41.5 cycle sampling */ \
ADC1->SMPR2 |= ADC_SMPR2_SMP0_2; \
ADC1->SQR3 &= ~ADC_SQR3_SQ1; \
ADC1->CR2 |= ADC_CR2_ADON; \
/* calibrate */ \
ADC1->CR2 |= ADC_CR2_RSTCAL; \
while(ADC1->CR2 & ADC_CR2_RSTCAL) \
; \
ADC1->CR2 |= ADC_CR2_CAL; \
while(ADC1->CR2 & ADC_CR2_CAL) \
; \
ADC1->CR2 |= ADC_CR2_EXTTRIG; \
ADC1->CR2 |= ADC_CR2_SWSTART; \
} \
#define MODEM_LL_INITIALIZE_DMA(buffer) { \
/* 16 bit memory region */ \
DMA1_Channel2->CCR |= DMA_CCR_MSIZE_0; \
DMA1_Channel2->CCR &= ~DMA_CCR_MSIZE_1; \
DMA1_Channel2->CCR |= DMA_CCR_PSIZE_0; \
DMA1_Channel2->CCR &= ~DMA_CCR_PSIZE_1; \
/* enable memory pointer increment, circular mode and interrupt generation */ \
DMA1_Channel2->CCR |= DMA_CCR_MINC | DMA_CCR_CIRC| DMA_CCR_TCIE; \
DMA1_Channel2->CNDTR = MODEM_LL_OVERSAMPLING_FACTOR; \
DMA1_Channel2->CPAR = (uintptr_t)&(ADC1->DR); \
DMA1_Channel2->CMAR = (uintptr_t)buffer; \
DMA1_Channel2->CCR |= DMA_CCR_EN; \
} \
#define MODEM_LL_ADC_TIMER_INITIALIZE() { \
/* 72 / 9 = 8 MHz */ \
TIM2->PSC = 8; \
/* enable DMA call instead of standard interrupt */ \
TIM2->DIER |= TIM_DIER_UDE; \
} \
#define MODEM_LL_DAC_TIMER_INITIALIZE() { \
/* 72 / 4 = 18 MHz */ \
TIM1->PSC = 3; \
TIM1->DIER |= TIM_DIER_UIE; \
} \
#define MODEM_LL_BAUDRATE_TIMER_INITIALIZE() { \
/* 72 / 4 = 18 MHz */ \
TIM3->PSC = 3; \
TIM3->DIER |= TIM_DIER_UIE; \
} \
#define MODEM_LL_PWM_INITIALIZE() { \
/* 72 / 3 = 24 MHz to provide 8 bit resolution at around 100 kHz */ \
TIM4->PSC = 2; \
/* 24 MHz / 258 = 93 kHz */ \
TIM4->ARR = 257; \
TIM4->CCMR1 |= TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2; \
TIM4->CCER |= TIM_CCER_CC1E; \
TIM4->CR1 |= TIM_CR1_CEN; \
} \
#define MODEM_LL_ADC_SET_SAMPLE_RATE(rate) {TIM2->ARR = (8000000 / (rate)) - 1;}
#define MODEM_LL_DAC_TIMER_CALCULATE_STEP(frequency) ((18000000 / (frequency)) - 1)
#define MODEM_LL_BAUDRATE_TIMER_CALCULATE_STEP(frequency) ((18000000 / (frequency)) - 1)
#endif
#endif /* DRIVERS_MODEM_LL_H_ */

81
Core/Inc/drivers/uart_ll.h 100644
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@ -0,0 +1,81 @@
/*
Copyright 2020-2023 Piotr Wilkon
This file is part of VP-Digi.
VP-Digi is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
VP-Digi is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with VP-Digi. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* This file is kind of HAL for UART
*/
#ifndef DRIVERS_UART_LL_H_
#define DRIVERS_UART_LL_H_
#if defined(STM32F103xB) || defined(STM32F103x8)
#include "stm32f1xx.h"
#define UART_LL_ENABLE(port) {port->CR1 |= USART_CR1_RXNEIE | USART_CR1_TE | USART_CR1_RE | USART_CR1_UE | USART_CR1_IDLEIE;}
#define UART_LL_DISABLE(port) {port->CR1 &= (~USART_CR1_RXNEIE) & (~USART_CR1_TE) & (~USART_CR1_RE) & (~USART_CR1_UE) & (~USART_CR1_IDLEIE);}
#define UART_LL_CHECK_RX_NOT_EMPTY(port) (port->SR & USART_SR_RXNE)
#define UART_LL_CLEAR_RX_NOT_EMPTY(port) {port->SR &= ~USART_SR_RXNE;}
#define UART_LL_CHECK_TX_EMPTY(port) (port->SR & USART_SR_TXE)
#define UART_LL_ENABLE_TX_EMPTY_INTERRUPT(port) {port->CR1 |= USART_CR1_TXEIE;}
#define UART_LL_DISABLE_TX_EMPTY_INTERRUPT(port) {port->CR1 &= ~USART_CR1_TXEIE;}
#define UART_LL_CHECK_ENABLED_TX_EMPTY_INTERRUPT(port) (port->CR1 & USART_CR1_TXEIE)
#define UART_LL_CHECK_RX_IDLE(port) (port->SR & USART_SR_IDLE)
#define UART_LL_GET_DATA(port) (port->DR)
#define UART_LL_PUT_DATA(port, data) {port->DR = (data);}
#define UART_LL_UART1_INTERUPT_HANDLER USART1_IRQHandler
#define UART_LL_UART2_INTERUPT_HANDLER USART2_IRQHandler
#define UART_LL_UART1_STRUCTURE USART1
#define UART_LL_UART2_STRUCTURE USART2
#define UART_LL_UART1_IRQ USART1_IRQn
#define UART_LL_UART2_IRQ USART2_IRQn
#define UART_LL_UART1_INITIALIZE_PERIPHERAL(baudrate) { \
RCC->APB2ENR |= RCC_APB2ENR_IOPAEN; \
RCC->APB2ENR |= RCC_APB2ENR_USART1EN; \
GPIOA->CRH |= GPIO_CRH_MODE9_1; \
GPIOA->CRH &= ~GPIO_CRH_CNF9_0; \
GPIOA->CRH |= GPIO_CRH_CNF9_1; \
GPIOA->CRH |= GPIO_CRH_CNF10_0; \
GPIOA->CRH &= ~GPIO_CRH_CNF10_1; \
UART_LL_UART1_STRUCTURE->BRR = (SystemCoreClock / baudrate); \
} \
#define UART_LL_UART2_INITIALIZE_PERIPHERAL(baudrate) { \
RCC->APB2ENR |= RCC_APB2ENR_IOPAEN; \
RCC->APB1ENR |= RCC_APB1ENR_USART2EN; \
GPIOA->CRL |= GPIO_CRL_MODE2_1; \
GPIOA->CRL &= ~GPIO_CRL_CNF2_0; \
GPIOA->CRL |= GPIO_CRL_CNF2_1; \
GPIOA->CRL |= GPIO_CRL_CNF3_0; \
GPIOA->CRL &= ~GPIO_CRL_CNF3_1; \
UART_LL_UART2_STRUCTURE->BRR = (SystemCoreClock / (baudrate * 2)); \
} \
#endif
#endif /* INC_DRIVERS_UART_LL_H_ */

34
Src/drivers/watchdog.c → Core/Inc/drivers/usb.h
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@ -1,4 +1,6 @@
/*
Copyright 2020-2023 Piotr Wilkon
This file is part of VP-Digi.
VP-Digi is free software: you can redistribute it and/or modify
@ -15,19 +17,27 @@ You should have received a copy of the GNU General Public License
along with VP-Digi. If not, see <http://www.gnu.org/licenses/>.
*/
#include "drivers/watchdog.h"
#ifndef DRIVERS_USB_H_
#define DRIVERS_USB_H_
#include "systick.h"
#if defined(STM32F103xB) || defined(STM32F103x8)
#include "stm32f1xx.h"
void Wdog_init(void)
{
IWDG->KR = 0x5555; //configuration mode
IWDG->PR = 0b101; //prescaler
IWDG->RLR = 0xFFF; //timeout register
IWDG->KR = 0xCCCC; //start
}
#define USB_FORCE_REENUMERATION() { \
/* Pull D+ to ground for a moment to force reenumeration */ \
RCC->APB2ENR |= RCC_APB2ENR_IOPAEN; \
GPIOA->CRH |= GPIO_CRH_MODE12_1; \
GPIOA->CRH &= ~GPIO_CRH_CNF12; \
GPIOA->BSRR = GPIO_BSRR_BR12; \
Delay(100); \
GPIOA->CRH &= ~GPIO_CRH_MODE12; \
GPIOA->CRH |= GPIO_CRH_CNF12_0; \
} \
#endif
void Wdog_reset(void)
{
IWDG->KR = 0xAAAA; //reset
}
#endif /* DRIVERS_USB_H_ */

19
Inc/drivers/watchdog.h → Core/Inc/drivers/watchdog.h
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@ -1,4 +1,6 @@
/*
Copyright 2020-2023 Piotr Wilkon
This file is part of VP-Digi.
VP-Digi is free software: you can redistribute it and/or modify
@ -18,17 +20,28 @@ along with VP-Digi. If not, see <http://www.gnu.org/licenses/>.
#ifndef DRIVERS_WATCHDOG_H_
#define DRIVERS_WATCHDOG_H_
#if defined(STM32F103xB) || defined(STM32F103x8)
/**
* @brief Initialize watchdog
*/
void Wdog_init(void);
void WdogInit(void)
{
IWDG->KR = 0x5555; //configuration mode
IWDG->PR = 0b101; //prescaler
IWDG->RLR = 0xFFF; //timeout register
IWDG->KR = 0xCCCC; //start
}
/**
* @brief Restart watchdog
* @attention Must be called continuously in main loop
*/
void Wdog_reset(void);
void WdogReset(void)
{
IWDG->KR = 0xAAAA; //reset
}
#endif
#endif /* DRIVERS_WATCHDOG_H_ */

76
Core/Inc/fx25.h 100644
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@ -0,0 +1,76 @@
/*
Copyright 2020-2023 Piotr Wilkon
This file is part of VP-Digi.
VP-Digi is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
VP-Digi is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with VP-Digi. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef FX25_H_
#define FX25_H_
#ifdef ENABLE_FX25
#include <stdint.h>
#include <stdbool.h>
#define FX25_MAX_BLOCK_SIZE 255
struct Fx25Mode
{
uint64_t tag; //correlation tag
uint16_t K; //data size
uint8_t T; //parity check size
};
extern const struct Fx25Mode Fx25ModeList[11];
/**
* @brief Get FX.25 mode for given correlation tag
* @param tag FX.25 correlation tag
* @return FX.25 mode structure pointer or NULL if not a FX.25 tag
*/
const struct Fx25Mode* Fx25GetModeForTag(uint64_t tag);
/**
* @brief Get FX.25 mode for given payload size
* @param size Payload size including flags and CRC
* @return FX.25 mode structure pointer or NULL if standard AX.25 must be used
*/
const struct Fx25Mode* Fx25GetModeForSize(uint16_t size);
/**
* @brief Encode AX.25 message in FX.25
* @param *buffer AX.25 message (bit-stuffed, with CRC and padding)
* @param *mode FX.25 mode
*/
void Fx25Encode(uint8_t *buffer, const struct Fx25Mode *mode);
/**
* @brief Decode/fix FX.25 packet
* @param *buffer Input buffer
* @param *mode FX.25 mode
* @param *fixed Number of bytes fixed
* @return True if message is valid, false if uncorrectable
*/
bool Fx25Decode(uint8_t *buffer, const struct Fx25Mode *mode, uint8_t *fixed);
/**
* @brief Initialize FX.25 module
*/
void Fx25Init(void);
#endif
#endif /* FX25_H_ */

42
Core/Inc/kiss.h 100644
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@ -0,0 +1,42 @@
/*
Copyright 2020-2023 Piotr Wilkon
This file is part of VP-Digi.
VP-Digi is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
VP-Digi is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with VP-Digi. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef KISS_H_
#define KISS_H_
#include <stdint.h>
#include "uart.h"
/**
* @brief Convert AX.25 frame to KISS and send
* @param *port UART structure
* @param *buf Frame buffer
* @param size Frame size
*/
void KissSend(Uart *port, uint8_t *buf, uint16_t size);
/**
* @brief Parse bytes received from UART to form a KISS frame (possibly) and send this frame
* @param *port UART structure
* @param data Received byte
*/
void KissParse(Uart *port, uint8_t data);
void KissProcess(Uart *port);
#endif /* KISS_H_ */

16
Inc/main.h → Core/Inc/main.h
Wyświetl plik

@ -7,18 +7,19 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
* All rights reserved.</center></h2>
* Copyright (c) 2023 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/*
Copyright 2020-2023 Piotr Wilkon
This file is part of VP-Digi.
VP-Digi is free software: you can redistribute it and/or modify
@ -75,6 +76,7 @@ void Error_Handler(void);
/* USER CODE END EFP */
/* Private defines -----------------------------------------------------------*/
/* USER CODE BEGIN Private defines */
/* USER CODE END Private defines */
@ -84,5 +86,3 @@ void Error_Handler(void);
#endif
#endif /* __MAIN_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

148
Core/Inc/modem.h 100644
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@ -0,0 +1,148 @@
/*
Copyright 2020-2023 Piotr Wilkon
This file is part of VP-Digi.
VP-Digi is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
VP-Digi is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with VP-Digi. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef DRIVERS_MODEM_H_
#define DRIVERS_MODEM_H_
#include <stdint.h>
//number of maximum parallel demodulators
//each demodulator must be explicitly configured in code
//currently used only for 1200 Bd modem
#define MODEM_MAX_DEMODULATOR_COUNT 2
enum ModemType
{
MODEM_1200 = 0,
MODEM_1200_V23,
MODEM_300,
MODEM_9600,
};
enum ModemTxTestMode
{
TEST_DISABLED,
TEST_MARK,
TEST_SPACE,
TEST_ALTERNATING,
};
struct ModemDemodConfig
{
enum ModemType modem;
uint8_t usePWM : 1; //0 - use R2R, 1 - use PWM
uint8_t flatAudioIn : 1; //0 - normal (deemphasized) audio input, 1 - flat audio (unfiltered) input
};
extern struct ModemDemodConfig ModemConfig;
enum ModemPrefilter
{
PREFILTER_NONE = 0,
PREFILTER_PREEMPHASIS,
PREFILTER_DEEMPHASIS,
PREFILTER_FLAT,
};
/**
* @brief Get measured signal level
* @param modem Modem number
* @param *peak Output signal positive peak in %
* @param *valley Output signal negative peak in %
* @param *level Output signal level in %
*/
void ModemGetSignalLevel(uint8_t modem, int8_t *peak, int8_t *valley, uint8_t *level);
/**
* @brief Get current modem baudrate
* @return Baudrate
*/
float ModemGetBaudrate(void);
/**
* @brief Get count of demodulators running in parallel
* @return Count of demodulators
*/
uint8_t ModemGetDemodulatorCount(void);
/**
* @brief Get prefilter type (preemphasis, deemphasis etc.) for given modem
* @param modem Modem number
* @return Filter type
*/
enum ModemPrefilter ModemGetFilterType(uint8_t modem);
/**
* @brief Get current DCD state
* @return 1 if channel busy, 0 if free
*/
uint8_t ModemDcdState(void);
/**
* @brief Check if there is a TX test mode enabled
* @return 1 if in TX test mode, 0 otherwise
*/
uint8_t ModemIsTxTestOngoing(void);
/**
* @brief Clear modem RMS counter
* @param number Modem number
*/
void ModemClearRMS(uint8_t number);
/**
* @brief Get RMS value for modem
* @param number Modem number
* @return RMS value
*/
uint16_t ModemGetRMS(uint8_t number);
/**
* @brief Start or restart TX test mode
* @param type TX test type: TEST_MARK, TEST_SPACE or TEST_ALTERNATING
*/
void ModemTxTestStart(enum ModemTxTestMode type);
/**
* @brief Stop TX test mode
*/
void ModemTxTestStop(void);
/**
* @brief Configure and start TX
* @info This function is used internally by protocol module.
* @warning Use Ax25TransmitStart() to initialize transmission
*/
void ModemTransmitStart(void);
/**
* @brief Stop TX and go back to RX
*/
void ModemTransmitStop(void);
/**
* @brief Initialize modem module
*/
void ModemInit(void);
#endif

56
Inc/stm32f1xx_hal_conf.h → Core/Inc/stm32f1xx_hal_conf.h
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@ -1,3 +1,4 @@
/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file stm32f1xx_hal_conf.h
@ -5,16 +6,16 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* USER CODE END Header */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_HAL_CONF_H
@ -83,11 +84,11 @@
* (when HSE is used as system clock source, directly or through the PLL).
*/
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
#define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (HSE_STARTUP_TIMEOUT)
#define HSE_STARTUP_TIMEOUT ((uint32_t)100) /*!< Time out for HSE start up, in ms */
#define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */
#endif /* HSE_STARTUP_TIMEOUT */
/**
@ -96,7 +97,7 @@
* (when HSI is used as system clock source, directly or through the PLL).
*/
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/
#define HSI_VALUE 8000000U /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
@ -113,11 +114,11 @@
* This value is used by the UART, RTC HAL module to compute the system frequency
*/
#if !defined (LSE_VALUE)
#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External oscillator in Hz*/
#define LSE_VALUE 32768U /*!< Value of the External oscillator in Hz*/
#endif /* LSE_VALUE */
#if !defined (LSE_STARTUP_TIMEOUT)
#define LSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for LSE start up, in ms */
#define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */
#endif /* LSE_STARTUP_TIMEOUT */
/* Tip: To avoid modifying this file each time you need to use different HSE,
@ -127,10 +128,10 @@
/**
* @brief This is the HAL system configuration section
*/
#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY ((uint32_t)0) /*!< tick interrupt priority (lowest by default) */
#define USE_RTOS 0
#define PREFETCH_ENABLE 1
#define VDD_VALUE 3300U /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY 15U /*!< tick interrupt priority (lowest by default) */
#define USE_RTOS 0U
#define PREFETCH_ENABLE 1U
#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */
#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */
@ -168,30 +169,30 @@
/* Section 1 : Ethernet peripheral configuration */
/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
#define MAC_ADDR0 2
#define MAC_ADDR1 0
#define MAC_ADDR2 0
#define MAC_ADDR3 0
#define MAC_ADDR4 0
#define MAC_ADDR5 0
#define MAC_ADDR0 2U
#define MAC_ADDR1 0U
#define MAC_ADDR2 0U
#define MAC_ADDR3 0U
#define MAC_ADDR4 0U
#define MAC_ADDR5 0U
/* Definition of the Ethernet driver buffers size and count */
#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
#define ETH_RXBUFNB ((uint32_t)8) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
#define ETH_TXBUFNB ((uint32_t)4) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
#define ETH_RXBUFNB 8U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
/* Section 2: PHY configuration section */
/* DP83848_PHY_ADDRESS Address*/
#define DP83848_PHY_ADDRESS 0x01U
/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
#define PHY_RESET_DELAY ((uint32_t)0x000000FF)
#define PHY_RESET_DELAY 0x000000FFU
/* PHY Configuration delay */
#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFF)
#define PHY_CONFIG_DELAY 0x00000FFFU
#define PHY_READ_TO ((uint32_t)0x0000FFFF)
#define PHY_WRITE_TO ((uint32_t)0x0000FFFF)
#define PHY_READ_TO 0x0000FFFFU
#define PHY_WRITE_TO 0x0000FFFFU
/* Section 3: Common PHY Registers */
@ -388,4 +389,3 @@ void assert_failed(uint8_t* file, uint32_t line);
#endif /* __STM32F1xx_HAL_CONF_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

13
Inc/stm32f1xx_it.h → Core/Inc/stm32f1xx_it.h
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@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
* All rights reserved.</center></h2>
* Copyright (c) 2023 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@ -66,5 +65,3 @@ void USB_LP_CAN1_RX0_IRQHandler(void);
#endif
#endif /* __STM32F1xx_IT_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

44
Core/Inc/systick.h 100644
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@ -0,0 +1,44 @@
/*
Copyright 2020-2023 Piotr Wilkon
This file is part of VP-Digi.
VP-Digi is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
VP-Digi is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with VP-Digi. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef SYSTICK_H_
#define SYSTICK_H_
#include <stdint.h>
#define SYSTICK_FREQUENCY 100 //systick frequency in Hz
#define SYSTICK_INTERVAL (1000 / SYSTICK_FREQUENCY) //systick interval in milliseconds
/**
* @brief Initialize SysTick
*/
void SysTickInit(void);
/**
* @brief Get current SysTick counter value
* @return Current SysTick counter value
*/
uint32_t SysTickGet(void);
/**
* @brief Execute a blocking delay
* @param ms Time in milliseconds
*/
void Delay(uint32_t ms);
#endif /* SYSTICK_H_ */

55
Core/Inc/terminal.h 100644
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@ -0,0 +1,55 @@
/*
Copyright 2020-2023 Piotr Wilkon
This file is part of VP-Digi.
VP-Digi is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
VP-Digi is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with VP-Digi. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef TERMINAL_H_
#define TERMINAL_H_
#include "uart.h"
#include <stdint.h>
/**
* @brief Send data to all available ports
* @param mode Output mode/data type
* @param *data Data buffer
* @param size Data size
*/
void TermSendToAll(enum UartMode mode, uint8_t *data, uint16_t size);
/**
* @brief Send signed number to all available ports
* @param mode Output mode/data type
* @param n Number to send
*/
void TermSendNumberToAll(enum UartMode mode, int32_t n);
/**
* @brief Handle "special" terminal cases like backspace or local echo
* @param *u UART structure
* @attention Must be called for every received data
*/
void TermHandleSpecial(Uart *u);
/**
* @brief Parse and process received data
* @param *src UART structure
*/
void TermParse(Uart *src);
#endif /* DEBUG_H_ */

114
Core/Inc/uart.h 100644
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@ -0,0 +1,114 @@
/*
Copyright 2020-2023 Piotr Wilkon
This file is part of VP-Digi.
VP-Digi is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
VP-Digi is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with VP-Digi. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef UART_H_
#define UART_H_
#include <stdint.h>
#include "usbd_cdc_if.h"
#include "ax25.h"
#include "drivers/uart_ll.h"
#define UART_BUFFER_SIZE 130
enum UartMode
{
MODE_KISS,
MODE_TERM,
MODE_MONITOR,
};
enum UartDataType
{
DATA_NOTHING = 0,
DATA_TERM,
DATA_KISS,
DATA_USB,
};
typedef struct
{
volatile USART_TypeDef *port; //UART peripheral
uint32_t baudrate; //baudrate 1200-115200
enum UartDataType rxType; //rx status
uint8_t enabled : 1;
uint8_t isUsb : 1;
volatile uint8_t rxBuffer[UART_BUFFER_SIZE];
volatile uint16_t rxBufferHead;
uint8_t txBuffer[UART_BUFFER_SIZE];
volatile uint16_t txBufferHead, txBufferTail;
volatile uint8_t txBufferFull : 1;
enum UartMode mode;
enum UartMode defaultMode;
volatile uint16_t lastRxBufferHead; //for special characters handling
volatile uint8_t kissBuffer[AX25_FRAME_MAX_SIZE + 1];
volatile uint16_t kissBufferHead;
volatile uint8_t kissProcessingOngoing;
volatile uint8_t kissTempBuffer[10];
volatile uint16_t kissTempBufferHead;
} Uart;
extern Uart Uart1, Uart2, UartUsb;
/**
* @brief Send byte
* @param[in] *port UART
* @param[in] data Data
*/
void UartSendByte(Uart *port, uint8_t data);
/**
* @brief Send string
* @param *port UART
* @param *data Buffer
* @param len Buffer length or 0 for null-terminated string
*/
void UartSendString(Uart *port, void *data, uint16_t datalen);
/**
* @brief Send signed number
* @param *port UART
* @param n Number
*/
void UartSendNumber(Uart *port, int32_t n);
/**
* @brief Initialize UART structures
* @param *port UART [prt
* @param *uart Physical UART peripheral. NULL if USB in CDC mode
* @param baud Baudrate
*/
void UartInit(Uart *port, USART_TypeDef *uart, uint32_t baud);
/**
* @brief Configure and enable/disable UART
* @param *port UART port
* @param state 0 - disable, 1 - enable
*/
void UartConfig(Uart *port, uint8_t state);
/**
* @brief Clear RX buffer and flags
* @param *port UART port
*/
void UartClearRx(Uart *port);
#endif

974
Core/Src/ax25.c 100644
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@ -0,0 +1,974 @@
/*
Copyright 2020-2023 Piotr Wilkon
This file is part of VP-Digi.
VP-Digi is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
VP-Digi is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with VP-Digi. If not, see <http://www.gnu.org/licenses/>.
*/
#include "modem.h"
#include "ax25.h"
#include <stdlib.h>
#include "common.h"
#include <stdbool.h>
#include <string.h>
#include "systick.h"
#include "digipeater.h"
struct Ax25ProtoConfig Ax25Config;
#ifdef ENABLE_FX25
#include "fx25.h"
#endif
#define FRAME_MAX_COUNT (10) //max count of frames in buffer
#define FRAME_BUFFER_SIZE (FRAME_MAX_COUNT * AX25_FRAME_MAX_SIZE) //circular frame buffer length
#define STATIC_HEADER_FLAG_COUNT 4 //number of flags sent before each frame
#define STATIC_FOOTER_FLAG_COUNT 8 //number of flags sent after each frame
#define MAX_TRANSMIT_RETRY_COUNT 8 //max number of retries if channel is busy
#define SYNC_BYTE 0x7E //preamble/postamble octet
struct FrameHandle
{
uint16_t start;
uint16_t size;
int8_t peak;
int8_t valley;
uint8_t level;
uint8_t corrected;
#ifdef ENABLE_FX25
struct Fx25Mode *fx25Mode;
#endif
};
static uint8_t rxBuffer[FRAME_BUFFER_SIZE]; //circular buffer for received frames
static uint16_t rxBufferHead = 0; //circular RX buffer write index
static struct FrameHandle rxFrame[FRAME_MAX_COUNT];
static uint8_t rxFrameHead = 0;
static uint8_t rxFrameTail = 0;
static bool rxFrameBufferFull = false;
static uint8_t txBuffer[FRAME_BUFFER_SIZE]; //circular TX frame buffer
static uint16_t txBufferHead = 0; //circular TX buffer write index
static uint16_t txBufferTail = 0;
static struct FrameHandle txFrame[FRAME_MAX_COUNT];
static uint8_t txFrameHead = 0;
static uint8_t txFrameTail = 0;
static bool txFrameBufferFull = false;
#ifdef ENABLE_FX25
static uint8_t txFx25Buffer[FX25_MAX_BLOCK_SIZE];
static uint8_t txTagByteIdx = 0;
#endif
static uint8_t frameReceived; //a bitmap of receivers that received the frame
enum TxStage
{
TX_STAGE_IDLE = 0,
TX_STAGE_PREAMBLE,
TX_STAGE_HEADER_FLAGS,
TX_STAGE_DATA,
TX_STAGE_CRC,
TX_STAGE_FOOTER_FLAGS,
TX_STAGE_TAIL,
#ifdef ENABLE_FX25
//stages used in FX.25 mode additionally
TX_STAGE_CORRELATION_TAG,
#endif
};
enum TxInitStage
{
TX_INIT_OFF,
TX_INIT_WAITING,
TX_INIT_TRANSMITTING
};
static uint8_t txByte = 0; //current TX byte
static uint16_t txByteIdx = 0; //current TX byte index
static int8_t txBitIdx = 0; //current bit index in txByte
static uint16_t txDelayElapsed = 0; //counter of TXDelay bytes already sent
static uint8_t txFlagsElapsed = 0; //counter of flag bytes already sent
static uint8_t txCrcByteIdx = 0; //currently transmitted byte of CRC
static uint8_t txBitstuff = 0; //bit-stuffing counter
static uint16_t txTailElapsed; //counter of TXTail bytes already sent
static uint16_t txCrc = 0xFFFF; //current CRC
static uint32_t txQuiet = 0; //quit time + current tick value
static uint8_t txRetries = 0; //number of TX retries
static enum TxInitStage txInitStage; //current TX initialization stage
static enum TxStage txStage; //current TX stage
struct RxState
{
uint16_t crc; //current CRC
uint8_t frame[AX25_FRAME_MAX_SIZE]; //raw frame buffer
uint16_t frameIdx; //index for raw frame buffer
uint8_t receivedByte; //byte being currently received
uint8_t receivedBitIdx; //bit index for recByte
uint8_t rawData; //raw data being currently received
enum Ax25RxStage rx; //current RX stage
uint8_t frameReceived; //frame received flag
#ifdef ENABLE_FX25
struct Fx25Mode *fx25Mode;
uint64_t tag; //received correlation tag
#endif
};
static struct RxState rxState[MODEM_MAX_DEMODULATOR_COUNT];
static uint16_t lastCrc = 0; //CRC of the last received frame. If not 0, a frame was successfully received
static uint16_t rxMultiplexDelay = 0; //simple delay for decoder multiplexer to avoid receiving the same frame twice
static uint16_t txDelay; //number of TXDelay bytes to send
static uint16_t txTail; //number of TXTail bytes to send
static uint8_t outputFrameBuffer[AX25_FRAME_MAX_SIZE];
#define GET_FREE_SIZE(max, head, tail) (((head) < (tail)) ? ((tail) - (head)) : ((max) - (head) + (tail)))
#define GET_USED_SIZE(max, head, tail) (max - GET_FREE_SIZE(max, head, tail))
/**
* @brief Recalculate CRC for one bit
* @param bit Input bit
* @param *crc CRC pointer
*/
static void calculateCRC(uint8_t bit, uint16_t *crc)
{
uint16_t xor_result;
xor_result = *crc ^ bit;
*crc >>= 1;
if (xor_result & 0x0001)
{
*crc ^= 0x8408;
}
}
uint8_t Ax25GetReceivedFrameBitmap(void)
{
return frameReceived;
}
void Ax25ClearReceivedFrameBitmap(void)
{
frameReceived = 0;
}
#ifdef ENABLE_FX25
static void removeLastFrameFromRxBuffer(void)
{
rxBufferHead = rxFrame[rxFrameHead].start;
if(rxFrameHead == 0)
rxFrameHead = FRAME_MAX_COUNT - 1;
else
rxFrameHead--;
rxFrameBufferFull = false;
}
static void *writeFx25Frame(uint8_t *data, uint16_t size)
{
//first calculate how big the frame can be
//this includes 2 flags, 2 CRC bytes and all bits added by bitstuffing
//bitstuffing occurs after 5 consecutive ones, so in worst scenario
//bits inserted by bitstuffing can occupy up to frame size / 5 additional bytes
//also add 1 in case there is a remainder when dividing
const struct Fx25Mode *fx25Mode = fx25Mode = Fx25GetModeForSize(size + 4 + (size / 5) + 1);
uint16_t requiredSize = size;
if(NULL != fx25Mode)
requiredSize = fx25Mode->K + fx25Mode->T;
else
return NULL; //frame will not fit in FX.25
uint16_t freeSize = GET_FREE_SIZE(FRAME_BUFFER_SIZE, txBufferHead, txBufferTail);
if(freeSize < requiredSize) //check if there is enough size to store full FX.25 (or AX.25) frame
{
return NULL; //if not, it may fit in standard AX.25
}
txFrame[txFrameHead].size = requiredSize;
txFrame[txFrameHead].start = txBufferHead;
txFrame[txFrameHead].fx25Mode = (struct Fx25Mode*)fx25Mode;
memset(txFx25Buffer, 0, sizeof(txFx25Buffer));
uint16_t index = 0;
//header flag
txFx25Buffer[index++] = 0x7E;
uint16_t crc = 0xFFFF;
uint8_t bits = 0; //bit counter within a byte
uint8_t bitstuff = 0;
for(uint16_t i = 0; i < size + 2; i++)
{
for(uint8_t k = 0; k < 8; k++)
{
txFx25Buffer[index] >>= 1;
bits++;
if(i < size) //frame data
{
if((data[i] >> k) & 1)
{
calculateCRC(1, &crc);
bitstuff++;
txFx25Buffer[index] |= 0x80;
}
else
{
calculateCRC(0, &crc);
bitstuff = 0;
}
}
else //crc
{
uint8_t c = 0;
if(i == size)
c = (crc & 0xFF) ^ 0xFF;
else
c = (crc >> 8) ^ 0xFF;
if((c >> k) & 1)
{
bitstuff++;
txFx25Buffer[index] |= 0x80;
}
else
{
bitstuff = 0;
}
}
if(bits == 8)
{
bits = 0;
index++;
}
if(bitstuff == 5)
{
bits++;
bitstuff = 0;
txFx25Buffer[index] >>= 1;
if(bits == 8)
{
bits = 0;
index++;
}
}
}
}
//pad with flags
while(index < fx25Mode->K)
{
for(uint8_t k = 0; k < 8; k++)
{
txFx25Buffer[index] >>= 1;
bits++;
if((0x7E >> k) & 1)
{
txFx25Buffer[index] |= 0x80;
}
if(bits == 8)
{
bits = 0;
index++;
}
}
}
Fx25Encode(txFx25Buffer, fx25Mode);
for(uint16_t i = 0; i < (fx25Mode->K + fx25Mode->T); i++)
{
txBuffer[txBufferHead++] = txFx25Buffer[i];
txBufferHead %= FRAME_BUFFER_SIZE;
}
void *ret = &txFrame[txFrameHead];
txFrameHead++;
txFrameHead %= FRAME_MAX_COUNT;
if(txFrameHead == txFrameTail)
txFrameBufferFull = true;
return ret;
}
static struct FrameHandle* parseFx25Frame(uint8_t *frame, uint16_t size, uint16_t *crc)
{
struct FrameHandle *h = &rxFrame[rxFrameHead];
uint16_t initialRxBufferHead = rxBufferHead;
if(!rxFrameBufferFull)
{
rxFrame[rxFrameHead++].start = rxBufferHead;
rxFrameHead %= FRAME_MAX_COUNT;
if(rxFrameHead == txFrameHead)
rxFrameBufferFull = true;
}
else
return NULL;
uint16_t i = 0; //input data index
uint16_t k = 0; //output data size
while(frame[i] == 0x7E)
i++;
uint8_t bitstuff = 0;
uint8_t outBit = 0;
for(; i < size; i++)
{
for(uint8_t b = 0; b < 8; b++)
{
if(frame[i] & (1 << b))
{
rxBuffer[rxBufferHead] >>= 1;
rxBuffer[rxBufferHead] |= 0x80;
bitstuff++;
}
else
{
if(bitstuff == 5) //zero after 5 ones, normal bitstuffing
{
bitstuff = 0;
continue;
}
else if(bitstuff == 6) //zero after 6 ones, this is a flag
{
goto endParseFx25Frame;
}
else if(bitstuff >= 7) //zero after 7 ones, illegal byte
{
removeLastFrameFromRxBuffer();
return NULL;
}
bitstuff = 0;
rxBuffer[rxBufferHead] >>= 1;
}
outBit++;
if(outBit == 8)
{
k++;
rxBufferHead++;
rxBufferHead %= FRAME_BUFFER_SIZE;
outBit = 0;
}
}
}
endParseFx25Frame:
*crc = 0xFFFF;
i = initialRxBufferHead;
for(uint16_t j = 0; j < (k - 2); j++)
{
for(uint8_t b = 0; b < 8; b++)
calculateCRC((rxBuffer[i] >> b) & 1, crc);
i++;
i %= FRAME_BUFFER_SIZE;
}
*crc ^= 0xFFFF;
if((rxBuffer[i] == (*crc & 0xFF) )
&& (rxBuffer[(i + 1) % FRAME_BUFFER_SIZE] == ((*crc >> 8) & 0xFF))) //check CRC
{
uint16_t pathEnd = initialRxBufferHead;
for(uint16_t j = 0; j < (k - 2); j++)
{
if(rxBuffer[pathEnd] & 1)
break;
pathEnd++;
pathEnd %= FRAME_BUFFER_SIZE;
}
if(Ax25Config.allowNonAprs || (((rxBuffer[(pathEnd + 1) % FRAME_BUFFER_SIZE] == 0x03) && (rxBuffer[(pathEnd + 2) % FRAME_BUFFER_SIZE] == 0xF0))))
{
h->size = k - 2;
return h;
}
}
removeLastFrameFromRxBuffer();
return NULL;
}
#endif
void *Ax25WriteTxFrame(uint8_t *data, uint16_t size)
{
if(txFrameBufferFull)
return NULL;
#ifdef ENABLE_FX25
if(Ax25Config.fx25 && Ax25Config.fx25Tx)
{
void *ret = writeFx25Frame(data, size);
if(ret)
return ret;
}
#endif
if(GET_FREE_SIZE(FRAME_BUFFER_SIZE, txBufferHead, txBufferTail) < size)
{
return NULL;
}
txFrame[txFrameHead].size = size;
txFrame[txFrameHead].start = txBufferHead;
#ifdef ENABLE_FX25
txFrame[txFrameHead].fx25Mode = NULL;
#endif
for(uint16_t i = 0; i < size; i++)
{
txBuffer[txBufferHead++] = data[i];
txBufferHead %= FRAME_BUFFER_SIZE;
}
void *ret = &txFrame[txFrameHead];
__disable_irq();
txFrameHead++;
txFrameHead %= FRAME_MAX_COUNT;
if(txFrameHead == txFrameTail)
txFrameBufferFull = true;
__enable_irq();
return ret;
}
bool Ax25ReadNextRxFrame(uint8_t **dst, uint16_t *size, int8_t *peak, int8_t *valley, uint8_t *level, uint8_t *corrected)
{
if((rxFrameHead == rxFrameTail) && !rxFrameBufferFull)
return false;
*dst = outputFrameBuffer;
for(uint16_t i = 0; i < rxFrame[rxFrameTail].size; i++)
{
(*dst)[i] = rxBuffer[(rxFrame[rxFrameTail].start + i) % FRAME_BUFFER_SIZE];
}
*peak = rxFrame[rxFrameTail].peak;
*valley = rxFrame[rxFrameTail].valley;
*level = rxFrame[rxFrameTail].level;
*size = rxFrame[rxFrameTail].size;
*corrected = rxFrame[rxFrameTail].corrected;
__disable_irq();
rxFrameBufferFull = false;
rxFrameTail++;
rxFrameTail %= FRAME_MAX_COUNT;
__enable_irq();
return true;
}
enum Ax25RxStage Ax25GetRxStage(uint8_t modem)
{
return rxState[modem].rx;
}
void Ax25BitParse(uint8_t bit, uint8_t modem)
{
if(lastCrc != 0) //there was a frame received
{
rxMultiplexDelay++;
if(rxMultiplexDelay > (4 * MODEM_MAX_DEMODULATOR_COUNT)) //hold it for a while and wait for other decoders to receive the frame
{
lastCrc = 0;
rxMultiplexDelay = 0;
for(uint8_t i = 0; i < MODEM_MAX_DEMODULATOR_COUNT; i++)
{
frameReceived |= ((rxState[i].frameReceived > 0) << i);
rxState[i].frameReceived = 0;
}
}
}
struct RxState *rx = (struct RxState*)&(rxState[modem]);
rx->rawData <<= 1; //store incoming bit
rx->rawData |= (bit > 0);
#ifdef ENABLE_FX25
rx->tag >>= 1;
if(bit)
rx->tag |= 0x8000000000000000;
if(Ax25Config.fx25
&& (rx->rx != RX_STAGE_FX25_FRAME)
&& (NULL != (rx->fx25Mode = (struct Fx25Mode*)Fx25GetModeForTag(rx->tag))))
{
rx->rx = RX_STAGE_FX25_FRAME;
rx->receivedByte = 0;
rx->receivedBitIdx = 0;
rx->frameIdx = 0;
return;
}
if(rx->rx != RX_STAGE_FX25_FRAME)
{
#endif
if(rx->rawData == 0x7E) //HDLC flag received
{
if(rx->rx == RX_STAGE_FRAME) //if we are in frame, this is the end of the frame
{
if(rx->frameIdx >= 17) //correct frame must be at least 17 bytes long (source+destination+control+CRC)
{
rx->crc ^= 0xFFFF;
if((rx->frame[rx->frameIdx - 2] == (rx->crc & 0xFF)) && (rx->frame[rx->frameIdx - 1] == ((rx->crc >> 8) & 0xFF))) //check CRC
{
uint16_t i = 13;
//start from 13, which is the SSID of source
for(; i < (rx->frameIdx - 2); i++) //look for path end bit
{
if(rx->frame[i] & 1)
break;
}
//if non-APRS frames are not allowed, check if this frame has control=0x03 and PID=0xF0
if(Ax25Config.allowNonAprs || (((rx->frame[i + 1] == 0x03) && (rx->frame[i + 2] == 0xF0))))
{
rx->frameReceived = 1;
rx->frameIdx -= 2; //remove CRC
if(rx->crc != lastCrc) //the other decoder has not received this frame yet, so store it in main frame buffer
{
lastCrc = rx->crc; //store CRC of this frame
if(!rxFrameBufferFull) //if enough space, store the frame
{
rxFrame[rxFrameHead].start = rxBufferHead;
ModemGetSignalLevel(modem, &rxFrame[rxFrameHead].peak, &rxFrame[rxFrameHead].valley, &rxFrame[rxFrameHead].level);
#ifdef ENABLE_FX25
rxFrame[rxFrameHead].fx25Mode = NULL;
#endif
rxFrame[rxFrameHead].corrected = AX25_NOT_FX25;
__disable_irq();
rxFrame[rxFrameHead++].size = rx->frameIdx;
rxFrameHead %= FRAME_MAX_COUNT;
if(rxFrameHead == rxFrameTail)
rxFrameBufferFull = true;
__enable_irq();
for(uint16_t i = 0; i < rx->frameIdx; i++)
{
rxBuffer[rxBufferHead++] = rx->frame[i];
rxBufferHead %= FRAME_BUFFER_SIZE;
}
}
}
}
}
}
}
rx->rx = RX_STAGE_FLAG;
rx->receivedByte = 0;
rx->receivedBitIdx = 0;
rx->frameIdx = 0;
rx->crc = 0xFFFF;
return;
}
else
rx->rx = RX_STAGE_FRAME;
#ifndef ENABLE_FX25
{
//this condition must not be checked when FX.25 is enabled
//because FX.25 parity bytes and tags contain >= 7 consecutive ones
if((rx->rawData & 0x7F) == 0x7F) //received 7 consecutive ones, this is an error
{
rx->rx = RX_STAGE_IDLE;
rx->receivedByte = 0;
rx->receivedBitIdx = 0;
rx->frameIdx = 0;
rx->crc = 0xFFFF;
return;
}
#endif
if((rx->rawData & 0x3F) == 0x3E) //dismiss bit 0 added by bit stuffing
return;
}
if(rx->rawData & 0x01) //received bit 1
rx->receivedByte |= 0x80; //store it
if(++rx->receivedBitIdx >= 8) //received full byte
{
if(rx->frameIdx >= 2)
{
for(uint8_t k = 0; k < 8; k++)
{
calculateCRC((rx->frame[rx->frameIdx - 2] >> k) & 1, &(rx->crc));
}
}
#ifdef ENABLE_FX25
//end of FX.25 reception, that is received full block
if((rx->fx25Mode != NULL) && (rx->frameIdx == (rx->fx25Mode->K + rx->fx25Mode->T)))
{
uint8_t fixed = 0;
bool fecSuccess = Fx25Decode(rx->frame, rx->fx25Mode, &fixed);
uint16_t crc;
struct FrameHandle *h = parseFx25Frame(rx->frame, rx->frameIdx, &crc);
if(h != NULL)
{
rx->frameReceived = 1;
ModemGetSignalLevel(modem, &h->peak, &h->valley, &h->level);
if(fecSuccess)
{
h->corrected = fixed;
h->fx25Mode = rx->fx25Mode;
}
else
h->corrected = AX25_NOT_FX25;
lastCrc = crc;
}
rx->rx = RX_STAGE_FLAG;
rx->receivedByte = 0;
rx->receivedBitIdx = 0;
rx->frameIdx = 0;
return;
}
#else
rx->rx = RX_STAGE_FRAME;
#endif
if(rx->frameIdx >= AX25_FRAME_MAX_SIZE) //frame is too long
{
rx->rx = RX_STAGE_IDLE;
rx->receivedByte = 0;
rx->receivedBitIdx = 0;
rx->frameIdx = 0;
rx->crc = 0xFFFF;
return;
}
rx->frame[rx->frameIdx++] = rx->receivedByte; //store received byte
rx->receivedByte = 0;
rx->receivedBitIdx = 0;
}
else
rx->receivedByte >>= 1;
}
uint8_t Ax25GetTxBit(void)
{
if(txBitIdx == 8)
{
txBitIdx = 0;
if(txStage == TX_STAGE_PREAMBLE) //transmitting preamble (TXDelay)
{
if(txDelayElapsed < txDelay)
{
txByte = SYNC_BYTE;
txDelayElapsed++;
}
else
{
txDelayElapsed = 0;
#ifdef ENABLE_FX25
if(NULL != txFrame[txFrameTail].fx25Mode)
{
txStage = TX_STAGE_CORRELATION_TAG;
txTagByteIdx = 0;
}
else
#endif
txStage = TX_STAGE_HEADER_FLAGS;
}
}
#ifdef ENABLE_FX25
transmitTag:
if(txStage == TX_STAGE_CORRELATION_TAG) //FX.25 correlation tag
{
if(txTagByteIdx < 8)
txByte = (txFrame[txFrameTail].fx25Mode->tag >> (8 * txTagByteIdx)) & 0xFF;
else
txStage = TX_STAGE_DATA;
txTagByteIdx++;
}
#endif
if(txStage == TX_STAGE_HEADER_FLAGS) //transmitting initial flags
{
if(txFlagsElapsed < STATIC_HEADER_FLAG_COUNT)
{
txByte = 0x7E;
txFlagsElapsed++;
}
else
{
txFlagsElapsed = 0;
txStage = TX_STAGE_DATA; //transmit data
}
}
if(txStage == TX_STAGE_DATA) //transmitting normal data
{
transmitNormalData:
__disable_irq();
if((txFrameHead != txFrameTail) || txFrameBufferFull)
{
__enable_irq();
if(txByteIdx < txFrame[txFrameTail].size) //send buffer
{
txByte = txBuffer[(txFrame[txFrameTail].start + txByteIdx) % FRAME_BUFFER_SIZE];
txByteIdx++;
}
#ifdef ENABLE_FX25
else if(txFrame[txFrameTail].fx25Mode != NULL)
{
__disable_irq();
txFrameBufferFull = false;
txFrameTail++;
txFrameTail %= FRAME_MAX_COUNT;
txByteIdx = 0;
__enable_irq();
if((txFrameHead != txFrameTail) || txFrameBufferFull)
{
if(txFrame[txFrameTail].fx25Mode != NULL)
{
txStage = TX_STAGE_CORRELATION_TAG;
txTagByteIdx = 0;
goto transmitTag;
}
else
goto transmitNormalData;
}
else
goto transmitTail;
}
#endif
else
{
txStage = TX_STAGE_CRC; //transmit CRC
txCrcByteIdx = 0;
}
}
else //no more frames
{
transmitTail:
__enable_irq();
txByteIdx = 0;
txBitIdx = 0;
txStage = TX_STAGE_TAIL;
}
}
if(txStage == TX_STAGE_CRC) //transmitting CRC
{
if(txCrcByteIdx <= 1)
{
txByte = (txCrc & 0xFF) ^ 0xFF;
txCrc >>= 8;
txCrcByteIdx++;
}
else
{
txCrc = 0xFFFF;
txStage = TX_STAGE_FOOTER_FLAGS; //now transmit flags
txFlagsElapsed = 0;
}
}
if(txStage == TX_STAGE_FOOTER_FLAGS)
{
if(txFlagsElapsed < STATIC_FOOTER_FLAG_COUNT)
{
txByte = 0x7E;
txFlagsElapsed++;
}
else
{
txFlagsElapsed = 0;
__disable_irq();
txFrameBufferFull = false;
txFrameTail++;
txFrameTail %= FRAME_MAX_COUNT;
txByteIdx = 0;
#ifdef ENABLE_FX25
if(((txFrameHead != txFrameTail) || txFrameBufferFull) && (txFrame[txFrameTail].fx25Mode != NULL))
{
__enable_irq();
txStage = TX_STAGE_CORRELATION_TAG;
txTagByteIdx = 0;
goto transmitTag;
}
#endif
__enable_irq();
txStage = TX_STAGE_DATA; //return to normal data transmission stage. There might be a next frame to transmit
goto transmitNormalData;
}
}
if(txStage == TX_STAGE_TAIL) //transmitting tail
{
if(txTailElapsed < txTail)
{
txByte = SYNC_BYTE;
txTailElapsed++;
}
else //tail transmitted, stop transmission
{
txTailElapsed = 0;
txStage = TX_STAGE_IDLE;
txCrc = 0xFFFF;
txBitstuff = 0;
txByte = 0;
txInitStage = TX_INIT_OFF;
txBufferTail = txBufferHead;
ModemTransmitStop();
return 0;
}
}
}
uint8_t txBit = 0;
//transmitting normal data or CRC in AX.25 mode
if(
#ifdef ENABLE_FX25
(NULL == txFrame[txFrameTail].fx25Mode) &&
#endif
((txStage == TX_STAGE_DATA) || (txStage == TX_STAGE_CRC)))
{
if(txBitstuff == 5) //5 consecutive ones transmitted
{
txBit = 0; //transmit bit-stuffed 0
txBitstuff = 0;
}
else
{
if(txByte & 1) //1 being transmitted
{
txBitstuff++; //increment bit stuffing counter
txBit = 1;
}
else
{
txBit = 0;
txBitstuff = 0; //0 being transmitted, reset bit stuffing counter
}
if(txStage == TX_STAGE_DATA) //calculate CRC only for normal data
calculateCRC(txByte & 1, &txCrc);
txByte >>= 1;
txBitIdx++;
}
}
//transmitting in FX.25 mode or in AX.25 mode, but these are preamble or flags, don't calculate CRC, don't use bit stuffing
else
{
txBit = txByte & 1;
txByte >>= 1;
txBitIdx++;
}
return txBit;
}
/**
* @brief Initialize transmission and start when possible
*/
void Ax25TransmitBuffer(void)
{
if(txInitStage == TX_INIT_WAITING)
return;
if(txInitStage == TX_INIT_TRANSMITTING)
return;
if((txFrameHead != txFrameTail) || txFrameBufferFull)
{
txQuiet = (SysTickGet() + (Ax25Config.quietTime / SYSTICK_INTERVAL) + Random(0, 200 / SYSTICK_INTERVAL)); //calculate required delay
txInitStage = TX_INIT_WAITING;
}
}
/**
* @brief Start transmission immediately
* @warning Transmission should be initialized using Ax25_transmitBuffer
*/
static void transmitStart(void)
{
txCrc = 0xFFFF; //initial CRC value
txStage = TX_STAGE_PREAMBLE;
txByte = 0;
txBitIdx = 0;
txFlagsElapsed = 0;
ModemTransmitStart();
}
/**
* @brief Start transmitting when possible
* @attention Must be continuously polled in main loop
*/
void Ax25TransmitCheck(void)
{
if(txInitStage == TX_INIT_OFF) //TX not initialized at all, nothing to transmit
return;
if(txInitStage == TX_INIT_TRANSMITTING) //already transmitting
return;
if(ModemIsTxTestOngoing()) //TX test is enabled, wait for now
return;
if(txQuiet < SysTickGet()) //quit time has elapsed
{
if(!ModemDcdState()) //channel is free
{
txInitStage = TX_INIT_TRANSMITTING; //transmit right now
txRetries = 0;
transmitStart();
}
else //channel is busy
{
if(txRetries == MAX_TRANSMIT_RETRY_COUNT) //timeout
{
txInitStage = TX_INIT_TRANSMITTING; //transmit right now
txRetries = 0;
transmitStart();
}
else //still trying
{
txQuiet = SysTickGet() + Random(100 / SYSTICK_INTERVAL, 500 / SYSTICK_INTERVAL); //try again after some random time
txRetries++;
}
}
}
}
void Ax25Init(void)
{
txCrc = 0xFFFF;
memset((void*)rxState, 0, sizeof(rxState));
for(uint8_t i = 0; i < (sizeof(rxState) / sizeof(rxState[0])); i++)
rxState[i].crc = 0xFFFF;
txDelay = ((float)Ax25Config.txDelayLength / (8.f * 1000.f / ModemGetBaudrate())); //change milliseconds to byte count
txTail = ((float)Ax25Config.txTailLength / (8.f * 1000.f / ModemGetBaudrate()));
}

130
Core/Src/beacon.c 100644
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@ -0,0 +1,130 @@
/*
Copyright 2020-2023 Piotr Wilkon
This file is part of VP-Digi.
VP-Digi is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
VP-Digi is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with VP-Digi. If not, see <http://www.gnu.org/licenses/>.
*/
#include "beacon.h"
#include "digipeater.h"
#include "common.h"
#include <string.h>
#include <systick.h>
#include "ax25.h"
#include "terminal.h"
struct Beacon beacon[8];
static uint32_t beaconDelay[8] = {0};
static uint8_t buf[150]; //frame buffer
/**
* @brief Send specified beacon
* @param[in] no Beacon number (0-7)
*/
void BeaconSend(uint8_t number)
{
if(beacon[number].enable == 0)
return; //beacon disabled
uint16_t idx = 0;
for(uint8_t i = 0; i < sizeof(GeneralConfig.dest); i++) //add destination address
buf[idx++] = GeneralConfig.dest[i];
for(uint8_t i = 0; i < sizeof(GeneralConfig.call); i++) //add source address
buf[idx++] = GeneralConfig.call[i];
buf[idx++] = ((GeneralConfig.callSsid << 1) + 0b01100000); //add source ssid
if(beacon[number].path[0] > 0) //this beacon has some path set
{
for(uint8_t i = 0; i < 14; i++) //loop through path
{
if((beacon[number].path[i] > 0) || (i == 6) || (i == 13)) //normal data, not a NULL symbol
{
buf[idx] = beacon[number].path[i]; //copy path
if((i == 6) || (i == 13)) //it was and ssid
{
buf[idx] = ((buf[idx] << 1) + 0b01100000); //add appropriate bits for ssid
}
idx++;
}
else //NULL in path
break; //end here
}
}
buf[idx - 1] |= 1; //add c-bit on the last element
buf[idx++] = 0x03; //control
buf[idx++] = 0xF0; //pid
for(uint8_t i = 0; i < strlen((char*)beacon[number].data); i++)
{
buf[idx++] = beacon[number].data[i]; //copy beacon comment
}
void *handle = NULL;
if(NULL != (handle = Ax25WriteTxFrame(buf, idx))) //try to write frame to TX buffer
{
if(GeneralConfig.kissMonitor) //monitoring mode, send own frames to KISS ports
{
TermSendToAll(MODE_KISS, buf, idx);
}
DigiStoreDeDupe(buf, idx); //store frame hash in duplicate protection buffer (to prevent from digipeating own packets)
TermSendToAll(MODE_MONITOR, (uint8_t*)"(AX.25) Transmitting beacon ", 0);
TermSendNumberToAll(MODE_MONITOR, number);
TermSendToAll(MODE_MONITOR, (uint8_t*)": ", 0);
SendTNC2(buf, idx);
TermSendToAll(MODE_MONITOR, (uint8_t*)"\r\n", 0);
}
}
/**
* @brief Check if any beacon should be transmitted and transmit if necessary
*/
void BeaconCheck(void)
{
for(uint8_t i = 0; i < 8; i++)
{
if(beacon[i].enable == 0)
continue;
if((beacon[i].interval > 0) && ((SysTickGet() >= beacon[i].next) || (beacon[i].next == 0)))
{
if(beaconDelay[i] > SysTickGet()) //check for beacon delay (only for the very first transmission)
continue;
beacon[i].next = SysTickGet() + beacon[i].interval; //save next beacon timestamp
beaconDelay[i] = 0;
BeaconSend(i);
}
}
}
/**
* @brief Initialize beacon module
*/
void BeaconInit(void)
{
for(uint8_t i = 0; i < 8; i++)
{
beaconDelay[i] = (beacon[i].delay * SYSTICK_FREQUENCY) + SysTickGet() + (30000 / SYSTICK_INTERVAL); //set delay for beacons and add constant 30 seconds of delay
beacon[i].next = 0;
}
}

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/*
Copyright 2020-2023 Piotr Wilkon
This file is part of VP-Digi.
VP-Digi is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
VP-Digi is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with VP-Digi. If not, see <http://www.gnu.org/licenses/>.
*/
#include <math.h>
#include <stdlib.h>
#include "common.h"
#include "ax25.h"
#include "usbd_cdc_if.h"
struct _GeneralConfig GeneralConfig =
{
.call = {'N' << 1, '0' << 1, 'C' << 1, 'A' << 1, 'L' << 1, 'L' << 1},
.callSsid = 0,
.dest = {130, 160, 156, 172, 96, 98, 96}, //destination address: APNV01-0 by default. SSID MUST remain 0.
.kissMonitor = 0,
};
const char versionString[] = "VP-Digi v. 2.0.0\r\nThe open-source standalone APRS digipeater controller and KISS TNC\r\n"
#ifdef ENABLE_FX25
"With FX.25 support compiled-in\r\n"
#endif
;
static uint64_t pow10i(uint16_t exp)
{
if(exp == 0)
return 1;
uint64_t n = 1;
while(exp--)
n *= 10;
return n;
}
int64_t StrToInt(const char *str, uint16_t len)
{
if(len == 0)
len = strlen(str);
int64_t tmp = 0;
for(int32_t i = (len - 1); i >= 0; i--)
{
if((i == 0) && (str[0] == '-'))
{
return -tmp;
}
else if(IS_NUMBER(str[i]))
tmp += ((str[i] - '0') * pow10i(len - 1 - i));
else
return 0;
}
return tmp;
}
int16_t Random(int16_t min, int16_t max)
{
int16_t tmp;
if (max >= min)
max -= min;
else
{
tmp = min - max;
min = max;
max = tmp;
}
return max ? (rand() % max + min) : min;
}
static void sendTNC2ToUart(Uart *uart, uint8_t *from, uint16_t len)
{
for(uint8_t i = 0; i < 6; i++) //source call
{
if((from[7 + i] >> 1) != ' ') //skip spaces
{
UartSendByte(uart, from[7 + i] >> 1);
}
}
uint8_t ssid = ((from[13] >> 1) & 0b00001111); //store ssid
if(ssid > 0) //SSID >0
{
UartSendByte(uart, '-'); //add -
UartSendNumber(uart, ssid);
}
UartSendByte(uart, '>'); //first separator
for(uint8_t i = 0; i < 6; i++) //destination call
{
if((from[i] >> 1) != ' ') //skip spaces
{
UartSendByte(uart, from[i] >> 1);
}
}
ssid = ((from[6] >> 1) & 0b00001111); //store ssid
if(ssid > 0) //SSID >0
{
UartSendByte(uart, '-'); //add -
UartSendNumber(uart, ssid);
}
uint16_t nextPathEl = 14; //next path element index
if(!(from[13] & 1)) //no c-bit in source address, there is a digi path
{
do //analyze all path elements
{
UartSendByte(uart, ','); //path separator
for(uint8_t i = 0; i < 6; i++) //copy element
{
if((from[nextPathEl + i] >> 1) != ' ') //skip spaces
{
UartSendByte(uart, from[nextPathEl + i] >> 1);
}
}
ssid = ((from[nextPathEl + 6] >> 1) & 0b00001111); //store ssid
if(ssid > 0) //SSID >0
{
UartSendByte(uart, '-'); //add -
UartSendNumber(uart, ssid);
}
if((from[nextPathEl + 6] & 0x80)) //h-bit in ssid
UartSendByte(uart, '*'); //add *
nextPathEl += 7; //next path element
if(nextPathEl > 56) //too many path elements
break;
}
while((from[nextPathEl - 1] & 1) == 0); //loop until the c-bit is found
}
UartSendByte(uart, ':'); //separator
if((from[nextPathEl] & 0b11101111) == 0b00000011) //check if UI packet
{
nextPathEl += 2; //skip Control and PID
UartSendString(uart, &(from[nextPathEl]), len - nextPathEl); //send information field
}
else
UartSendString(uart, "<not UI packet>", 0);
UartSendByte(uart, 0); //terminate with NULL
}
void SendTNC2(uint8_t *from, uint16_t len)
{
if(UartUsb.mode == MODE_MONITOR)
sendTNC2ToUart(&UartUsb, from, len);
if(Uart1.mode == MODE_MONITOR)
sendTNC2ToUart(&Uart1, from, len);
if(Uart2.mode == MODE_MONITOR)
sendTNC2ToUart(&Uart2, from, len);
}
uint32_t Crc32(uint32_t crc0, uint8_t *s, uint64_t n)
{
uint32_t crc = ~crc0;
for(uint64_t i = 0; i < n; i++)
{
uint8_t ch = s[i];
for(uint8_t j = 0; j < 8; j++) {
uint32_t b = (ch ^ crc) & 1;
crc >>= 1;
if(b) crc ^= 0xEDB88320;
ch >>= 1;
}
}
return ~crc;
}
bool ParseCallsign(const char *in, uint16_t size, uint8_t *out)
{
if(size > 6)
return false;
uint8_t tmp[6];
uint8_t i = 0;
for(; i < size; i++)
{
if(!IS_UPPERCASE_ALPHANUMERIC(in[i]))
return false;
tmp[i] = in[i] << 1;
}
for(uint8_t k = 0; k < i; k++)
out[k] = tmp[k];
for(; i < 6; i++)
out[i] = ' ' << 1;
return true;
}
bool ParseCallsignWithSsid(const char *in, uint16_t size, uint8_t *out, uint8_t *ssid)
{
uint16_t ssidPosition = size;
for(uint16_t i = 0; i < size; i++)
{
if(in[i] == '-')
{
ssidPosition = i;
break;
}
}
ssidPosition++;
if(!ParseCallsign(in, ssidPosition - 1, out))
return false;
if(ssidPosition == size)
{
*ssid = 0;
return true;
}
if(!ParseSsid(&in[ssidPosition], size - ssidPosition, ssid))
return false;
return true;
}
bool ParseSsid(const char *in, uint16_t size, uint8_t *out)
{
int64_t ssid = StrToInt(in, size);
if((ssid >= 0) && (ssid <= 15))
{
*out = (uint8_t)ssid;
return true;
}
return false;
}

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/*
Copyright 2020-2023 Piotr Wilkon
This file is part of VP-Digi.
VP-Digi is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
VP-Digi is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with VP-Digi. If not, see <http://www.gnu.org/licenses/>.
*/
#include "modem.h"
#include "uart.h"
#include "config.h"
#include "common.h"
#include "usbd_cdc_if.h"
#include "digipeater.h"
#include "ax25.h"
#include "beacon.h"
#include "stm32f1xx.h"
#define CONFIG_ADDRESS 0x800F000
#define CONFIG_PAGE_COUNT 2
#define CONFIG_PAGE_SIZE 1024 //1024 words (2048 bytes)
#define CONFIG_FLAG_WRITTEN 0x6B
//these are relative addresses, absolute address is calculated as relative address + MEM_CONFIG
//all fields are 16-bit or n*16-bit long, as data in flash is stored in 16-bit words
#define CONFIG_FLAG 0 //configuration written flag
#define CONFIG_CALL 2
#define CONFIG_SSID 8
#define CONFIG_TXDELAY 10
#define CONFIG_TXTAIL 12
#define CONFIG_TXQUIET 14
#define CONFIG_RS1BAUD 16
#define CONFIG_RS2BAUD 20
#define CONFIG_BEACONS 24
#define CONFIG_BCIV 26 //beacon intervals
#define CONFIG_BCDL 42 //beacon delays
#define CONFIG_BC0 58 //beacon information fields, null terminated
#define CONFIG_BC1 158
#define CONFIG_BC2 258
#define CONFIG_BC3 358
#define CONFIG_BC4 458
#define CONFIG_BC5 558
#define CONFIG_BC6 658
#define CONFIG_BC7 758
#define CONFIG_BCP0 858 //beacon paths, 14 bytes each
#define CONFIG_BCP1 872
#define CONFIG_BCP2 886
#define CONFIG_BCP3 900
#define CONFIG_BCP4 914
#define CONFIG_BCP5 928
#define CONFIG_BCP6 942
#define CONFIG_BCP7 956
#define CONFIG_DIGION 970
#define CONFIG_DIGIEN 972
#define CONFIG_DIGIVISC 974 //viscous-delay settings in higher half, direct-only in lower half
#define CONFIG_DIGIAL0 976
#define CONFIG_DIGIAL1 982
#define CONFIG_DIGIAL2 988
#define CONFIG_DIGIAL3 994
#define CONFIG_DIGIAL4 1000
#define CONFIG_DIGIAL5 1008
#define CONFIG_DIGIAL6 1016
#define CONFIG_DIGIAL7 1024
#define CONFIG_DIGIMAX0 1032
#define CONFIG_DIGIMAX1 1034
#define CONFIG_DIGIMAX2 1036
#define CONFIG_DIGIMAX3 1038
#define CONFIG_DIGIREP0 1040
#define CONFIG_DIGIREP1 1042
#define CONFIG_DIGIREP2 1044
#define CONFIG_DIGIREP3 1046
#define CONFIG_DIGITRACE 1048
#define CONFIG_DIGIDEDUPE 1050
#define CONFIG_DIGICALLFILEN 1052
#define CONFIG_DIGIFILLIST 1054
#define CONFIG_DIGIFILTYPE 1194
#define CONFIG_DIGISSID4 1196
#define CONFIG_DIGISSID5 1198
#define CONFIG_DIGISSID6 1200
#define CONFIG_DIGISSID7 1202
#define CONFIG_PWM_FLAT 1204
#define CONFIG_KISSMONITOR 1206
#define CONFIG_DEST 1208
#define CONFIG_ALLOWNONAPRS 1214
#define CONFIG_FX25 1216
#define CONFIG_MODEM 1218
#define CONFIG_MODE_USB 1220
#define CONFIG_MODE_UART1 1222
#define CONFIG_MODE_UART2 1224
#define CONFIG_XXX 1226 //next address (not used)
/**
* @brief Write word to configuration part in flash
* @param[in] address Relative address
* @param[in] data Data to write
* @warning Flash must be unlocked first
*/
static void write(uint32_t address, uint16_t data)
{
FLASH->CR |= FLASH_CR_PG; //programming mode
*((volatile uint16_t*)(address + CONFIG_ADDRESS)) = data; //store data
while (FLASH->SR & FLASH_SR_BSY);; //wait for completion
if(!(FLASH->SR & FLASH_SR_EOP)) //an error occurred
FLASH->CR &= ~FLASH_CR_PG;
else
FLASH->SR |= FLASH_SR_EOP;
}
/**
* @brief Write data array to configuration part in flash
* @param[in] address Relative address
* @param[in] *data Data to write
* @param[in] len Data length
* @warning Flash must be unlocked first
*/
static void writeString(uint32_t address, uint8_t *data, uint16_t len)
{
uint16_t i = 0;
for(; i < (len / 2); i++)
{
write(address + (i << 1), *(data + (i << 1)) | (*(data + 1 + (i << 1)) << 8)); //program memory
}
if((len % 2) > 0)
{
write(address + (i << 1), *(data + (i << 1))); //store last byte if number of bytes is odd
}
}
/**
* @brief Read single word from configuration part in flash
* @param[in] address Relative address
* @return Data (word)
*/
static uint16_t read(uint32_t address)
{
return *(volatile uint16_t*)((address + CONFIG_ADDRESS));
}
/**
* @brief Read array from configuration part in flash
* @param[in] address Relative address
* @param[out] *data Data
* @param[in] len Byte count
*/
static void readString(uint32_t address, uint8_t *data, uint16_t len)
{
uint16_t i = 0;
for(; i < (len >> 1); i++)
{
*(data + (i << 1)) = (uint8_t)read(address + (i << 1));
*(data + 1 + (i << 1)) = (uint8_t)read(address + 1 + (i << 1));
}
if((len % 2) > 0)
{
*(data + (i << 1)) = (uint8_t)read(address + (i << 1));
}
}
void ConfigErase(void)
{
FLASH->KEYR = 0x45670123; //unlock memory
FLASH->KEYR = 0xCDEF89AB;
while (FLASH->SR & FLASH_SR_BSY)
;
FLASH->CR |= FLASH_CR_PER; //erase mode
for(uint8_t i = 0; i < CONFIG_PAGE_COUNT; i++)
{
FLASH->AR = CONFIG_ADDRESS + (CONFIG_PAGE_SIZE * i);
FLASH->CR |= FLASH_CR_STRT; //start erase
while (FLASH->SR & FLASH_SR_BSY)
;
if(!(FLASH->SR & FLASH_SR_EOP))
{
FLASH->CR &= ~FLASH_CR_PER;
return;
}
else
FLASH->SR |= FLASH_SR_EOP;
}
FLASH->CR &= ~FLASH_CR_PER;
}
/**
* @brief Store configuration from RAM to Flash
*/
void ConfigWrite(void)
{
ConfigErase();
writeString(CONFIG_CALL, GeneralConfig.call, 6);
write(CONFIG_SSID, GeneralConfig.callSsid);
writeString(CONFIG_DEST, GeneralConfig.dest, 6);
write(CONFIG_TXDELAY, Ax25Config.txDelayLength);
write(CONFIG_TXTAIL, Ax25Config.txTailLength);
write(CONFIG_TXQUIET, Ax25Config.quietTime);
writeString(CONFIG_RS1BAUD, (uint8_t*)&Uart1.baudrate, 4);
writeString(CONFIG_RS2BAUD, (uint8_t*)&Uart2.baudrate, 4);
write(CONFIG_BEACONS, (beacon[0].enable > 0) | ((beacon[1].enable > 0) << 1) | ((beacon[2].enable > 0) << 2) | ((beacon[3].enable > 0) << 3) | ((beacon[4].enable > 0) << 4) | ((beacon[5].enable > 0) << 5) | ((beacon[6].enable > 0) << 6) | ((beacon[7].enable > 0) << 7));
for(uint8_t s = 0; s < 8; s++)
{
write(CONFIG_BCIV + (2 * s), beacon[s].interval / 6000);
}
for(uint8_t s = 0; s < 8; s++)
{
write(CONFIG_BCDL + (2 * s), beacon[s].delay / 60);
}
writeString(CONFIG_BC0, beacon[0].data, 100);
writeString(CONFIG_BC1, beacon[1].data, 100);
writeString(CONFIG_BC2, beacon[2].data, 100);
writeString(CONFIG_BC3, beacon[3].data, 100);
writeString(CONFIG_BC4, beacon[4].data, 100);
writeString(CONFIG_BC5, beacon[5].data, 100);
writeString(CONFIG_BC6, beacon[6].data, 100);
writeString(CONFIG_BC7, beacon[7].data, 100);
writeString(CONFIG_BCP0, beacon[0].path, 14);
writeString(CONFIG_BCP1, beacon[1].path, 14);
writeString(CONFIG_BCP2, beacon[2].path, 14);
writeString(CONFIG_BCP3, beacon[3].path, 14);
writeString(CONFIG_BCP4, beacon[4].path, 14);
writeString(CONFIG_BCP5, beacon[5].path, 14);
writeString(CONFIG_BCP6, beacon[6].path, 14);
writeString(CONFIG_BCP7, beacon[7].path, 14);
write(CONFIG_DIGION, DigiConfig.enable);
write(CONFIG_DIGIEN, DigiConfig.enableAlias);
write(CONFIG_DIGIVISC, ((uint16_t)DigiConfig.viscous << 8) | (uint16_t)DigiConfig.directOnly);
writeString(CONFIG_DIGIAL0, DigiConfig.alias[0], 5);
writeString(CONFIG_DIGIAL1, DigiConfig.alias[1], 5);
writeString(CONFIG_DIGIAL2, DigiConfig.alias[2], 5);
writeString(CONFIG_DIGIAL3, DigiConfig.alias[3], 5);
writeString(CONFIG_DIGIAL4, DigiConfig.alias[4], 6);
writeString(CONFIG_DIGIAL5, DigiConfig.alias[5], 6);
writeString(CONFIG_DIGIAL6, DigiConfig.alias[6], 6);
writeString(CONFIG_DIGIAL7, DigiConfig.alias[7], 6);
write(CONFIG_DIGISSID4, DigiConfig.ssid[0]);
write(CONFIG_DIGISSID5, DigiConfig.ssid[1]);
write(CONFIG_DIGISSID6, DigiConfig.ssid[2]);
write(CONFIG_DIGISSID7, DigiConfig.ssid[3]);
write(CONFIG_DIGIMAX0, DigiConfig.max[0]);
write(CONFIG_DIGIMAX1, DigiConfig.max[1]);
write(CONFIG_DIGIMAX2, DigiConfig.max[2]);
write(CONFIG_DIGIMAX3, DigiConfig.max[3]);
write(CONFIG_DIGIREP0, DigiConfig.rep[0]);
write(CONFIG_DIGIREP1, DigiConfig.rep[1]);
write(CONFIG_DIGIREP2, DigiConfig.rep[2]);
write(CONFIG_DIGIREP3, DigiConfig.rep[3]);
write(CONFIG_DIGITRACE, DigiConfig.traced);
write(CONFIG_DIGIDEDUPE, DigiConfig.dupeTime);
write(CONFIG_DIGICALLFILEN, DigiConfig.callFilterEnable);
write(CONFIG_DIGIFILTYPE, DigiConfig.filterPolarity);
writeString(CONFIG_DIGIFILLIST, DigiConfig.callFilter[0], sizeof(DigiConfig.callFilter));
write(CONFIG_PWM_FLAT, ModemConfig.usePWM | (ModemConfig.flatAudioIn << 1));
write(CONFIG_KISSMONITOR, GeneralConfig.kissMonitor);
write(CONFIG_ALLOWNONAPRS, Ax25Config.allowNonAprs);
write(CONFIG_FX25, Ax25Config.fx25 | (Ax25Config.fx25Tx << 1));
write(CONFIG_MODEM, ModemConfig.modem);
write(CONFIG_MODE_USB, UartUsb.defaultMode);
write(CONFIG_MODE_UART1, Uart1.defaultMode);
write(CONFIG_MODE_UART2, Uart2.defaultMode);
write(CONFIG_FLAG, CONFIG_FLAG_WRITTEN);
FLASH->CR &= ~FLASH_CR_PG;
FLASH->CR |= FLASH_CR_LOCK;
}
uint8_t ConfigRead(void)
{
if(read(CONFIG_FLAG) != CONFIG_FLAG_WRITTEN) //no configuration stored
{
return 0;
}
readString(CONFIG_CALL, GeneralConfig.call, sizeof(GeneralConfig.call));
GeneralConfig.callSsid = (uint8_t)read(CONFIG_SSID);
uint8_t temp[6];
readString(CONFIG_DEST, temp, 6);
if((temp[0] >= ('A' << 1)) && (temp[0] <= ('Z' << 1)) && ((temp[0] & 1) == 0)) //check if stored destination address is correct (we just assume it by reading the first byte)
{
memcpy(GeneralConfig.dest, temp, 6);
}
Ax25Config.txDelayLength = read(CONFIG_TXDELAY);
Ax25Config.txTailLength = read(CONFIG_TXTAIL);
Ax25Config.quietTime = read(CONFIG_TXQUIET);
readString(CONFIG_RS1BAUD, (uint8_t*)&Uart1.baudrate, 4);
readString(CONFIG_RS2BAUD, (uint8_t*)&Uart2.baudrate, 4);
uint8_t bce = (uint8_t)read(CONFIG_BEACONS);
beacon[0].enable = (bce & 1) > 0;
beacon[1].enable = (bce & 2) > 0;
beacon[2].enable = (bce & 4) > 0;
beacon[3].enable = (bce & 8) > 0;
beacon[4].enable = (bce & 16) > 0;
beacon[5].enable = (bce & 32) > 0;
beacon[6].enable = (bce & 64) > 0;
beacon[7].enable = (bce & 128) > 0;
for(uint8_t s = 0; s < (sizeof(beacon) / sizeof(*beacon)); s++)
{
beacon[s].interval = read(CONFIG_BCIV + (2 * s)) * 6000;
}
for(uint8_t s = 0; s < (sizeof(beacon) / sizeof(*beacon)); s++)
{
beacon[s].delay = read(CONFIG_BCDL + (2 * s)) * 60;
}
for(uint8_t g = 0; g < (sizeof(beacon) / sizeof(*beacon)); g++)
{
readString(CONFIG_BC0 + (g * 100), beacon[g].data, 100);
}
for(uint8_t g = 0; g < (sizeof(beacon) / sizeof(*beacon)); g++)
{
readString(CONFIG_BCP0 + (g * 14), beacon[g].path, 14);
}
DigiConfig.enable = (uint8_t)read(CONFIG_DIGION);
DigiConfig.enableAlias = (uint8_t)read(CONFIG_DIGIEN);
uint16_t t = read(CONFIG_DIGIVISC);
DigiConfig.viscous = (t & 0xFF00) >> 8;
DigiConfig.directOnly = t & 0xFF;
readString(CONFIG_DIGIAL0, DigiConfig.alias[0], 5);
readString(CONFIG_DIGIAL1, DigiConfig.alias[1], 5);
readString(CONFIG_DIGIAL2, DigiConfig.alias[2], 5);
readString(CONFIG_DIGIAL3, DigiConfig.alias[3], 5);
readString(CONFIG_DIGIAL4, DigiConfig.alias[4], 6);
readString(CONFIG_DIGIAL5, DigiConfig.alias[5], 6);
readString(CONFIG_DIGIAL6, DigiConfig.alias[6], 6);
readString(CONFIG_DIGIAL7, DigiConfig.alias[7], 6);
DigiConfig.ssid[0] = (uint8_t)read(CONFIG_DIGISSID4);
DigiConfig.ssid[1] = (uint8_t)read(CONFIG_DIGISSID5);
DigiConfig.ssid[2] = (uint8_t)read(CONFIG_DIGISSID6);
DigiConfig.ssid[3] = (uint8_t)read(CONFIG_DIGISSID7);
DigiConfig.max[0] = (uint8_t)read(CONFIG_DIGIMAX0);
DigiConfig.max[1] = (uint8_t)read(CONFIG_DIGIMAX1);
DigiConfig.max[2] = (uint8_t)read(CONFIG_DIGIMAX2);
DigiConfig.max[3] = (uint8_t)read(CONFIG_DIGIMAX3);
DigiConfig.rep[0] = (uint8_t)read(CONFIG_DIGIREP0);
DigiConfig.rep[1] = (uint8_t)read(CONFIG_DIGIREP1);
DigiConfig.rep[2] = (uint8_t)read(CONFIG_DIGIREP2);
DigiConfig.rep[3] = (uint8_t)read(CONFIG_DIGIREP3);
DigiConfig.traced = (uint8_t)read(CONFIG_DIGITRACE);
DigiConfig.dupeTime = (uint8_t)read(CONFIG_DIGIDEDUPE);
DigiConfig.callFilterEnable = (uint8_t)read(CONFIG_DIGICALLFILEN);
DigiConfig.filterPolarity = (uint8_t)read(CONFIG_DIGIFILTYPE);
readString(CONFIG_DIGIFILLIST, DigiConfig.callFilter[0], 140);
t = (uint8_t)read(CONFIG_PWM_FLAT);
ModemConfig.usePWM = t & 1;
ModemConfig.flatAudioIn = (t & 2) > 0;
GeneralConfig.kissMonitor = (read(CONFIG_KISSMONITOR) == 1);
Ax25Config.allowNonAprs = (read(CONFIG_ALLOWNONAPRS) == 1);
t = (uint8_t)read(CONFIG_FX25);
Ax25Config.fx25 = t & 1;
Ax25Config.fx25Tx = (t & 2) > 0;
ModemConfig.modem = read(CONFIG_MODEM);
UartUsb.defaultMode = read(CONFIG_MODE_USB);
Uart1.defaultMode = read(CONFIG_MODE_UART1);
Uart2.defaultMode = read(CONFIG_MODE_UART2);
return 1;
}

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/*
Copyright 2020-2023 Piotr Wilkon
This file is part of VP-Digi.
VP-Digi is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
VP-Digi is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with VP-Digi. If not, see <http://www.gnu.org/licenses/>.
*/
#include "digipeater.h"
#include "terminal.h"
#include <string.h>
#include "common.h"
#include "ax25.h"
#include <math.h>
#include <modem.h>
#include <systick.h>
struct _DigiConfig DigiConfig;
#define VISCOUS_MAX_FRAME_COUNT 10 //max frames in viscous-delay buffer
#define VISCOUS_MAX_FRAME_SIZE 150
struct ViscousData
{
uint32_t hash;
uint32_t timeLimit;
uint8_t frame[VISCOUS_MAX_FRAME_SIZE];
uint16_t size;
};
static struct ViscousData viscous[VISCOUS_MAX_FRAME_COUNT];
#define VISCOUS_HOLD_TIME 5000 //viscous-delay hold time in ms
struct DeDupeData
{
uint32_t hash;
uint32_t timeLimit;
};
#define DEDUPE_SIZE (50) //duplicate protection buffer size (number of hashes)
static struct DeDupeData deDupe[DEDUPE_SIZE]; //duplicate protection hash buffer
static uint8_t deDupeCount = 0; //duplicate protection buffer index
static uint8_t buf[AX25_FRAME_MAX_SIZE];
/**
* @brief Check if frame with specified hash is already in viscous-delay buffer and delete it if so
* @param[in] hash Frame hash
* @return 0 if not in buffer, 1 if in buffer
*/
static uint8_t viscousCheckAndRemove(uint32_t hash)
{
for(uint8_t i = 0; i < VISCOUS_MAX_FRAME_COUNT; i++)
{
if(viscous[i].hash == hash) //matching hash
{
viscous[i].hash = 0; //clear slot
viscous[i].timeLimit = 0;
viscous[i].size = 0;
TermSendToAll(MODE_MONITOR, (uint8_t*)"Digipeated frame received, dropping old frame from viscous-delay buffer\r\n", 0);
return 1;
}
}
return 0;
}
void DigiViscousRefresh(void)
{
if(DigiConfig.viscous == 0) //viscous digipeating disabled on every alias
{
return;
}
for(uint8_t i = 0; i < VISCOUS_MAX_FRAME_COUNT; i++)
{
if((viscous[i].timeLimit > 0) && (SysTickGet() >= viscous[i].timeLimit)) //it's time to transmit this frame
{
void *handle = NULL;
if(NULL != (handle = Ax25WriteTxFrame(viscous[i].frame, viscous[i].size)))
{
if(GeneralConfig.kissMonitor) //monitoring mode, send own frames to KISS ports
{
TermSendToAll(MODE_KISS, viscous[i].frame, viscous[i].size);
}
TermSendToAll(MODE_MONITOR, (uint8_t*)"(AX.25) Transmitting viscous-delayed frame: ", 0);
SendTNC2(viscous[i].frame, viscous[i].size);
TermSendToAll(MODE_MONITOR, (uint8_t*)"\r\n", 0);
}
viscous[i].hash = 0; //clear slot
viscous[i].timeLimit = 0;
viscous[i].size = 0;
}
}
}
/**
* @brief Compare callsign with specified call in call filter table - helper function.
* @param *call Callsign
* @param index Callsign filter table index
* @return 1 if matched, 0 otherwise
*/
static uint8_t compareFilterCall(uint8_t *call, uint8_t index)
{
uint8_t err = 0;
for(uint8_t i = 0; i < 6; i++)
{
if((DigiConfig.callFilter[index][i] < 0xff) && ((call[i] >> 1) != DigiConfig.callFilter[index][i]))
err = 1;
}
if((DigiConfig.callFilter[index][6] < 0xff) && ((call[6] - 96) != DigiConfig.callFilter[index][6])) //special case for ssid
err = 1;
return (err == 0);
}
/**
* @brief Check frame with call filter
* @param[in] *call Callsign in incoming frame
* @param[in] alias Digi alias index currently used
* @return 1 if accepted, 0 if rejected
*/
static uint8_t filterFrameCheck(uint8_t *call, uint8_t alias)
{
//filter by call
if((DigiConfig.callFilterEnable >> alias) & 1) //check if enabled
{
for(uint8_t i = 0; i < (sizeof(DigiConfig.callFilter) / sizeof(DigiConfig.callFilter[0])); i++)
{
if(compareFilterCall(call, i)) //if callsigns match...
{
if(DigiConfig.filterPolarity == 0)
return 0; //...and blacklist is enabled, drop the frame
else
return 1; //...and whitelist is enabled, accept the frame
}
}
//if callsign is not on the list...
if((DigiConfig.filterPolarity) == 0)
return 1; //...and blacklist is enabled, accept the frame
else
return 0; //...and whitelist is enabled, drop the frame
}
//filter by call disabled
return 1;
}
/**
* @brief Produce and push digipeated frame to transmit buffer
* @param[in] *frame Pointer to frame buffer
* @param[in] elStart Index of the current path element very first byte
* @param[in] len Frame length
* @param[in] hash Frame hash
* @param[in] alias Alias number: 0-3 - n-N aliases, 4-7 - simple aliases, 8 - own call
* @param[in] simple If 1, it is a simple alias or should be treated as a simple alias
* @param[in] n Number in n-N type alias, e.g. in WIDE2-1 n=2
*/
static void makeFrame(uint8_t *frame, uint16_t elStart, uint16_t len, uint32_t hash, uint8_t alias, uint8_t simple, uint8_t n)
{
uint16_t _index = 0; //underlying index for buffer if not in viscous-delay mode
uint8_t *buffer; //buffer to store frame being prepared
uint16_t *index = &_index; //index in buffer
uint8_t viscousSlot = 0; //viscous delay frame slot we will use
if((alias < 8) && (DigiConfig.viscous & (1 << (alias)))) //viscous delay mode
{
for(uint8_t i = 0; i < VISCOUS_MAX_FRAME_COUNT; i++)
{
if(viscous[i].timeLimit == 0) //look for the first available slot
{
viscousSlot = i;
break;
}
}
if((len + 7) > VISCOUS_MAX_FRAME_SIZE) //if frame length (+ 7 bytes for inserted call) is bigger than buffer size
return; //drop
buffer = viscous[viscousSlot].frame;
index = &(viscous[viscousSlot].size);
*index = 0;
}
else //normal mode
{
if((uint16_t)sizeof(buf) < (len + 7))
return;
buffer = buf;
}
if(alias < 8)
{
if(!filterFrameCheck(&frame[7], alias)) //push source callsign through the filter
return;
}
uint8_t ssid = (frame[elStart + 6] >> 1) - 48; //store SSID (N)
if(alias < 8)
{
if((DigiConfig.viscous & (1 << (alias))) || (DigiConfig.directOnly & (1 << alias))) //viscous-delay or direct-only enabled
{
if(elStart != 14)
return; //this is not the very first path element, frame not received directly
if((alias <= 3) && (ssid != n))
return; //n-N type alias, but n is not equal to N, frame not received directly
}
}
if(simple) //if this is a simple alias, our own call or we treat n-N as a simple alias
{
while(*index < len) //copy whole frame
{
buffer[*index] = frame[*index];
(*index)++;
}
if((alias == 8) || ((DigiConfig.traced & (1 << alias)) == 0)) //own call or untraced
{
buffer[elStart + 6] += 128; //add h-bit
}
else //not our call, but treat it as a simple alias
{
for(uint8_t i = 0; i < sizeof(GeneralConfig.call); i++) //replace with own call
buffer[elStart + i] = GeneralConfig.call[i];
buffer[elStart + 6] &= 1; //clear everything but path end bit
buffer[elStart + 6] |= ((GeneralConfig.callSsid << 1) + 0b11100000); //insert ssid and h-bit
}
}
else //standard n-N alias
{
while(*index < elStart) //copy all data before current path element
{
buffer[*index] = frame[*index];
(*index)++;
}
uint16_t shift = 0;
//insert own callsign to path if:
//1. this is a traced alias OR
//2. this is an untraced alias, but it is the very first hop (heard directly)
if((DigiConfig.traced & (1 << alias)) || ((ssid == n) && (elStart == 14)))
{
for(uint8_t i = 0; i < sizeof(GeneralConfig.call); i++) //insert own call
buffer[(*index)++] = GeneralConfig.call[i];
buffer[(*index)++] = ((GeneralConfig.callSsid << 1) + 0b11100000); //insert ssid and h-bit
shift = 7; //additional shift when own call is inserted
}
while(*index < (len + shift)) //copy rest of the frame
{
buffer[*index] = frame[*index - shift];
(*index)++;
}
buffer[elStart + shift + 6] -= 2; //decrement SSID in alias (2 because ssid is shifted left by 1)
if((buffer[elStart + shift + 6] & 0b11110) == 0) //if SSID is 0
{
buffer[elStart + shift + 6] += 0x80; //add h-bit
}
}
if((alias < 8) && (DigiConfig.viscous & (1 << alias)))
{
viscous[viscousSlot].hash = hash;
viscous[viscousSlot].timeLimit = SysTickGet() + (VISCOUS_HOLD_TIME / SYSTICK_INTERVAL);
TermSendToAll(MODE_MONITOR, (uint8_t*)"Saving frame for viscous-delay digipeating\r\n", 0);
}
else
{
void *handle = NULL;
if(NULL != (handle = Ax25WriteTxFrame(buffer, *index)))
{
DigiStoreDeDupe(buffer, *index);
if(GeneralConfig.kissMonitor) //monitoring mode, send own frames to KISS ports
{
TermSendToAll(MODE_KISS, buffer, *index);
}
TermSendToAll(MODE_MONITOR, (uint8_t*)"(AX.25) Digipeating frame: ", 0);
SendTNC2(buffer, *index);
TermSendToAll(MODE_MONITOR, (uint8_t*)"\r\n", 0);
}
}
}
void DigiDigipeat(uint8_t *frame, uint16_t len)
{
if(!DigiConfig.enable)
return;
uint16_t t = 13; //start from first byte that can contain path end bit
while((frame[t] & 1) == 0) //look for path end
{
if((t + 7) >= len)
return;
t += 7;
}
//calculate frame "hash"
uint32_t hash = Crc32(CRC32_INIT, frame, 14); //use destination and source address, skip path
hash = Crc32(hash, &frame[t + 1], len - t - 1); //continue through all remaining data
if(DigiConfig.viscous) //viscous-delay enabled on any slot
{
if(viscousCheckAndRemove(hash)) //check if this frame was received twice
return; //if so, drop it
}
for(uint8_t i = 0; i < DEDUPE_SIZE; i++) //check if frame is already in duplicate filtering buffer
{
if(deDupe[i].hash == hash)
{
if(SysTickGet() < (deDupe[i].timeLimit))
return; //filter out duplicate frame
}
}
if(t == 13) //path end bit in source address, no path in this frame
{
return; //drop it
}
while((frame[t] & 0x80) == 0) //look for h-bit
{
if(t == 13)
{
break; //no h-bit found and we are in source address, we can proceed with the first path element
}
t -= 7; //look backwards for h-bit
}
t++; //now t is the index for the first byte in path element we want to process
uint8_t ssid = ((frame[t + 6] >> 1) - 0b00110000); //current path element SSID
uint8_t err = 0;
for(uint8_t i = 0; i < sizeof(GeneralConfig.call); i++) //compare with our call
{
if(frame[t + i] != GeneralConfig.call[i])
{
err = 1;
break;
}
}
if(ssid != GeneralConfig.callSsid) //compare SSID also
err = 1;
if(err == 0) //our callsign is in the path
{
makeFrame(frame, t, len, hash, 8, 1, 0);
return;
}
for(uint8_t i = 0; i < 4; i++) //check for simple alias match
{
err = 0;
for(uint8_t j = 0; j < sizeof(DigiConfig.alias[0]); j++)
{
if(frame[t + j] != DigiConfig.alias[i + 4][j])
{
err = 1;
break;
}
}
if(ssid != DigiConfig.ssid[i])
err = 1;
if(err == 0) //no error
{
makeFrame(frame, t, len, hash, i + 4, 1, 0);
return;
}
}
//n-N style alias handling
for(uint8_t i = 0; i < 4; i++)
{
err = 0;
uint8_t j = 0;
for(; j < strlen((const char *)DigiConfig.alias[i]); j++)
{
if(frame[t + j] != DigiConfig.alias[i][j]) //check for matching alias
{
err = 1; //alias not matching
break;
}
}
if(err == 0) //alias matching, check further
{
uint8_t n = ((frame[t + j] >> 1) - 48); //get n from alias (e.g. WIDEn-N) - N is in ssid variable
//every path must meet several requirements
//say we have a WIDEn-N path. Then:
//N <= n
//0 < n < 8
//0 < N < 8
if(((ssid > 0) && (ssid < 8) && (n > 0) && (n < 8) && (ssid <= n)) == 0) //path is broken or already used (N=0)
return;
//check if n and N <= digi max
if((n <= DigiConfig.max[i]) && (ssid <= DigiConfig.max[i]))
{
if(DigiConfig.enableAlias & (1 << i))
makeFrame(frame, t, len, hash, i, 0, n); //process as a standard n-N frame
}
else if((DigiConfig.rep[i] > 0) && (n >= DigiConfig.rep[i])) //else check if n and N >= digi replace
{
if(DigiConfig.enableAlias & (1 << i))
makeFrame(frame, t, len, hash, i, 1, n);
}
}
}
}
void DigiStoreDeDupe(uint8_t *buf, uint16_t size)
{
uint32_t hash = Crc32(CRC32_INIT, buf, 14); //calculate for destination and source address
uint16_t i = 13;
while((buf[i] & 1) == 0) //look for path end bit (skip path)
{
i++;
if(i == size)
return;
}
i++;
hash = Crc32(hash, &buf[i], size - i);
deDupeCount %= DEDUPE_SIZE;
deDupe[deDupeCount].hash = hash;
deDupe[deDupeCount].timeLimit = SysTickGet() + (DigiConfig.dupeTime * 1000 / SYSTICK_INTERVAL);
deDupeCount++;
}

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/*
Copyright 2020-2023 Piotr Wilkon
This file is part of VP-Digi.
VP-Digi is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
VP-Digi is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with VP-Digi. If not, see <http://www.gnu.org/licenses/>.
*/
#ifdef ENABLE_FX25
#include "fx25.h"
#include <stddef.h>
#include "rs.h"
#define FX25_RS_FCR 1
#define FX25_PREGENERATE_POLYS
#define FX25_MAX_DISTANCE 10 //maximum Hamming distance when comparing tags
const struct Fx25Mode Fx25ModeList[11] =
{
{.tag = 0xB74DB7DF8A532F3E, .K = 239, .T = 16},
{.tag = 0x26FF60A600CC8FDE, .K = 128, .T = 16},
{.tag = 0xC7DC0508F3D9B09E, .K = 64, .T = 16},
{.tag = 0x8F056EB4369660EE, .K = 32, .T = 16},
{.tag = 0x6E260B1AC5835FAE, .K = 223, .T = 32},
{.tag = 0xFF94DC634F1CFF4E, .K = 128, .T = 32},
{.tag = 0x1EB7B9CDBC09C00E, .K = 64, .T = 32},
{.tag = 0xDBF869BD2DBB1776, .K = 32, .T = 32},
{.tag = 0x3ADB0C13DEAE2836, .K = 191, .T = 64},
{.tag = 0xAB69DB6A543188D6, .K = 128, .T = 64},
{.tag = 0x4A4ABEC4A724B796, .K = 64, .T = 64}
};
const struct Fx25Mode* Fx25GetModeForTag(uint64_t tag)
{
for(uint8_t i = 0; i < sizeof(Fx25ModeList) / sizeof(*Fx25ModeList); i++)
{
if(__builtin_popcountll(tag ^ Fx25ModeList[i].tag) <= FX25_MAX_DISTANCE)
return &Fx25ModeList[i];
}
return NULL;
}
const struct Fx25Mode* Fx25GetModeForSize(uint16_t size)
{
//use "UZ7HO Soundmodem standard" for choosing FX.25 mode
if(size <= 32)
return &Fx25ModeList[3];
else if(size <= 64)
return &Fx25ModeList[2];
else if(size <= 128)
return &Fx25ModeList[5];
else if(size <= 191)
return &Fx25ModeList[8];
else if(size <= 223)
return &Fx25ModeList[4];
else if(size <= 239)
return &Fx25ModeList[0];
else
return NULL; //frame too big, do not use FX.25
}
#ifdef FX25_PREGENERATE_POLYS
static struct LwFecRS rs16, rs32, rs64;
#else
static struct LwFecRS rs;
#endif
void Fx25Encode(uint8_t *buffer, const struct Fx25Mode *mode)
{
#ifdef FX25_PREGENERATE_POLYS
struct LwFecRS *rs = NULL;
switch(mode->T)
{
case 16:
rs = &rs16;
break;
case 32:
rs = &rs32;
break;
case 64:
rs = &rs64;
break;
default:
rs = &rs16;
break;
}
RsEncode(rs, buffer, mode->K);
#else
RsInit(&rs, mode->T, FX25_RS_FCR);
RsEncode(&rs, buffer, mode->K);
#endif
}
bool Fx25Decode(uint8_t *buffer, const struct Fx25Mode *mode, uint8_t *fixed)
{
#ifdef FX25_PREGENERATE_POLYS
struct LwFecRS *rs = NULL;
switch(mode->T)
{
case 16:
rs = &rs16;
break;
case 32:
rs = &rs32;
break;
case 64:
rs = &rs64;
break;
default:
rs = &rs16;
break;
}
return RsDecode(rs, buffer, mode->K, fixed);
#else
RsInit(&rs, mode->T, FX25_RS_FCR);
return RsDecode(&rs, buffer, mode->K, fixed);
#endif
}
void Fx25Init(void)
{
#ifdef FX25_PREGENERATE_POLYS
RsInit(&rs16, 16, FX25_RS_FCR);
RsInit(&rs32, 32, FX25_RS_FCR);
RsInit(&rs64, 64, FX25_RS_FCR);
#else
#endif
}
#endif

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/*
Copyright 2020-2023 Piotr Wilkon
This file is part of VP-Digi.
VP-Digi is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
VP-Digi is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with VP-Digi. If not, see <http://www.gnu.org/licenses/>.
*/
#include "kiss.h"
#include "ax25.h"
#include "digipeater.h"
void KissSend(Uart *port, uint8_t *buf, uint16_t size)
{
if(port->mode == MODE_KISS)
{
UartSendByte(port, 0xC0);
UartSendByte(port, 0x00);
for(uint16_t i = 0; i < size; i++)
{
if(buf[i] == 0xC0) //frame end in data
{
UartSendByte(port, 0xDB); //frame escape
UartSendByte(port, 0xDC); //transposed frame end
}
else if(buf[i] == 0xDB) //frame escape in data
{
UartSendByte(port, 0xDB); //frame escape
UartSendByte(port, 0xDD); //transposed frame escape
}
else
UartSendByte(port, buf[i]);
}
UartSendByte(port, 0xC0);
}
}
void KissParse(Uart *port, uint8_t data)
{
volatile uint8_t *buf = NULL;
volatile uint16_t *index = NULL;
if(!port->kissProcessingOngoing)
{
buf = port->kissBuffer;
index = &port->kissBufferHead;
}
else
{
buf = port->kissTempBuffer;
index = &port->kissTempBufferHead;
}
if(data == 0xC0) //frame end marker
{
if(port->kissProcessingOngoing)
{
*index = 0;
return;
}
if(port->kissBufferHead < 16) //command+source+destination+Control=16
{
port->kissBufferHead = 0;
return;
}
if((port->kissBuffer[0] & 0xF) != 0) //check if this is an actual frame
{
port->kissBufferHead = 0;
return;
}
//simple sanity check
//check if LSbits in the first 13 bytes are set to 0
//they should always be in an AX.25 frame
for(uint8_t i = 0; i < 13; i++)
{
if((port->kissBuffer[i + 1] & 1) != 0)
{
port->kissBufferHead = 0;
return;
}
}
uint16_t pathEnd = 0;
//find path end bit (C-bit)
for(uint16_t i = 0; i < port->kissBufferHead; i++)
{
if((port->kissBuffer[i + 1] & 1) != 0)
{
pathEnd = i + 1;
break;
}
}
//C-bit must lay on a 7 byte boundary (every path element is 7 bytes long)
if(pathEnd % 7)
{
port->kissBufferHead = 0;
return;
}
__disable_irq();
port->kissProcessingOngoing = 1;
port->kissTempBufferHead = 0;
__enable_irq();
port->rxType = DATA_KISS;
return;
}
else if(*index > 0)
{
if((data == 0xDC) && (buf[*index - 1] == 0xDB)) //escape character with transposed frame end
{
buf[*index - 1] = 0xC0;
return;
}
else if((data == 0xDD) && (buf[*index - 1] == 0xDB)) //escape character with transposed escape character
{
buf[*index - 1] = 0xDB;
return;
}
}
buf[(*index)++] = data;
if(!port->kissProcessingOngoing)
port->kissBufferHead %= sizeof(port->kissBuffer);
else
port->kissTempBufferHead %= sizeof(port->kissTempBuffer);
}
void KissProcess(Uart *port)
{
if(port->rxType == DATA_KISS)
{
Ax25WriteTxFrame((uint8_t*)&port->kissBuffer[1], port->kissBufferHead - 1);
DigiStoreDeDupe((uint8_t*)&port->kissBuffer[1], port->kissBufferHead - 1);
port->kissBufferHead = 0;
__disable_irq();
port->kissProcessingOngoing = 0;
if(port->kissTempBufferHead > 0)
{
memcpy((uint8_t*)port->kissBuffer, (uint8_t*)port->kissTempBuffer, port->kissTempBufferHead);
port->kissBufferHead = port->kissTempBufferHead;
port->kissTempBufferHead = 0;
}
__enable_irq();
port->rxType = DATA_NOTHING;
}
}

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/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file : main.c
* @brief : Main program body
******************************************************************************
* @attention
*
* Copyright (c) 2023 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/*
Copyright 2020-2023 Piotr Wilkon
This file is part of VP-Digi.
VP-Digi is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
VP-Digi is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with VP-Digi. If not, see <http://www.gnu.org/licenses/>.
*/
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "main.h"
#include "usb_device.h"
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
#include <stdint.h>
#include "systick.h"
#include "modem.h"
#include "ax25.h"
#include "digipeater.h"
#include "common.h"
#include "drivers/watchdog.h"
#include "beacon.h"
#include "terminal.h"
#include "config.h"
#include "uart.h"
#include "drivers/usb.h"
#include "kiss.h"
#ifdef ENABLE_FX25
#include "fx25.h"
#endif
/* USER CODE END Includes */
/* Private typedef -----------------------------------------------------------*/
/* USER CODE BEGIN PTD */
/* USER CODE END PTD */
/* Private define ------------------------------------------------------------*/
/* USER CODE BEGIN PD */
/* USER CODE END PD */
/* Private macro -------------------------------------------------------------*/
/* USER CODE BEGIN PM */
/* USER CODE END PM */
/* Private variables ---------------------------------------------------------*/
/* USER CODE BEGIN PV */
/* USER CODE END PV */
/* Private function prototypes -----------------------------------------------*/
void SystemClock_Config(void);
static void MX_GPIO_Init(void);
/* USER CODE BEGIN PFP */
/* USER CODE END PFP */
/* Private user code ---------------------------------------------------------*/
/* USER CODE BEGIN 0 */
/**
* @brief Handle received frame
*/
static void handleFrame(void)
{
uint8_t modemBitmap = Ax25GetReceivedFrameBitmap(); //store states
Ax25ClearReceivedFrameBitmap();
uint8_t *buf;
uint16_t size = 0;
int8_t peak = 0;
int8_t valley = 0;
uint8_t signalLevel = 0;
uint8_t fixed = 0;
while(Ax25ReadNextRxFrame(&buf, &size, &peak, &valley, &signalLevel, &fixed))
{
TermSendToAll(MODE_KISS, buf, size);
if(((UartUsb.mode == MODE_MONITOR) || (Uart1.mode == MODE_MONITOR) || (Uart2.mode == MODE_MONITOR)))
{
if(signalLevel > 70)
{
TermSendToAll(MODE_MONITOR, (uint8_t*)"\r\nInput level too high! Please reduce so most stations are around 30-50%.\r\n", 0);
}
else if(signalLevel < 5)
{
TermSendToAll(MODE_MONITOR, (uint8_t*)"\r\nInput level too low! Please increase so most stations are around 30-50%.\r\n", 0);
}
TermSendToAll(MODE_MONITOR, (uint8_t*)"(AX.25) Frame received [", 0);
for(uint8_t i = 0; i < ModemGetDemodulatorCount(); i++)
{
if(modemBitmap & (1 << i))
{
enum ModemPrefilter m = ModemGetFilterType(i);
switch(m)
{
case PREFILTER_PREEMPHASIS:
TermSendToAll(MODE_MONITOR, (uint8_t*)"P", 1);
break;
case PREFILTER_DEEMPHASIS:
TermSendToAll(MODE_MONITOR, (uint8_t*)"D", 1);
break;
case PREFILTER_FLAT:
TermSendToAll(MODE_MONITOR, (uint8_t*)"F", 1);
break;
case PREFILTER_NONE:
TermSendToAll(MODE_MONITOR, (uint8_t*)"N", 1);
}
}
else
TermSendToAll(MODE_MONITOR, (uint8_t*)"_", 1);
}
TermSendToAll(MODE_MONITOR, (uint8_t*)"], ", 0);
if(fixed != AX25_NOT_FX25)
{
TermSendNumberToAll(MODE_MONITOR, fixed);
TermSendToAll(MODE_MONITOR, (uint8_t*)" bytes fixed, ", 0);
}
TermSendToAll(MODE_MONITOR, (uint8_t*)"signal level ", 0);
TermSendNumberToAll(MODE_MONITOR, signalLevel);
TermSendToAll(MODE_MONITOR, (uint8_t*)"% (", 0);
TermSendNumberToAll(MODE_MONITOR, peak);
TermSendToAll(MODE_MONITOR, (uint8_t*)"%/", 0);
TermSendNumberToAll(MODE_MONITOR, valley);
TermSendToAll(MODE_MONITOR, (uint8_t*)"%): ", 0);
SendTNC2(buf, size);
TermSendToAll(MODE_MONITOR, (uint8_t*)"\r\n", 0);
}
DigiDigipeat(buf, size);
}
}
/* USER CODE END 0 */
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
/* USER CODE BEGIN SysInit */
SysTickInit();
USB_FORCE_REENUMERATION();
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
MX_USB_DEVICE_Init();
/* USER CODE BEGIN 2 */
WdogInit(); //initialize watchdog
memset(&beacon, 0, sizeof(beacon));
memset(&Ax25Config, 0, sizeof(Ax25Config));
memset(&ModemConfig, 0, sizeof(ModemConfig));
memset(&DigiConfig, 0, sizeof(DigiConfig));
//set some initial values in case there is no configuration saved in memory
Uart1.baudrate = 9600;
Uart1.defaultMode = MODE_KISS;
Uart2.baudrate = 9600;
Uart2.defaultMode = MODE_KISS;
UartUsb.defaultMode = MODE_KISS;
ModemConfig.usePWM = 1; //use PWM by default
ModemConfig.flatAudioIn = 0;
Ax25Config.quietTime = 300;
Ax25Config.txDelayLength = 300;
Ax25Config.txTailLength = 30;
Ax25Config.fx25 = 0;
DigiConfig.dupeTime = 30;
ConfigRead();
ModemInit();
Ax25Init();
#ifdef ENABLE_FX25
Fx25Init();
#endif
UartInit(&Uart1, UART_LL_UART1_STRUCTURE, Uart1.baudrate);
UartInit(&Uart2, UART_LL_UART2_STRUCTURE, Uart2.baudrate);
UartInit(&UartUsb, NULL, 1);
UartConfig(&Uart1, 1);
UartConfig(&Uart2, 1);
UartConfig(&UartUsb, 1);
BeaconInit();
/* USER CODE END 2 */
/* Infinite loop */
/* USER CODE BEGIN WHILE */
while (1)
{
/* USER CODE END WHILE */
/* USER CODE BEGIN 3 */
WdogReset();
if(Ax25GetReceivedFrameBitmap())
handleFrame();
DigiViscousRefresh(); //refresh viscous-delay buffers
Ax25TransmitBuffer(); //transmit buffer (will return if nothing to be transmitted)
Ax25TransmitCheck(); //check for pending transmission request
if(UartUsb.rxType != DATA_NOTHING)
{
TermHandleSpecial(&UartUsb);
if(UartUsb.rxType == DATA_KISS)
{
KissProcess(&UartUsb);
}
else if(UartUsb.rxType != DATA_USB)
{
TermParse(&UartUsb);
UartClearRx(&UartUsb);
}
UartUsb.rxType = DATA_NOTHING;
}
if(Uart1.rxType != DATA_NOTHING)
{
if(Uart1.rxType == DATA_KISS)
{
KissProcess(&Uart1);
}
else
{
TermParse(&Uart1);
UartClearRx(&Uart1);
}
}
if(Uart2.rxType != DATA_NOTHING)
{
if(Uart2.rxType == DATA_KISS)
{
KissProcess(&Uart2);
}
else
{
TermParse(&Uart2);
UartClearRx(&Uart2);
}
}
BeaconCheck(); //check beacons
if(SysTickGet() > 0xFFFFF000) //going to wrap around soon - hard reset the device
NVIC_SystemReset();
}
/* USER CODE END 3 */
}
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9;
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
{
Error_Handler();
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
{
Error_Handler();
}
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLL_DIV1_5;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
{
Error_Handler();
}
}
/**
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
/* USER CODE BEGIN MX_GPIO_Init_1 */
/* USER CODE END MX_GPIO_Init_1 */
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOD_CLK_ENABLE();
__HAL_RCC_GPIOA_CLK_ENABLE();
/* USER CODE BEGIN MX_GPIO_Init_2 */
/* USER CODE END MX_GPIO_Init_2 */
}
/* USER CODE BEGIN 4 */
/* USER CODE END 4 */
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
{
}
/* USER CODE END Error_Handler_Debug */
}
#ifdef USE_FULL_ASSERT
/**
* @brief Reports the name of the source file and the source line number
* where the assert_param error has occurred.
* @param file: pointer to the source file name
* @param line: assert_param error line source number
* @retval None
*/
void assert_failed(uint8_t *file, uint32_t line)
{
/* USER CODE BEGIN 6 */
/* User can add his own implementation to report the file name and line number,
ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
/* USER CODE END 6 */
}
#endif /* USE_FULL_ASSERT */

897
Core/Src/modem.c 100644
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@ -0,0 +1,897 @@
/*
Copyright 2020-2023 Piotr Wilkon
This file is part of VP-Digi.
VP-Digi is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
VP-Digi is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with VP-Digi. If not, see <http://www.gnu.org/licenses/>.
*/
#include <string.h>
#include <math.h>
#include "modem.h"
#include <stdlib.h>
#include <stdbool.h>
#include "ax25.h"
#include "common.h"
#include "systick.h"
#include "drivers/modem_ll.h"
/*
* Configuration for PLL-based data carrier detection
* 1. MAXPULSE - the maximum value of the DCD pulse counter. Higher values allow for more stability when a correct signal is detected,
* but introduce a delay when releasing DCD
* 2. THRES - the threshold value of the DCD pulse counter. When reached the input signal is assumed to be valid. Higher values mean more immunity to noise,
* but introduce delay when setting DCD
* 3. MAXPULSE and THRES difference sets the DCD "inertia" so that the DCD state won't change rapidly when a valid signal is present
* 4. INC is the DCD pulse counter incrementation value when symbol changes near the PLL counter zero
* 5. DEC is the DCD pulse counter decrementation value when symbol changes too far from PLL counter zero
* 6. TUNE is the PLL counter tuning coefficient. It is applied when there is a symbol change (as the symbol change should occur when the PLL counter crosses zero)
*
* [ DCD OFF * | DCD ON ]
* 0 COUNTER THRES MAXPULSE
* <-DEC INC->
*
* The DCD mechanism is described in demodulate().
* All values were selected by trial and error
*/
#define DCD1200_MAXPULSE 60
#define DCD1200_THRES 20
#define DCD1200_INC 2
#define DCD1200_DEC 1
#define DCD1200_TUNE 0.74f
#define DCD9600_MAXPULSE 60
#define DCD9600_THRES 40
#define DCD9600_INC 1
#define DCD9600_DEC 1
#define DCD9600_TUNE 0.74f
#define DCD300_MAXPULSE 80
#define DCD300_THRES 20
#define DCD300_INC 4
#define DCD300_DEC 1
#define DCD300_TUNE 0.74f
#define N1200 8 //samples per symbol @ fs=9600, oversampling = 38400 Hz
#define N9600 4 //fs=38400, oversampling = 153600 Hz
#define N300 32 //fs=9600, oversampling = 38400 Hz
#define NMAX 32 //keep this value equal to the biggest Nx
#define PLL1200_STEP (((uint64_t)1 << 32) / N1200) //PLL tick increment value
#define PLL9600_STEP (((uint64_t)1 << 32) / N9600)
#define PLL300_STEP (((uint64_t)1 << 32) / N300)
#define PLL1200_LOCKED_TUNE 0.74f
#define PLL1200_NOT_LOCKED_TUNE 0.50f
#define PLL9600_LOCKED_TUNE 0.89f
#define PLL9600_NOT_LOCKED_TUNE 0.50f //I have 0.67 noted somewhere as possibly better value
#define PLL300_LOCKED_TUNE 0.74f
#define PLL300_NOT_LOCKED_TUNE 0.50f
#define AMP_TRACKING_ATTACK 0.16f //0.16
#define AMP_TRACKING_DECAY 0.00004f //0.00004
#define DAC_SINE_SIZE 128 //DAC sine table size
#define PLL_TUNE_BITS 8 //number of bits when tuning PLL to avoid floating point operations
struct ModemDemodConfig ModemConfig;
static uint8_t N; //samples per symbol
static enum ModemTxTestMode txTestState; //current TX test mode
static uint8_t demodCount; //actual number of parallel demodulators
static uint16_t dacSine[DAC_SINE_SIZE]; //sine samples for DAC
static uint8_t dacSineIdx; //current sine sample index
static volatile uint16_t samples[MODEM_LL_OVERSAMPLING_FACTOR]; //very raw received samples, filled directly by DMA
static uint8_t currentSymbol; //current symbol for NRZI encoding
static uint8_t scrambledSymbol; //current symbol after scrambling
static float markFreq; //mark frequency
static float spaceFreq; //space frequency
static float baudRate; //baudrate
static uint8_t markStep; //mark timer step
static uint8_t spaceStep; //space timer step
static uint16_t baudRateStep; //baudrate timer step
static int16_t coeffHiI[NMAX], coeffLoI[NMAX], coeffHiQ[NMAX], coeffLoQ[NMAX]; //correlator IQ coefficients
static uint8_t dcd = 0; //multiplexed DCD state from both demodulators
static uint32_t lfsr = 0xFFFFF; //LFSR for 9600 Bd
/**
* @brief BPF filter with 2200 Hz tone 6 dB preemphasis (it actually attenuates 1200 Hz tone by 6 dB)
*/
static const int16_t bpf1200[8] =
{
728,
-13418,
-554,
19493,
-554,
-13418,
728,
2104
};
/**
* @brief BPF filter with 2200 Hz tone 6 dB deemphasis
*/
static const int16_t bpf1200Inv[8] =
{
-10513,
-10854,
9589,
23884,
9589,
-10854,
-10513,
-879
};
//fs=9600, rectangular, fc1=1500, fc2=1900, 0 dB @ 1600 Hz and 1800 Hz, N = 15, gain 65536
static const int16_t bpf300[15] =
{
186, 8887, 8184, -1662, -10171, -8509, 386, 5394, 386, -8509, -10171, -1662, 8184, 8887, 186,
};
#define BPF_MAX_TAPS 15
//fs=9600 Hz, raised cosine, fc=300 Hz (BR=600 Bd), beta=0.8, N=14, gain=65536
static const int16_t lpf300[14] =
{
4385, 4515, 4627, 4720, 4793, 4846, 4878, 4878, 4846, 4793, 4720, 4627, 4515, 4385,
};
//I don't remember what are this filter parameters,
//but it seems to be the best among all I have tested
static const int16_t lpf1200[15] =
{
-6128,
-5974,
-2503,
4125,
12679,
21152,
27364,
29643,
27364,
21152,
12679,
4125,
-2503,
-5974,
-6128
};
//fs=38400 Hz, Gaussian, fc=4800 Hz (9600 Bd), N=9, gain=65536
//seems like there is almost no difference between N=9 and any higher order
static const int16_t lpf9600[9] = {497, 2360, 7178, 13992, 17478, 13992, 7178, 2360, 497};
#define LPF_MAX_TAPS 15
#define FILTER_MAX_TAPS ((LPF_MAX_TAPS > BPF_MAX_TAPS) ? LPF_MAX_TAPS : BPF_MAX_TAPS)
struct Filter
{
int16_t *coeffs;
uint8_t taps;
int32_t samples[FILTER_MAX_TAPS];
uint8_t gainShift;
};
struct DemodState
{
uint8_t rawSymbols; //raw, unsynchronized symbols
uint8_t syncSymbols; //synchronized symbols
enum ModemPrefilter prefilter;
struct Filter bpf;
int16_t correlatorSamples[NMAX];
uint8_t correlatorSamplesIdx;
struct Filter lpf;
uint8_t dcd : 1; //DCD state
int32_t pll; //bit recovery PLL counter
int32_t pllStep;
int32_t pllLockedTune;
int32_t pllNotLockedTune;
int32_t dcdPll; //DCD PLL main counter
uint8_t dcdLastSymbol; //last symbol for DCD
uint16_t dcdCounter; //DCD "pulse" counter (incremented when RX signal is correct)
uint16_t dcdMax;
uint16_t dcdThres;
uint16_t dcdInc;
uint16_t dcdDec;
int32_t dcdTune;
int16_t peak;
int16_t valley;
};
static struct DemodState demodState[MODEM_MAX_DEMODULATOR_COUNT];
static void decode(uint8_t symbol, uint8_t demod);
static int32_t demodulate(int16_t sample, struct DemodState *dem);
static void setPtt(bool state);
static int32_t filter(struct Filter *filter, int32_t input)
{
int32_t out = 0;
for(uint8_t i = filter->taps - 1; i > 0; i--)
filter->samples[i] = filter->samples[i - 1]; //shift old samples
filter->samples[0] = input; //store new sample
for(uint8_t i = 0; i < filter->taps; i++)
{
out += (int32_t)filter->coeffs[i] * filter->samples[i];
}
return out >> filter->gainShift;
}
float ModemGetBaudrate(void)
{
return baudRate;
}
uint8_t ModemGetDemodulatorCount(void)
{
return demodCount;
}
uint8_t ModemDcdState(void)
{
return dcd;
}
uint8_t ModemIsTxTestOngoing(void)
{
if(txTestState != TEST_DISABLED)
return 1;
return 0;
}
void ModemGetSignalLevel(uint8_t modem, int8_t *peak, int8_t *valley, uint8_t *level)
{
*peak = (100 * (int32_t)demodState[modem].peak) >> 12;
*valley = (100 * (int32_t)demodState[modem].valley) >> 12;
*level = (100 * (int32_t)(demodState[modem].peak - demodState[modem].valley)) >> 13;
}
enum ModemPrefilter ModemGetFilterType(uint8_t modem)
{
return demodState[modem].prefilter;
}
/**
* @brief Set DCD LED
* @param[in] state False - OFF, true - ON
*/
static void setDcd(bool state)
{
if(state)
{
MODEM_LL_DCD_LED_ON();
}
else
{
MODEM_LL_DCD_LED_OFF();
}
}
static inline uint8_t descramble(uint8_t in)
{
//G3RUH descrambling (x^17+x^12+1)
uint8_t bit = ((lfsr & 0x10000) > 0) ^ ((lfsr & 0x800) > 0) ^ (in > 0);
lfsr <<= 1;
lfsr |= in;
return bit;
}
static inline uint8_t scramble(uint8_t in)
{
//G3RUH scrambling (x^17+x^12+1)
uint8_t bit = ((lfsr & 0x10000) > 0) ^ ((lfsr & 0x800) > 0) ^ (in > 0);
lfsr <<= 1;
lfsr |= bit;
return bit;
}
/**
* @brief ISR for demodulator
*/
void MODEM_LL_DMA_INTERRUPT_HANDLER(void) __attribute__ ((interrupt));
void MODEM_LL_DMA_INTERRUPT_HANDLER(void)
{
if(MODEM_LL_DMA_TRANSFER_COMPLETE_FLAG)
{
MODEM_LL_DMA_CLEAR_TRANSFER_COMPLETE_FLAG();
//each sample is 12 bits, output sample is 13 bits
int32_t sample = ((samples[0] + samples[1] + samples[2] + samples[3]) >> 1) - 4095; //calculate input sample (decimation)
bool partialDcd = false;
for(uint8_t i = 0; i < demodCount; i++)
{
uint8_t symbol = (demodulate(sample, (struct DemodState*)&demodState[i]) > 0); //demodulate sample
decode(symbol, i); //recover bits, decode NRZI and call higher level function
if(demodState[i].dcd)
partialDcd = true;
}
if(partialDcd) //DCD on any of the demodulators
{
dcd = 1;
setDcd(true);
}
else //no DCD on both demodulators
{
dcd = 0;
setDcd(false);
}
}
}
/**
* @brief ISR for pushing DAC samples
*/
void MODEM_LL_DAC_INTERRUPT_HANDLER(void) __attribute__ ((interrupt));
void MODEM_LL_DAC_INTERRUPT_HANDLER(void)
{
MODEM_LL_DAC_TIMER_CLEAR_INTERRUPT_FLAG;
int32_t sample = 0;
if(ModemConfig.modem == MODEM_9600)
{
if(ModemConfig.usePWM)
sample = scrambledSymbol ? 256 : 1;
else
sample = scrambledSymbol ? 15 : 0;
sample = filter(&demodState[0].lpf, sample);
}
else
{
sample = dacSine[dacSineIdx];
dacSineIdx++;
dacSineIdx %= DAC_SINE_SIZE;
}
if(ModemConfig.usePWM)
{
MODEM_LL_PWM_PUT_VALUE(sample);
}
else
{
MODEM_LL_R2R_PUT_VALUE(sample);
}
}
/**
* @brief ISR for baudrate generator timer. NRZI encoding is done here.
*/
void MODEM_LL_BAUDRATE_TIMER_INTERRUPT_HANDLER(void) __attribute__ ((interrupt));
void MODEM_LL_BAUDRATE_TIMER_INTERRUPT_HANDLER(void)
{
MODEM_LL_BAUDRATE_TIMER_CLEAR_INTERRUPT_FLAG();
if(txTestState == TEST_DISABLED) //transmitting normal data
{
if(Ax25GetTxBit() == 0) //get next bit and check if it's 0
{
currentSymbol ^= 1; //change symbol - NRZI encoding
}
//if 1, no symbol change
}
else //transmit test mode
{
if(ModemConfig.modem == MODEM_9600)
{
scrambledSymbol ^= 1;
return;
}
currentSymbol ^= 1; //change symbol
}
if(ModemConfig.modem == MODEM_9600)
{
scrambledSymbol = scramble(currentSymbol);
}
else
{
MODEM_LL_DAC_TIMER_SET_CURRENT_VALUE(0);
if(currentSymbol)
{
MODEM_LL_DAC_TIMER_SET_RELOAD_VALUE(spaceStep);
}
else
{
MODEM_LL_DAC_TIMER_SET_RELOAD_VALUE(markStep);
}
}
}
/**
* @brief Demodulate received sample (4x oversampling)
* @param[in] sample Received sample, no more than 13 bits
* @param[in] *dem Demodulator state
* @return Current tone (0 or 1)
*/
static int32_t demodulate(int16_t sample, struct DemodState *dem)
{
//input signal amplitude tracking
if(sample >= dem->peak)
{
dem->peak += (((int32_t)(AMP_TRACKING_ATTACK * (float)32768) * (int32_t)(sample - dem->peak)) >> 15);
}
else
{
dem->peak += (((int32_t)(AMP_TRACKING_DECAY * (float)32768) * (int32_t)(sample - dem->peak)) >> 15);
}
if(sample <= dem->valley)
{
dem->valley -= (((int32_t)(AMP_TRACKING_ATTACK * (float)32768) * (int32_t)(dem->valley - sample)) >> 15);
}
else
{
dem->valley -= (((int32_t)(AMP_TRACKING_DECAY * (float)32768) * (int32_t)(dem->valley - sample)) >> 15);
}
if(ModemConfig.modem != MODEM_9600)
{
if(dem->prefilter != PREFILTER_NONE) //filter is used
{
dem->correlatorSamples[dem->correlatorSamplesIdx++] = filter(&dem->bpf, sample);
}
else //no pre/deemphasis
{
dem->correlatorSamples[dem->correlatorSamplesIdx++] = sample;
}
dem->correlatorSamplesIdx %= N;
int32_t outLoI = 0, outLoQ = 0, outHiI = 0, outHiQ = 0; //output values after correlating
for(uint8_t i = 0; i < N; i++)
{
int16_t t = dem->correlatorSamples[(dem->correlatorSamplesIdx + i) % N]; //read sample
outLoI += t * coeffLoI[i]; //correlate sample
outLoQ += t * coeffLoQ[i];
outHiI += t * coeffHiI[i];
outHiQ += t * coeffHiQ[i];
}
outHiI >>= 14;
outHiQ >>= 14;
outLoI >>= 14;
outLoQ >>= 14;
sample = (abs(outLoI) + abs(outLoQ)) - (abs(outHiI) + abs(outHiQ));
}
//DCD using "PLL"
//PLL is running nominally at the frequency equal to the baudrate
//PLL timer is counting up and eventually overflows to a minimal negative value
//so it crosses zero in the middle
//tone change should happen somewhere near this zero-crossing (in ideal case of exactly same TX and RX baudrates)
//nothing is ideal, so we need to have some region around zero where tone change is expected
//however in case of noise the demodulated output is completely random and has many symbol changes in different places
//other than the PLL zero-crossing, thus making it easier to utilize this mechanism
//if tone changed inside this region, then we add something to the DCD pulse counter and adjust counter phase for the counter to be closer to 0
//if tone changes outside this region, then we subtract something from the DCD pulse counter
//if some DCD pulse threshold is reached, then we claim that the incoming signal is correct and set DCD flag
//when configured properly, it's generally immune to noise and sensitive to correct signal
//it's also important to set some maximum value for DCD counter, otherwise the DCD is "sticky"
dem->dcdPll = (int32_t)((uint32_t)(dem->dcdPll) + (uint32_t)(dem->pllStep)); //keep PLL ticking at the frequency equal to baudrate
if((sample > 0) != dem->dcdLastSymbol) //tone changed
{
if((uint32_t)abs(dem->dcdPll) < (uint32_t)(dem->pllStep)) //tone change occurred near zero
{
dem->dcdCounter += dem->dcdInc; //increase DCD counter
if(dem->dcdCounter > dem->dcdMax) //maximum DCD counter value reached
dem->dcdCounter = dem->dcdMax; //avoid "sticky" DCD and counter overflow
}
else //tone change occurred far from zero
{
if(dem->dcdCounter >= dem->dcdDec) //avoid overflow
dem->dcdCounter -= dem->dcdDec; //decrease DCD counter
else
dem->dcdCounter = 0;
}
//avoid floating point operations
dem->dcdPll = ((int64_t)dem->dcdPll * (int64_t)dem->dcdTune) >> PLL_TUNE_BITS;
}
dem->dcdLastSymbol = sample > 0; //store last symbol for symbol change detection
if(dem->dcdCounter > dem->dcdThres) //DCD threshold reached
dem->dcd = 1; //DCD!
else //below DCD threshold
dem->dcd = 0; //no DCD
return filter(&dem->lpf, sample) > 0;
}
/**
* @brief Decode received symbol: bit recovery, NRZI decoding and pass the decoded bit to higher level protocol
* @param[in] symbol Received symbol
* @param demod Demodulator index
*/
static void decode(uint8_t symbol, uint8_t demod)
{
struct DemodState *dem = (struct DemodState*)&demodState[demod];
//This function provides bit/clock recovery and NRZI decoding
//Bit recovery is based on PLL which is described in the function above (DCD PLL)
//Current symbol is sampled at PLL counter overflow, so symbol transition should occur at PLL counter zero
int32_t previous = dem->pll; //store last clock state
dem->pll = (int32_t)((uint32_t)(dem->pll) + (uint32_t)(dem->pllStep)); //keep PLL running
dem->rawSymbols <<= 1; //store received unsynchronized symbol
dem->rawSymbols |= (symbol & 1);
if ((dem->pll < 0) && (previous > 0)) //PLL counter overflow, sample symbol, decode NRZI and process in higher layer
{
dem->syncSymbols <<= 1; //shift recovered (received, synchronized) bit register
uint8_t sym = dem->rawSymbols & 0x07; //take last three symbols for sampling. Seems that 1 symbol is not enough, but 3 symbols work well
if(sym == 0b111 || sym == 0b110 || sym == 0b101 || sym == 0b011) //if there are 2 or 3 ones, then the received symbol is 1
sym = 1;
else
sym = 0;
if(ModemConfig.modem == MODEM_9600)
sym = descramble(sym); //descramble
dem->syncSymbols |= sym;
//NRZI decoding
if (((dem->syncSymbols & 0x03) == 0b11) || ((dem->syncSymbols & 0x03) == 0b00)) //two last symbols are the same - no symbol transition - decoded bit 1
{
Ax25BitParse(1, demod);
}
else //symbol transition - decoded bit 0
{
Ax25BitParse(0, demod);
}
}
if(((dem->rawSymbols & 0x03) == 0b10) || ((dem->rawSymbols & 0x03) == 0b01)) //if there was a symbol transition, adjust PLL
{
//avoid floating point operations. Multiply by n-bit value and shift by n bits
if(!dem->dcd) //PLL not locked
{
dem->pll = ((int64_t)dem->pll * (int64_t)dem->pllNotLockedTune) >> PLL_TUNE_BITS; //adjust PLL faster
}
else //PLL locked
{
dem->pll = ((int64_t)dem->pll * (int64_t)dem->pllLockedTune) >> PLL_TUNE_BITS; //adjust PLL slower
}
}
}
void ModemTxTestStart(enum ModemTxTestMode type)
{
if(txTestState != TEST_DISABLED) //TX test is already running
ModemTxTestStop(); //stop this test
setPtt(true); //PTT on
txTestState = type;
MODEM_LL_ADC_TIMER_DISABLE();
MODEM_LL_DAC_TIMER_ENABLE();
NVIC_DisableIRQ(MODEM_LL_DMA_IRQ);
NVIC_EnableIRQ(MODEM_LL_DAC_IRQ);
if(ModemConfig.modem == MODEM_9600)
{
MODEM_LL_DAC_TIMER_SET_RELOAD_VALUE(markStep);
MODEM_LL_BAUDRATE_TIMER_ENABLE();
NVIC_EnableIRQ(MODEM_LL_BAUDRATE_TIMER_IRQ);
return;
}
if(type == TEST_MARK)
{
MODEM_LL_DAC_TIMER_SET_RELOAD_VALUE(markStep);
}
else if(type == TEST_SPACE)
{
MODEM_LL_DAC_TIMER_SET_RELOAD_VALUE(spaceStep);
}
else //alternating tones
{
MODEM_LL_BAUDRATE_TIMER_ENABLE();
NVIC_EnableIRQ(MODEM_LL_BAUDRATE_TIMER_IRQ); //enable interrupt in NVIC
}
}
void ModemTxTestStop(void)
{
txTestState = TEST_DISABLED;
MODEM_LL_BAUDRATE_TIMER_DISABLE();
MODEM_LL_DAC_TIMER_DISABLE(); //disable DAC timer
MODEM_LL_ADC_TIMER_ENABLE(); //enable RX timer
NVIC_DisableIRQ(MODEM_LL_BAUDRATE_TIMER_IRQ);
NVIC_DisableIRQ(MODEM_LL_DAC_IRQ);
NVIC_EnableIRQ(MODEM_LL_DMA_IRQ);
setPtt(false); //PTT off
}
void ModemTransmitStart(void)
{
setPtt(true); //PTT on
if(ModemConfig.modem == MODEM_9600)
{
MODEM_LL_DAC_TIMER_SET_RELOAD_VALUE(markStep);
}
MODEM_LL_BAUDRATE_TIMER_ENABLE();
MODEM_LL_DAC_TIMER_ENABLE();
MODEM_LL_ADC_TIMER_DISABLE();
NVIC_DisableIRQ(MODEM_LL_DMA_IRQ);
NVIC_EnableIRQ(MODEM_LL_DAC_IRQ);
NVIC_EnableIRQ(MODEM_LL_BAUDRATE_TIMER_IRQ);
}
/**
* @brief Stop TX and go back to RX
*/
void ModemTransmitStop(void)
{
MODEM_LL_ADC_TIMER_ENABLE();
MODEM_LL_DAC_TIMER_DISABLE();
MODEM_LL_BAUDRATE_TIMER_DISABLE();
NVIC_DisableIRQ(MODEM_LL_DAC_IRQ);
NVIC_DisableIRQ(MODEM_LL_BAUDRATE_TIMER_IRQ);
NVIC_EnableIRQ(MODEM_LL_DMA_IRQ);
setPtt(false);
}
/**
* @brief Controls PTT output
* @param state False - PTT off, true - PTT on
*/
static void setPtt(bool state)
{
if(state)
{
MODEM_LL_PTT_ON();
}
else
{
MODEM_LL_PTT_OFF();
}
}
/**
* @brief Initialize AFSK module
*/
void ModemInit(void)
{
memset(demodState, 0, sizeof(demodState));
MODEM_LL_INITIALIZE_RCC(); //initialize peripheral clocks
MODEM_LL_INITIALIZE_OUTPUTS();
MODEM_LL_INITIALIZE_ADC();
MODEM_LL_INITIALIZE_DMA(samples);
NVIC_EnableIRQ(MODEM_LL_DMA_IRQ);
MODEM_LL_ADC_TIMER_INITIALIZE();
MODEM_LL_DAC_TIMER_INITIALIZE();
MODEM_LL_BAUDRATE_TIMER_INITIALIZE();
if(ModemConfig.modem > MODEM_9600)
ModemConfig.modem = MODEM_1200;
if((ModemConfig.modem == MODEM_1200) || (ModemConfig.modem == MODEM_1200_V23))
{
//use one modem in FX.25 mode
//FX.25 (RS) functions are not reentrant
if(
#ifdef ENABLE_FX25
Ax25Config.fx25
#else
0
#endif
)
demodCount = 1;
else
demodCount = 2;
N = N1200;
baudRate = 1200.f;
demodState[0].pllStep = PLL1200_STEP;
demodState[0].pllLockedTune = PLL1200_LOCKED_TUNE * (float)((uint32_t)1 << PLL_TUNE_BITS);
demodState[0].pllNotLockedTune = PLL1200_NOT_LOCKED_TUNE * (float)((uint32_t)1 << PLL_TUNE_BITS);
demodState[0].dcdMax = DCD1200_MAXPULSE;
demodState[0].dcdThres = DCD1200_THRES;
demodState[0].dcdInc = DCD1200_INC;
demodState[0].dcdDec = DCD1200_DEC;
demodState[0].dcdTune = DCD1200_TUNE * (float)((uint32_t)1 << PLL_TUNE_BITS);
demodState[1].pllStep = PLL1200_STEP;
demodState[1].pllLockedTune = PLL1200_LOCKED_TUNE * (float)((uint32_t)1 << PLL_TUNE_BITS);
demodState[1].pllNotLockedTune = PLL1200_NOT_LOCKED_TUNE * (float)((uint32_t)1 << PLL_TUNE_BITS);
demodState[1].dcdMax = DCD1200_MAXPULSE;
demodState[1].dcdThres = DCD1200_THRES;
demodState[1].dcdInc = DCD1200_INC;
demodState[1].dcdDec = DCD1200_DEC;
demodState[1].dcdTune = DCD1200_TUNE * (float)((uint32_t)1 << PLL_TUNE_BITS);
demodState[1].prefilter = PREFILTER_NONE;
demodState[1].lpf.coeffs = (int16_t*)lpf1200;
demodState[1].lpf.taps = sizeof(lpf1200) / sizeof(*lpf1200);
demodState[1].lpf.gainShift = 15;
demodState[0].lpf.coeffs = (int16_t*)lpf1200;
demodState[0].lpf.taps = sizeof(lpf1200) / sizeof(*lpf1200);
demodState[0].lpf.gainShift = 15;
demodState[0].prefilter = PREFILTER_NONE;
if(ModemConfig.flatAudioIn) //when used with flat audio input, use deemphasis and flat modems
{
#ifdef ENABLE_FX25
if(Ax25Config.fx25)
demodState[0].prefilter = PREFILTER_NONE;
else
#endif
demodState[0].prefilter = PREFILTER_DEEMPHASIS;
demodState[0].bpf.coeffs = (int16_t*)bpf1200Inv;
demodState[0].bpf.taps = sizeof(bpf1200Inv) / sizeof(*bpf1200Inv);
demodState[0].bpf.gainShift = 15;
}
else //when used with normal (filtered) audio input, use flat and preemphasis modems
{
demodState[0].prefilter = PREFILTER_PREEMPHASIS;
demodState[0].bpf.coeffs = (int16_t*)bpf1200;
demodState[0].bpf.taps = sizeof(bpf1200) / sizeof(*bpf1200);
demodState[0].bpf.gainShift = 15;
}
if(ModemConfig.modem == MODEM_1200) //Bell 202
{
markFreq = 1200.f;
spaceFreq = 2200.f;
}
else //V.23
{
markFreq = 1300.f;
spaceFreq = 2100.f;
}
}
else if(ModemConfig.modem == MODEM_300)
{
demodCount = 1;
N = N300;
baudRate = 300.f;
markFreq = 1600.f;
spaceFreq = 1800.f;
demodState[0].pllStep = PLL300_STEP;
demodState[0].pllLockedTune = PLL300_LOCKED_TUNE * (float)((uint32_t)1 << PLL_TUNE_BITS);
demodState[0].pllNotLockedTune = PLL300_NOT_LOCKED_TUNE * (float)((uint32_t)1 << PLL_TUNE_BITS);
demodState[0].dcdMax = DCD300_MAXPULSE;
demodState[0].dcdThres = DCD300_THRES;
demodState[0].dcdInc = DCD300_INC;
demodState[0].dcdDec = DCD300_DEC;
demodState[0].dcdTune = DCD300_TUNE * (float)((uint32_t)1 << PLL_TUNE_BITS);
demodState[0].prefilter = PREFILTER_FLAT;
demodState[0].bpf.coeffs = (int16_t*)bpf300;
demodState[0].bpf.taps = sizeof(bpf300) / sizeof(*bpf300);
demodState[0].bpf.gainShift = 16;
demodState[0].lpf.coeffs = (int16_t*)lpf300;
demodState[0].lpf.taps = sizeof(lpf300) / sizeof(*lpf300);
demodState[0].lpf.gainShift = 15;
}
else if(ModemConfig.modem == MODEM_9600)
{
demodCount = 1;
N = N9600;
baudRate = 9600.f;
markFreq = 38400.f / (float)DAC_SINE_SIZE; //use as DAC sample rate
demodState[0].pllStep = PLL9600_STEP;
demodState[0].pllLockedTune = PLL9600_LOCKED_TUNE * (float)((uint32_t)1 << PLL_TUNE_BITS);
demodState[0].pllNotLockedTune = PLL9600_NOT_LOCKED_TUNE * (float)((uint32_t)1 << PLL_TUNE_BITS);
demodState[0].dcdMax = DCD9600_MAXPULSE;
demodState[0].dcdThres = DCD9600_THRES;
demodState[0].dcdInc = DCD9600_INC;
demodState[0].dcdDec = DCD9600_DEC;
demodState[0].dcdTune = DCD9600_TUNE * (float)((uint32_t)1 << PLL_TUNE_BITS);
demodState[0].prefilter = PREFILTER_NONE;
//this filter will be used for RX and TX
demodState[0].lpf.coeffs = (int16_t*)lpf9600;
demodState[0].lpf.taps = sizeof(lpf9600) / sizeof(*lpf9600);
demodState[0].lpf.gainShift = 16;
}
MODEM_LL_ADC_SET_SAMPLE_RATE(baudRate * N * MODEM_LL_OVERSAMPLING_FACTOR);
MODEM_LL_ADC_TIMER_ENABLE();
markStep = MODEM_LL_DAC_TIMER_CALCULATE_STEP(DAC_SINE_SIZE * markFreq);
spaceStep = MODEM_LL_DAC_TIMER_CALCULATE_STEP(DAC_SINE_SIZE * spaceFreq);
baudRateStep = MODEM_LL_BAUDRATE_TIMER_CALCULATE_STEP(baudRate);
MODEM_LL_BAUDRATE_TIMER_SET_RELOAD_VALUE(baudRateStep);
for(uint8_t i = 0; i < N; i++) //calculate correlator coefficients
{
coeffLoI[i] = 4095.f * cosf(2.f * 3.1416f * (float)i / (float)N * markFreq / baudRate);
coeffLoQ[i] = 4095.f * sinf(2.f * 3.1416f * (float)i / (float)N * markFreq / baudRate);
coeffHiI[i] = 4095.f * cosf(2.f * 3.1416f * (float)i / (float)N * spaceFreq / baudRate);
coeffHiQ[i] = 4095.f * sinf(2.f * 3.1416f * (float)i / (float)N * spaceFreq / baudRate);
}
for(uint8_t i = 0; i < DAC_SINE_SIZE; i++) //calculate DAC sine samples
{
if(ModemConfig.usePWM)
//produce values in range 1 to 256
dacSine[i] = ((sinf(2.f * 3.1416f * (float)i / (float)DAC_SINE_SIZE) + 1.f) * 128.f);
else
dacSine[i] = ((7.f * sinf(2.f * 3.1416f * (float)i / (float)DAC_SINE_SIZE)) + 8.f);
}
if(ModemConfig.usePWM)
{
MODEM_LL_PWM_INITIALIZE();
}
}

26
Src/stm32f1xx_hal_msp.c → Core/Src/stm32f1xx_hal_msp.c
Wyświetl plik

@ -1,19 +1,18 @@
/* USER CODE BEGIN Header */
/**
******************************************************************************
* File Name : stm32f1xx_hal_msp.c
* Description : This file provides code for the MSP Initialization
* and de-Initialization codes.
* @file stm32f1xx_hal_msp.c
* @brief This file provides code for the MSP Initialization
* and de-Initialization codes.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
* All rights reserved.</center></h2>
* Copyright (c) 2023 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@ -21,6 +20,7 @@
/* Includes ------------------------------------------------------------------*/
#include "main.h"
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
@ -32,7 +32,7 @@
/* Private define ------------------------------------------------------------*/
/* USER CODE BEGIN Define */
/* USER CODE END Define */
/* Private macro -------------------------------------------------------------*/
@ -72,9 +72,9 @@ void HAL_MspInit(void)
/* System interrupt init*/
/** NONJTRST: Full SWJ (JTAG-DP + SW-DP) but without NJTRST
/** NOJTAG: JTAG-DP Disabled and SW-DP Enabled
*/
__HAL_AFIO_REMAP_SWJ_NONJTRST();
__HAL_AFIO_REMAP_SWJ_NOJTAG();
/* USER CODE BEGIN MspInit 1 */
@ -84,5 +84,3 @@ void HAL_MspInit(void)
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

24
Src/stm32f1xx_it.c → Core/Src/stm32f1xx_it.c
Wyświetl plik

@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
* All rights reserved.</center></h2>
* Copyright (c) 2023 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under Ultimate Liberty license
* SLA0044, the "License"; You may not use this file except in compliance with
* the License. You may obtain a copy of the License at:
* www.st.com/SLA0044
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@ -23,7 +22,6 @@
#include "stm32f1xx_it.h"
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
#include "Drivers/systick.h"
/* USER CODE END Includes */
/* Private typedef -----------------------------------------------------------*/
@ -33,7 +31,7 @@
/* Private define ------------------------------------------------------------*/
/* USER CODE BEGIN PD */
/* USER CODE END PD */
/* Private macro -------------------------------------------------------------*/
@ -71,10 +69,12 @@ extern PCD_HandleTypeDef hpcd_USB_FS;
void NMI_Handler(void)
{
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
NVIC_SystemReset();
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
NVIC_SystemReset();
while (1)
{
}
/* USER CODE END NonMaskableInt_IRQn 1 */
}
@ -187,7 +187,8 @@ void SysTick_Handler(void)
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
/* USER CODE BEGIN SysTick_IRQn 1 */
ticks++;
extern volatile uint32_t ticks;
ticks++;
/* USER CODE END SysTick_IRQn 1 */
}
@ -215,4 +216,3 @@ void USB_LP_CAN1_RX0_IRQHandler(void)
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

176
Core/Src/syscalls.c 100644
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@ -0,0 +1,176 @@
/**
******************************************************************************
* @file syscalls.c
* @author Auto-generated by STM32CubeIDE
* @brief STM32CubeIDE Minimal System calls file
*
* For more information about which c-functions
* need which of these lowlevel functions
* please consult the Newlib libc-manual
******************************************************************************
* @attention
*
* Copyright (c) 2020-2023 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Includes */
#include <sys/stat.h>
#include <stdlib.h>
#include <errno.h>
#include <stdio.h>
#include <signal.h>
#include <time.h>
#include <sys/time.h>
#include <sys/times.h>
/* Variables */
extern int __io_putchar(int ch) __attribute__((weak));
extern int __io_getchar(void) __attribute__((weak));
char *__env[1] = { 0 };
char **environ = __env;
/* Functions */
void initialise_monitor_handles()
{
}
int _getpid(void)
{
return 1;
}
int _kill(int pid, int sig)
{
(void)pid;
(void)sig;
errno = EINVAL;
return -1;
}
void _exit (int status)
{
_kill(status, -1);
while (1) {} /* Make sure we hang here */
}
__attribute__((weak)) int _read(int file, char *ptr, int len)
{
(void)file;
int DataIdx;
for (DataIdx = 0; DataIdx < len; DataIdx++)
{
*ptr++ = __io_getchar();
}
return len;
}
__attribute__((weak)) int _write(int file, char *ptr, int len)
{
(void)file;
int DataIdx;
for (DataIdx = 0; DataIdx < len; DataIdx++)
{
__io_putchar(*ptr++);
}
return len;
}
int _close(int file)
{
(void)file;
return -1;
}
int _fstat(int file, struct stat *st)
{
(void)file;
st->st_mode = S_IFCHR;
return 0;
}
int _isatty(int file)
{
(void)file;
return 1;
}
int _lseek(int file, int ptr, int dir)
{
(void)file;
(void)ptr;
(void)dir;
return 0;
}
int _open(char *path, int flags, ...)
{
(void)path;
(void)flags;
/* Pretend like we always fail */
return -1;
}
int _wait(int *status)
{
(void)status;
errno = ECHILD;
return -1;
}
int _unlink(char *name)
{
(void)name;
errno = ENOENT;
return -1;
}
int _times(struct tms *buf)
{
(void)buf;
return -1;
}
int _stat(char *file, struct stat *st)
{
(void)file;
st->st_mode = S_IFCHR;
return 0;
}
int _link(char *old, char *new)
{
(void)old;
(void)new;
errno = EMLINK;
return -1;
}
int _fork(void)
{
errno = EAGAIN;
return -1;
}
int _execve(char *name, char **argv, char **env)
{
(void)name;
(void)argv;
(void)env;
errno = ENOMEM;
return -1;
}

79
Core/Src/sysmem.c 100644
Wyświetl plik

@ -0,0 +1,79 @@
/**
******************************************************************************
* @file sysmem.c
* @author Generated by STM32CubeIDE
* @brief STM32CubeIDE System Memory calls file
*
* For more information about which C functions
* need which of these lowlevel functions
* please consult the newlib libc manual
******************************************************************************
* @attention
*
* Copyright (c) 2023 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Includes */
#include <errno.h>
#include <stdint.h>
/**
* Pointer to the current high watermark of the heap usage
*/
static uint8_t *__sbrk_heap_end = NULL;
/**
* @brief _sbrk() allocates memory to the newlib heap and is used by malloc
* and others from the C library
*
* @verbatim
* ############################################################################
* # .data # .bss # newlib heap # MSP stack #
* # # # # Reserved by _Min_Stack_Size #
* ############################################################################
* ^-- RAM start ^-- _end _estack, RAM end --^
* @endverbatim
*
* This implementation starts allocating at the '_end' linker symbol
* The '_Min_Stack_Size' linker symbol reserves a memory for the MSP stack
* The implementation considers '_estack' linker symbol to be RAM end
* NOTE: If the MSP stack, at any point during execution, grows larger than the
* reserved size, please increase the '_Min_Stack_Size'.
*
* @param incr Memory size
* @return Pointer to allocated memory
*/
void *_sbrk(ptrdiff_t incr)
{
extern uint8_t _end; /* Symbol defined in the linker script */
extern uint8_t _estack; /* Symbol defined in the linker script */
extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */
const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size;
const uint8_t *max_heap = (uint8_t *)stack_limit;
uint8_t *prev_heap_end;
/* Initialize heap end at first call */
if (NULL == __sbrk_heap_end)
{
__sbrk_heap_end = &_end;
}
/* Protect heap from growing into the reserved MSP stack */
if (__sbrk_heap_end + incr > max_heap)
{
errno = ENOMEM;
return (void *)-1;
}
prev_heap_end = __sbrk_heap_end;
__sbrk_heap_end += incr;
return (void *)prev_heap_end;
}

92
Src/system_stm32f1xx.c → Core/Src/system_stm32f1xx.c
Wyświetl plik

@ -33,13 +33,12 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
* Copyright (c) 2017-2021 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@ -89,12 +88,31 @@
/* #define DATA_IN_ExtSRAM */
#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
/* #define VECT_TAB_SRAM */
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
/* Note: Following vector table addresses must be defined in line with linker
configuration. */
/*!< Uncomment the following line if you need to relocate the vector table
anywhere in Flash or Sram, else the vector table is kept at the automatic
remap of boot address selected */
/* #define USER_VECT_TAB_ADDRESS */
#if defined(USER_VECT_TAB_ADDRESS)
/*!< Uncomment the following line if you need to relocate your vector Table
in Sram else user remap will be done in Flash. */
/* #define VECT_TAB_SRAM */
#if defined(VECT_TAB_SRAM)
#define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field.
This value must be a multiple of 0x200. */
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
#else
#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field.
This value must be a multiple of 0x200. */
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
#endif /* VECT_TAB_SRAM */
#endif /* USER_VECT_TAB_ADDRESS */
/******************************************************************************/
/**
* @}
@ -156,57 +174,16 @@ const uint8_t APBPrescTable[8U] = {0, 0, 0, 0, 1, 2, 3, 4};
*/
void SystemInit (void)
{
/* Reset the RCC clock configuration to the default reset state(for debug purpose) */
/* Set HSION bit */
RCC->CR |= 0x00000001U;
/* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
#if !defined(STM32F105xC) && !defined(STM32F107xC)
RCC->CFGR &= 0xF8FF0000U;
#else
RCC->CFGR &= 0xF0FF0000U;
#endif /* STM32F105xC */
/* Reset HSEON, CSSON and PLLON bits */
RCC->CR &= 0xFEF6FFFFU;
/* Reset HSEBYP bit */
RCC->CR &= 0xFFFBFFFFU;
/* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
RCC->CFGR &= 0xFF80FFFFU;
#if defined(STM32F105xC) || defined(STM32F107xC)
/* Reset PLL2ON and PLL3ON bits */
RCC->CR &= 0xEBFFFFFFU;
/* Disable all interrupts and clear pending bits */
RCC->CIR = 0x00FF0000U;
/* Reset CFGR2 register */
RCC->CFGR2 = 0x00000000U;
#elif defined(STM32F100xB) || defined(STM32F100xE)
/* Disable all interrupts and clear pending bits */
RCC->CIR = 0x009F0000U;
/* Reset CFGR2 register */
RCC->CFGR2 = 0x00000000U;
#else
/* Disable all interrupts and clear pending bits */
RCC->CIR = 0x009F0000U;
#endif /* STM32F105xC */
#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
#ifdef DATA_IN_ExtSRAM
SystemInit_ExtMemCtl();
#endif /* DATA_IN_ExtSRAM */
#endif
#ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
#else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
#endif
/* Configure the Vector Table location -------------------------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
#endif /* USER_VECT_TAB_ADDRESS */
}
/**
@ -426,5 +403,4 @@ void SystemInit_ExtMemCtl(void)
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
*/

21
Src/drivers/systick.c → Core/Src/systick.c
Wyświetl plik

@ -1,4 +1,6 @@
/*
Copyright 2020-2023 Piotr Wilkon
This file is part of VP-Digi.
VP-Digi is free software: you can redistribute it and/or modify
@ -15,7 +17,8 @@ You should have received a copy of the GNU General Public License
along with VP-Digi. If not, see <http://www.gnu.org/licenses/>.
*/
#include "drivers/systick.h"
#include "stm32f1xx.h"
#include "systick.h"
volatile uint32_t ticks = 0; //SysTick counter
@ -25,7 +28,19 @@ volatile uint32_t ticks = 0; //SysTick counter
//ticks++;
//}
void SysTick_init(void)
void SysTickInit(void)
{
SysTick_Config(SystemCoreClock / 100); //SysTick every 10 ms
SysTick_Config(SystemCoreClock / SYSTICK_FREQUENCY); //SysTick every 10 ms
}
uint32_t SysTickGet(void)
{
return ticks;
}
void Delay(uint32_t ms)
{
uint32_t target = SysTickGet() + ms / SYSTICK_INTERVAL;
while(target > SysTickGet())
;
}

1113
Core/Src/terminal.c 100644
Wyświetl plik

Plik diff jest za duży Load Diff

224
Core/Src/uart.c 100644
Wyświetl plik

@ -0,0 +1,224 @@
/*
Copyright 2020-2023 Piotr Wilkon
This file is part of VP-Digi.
VP-Digi is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
VP-Digi is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with VP-Digi. If not, see <http://www.gnu.org/licenses/>.
*/
#include "terminal.h"
#include "ax25.h"
#include "common.h"
#include <string.h>
#include <systick.h>
#include <uart.h>
#include "digipeater.h"
#include "kiss.h"
Uart Uart1 = {.defaultMode = MODE_KISS}, Uart2 = {.defaultMode = MODE_KISS}, UartUsb= {.defaultMode = MODE_KISS};
static void handleInterrupt(Uart *port)
{
if(UART_LL_CHECK_RX_NOT_EMPTY(port->port)) //byte received
{
UART_LL_CLEAR_RX_NOT_EMPTY(port->port);
uint8_t data = port->port->DR;
port->rxBuffer[port->rxBufferHead++] = data; //store it
port->rxBufferHead %= UART_BUFFER_SIZE;
KissParse(port, data);
TermHandleSpecial(port);
}
if(UART_LL_CHECK_RX_IDLE(port->port)) //line is idle, end of data reception
{
UART_LL_GET_DATA(port->port); //reset idle flag by dummy read
if(port->rxBufferHead != 0)
{
if(((port->rxBuffer[port->rxBufferHead - 1] == '\r') || (port->rxBuffer[port->rxBufferHead - 1] == '\n'))) //data ends with \r or \n, process as data
{
port->rxType = DATA_TERM;
}
}
}
if(UART_LL_CHECK_TX_EMPTY(port->port)) //TX buffer empty
{
if((port->txBufferHead != port->txBufferTail) || port->txBufferFull) //if there is anything to transmit
{
UART_LL_PUT_DATA(port->port, port->txBuffer[port->txBufferTail++]);
port->txBufferTail %= UART_BUFFER_SIZE;
port->txBufferFull = 0;
}
else //nothing more to be transmitted
{
UART_LL_DISABLE_TX_EMPTY_INTERRUPT(port->port);
}
}
}
void UART_LL_UART1_INTERUPT_HANDLER(void) __attribute__ ((interrupt));
void UART_LL_UART1_INTERUPT_HANDLER(void)
{
handleInterrupt(&Uart1);
}
void UART_LL_UART2_INTERUPT_HANDLER(void) __attribute__ ((interrupt));
void UART_LL_UART2_INTERUPT_HANDLER(void)
{
handleInterrupt(&Uart2);
}
void UartSendByte(Uart *port, uint8_t data)
{
if(!port->enabled)
return;
if(port->isUsb)
{
CDC_Transmit_FS(&data, 1);
}
else
{
while(port->txBufferFull)
;
port->txBuffer[port->txBufferHead++] = data;
port->txBufferHead %= UART_BUFFER_SIZE;
__disable_irq();
if(port->txBufferHead == port->txBufferTail)
port->txBufferFull = 1;
if(0 == (UART_LL_CHECK_ENABLED_TX_EMPTY_INTERRUPT(port->port)))
UART_LL_ENABLE_TX_EMPTY_INTERRUPT(port->port);
__enable_irq();
}
}
void UartSendString(Uart *port, void *data, uint16_t len)
{
if(0 == len)
len = strlen((char*)data);
for(uint16_t i = 0; i < len; i++)
{
UartSendByte(port, ((uint8_t*)data)[i]);
}
}
static unsigned int findHighestPosition(unsigned int n)
{
unsigned int i = 1;
while((i * 10) <= n)
i *= 10;
return i;
}
void UartSendNumber(Uart *port, int32_t n)
{
if(n < 0)
UartSendByte(port, '-');
n = abs(n);
unsigned int position = findHighestPosition(n);
while(position)
{
unsigned int number = n / position;
UartSendByte(port, (number + 48));
n -= (number * position);
position /= 10;
}
}
void UartInit(Uart *port, USART_TypeDef *uart, uint32_t baud)
{
port->port = uart;
port->baudrate = baud;
port->rxType = DATA_NOTHING;
port->rxBufferHead = 0;
port->txBufferHead = 0;
port->txBufferTail = 0;
port->txBufferFull = 0;
if(port->defaultMode > MODE_MONITOR)
port->defaultMode = MODE_KISS;
port->mode = port->defaultMode;
port->enabled = 0;
port->kissBufferHead = 0;
port->lastRxBufferHead = 0;
memset((void*)port->rxBuffer, 0, sizeof(port->rxBuffer));
memset((void*)port->txBuffer, 0, sizeof(port->txBuffer));
memset((void*)port->kissBuffer, 0, sizeof(port->kissBuffer));
}
void UartConfig(Uart *port, uint8_t state)
{
if(port->port == UART_LL_UART1_STRUCTURE)
{
UART_LL_UART1_INITIALIZE_PERIPHERAL(port->baudrate);
if(state)
{
UART_LL_ENABLE(port->port);
}
else
{
UART_LL_DISABLE(port->port);
}
NVIC_SetPriority(UART_LL_UART1_IRQ, 2);
if(state)
NVIC_EnableIRQ(UART_LL_UART1_IRQ);
else
NVIC_DisableIRQ(UART_LL_UART1_IRQ);
port->enabled = state > 0;
port->isUsb = 0;
}
else if(port->port == UART_LL_UART2_STRUCTURE)
{
UART_LL_UART2_INITIALIZE_PERIPHERAL(port->baudrate);
if(state)
{
UART_LL_ENABLE(port->port);
}
else
{
UART_LL_DISABLE(port->port);
}
NVIC_SetPriority(UART_LL_UART2_IRQ, 2);
if(state)
NVIC_EnableIRQ(UART_LL_UART2_IRQ);
else
NVIC_DisableIRQ(UART_LL_UART2_IRQ);
port->enabled = state > 0;
port->isUsb = 0;
}
else
{
port->isUsb = 1;
port->enabled = state > 0;
}
}
void UartClearRx(Uart *port)
{
port->rxBufferHead = 0;
port->rxType = DATA_NOTHING;
}

50
startup/startup_stm32f103xb.s → Core/Startup/startup_stm32f103c8tx.s
Wyświetl plik

@ -15,13 +15,12 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
* Copyright (c) 2017-2021 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@ -61,36 +60,40 @@ defined in linker script */
.type Reset_Handler, %function
Reset_Handler:
/* Call the clock system initialization function.*/
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
str r3, [r2], #4
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
cmp r2, r4
bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
@ -358,5 +361,4 @@ g_pfnVectors:
.weak USBWakeUp_IRQHandler
.thumb_set USBWakeUp_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

54
Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h
Wyświetl plik

@ -9,18 +9,17 @@
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
* - Macros to access peripheral’s registers hardware
* - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
* Copyright (c) 2017-2021 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@ -695,7 +694,15 @@ typedef struct
/** @addtogroup Exported_constants
* @{
*/
/** @addtogroup Hardware_Constant_Definition
* @{
*/
#define LSI_STARTUP_TIME 85U /*!< LSI Maximum startup time in us */
/**
* @}
*/
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
@ -1376,7 +1383,7 @@ typedef struct
#define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
#define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
/*!< RTC congiguration */
/*!< RTC configuration */
#define RCC_BDCR_RTCSEL_NOCLOCK 0x00000000U /*!< No clock */
#define RCC_BDCR_RTCSEL_LSE 0x00000100U /*!< LSE oscillator clock used as RTC clock */
#define RCC_BDCR_RTCSEL_LSI 0x00000200U /*!< LSI oscillator clock used as RTC clock */
@ -3378,7 +3385,7 @@ typedef struct
#define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!< ADC DMA transfer enable */
#define ADC_CR2_ALIGN_Pos (11U)
#define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */
#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignment */
#define ADC_CR2_JEXTSEL_Pos (12U)
#define ADC_CR2_JEXTSEL_Msk (0x7UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00007000 */
@ -9190,12 +9197,10 @@ typedef struct
#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
/****************** Bit definition for SPI_I2SCFGR register *****************/
#define SPI_I2SCFGR_I2SMOD_Pos (11U)
#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< I2S mode selection */
/******************************************************************************/
/* */
/* Inter-integrated Circuit Interface */
@ -10021,8 +10026,6 @@ typedef struct
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
@ -10182,40 +10185,40 @@ typedef struct
/* Aliases for __IRQn */
#define ADC1_IRQn ADC1_2_IRQn
#define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn
#define TIM9_IRQn TIM1_BRK_IRQn
#define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn
#define TIM1_BRK_TIM15_IRQn TIM1_BRK_IRQn
#define TIM11_IRQn TIM1_TRG_COM_IRQn
#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn
#define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn
#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn
#define TIM11_IRQn TIM1_TRG_COM_IRQn
#define TIM10_IRQn TIM1_UP_IRQn
#define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn
#define TIM1_UP_TIM16_IRQn TIM1_UP_IRQn
#define OTG_FS_WKUP_IRQn USBWakeUp_IRQn
#define CEC_IRQn USBWakeUp_IRQn
#define CAN1_TX_IRQn USB_HP_CAN1_TX_IRQn
#define USB_HP_IRQn USB_HP_CAN1_TX_IRQn
#define USB_LP_IRQn USB_LP_CAN1_RX0_IRQn
#define CAN1_TX_IRQn USB_HP_CAN1_TX_IRQn
#define CAN1_RX0_IRQn USB_LP_CAN1_RX0_IRQn
#define USB_LP_IRQn USB_LP_CAN1_RX0_IRQn
/* Aliases for __IRQHandler */
#define ADC1_IRQHandler ADC1_2_IRQHandler
#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler
#define TIM9_IRQHandler TIM1_BRK_IRQHandler
#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler
#define TIM1_BRK_TIM15_IRQHandler TIM1_BRK_IRQHandler
#define TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
#define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler
#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
#define TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
#define TIM10_IRQHandler TIM1_UP_IRQHandler
#define TIM1_UP_TIM10_IRQHandler TIM1_UP_IRQHandler
#define TIM1_UP_TIM16_IRQHandler TIM1_UP_IRQHandler
#define OTG_FS_WKUP_IRQHandler USBWakeUp_IRQHandler
#define CEC_IRQHandler USBWakeUp_IRQHandler
#define CAN1_TX_IRQHandler USB_HP_CAN1_TX_IRQHandler
#define USB_HP_IRQHandler USB_HP_CAN1_TX_IRQHandler
#define USB_LP_IRQHandler USB_LP_CAN1_RX0_IRQHandler
#define CAN1_TX_IRQHandler USB_HP_CAN1_TX_IRQHandler
#define CAN1_RX0_IRQHandler USB_LP_CAN1_RX0_IRQHandler
#define USB_LP_IRQHandler USB_LP_CAN1_RX0_IRQHandler
/**
@ -10234,5 +10237,4 @@ typedef struct
#endif /* __STM32F103xB_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

75
Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h
Wyświetl plik

@ -8,21 +8,20 @@
* is using in the C source code, usually in main.c. This file contains:
* - Configuration section that allows to select:
* - The STM32F1xx device used in the target application
* - To use or not the peripheral’s drivers in application code(i.e.
* code will be based on direct access to peripheral’s registers
* - To use or not the peripheral's drivers in application code(i.e.
* code will be based on direct access to peripheral's registers
* rather than drivers API), this option is controlled by
* "#define USE_HAL_DRIVER"
*
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
* Copyright (c) 2017-2021 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@ -90,11 +89,11 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V4.3.1
* @brief CMSIS Device version number
*/
#define __STM32F1_CMSIS_VERSION_MAIN (0x04) /*!< [31:24] main version */
#define __STM32F1_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32F1_CMSIS_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
#define __STM32F1_CMSIS_VERSION_SUB2 (0x04) /*!< [15:8] sub2 version */
#define __STM32F1_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F1_CMSIS_VERSION ((__STM32F1_CMSIS_VERSION_MAIN << 24)\
|(__STM32F1_CMSIS_VERSION_SUB1 << 16)\
@ -191,6 +190,61 @@ typedef enum
#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
/* Use of CMSIS compiler intrinsics for register exclusive access */
/* Atomic 32-bit register access macro to set one or several bits */
#define ATOMIC_SET_BIT(REG, BIT) \
do { \
uint32_t val; \
do { \
val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT); \
} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
} while(0)
/* Atomic 32-bit register access macro to clear one or several bits */
#define ATOMIC_CLEAR_BIT(REG, BIT) \
do { \
uint32_t val; \
do { \
val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT); \
} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
} while(0)
/* Atomic 32-bit register access macro to clear and set one or several bits */
#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \
do { \
uint32_t val; \
do { \
val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
} while(0)
/* Atomic 16-bit register access macro to set one or several bits */
#define ATOMIC_SETH_BIT(REG, BIT) \
do { \
uint16_t val; \
do { \
val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT); \
} while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
} while(0)
/* Atomic 16-bit register access macro to clear one or several bits */
#define ATOMIC_CLEARH_BIT(REG, BIT) \
do { \
uint16_t val; \
do { \
val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT); \
} while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
} while(0)
/* Atomic 16-bit register access macro to clear and set one or several bits */
#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) \
do { \
uint16_t val; \
do { \
val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
} while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
} while(0)
/**
* @}
@ -217,4 +271,3 @@ typedef enum
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

16
Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h
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@ -1,18 +1,17 @@
/**
******************************************************************************
* @file system_stm32f10x.h
* @file system_stm32f1xx.h
* @author MCD Application Team
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
* Copyright (c) 2017-2021 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@ -94,5 +93,4 @@ extern void SystemCoreClockUpdate(void);
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
*/

6
Drivers/CMSIS/Device/ST/STM32F1xx/LICENSE.txt 100644
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@ -0,0 +1,6 @@
This software component is provided to you as part of a software package and
applicable license terms are in the Package_license file. If you received this
software component outside of a package or without applicable license terms,
the terms of the Apache-2.0 license shall apply.
You may obtain a copy of the Apache-2.0 at:
https://opensource.org/licenses/Apache-2.0

201
Drivers/CMSIS/LICENSE.txt 100644
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@ -0,0 +1,201 @@
Apache License
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http://www.apache.org/licenses/
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limitations under the License.

929
Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
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Plik diff jest za duży Load Diff

14
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h
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@ -7,13 +7,12 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@ -57,6 +56,7 @@ typedef enum
* @}
*/
/* Exported types ------------------------------------------------------------*/
extern __IO uint32_t uwTick;
extern uint32_t uwTickPrio;
extern HAL_TickFreqTypeDef uwTickFreq;
@ -354,4 +354,4 @@ void HAL_DBGMCU_DisableDBGStandbyMode(void);
#endif /* __STM32F1xx_HAL_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

12
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h
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@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
* This software is licensed under terms that can be found in the LICENSE file in
* the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@ -407,4 +406,3 @@ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
#endif /* __STM32F1xx_HAL_CORTEX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

49
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h
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@ -7,13 +7,12 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@ -28,9 +27,7 @@ extern "C" {
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx.h"
#if defined(USE_HAL_LEGACY)
#include "Legacy/stm32_hal_legacy.h"
#endif
#include <stddef.h>
/* Exported types ------------------------------------------------------------*/
@ -67,7 +64,9 @@ typedef enum
(__DMA_HANDLE__).Parent = (__HANDLE__); \
} while(0U)
#if !defined(UNUSED)
#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */
#endif /* UNUSED */
/** @brief Reset the Handle's State field.
* @param __HANDLE__ specifies the Peripheral Handle.
@ -108,7 +107,14 @@ typedef enum
}while (0U)
#endif /* USE_RTOS */
#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
#ifndef __weak
#define __weak __attribute__((weak))
#endif
#ifndef __packed
#define __packed __attribute__((packed))
#endif
#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
#ifndef __weak
#define __weak __attribute__((weak))
#endif /* __weak */
@ -119,7 +125,14 @@ typedef enum
/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
#ifndef __ALIGN_BEGIN
#define __ALIGN_BEGIN
#endif
#ifndef __ALIGN_END
#define __ALIGN_END __attribute__ ((aligned (4)))
#endif
#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
#ifndef __ALIGN_END
#define __ALIGN_END __attribute__ ((aligned (4)))
#endif /* __ALIGN_END */
@ -131,7 +144,7 @@ typedef enum
#define __ALIGN_END
#endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN
#if defined (__CC_ARM) /* ARM Compiler */
#if defined (__CC_ARM) /* ARM Compiler V5*/
#define __ALIGN_BEGIN __align(4)
#elif defined (__ICCARM__) /* IAR Compiler */
#define __ALIGN_BEGIN
@ -143,9 +156,9 @@ typedef enum
/**
* @brief __RAM_FUNC definition
*/
#if defined ( __CC_ARM )
/* ARM Compiler
------------
#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
/* ARM Compiler V4/V5 and V6
--------------------------
RAM functions are defined using the toolchain options.
Functions that are executed in RAM should reside in a separate source module.
Using the 'Options for File' dialog you can simply change the 'Code / Const'
@ -175,9 +188,9 @@ typedef enum
/**
* @brief __NOINLINE definition
*/
#if defined ( __CC_ARM ) || defined ( __GNUC__ )
/* ARM & GNUCompiler
----------------
#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ )
/* ARM V4/V5 and V6 & GNU Compiler
-------------------------------
*/
#define __NOINLINE __attribute__ ( (noinline) )
@ -195,4 +208,4 @@ typedef enum
#endif /* ___STM32F1xx_HAL_DEF */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

36
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h
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@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
* This software is licensed under terms that can be found in the LICENSE file in
* the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@ -110,29 +109,29 @@ typedef enum
*/
typedef struct __DMA_HandleTypeDef
{
DMA_Channel_TypeDef *Instance; /*!< Register base address */
DMA_Channel_TypeDef *Instance; /*!< Register base address */
DMA_InitTypeDef Init; /*!< DMA communication parameters */
DMA_InitTypeDef Init; /*!< DMA communication parameters */
HAL_LockTypeDef Lock; /*!< DMA locking object */
HAL_LockTypeDef Lock; /*!< DMA locking object */
HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
__IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
void *Parent; /*!< Parent object state */
void *Parent; /*!< Parent object state */
void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */
void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */
__IO uint32_t ErrorCode; /*!< DMA Error code */
__IO uint32_t ErrorCode; /*!< DMA Error code */
DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */
DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */
uint32_t ChannelIndex; /*!< DMA Channel Index */
uint32_t ChannelIndex; /*!< DMA Channel Index */
} DMA_HandleTypeDef;
/**
@ -454,4 +453,3 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
#endif /* __STM32F1xx_HAL_DMA_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

12
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h
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@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
* This software is licensed under terms that can be found in the LICENSE file in
* the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@ -274,4 +273,3 @@
#endif /* __STM32F1xx_HAL_DMA_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

30
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h
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@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@ -217,19 +216,19 @@ typedef struct
/** @defgroup EXTI_Private_Macros EXTI Private Macros
* @{
*/
#define IS_EXTI_LINE(__LINE__) ((((__LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_PIN_MASK)) == 0x00u) && \
((((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \
(((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \
(((__LINE__) & EXTI_PIN_MASK) < EXTI_LINE_NB))
#define IS_EXTI_LINE(__EXTI_LINE__) ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_PIN_MASK)) == 0x00u) && \
((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \
(((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \
(((__EXTI_LINE__) & EXTI_PIN_MASK) < EXTI_LINE_NB))
#define IS_EXTI_MODE(__LINE__) ((((__LINE__) & EXTI_MODE_MASK) != 0x00u) && \
(((__LINE__) & ~EXTI_MODE_MASK) == 0x00u))
#define IS_EXTI_MODE(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00u) && \
(((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00u))
#define IS_EXTI_TRIGGER(__LINE__) (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u)
#define IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u)
#define IS_EXTI_PENDING_EDGE(__LINE__) ((__LINE__) == EXTI_TRIGGER_RISING_FALLING)
#define IS_EXTI_PENDING_EDGE(__EXTI_LINE__) ((__EXTI_LINE__) == EXTI_TRIGGER_RISING_FALLING)
#define IS_EXTI_CONFIG_LINE(__LINE__) (((__LINE__) & EXTI_CONFIG) != 0x00u)
#define IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00u)
#if defined (GPIOG)
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
@ -317,4 +316,3 @@ void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti);
#endif /* STM32F1xx_HAL_EXTI_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

13
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h
Wyświetl plik

@ -6,14 +6,12 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file in
* the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
@ -324,5 +322,4 @@ HAL_StatusTypeDef FLASH_WaitForLastOperationBank2(uint32_t Timeout);
#endif /* __STM32F1xx_HAL_FLASH_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

13
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h
Wyświetl plik

@ -6,14 +6,12 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file in
* the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
@ -783,4 +781,3 @@ uint32_t HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress);
#endif /* __STM32F1xx_HAL_FLASH_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

12
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h
Wyświetl plik

@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@ -305,4 +304,3 @@ void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
#endif /* STM32F1xx_HAL_GPIO_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

12
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h
Wyświetl plik

@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@ -891,4 +890,3 @@ void HAL_GPIOEx_DisableEventout(void);
#endif /* STM32F1xx_HAL_GPIO_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

417
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pcd.h
Wyświetl plik

@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@ -104,23 +103,24 @@ typedef struct __PCD_HandleTypeDef
typedef struct
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
PCD_TypeDef *Instance; /*!< Register base address */
PCD_InitTypeDef Init; /*!< PCD required parameters */
__IO uint8_t USB_Address; /*!< USB Address */
PCD_TypeDef *Instance; /*!< Register base address */
PCD_InitTypeDef Init; /*!< PCD required parameters */
__IO uint8_t USB_Address; /*!< USB Address */
#if defined (USB_OTG_FS)
PCD_EPTypeDef IN_ep[16]; /*!< IN endpoint parameters */
PCD_EPTypeDef OUT_ep[16]; /*!< OUT endpoint parameters */
PCD_EPTypeDef IN_ep[16]; /*!< IN endpoint parameters */
PCD_EPTypeDef OUT_ep[16]; /*!< OUT endpoint parameters */
#endif /* defined (USB_OTG_FS) */
#if defined (USB)
PCD_EPTypeDef IN_ep[8]; /*!< IN endpoint parameters */
PCD_EPTypeDef OUT_ep[8]; /*!< OUT endpoint parameters */
PCD_EPTypeDef IN_ep[8]; /*!< IN endpoint parameters */
PCD_EPTypeDef OUT_ep[8]; /*!< OUT endpoint parameters */
#endif /* defined (USB) */
HAL_LockTypeDef Lock; /*!< PCD peripheral status */
__IO PCD_StateTypeDef State; /*!< PCD communication state */
__IO uint32_t ErrorCode; /*!< PCD Error code */
uint32_t Setup[12]; /*!< Setup packet buffer */
PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */
HAL_LockTypeDef Lock; /*!< PCD peripheral status */
__IO PCD_StateTypeDef State; /*!< PCD communication state */
__IO uint32_t ErrorCode; /*!< PCD Error code */
uint32_t Setup[12]; /*!< Setup packet buffer */
PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */
uint32_t BESL;
uint32_t FrameNumber; /*!< Store Current Frame number */
void *pData; /*!< Pointer to upper stack Handler */
@ -191,24 +191,27 @@ typedef struct
/* Exported macros -----------------------------------------------------------*/
/** @defgroup PCD_Exported_Macros PCD Exported Macros
* @brief macros to handle interrupts and specific clock configurations
* @{
*/
#if defined (USB_OTG_FS)
* @brief macros to handle interrupts and specific clock configurations
* @{
*/
#define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
#define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) &= (__INTERRUPT__))
#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) \
((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
#if defined (USB_OTG_FS)
#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) &= (__INTERRUPT__))
#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) \
*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= ~(USB_OTG_PCGCCTL_STOPCLK)
#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= \
~(USB_OTG_PCGCCTL_STOPCLK)
#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) \
*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U)
#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) \
((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U)
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_OTG_FS_WAKEUP_EXTI_LINE
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)
@ -216,28 +219,26 @@ typedef struct
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = USB_OTG_FS_WAKEUP_EXTI_LINE
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE() \
do { \
EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE); \
EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE; \
} while(0U)
do { \
EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE); \
EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE; \
} while(0U)
#endif /* defined (USB_OTG_FS) */
#if defined (USB)
#define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
#define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR) &= ~(__INTERRUPT__))
#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR)\
&= (uint16_t)(~(__INTERRUPT__)))
#define __HAL_USB_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_WAKEUP_EXTI_LINE
#define __HAL_USB_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_WAKEUP_EXTI_LINE)
#define __HAL_USB_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_WAKEUP_EXTI_LINE)
#define __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = USB_WAKEUP_EXTI_LINE
#define __HAL_USB_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_WAKEUP_EXTI_LINE
#define __HAL_USB_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_WAKEUP_EXTI_LINE)
#define __HAL_USB_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_WAKEUP_EXTI_LINE)
#define __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = USB_WAKEUP_EXTI_LINE
#define __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE() \
do { \
EXTI->FTSR &= ~(USB_WAKEUP_EXTI_LINE); \
EXTI->RTSR |= USB_WAKEUP_EXTI_LINE; \
} while(0U)
#define __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE() \
do { \
EXTI->FTSR &= ~(USB_WAKEUP_EXTI_LINE); \
EXTI->RTSR |= USB_WAKEUP_EXTI_LINE; \
} while(0U)
#endif /* defined (USB) */
@ -272,7 +273,7 @@ typedef enum
HAL_PCD_SUSPEND_CB_ID = 0x04, /*!< USB PCD Suspend callback ID */
HAL_PCD_RESUME_CB_ID = 0x05, /*!< USB PCD Resume callback ID */
HAL_PCD_CONNECT_CB_ID = 0x06, /*!< USB PCD Connect callback ID */
HAL_PCD_DISCONNECT_CB_ID = 0x07, /*!< USB PCD Disconnect callback ID */
HAL_PCD_DISCONNECT_CB_ID = 0x07, /*!< USB PCD Disconnect callback ID */
HAL_PCD_MSPINIT_CB_ID = 0x08, /*!< USB PCD MspInit callback ID */
HAL_PCD_MSPDEINIT_CB_ID = 0x09 /*!< USB PCD MspDeInit callback ID */
@ -297,19 +298,29 @@ typedef void (*pPCD_IsoInIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t
* @}
*/
HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID,
pPCD_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID);
HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd,
pPCD_DataOutStageCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd,
pPCD_DataInStageCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd,
pPCD_IsoOutIncpltCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd,
pPCD_IsoInIncpltCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
@ -325,6 +336,7 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd)
HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);
void HAL_PCD_WKUP_IRQHandler(PCD_HandleTypeDef *hpcd);
void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);
void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
@ -353,12 +365,13 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint
HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef const *hpcd, uint8_t ep_addr);
/**
* @}
*/
@ -367,7 +380,7 @@ HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
/** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions
* @{
*/
PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd);
/**
* @}
*/
@ -384,15 +397,11 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @{
*/
#if defined (USB_OTG_FS)
#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE 0x08U
#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE 0x0CU
#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE 0x10U
#define USB_OTG_FS_WAKEUP_EXTI_LINE (0x1U << 18) /*!< USB FS EXTI Line WakeUp Interrupt */
#endif /* defined (USB_OTG_FS) */
#if defined (USB)
#define USB_WAKEUP_EXTI_LINE (0x1U << 18) /*!< USB FS EXTI Line WakeUp Interrupt */
#define USB_WAKEUP_EXTI_LINE (0x1U << 18) /*!< USB FS EXTI Line WakeUp Interrupt */
#endif /* defined (USB) */
/**
@ -402,10 +411,10 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
/** @defgroup PCD_EP0_MPS PCD EP0 MPS
* @{
*/
#define PCD_EP0MPS_64 DEP0CTL_MPS_64
#define PCD_EP0MPS_32 DEP0CTL_MPS_32
#define PCD_EP0MPS_16 DEP0CTL_MPS_16
#define PCD_EP0MPS_08 DEP0CTL_MPS_8
#define PCD_EP0MPS_64 EP_MPS_64
#define PCD_EP0MPS_32 EP_MPS_32
#define PCD_EP0MPS_16 EP_MPS_16
#define PCD_EP0MPS_08 EP_MPS_8
/**
* @}
*/
@ -441,46 +450,45 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
#if defined (USB_OTG_FS)
#ifndef USB_OTG_DOEPINT_OTEPSPR
#define USB_OTG_DOEPINT_OTEPSPR (0x1UL << 5) /*!< Status Phase Received interrupt */
#endif
#endif /* defined USB_OTG_DOEPINT_OTEPSPR */
#ifndef USB_OTG_DOEPMSK_OTEPSPRM
#define USB_OTG_DOEPMSK_OTEPSPRM (0x1UL << 5) /*!< Setup Packet Received interrupt mask */
#endif
#endif /* defined USB_OTG_DOEPMSK_OTEPSPRM */
#ifndef USB_OTG_DOEPINT_NAK
#define USB_OTG_DOEPINT_NAK (0x1UL << 13) /*!< NAK interrupt */
#endif
#endif /* defined USB_OTG_DOEPINT_NAK */
#ifndef USB_OTG_DOEPMSK_NAKM
#define USB_OTG_DOEPMSK_NAKM (0x1UL << 13) /*!< OUT Packet NAK interrupt mask */
#endif
#endif /* defined USB_OTG_DOEPMSK_NAKM */
#ifndef USB_OTG_DOEPINT_STPKTRX
#define USB_OTG_DOEPINT_STPKTRX (0x1UL << 15) /*!< Setup Packet Received interrupt */
#endif
#endif /* defined USB_OTG_DOEPINT_STPKTRX */
#ifndef USB_OTG_DOEPMSK_NYETM
#define USB_OTG_DOEPMSK_NYETM (0x1UL << 14) /*!< Setup Packet Received interrupt mask */
#endif
#endif /* defined USB_OTG_DOEPMSK_NYETM */
#endif /* defined (USB_OTG_FS) */
/* Private macros ------------------------------------------------------------*/
/** @defgroup PCD_Private_Macros PCD Private Macros
* @{
*/
* @{
*/
#if defined (USB)
/******************** Bit definition for USB_COUNTn_RX register *************/
#define USB_CNTRX_NBLK_MSK (0x1FU << 10)
#define USB_CNTRX_BLSIZE (0x1U << 15)
/* SetENDPOINT */
#define PCD_SET_ENDPOINT(USBx, bEpNum, wRegValue) (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)) = (uint16_t)(wRegValue))
#define PCD_SET_ENDPOINT(USBx, bEpNum, wRegValue) \
(*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)) = (uint16_t)(wRegValue))
/* GetENDPOINT */
#define PCD_GET_ENDPOINT(USBx, bEpNum) (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)))
#define PCD_GET_ENDPOINT(USBx, bEpNum) (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)))
/* ENDPOINT transfer */
#define USB_EP0StartXfer USB_EPStartXfer
/**
* @brief sets the type in the endpoint register(bits EP_TYPE[1:0])
@ -489,8 +497,10 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @param wType Endpoint Type.
* @retval None
*/
#define PCD_SET_EPTYPE(USBx, bEpNum, wType) (PCD_SET_ENDPOINT((USBx), (bEpNum), \
((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType) | USB_EP_CTR_TX | USB_EP_CTR_RX)))
#define PCD_SET_EPTYPE(USBx, bEpNum, wType) \
(PCD_SET_ENDPOINT((USBx), (bEpNum), \
((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType) | USB_EP_CTR_TX | USB_EP_CTR_RX)))
/**
* @brief gets the type in the endpoint register(bits EP_TYPE[1:0])
@ -507,18 +517,19 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @param bEpNum, bDir
* @retval None
*/
#define PCD_FreeUserBuffer(USBx, bEpNum, bDir) do { \
if ((bDir) == 0U) \
{ \
/* OUT double buffered endpoint */ \
PCD_TX_DTOG((USBx), (bEpNum)); \
} \
else if ((bDir) == 1U) \
{ \
/* IN double buffered endpoint */ \
PCD_RX_DTOG((USBx), (bEpNum)); \
} \
} while(0)
#define PCD_FREE_USER_BUFFER(USBx, bEpNum, bDir) \
do { \
if ((bDir) == 0U) \
{ \
/* OUT double buffered endpoint */ \
PCD_TX_DTOG((USBx), (bEpNum)); \
} \
else if ((bDir) == 1U) \
{ \
/* IN double buffered endpoint */ \
PCD_RX_DTOG((USBx), (bEpNum)); \
} \
} while(0)
/**
* @brief sets the status for tx transfer (bits STAT_TX[1:0]).
@ -527,21 +538,22 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @param wState new state
* @retval None
*/
#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) do { \
register uint16_t _wRegVal; \
\
#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) \
do { \
uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_DTOGMASK; \
/* toggle first bit ? */ \
if ((USB_EPTX_DTOG1 & (wState))!= 0U) \
{ \
/* toggle first bit ? */ \
if ((USB_EPTX_DTOG1 & (wState))!= 0U) \
{ \
_wRegVal ^= USB_EPTX_DTOG1; \
} \
/* toggle second bit ? */ \
if ((USB_EPTX_DTOG2 & (wState))!= 0U) \
{ \
} \
/* toggle second bit ? */ \
if ((USB_EPTX_DTOG2 & (wState))!= 0U) \
{ \
_wRegVal ^= USB_EPTX_DTOG2; \
} \
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
} \
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
} while(0) /* PCD_SET_EP_TX_STATUS */
/**
@ -551,19 +563,20 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @param wState new state
* @retval None
*/
#define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) do { \
register uint16_t _wRegVal; \
#define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) \
do { \
uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_DTOGMASK; \
/* toggle first bit ? */ \
if ((USB_EPRX_DTOG1 & (wState))!= 0U) \
{ \
_wRegVal ^= USB_EPRX_DTOG1; \
_wRegVal ^= USB_EPRX_DTOG1; \
} \
/* toggle second bit ? */ \
if ((USB_EPRX_DTOG2 & (wState))!= 0U) \
{ \
_wRegVal ^= USB_EPRX_DTOG2; \
_wRegVal ^= USB_EPRX_DTOG2; \
} \
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
} while(0) /* PCD_SET_EP_RX_STATUS */
@ -576,8 +589,9 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @param wStatetx new state.
* @retval None
*/
#define PCD_SET_EP_TXRX_STATUS(USBx, bEpNum, wStaterx, wStatetx) do { \
register uint16_t _wRegVal; \
#define PCD_SET_EP_TXRX_STATUS(USBx, bEpNum, wStaterx, wStatetx) \
do { \
uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (USB_EPRX_DTOGMASK | USB_EPTX_STAT); \
/* toggle first bit ? */ \
@ -629,10 +643,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @param bEpNum Endpoint Number.
* @retval TRUE = endpoint in stall condition.
*/
#define PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_TX_STATUS((USBx), (bEpNum)) \
== USB_EP_TX_STALL)
#define PCD_GET_EP_RX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_RX_STATUS((USBx), (bEpNum)) \
== USB_EP_RX_STALL)
#define PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_TX_STATUS((USBx), (bEpNum)) == USB_EP_TX_STALL)
#define PCD_GET_EP_RX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_RX_STATUS((USBx), (bEpNum)) == USB_EP_RX_STALL)
/**
* @brief set & clear EP_KIND bit.
@ -640,16 +652,18 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @param bEpNum Endpoint Number.
* @retval None
*/
#define PCD_SET_EP_KIND(USBx, bEpNum) do { \
register uint16_t _wRegVal; \
#define PCD_SET_EP_KIND(USBx, bEpNum) \
do { \
uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \
\
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_KIND)); \
} while(0) /* PCD_SET_EP_KIND */
#define PCD_CLEAR_EP_KIND(USBx, bEpNum) do { \
register uint16_t _wRegVal; \
#define PCD_CLEAR_EP_KIND(USBx, bEpNum) \
do { \
uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPKIND_MASK; \
\
@ -671,8 +685,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @param bEpNum Endpoint Number.
* @retval None
*/
#define PCD_SET_EP_DBUF(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum))
#define PCD_CLEAR_EP_DBUF(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum))
#define PCD_SET_BULK_EP_DBUF(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum))
#define PCD_CLEAR_BULK_EP_DBUF(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum))
/**
* @brief Clears bit CTR_RX / CTR_TX in the endpoint register.
@ -680,16 +694,18 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @param bEpNum Endpoint Number.
* @retval None
*/
#define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) do { \
register uint16_t _wRegVal; \
#define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) \
do { \
uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0x7FFFU & USB_EPREG_MASK); \
\
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_TX)); \
} while(0) /* PCD_CLEAR_RX_EP_CTR */
#define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) do { \
register uint16_t _wRegVal; \
#define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) \
do { \
uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0xFF7FU & USB_EPREG_MASK); \
\
@ -702,16 +718,18 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @param bEpNum Endpoint Number.
* @retval None
*/
#define PCD_RX_DTOG(USBx, bEpNum) do { \
register uint16_t _wEPVal; \
#define PCD_RX_DTOG(USBx, bEpNum) \
do { \
uint16_t _wEPVal; \
\
_wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \
\
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wEPVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_DTOG_RX)); \
} while(0) /* PCD_RX_DTOG */
#define PCD_TX_DTOG(USBx, bEpNum) do { \
register uint16_t _wEPVal; \
#define PCD_TX_DTOG(USBx, bEpNum) \
do { \
uint16_t _wEPVal; \
\
_wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \
\
@ -723,8 +741,9 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @param bEpNum Endpoint Number.
* @retval None
*/
#define PCD_CLEAR_RX_DTOG(USBx, bEpNum) do { \
register uint16_t _wRegVal; \
#define PCD_CLEAR_RX_DTOG(USBx, bEpNum) \
do { \
uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \
\
@ -734,8 +753,9 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
} \
} while(0) /* PCD_CLEAR_RX_DTOG */
#define PCD_CLEAR_TX_DTOG(USBx, bEpNum) do { \
register uint16_t _wRegVal; \
#define PCD_CLEAR_TX_DTOG(USBx, bEpNum) \
do { \
uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \
\
@ -752,8 +772,9 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @param bAddr Address.
* @retval None
*/
#define PCD_SET_EP_ADDRESS(USBx, bEpNum, bAddr) do { \
register uint16_t _wRegVal; \
#define PCD_SET_EP_ADDRESS(USBx, bEpNum, bAddr) \
do { \
uint16_t _wRegVal; \
\
_wRegVal = (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK) | (bAddr); \
\
@ -768,8 +789,14 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
*/
#define PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD))
#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint16_t *)((((uint32_t)(USBx)->BTABLE + ((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U)))
#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint16_t *)((((uint32_t)(USBx)->BTABLE + ((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U)))
#define PCD_EP_TX_CNT(USBx, bEpNum) \
((uint16_t *)((((uint32_t)(USBx)->BTABLE + \
((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U)))
#define PCD_EP_RX_CNT(USBx, bEpNum) \
((uint16_t *)((((uint32_t)(USBx)->BTABLE + \
((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U)))
/**
* @brief sets address of the tx/rx buffer.
@ -778,23 +805,25 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @param wAddr address to be set (must be word aligned).
* @retval None
*/
#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum, wAddr) do { \
register __IO uint16_t *_wRegVal; \
register uint32_t _wRegBase = (uint32_t)USBx; \
\
_wRegBase += (uint32_t)(USBx)->BTABLE; \
_wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + (((uint32_t)(bEpNum) * 8U) * PMA_ACCESS)); \
*_wRegVal = ((wAddr) >> 1) << 1; \
} while(0) /* PCD_SET_EP_TX_ADDRESS */
#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum, wAddr) \
do { \
__IO uint16_t *_wRegVal; \
uint32_t _wRegBase = (uint32_t)USBx; \
\
_wRegBase += (uint32_t)(USBx)->BTABLE; \
_wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + (((uint32_t)(bEpNum) * 8U) * PMA_ACCESS)); \
*_wRegVal = ((wAddr) >> 1) << 1; \
} while(0) /* PCD_SET_EP_TX_ADDRESS */
#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum, wAddr) do { \
register __IO uint16_t *_wRegVal; \
register uint32_t _wRegBase = (uint32_t)USBx; \
\
_wRegBase += (uint32_t)(USBx)->BTABLE; \
_wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 4U) * PMA_ACCESS)); \
*_wRegVal = ((wAddr) >> 1) << 1; \
} while(0) /* PCD_SET_EP_RX_ADDRESS */
#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum, wAddr) \
do { \
__IO uint16_t *_wRegVal; \
uint32_t _wRegBase = (uint32_t)USBx; \
\
_wRegBase += (uint32_t)(USBx)->BTABLE; \
_wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 4U) * PMA_ACCESS)); \
*_wRegVal = ((wAddr) >> 1) << 1; \
} while(0) /* PCD_SET_EP_RX_ADDRESS */
/**
* @brief Gets address of the tx/rx buffer.
@ -812,45 +841,54 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @param wNBlocks no. of Blocks.
* @retval None
*/
#define PCD_CALC_BLK32(pdwReg, wCount, wNBlocks) do { \
#define PCD_CALC_BLK32(pdwReg, wCount, wNBlocks) \
do { \
(wNBlocks) = (wCount) >> 5; \
if (((wCount) & 0x1fU) == 0U) \
{ \
(wNBlocks)--; \
} \
*(pdwReg) = (uint16_t)(((wNBlocks) << 10) | USB_CNTRX_BLSIZE); \
*(pdwReg) |= (uint16_t)(((wNBlocks) << 10) | USB_CNTRX_BLSIZE); \
} while(0) /* PCD_CALC_BLK32 */
#define PCD_CALC_BLK2(pdwReg, wCount, wNBlocks) do { \
#define PCD_CALC_BLK2(pdwReg, wCount, wNBlocks) \
do { \
(wNBlocks) = (wCount) >> 1; \
if (((wCount) & 0x1U) != 0U) \
{ \
(wNBlocks)++; \
} \
*(pdwReg) = (uint16_t)((wNBlocks) << 10); \
*(pdwReg) |= (uint16_t)((wNBlocks) << 10); \
} while(0) /* PCD_CALC_BLK2 */
#define PCD_SET_EP_CNT_RX_REG(pdwReg, wCount) do { \
#define PCD_SET_EP_CNT_RX_REG(pdwReg, wCount) \
do { \
uint32_t wNBlocks; \
if ((wCount) == 0U) \
{ \
*(pdwReg) &= (uint16_t)~USB_CNTRX_NBLK_MSK; \
*(pdwReg) |= USB_CNTRX_BLSIZE; \
} \
else if((wCount) <= 62U) \
{ \
PCD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \
} \
else \
\
*(pdwReg) &= 0x3FFU; \
\
if ((wCount) > 62U) \
{ \
PCD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \
} \
else \
{ \
if ((wCount) == 0U) \
{ \
*(pdwReg) |= USB_CNTRX_BLSIZE; \
} \
else \
{ \
PCD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \
} \
} \
} while(0) /* PCD_SET_EP_CNT_RX_REG */
#define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum, wCount) do { \
register uint32_t _wRegBase = (uint32_t)(USBx); \
register __IO uint16_t *pdwReg; \
\
#define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum, wCount) \
do { \
uint32_t _wRegBase = (uint32_t)(USBx); \
__IO uint16_t *pdwReg; \
\
_wRegBase += (uint32_t)(USBx)->BTABLE; \
pdwReg = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \
PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount)); \
@ -863,23 +901,25 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @param wCount Counter value.
* @retval None
*/
#define PCD_SET_EP_TX_CNT(USBx, bEpNum, wCount) do { \
register uint32_t _wRegBase = (uint32_t)(USBx); \
register __IO uint16_t *_wRegVal; \
#define PCD_SET_EP_TX_CNT(USBx, bEpNum, wCount) \
do { \
uint32_t _wRegBase = (uint32_t)(USBx); \
__IO uint16_t *_wRegVal; \
\
_wRegBase += (uint32_t)(USBx)->BTABLE; \
_wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \
*_wRegVal = (uint16_t)(wCount); \
} while(0)
} while(0)
#define PCD_SET_EP_RX_CNT(USBx, bEpNum, wCount) do { \
register uint32_t _wRegBase = (uint32_t)(USBx); \
register __IO uint16_t *_wRegVal; \
#define PCD_SET_EP_RX_CNT(USBx, bEpNum, wCount) \
do { \
uint32_t _wRegBase = (uint32_t)(USBx); \
__IO uint16_t *_wRegVal; \
\
_wRegBase += (uint32_t)(USBx)->BTABLE; \
_wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \
PCD_SET_EP_CNT_RX_REG(_wRegVal, (wCount)); \
} while(0)
} while(0)
/**
* @brief gets counter of the tx buffer.
@ -897,10 +937,13 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @param wBuf0Addr buffer 0 address.
* @retval Counter value
*/
#define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum, wBuf0Addr) do { \
#define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum, wBuf0Addr) \
do { \
PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr)); \
} while(0) /* PCD_SET_EP_DBUF0_ADDR */
#define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum, wBuf1Addr) do { \
#define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum, wBuf1Addr) \
do { \
PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr)); \
} while(0) /* PCD_SET_EP_DBUF1_ADDR */
@ -912,7 +955,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @param wBuf1Addr = buffer 1 address.
* @retval None
*/
#define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum, wBuf0Addr, wBuf1Addr) do { \
#define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum, wBuf0Addr, wBuf1Addr) \
do { \
PCD_SET_EP_DBUF0_ADDR((USBx), (bEpNum), (wBuf0Addr)); \
PCD_SET_EP_DBUF1_ADDR((USBx), (bEpNum), (wBuf1Addr)); \
} while(0) /* PCD_SET_EP_DBUF_ADDR */
@ -935,7 +979,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @param wCount: Counter value
* @retval None
*/
#define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount) do { \
#define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount) \
do { \
if ((bDir) == 0U) \
/* OUT endpoint */ \
{ \
@ -951,8 +996,9 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
} \
} while(0) /* SetEPDblBuf0Count*/
#define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount) do { \
register uint32_t _wBase = (uint32_t)(USBx); \
#define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount) \
do { \
uint32_t _wBase = (uint32_t)(USBx); \
__IO uint16_t *_wEPRegVal; \
\
if ((bDir) == 0U) \
@ -972,10 +1018,11 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
} \
} while(0) /* SetEPDblBuf1Count */
#define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) do { \
#define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) \
do { \
PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)); \
PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)); \
} while(0) /* PCD_SET_EP_DBUF_CNT */
} while(0) /* PCD_SET_EP_DBUF_CNT */
/**
* @brief Gets buffer 0/1 rx/tx counter for double buffering.
@ -1006,5 +1053,3 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
#endif
#endif /* STM32F1xx_HAL_PCD_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

23
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pcd_ex.h
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@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@ -23,7 +22,7 @@
#ifdef __cplusplus
extern "C" {
#endif
#endif /* __cplusplus */
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal_def.h"
@ -53,10 +52,8 @@ HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size);
#endif /* defined (USB_OTG_FS) */
#if defined (USB)
HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd,
uint16_t ep_addr,
uint16_t ep_kind,
uint32_t pmaadress);
HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr,
uint16_t ep_kind, uint32_t pmaadress);
void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state);
#endif /* defined (USB) */
@ -82,9 +79,7 @@ void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);
#ifdef __cplusplus
}
#endif
#endif /* __cplusplus */
#endif /* STM32F1xx_HAL_PCD_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

13
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h
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@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@ -384,5 +383,3 @@ void HAL_PWR_PVDCallback(void);
#endif /* __STM32F1xx_HAL_PWR_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

15
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h
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@ -6,14 +6,12 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file in
* the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
@ -614,7 +612,7 @@ typedef struct
* @brief Force or release APB1 peripheral reset.
* @{
*/
#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU)
#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
@ -1374,5 +1372,4 @@ void HAL_RCC_CSSCallback(void);
#endif /* __STM32F1xx_HAL_RCC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

19
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h
Wyświetl plik

@ -6,14 +6,12 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file in
* the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
@ -330,11 +328,11 @@ typedef struct
*/
#define RCC_PERIPHCLK_RTC 0x00000001U
#define RCC_PERIPHCLK_ADC 0x00000002U
#if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\
|| defined(STM32F107xC)
#if defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE)\
|| defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
#define RCC_PERIPHCLK_I2S2 0x00000004U
#define RCC_PERIPHCLK_I2S3 0x00000008U
#endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
#endif /* STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
|| defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
|| defined(STM32F105xC) || defined(STM32F107xC)
@ -1904,5 +1902,4 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void);
#endif /* __STM32F1xx_HAL_RCC_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

448
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h
Wyświetl plik

@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@ -65,8 +64,10 @@ typedef struct
This means in PWM mode that (N+1) corresponds to:
- the number of PWM periods in edge-aligned mode
- the number of half PWM period in center-aligned mode
GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
GP timers: this parameter must be a number between Min_Data = 0x00 and
Max_Data = 0xFF.
Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
Max_Data = 0xFFFF. */
uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload.
This parameter can be a value of @ref TIM_AutoReloadPreload */
@ -167,7 +168,7 @@ typedef struct
This parameter can be a value of @ref TIM_Encoder_Mode */
uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
This parameter can be a value of @ref TIM_Input_Capture_Polarity */
This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
uint32_t IC1Selection; /*!< Specifies the input.
This parameter can be a value of @ref TIM_Input_Capture_Selection */
@ -179,7 +180,7 @@ typedef struct
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
This parameter can be a value of @ref TIM_Input_Capture_Polarity */
This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
uint32_t IC2Selection; /*!< Specifies the input.
This parameter can be a value of @ref TIM_Input_Capture_Selection */
@ -218,7 +219,8 @@ typedef struct
uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
This parameter can be a value of @ref TIM_ClearInput_Polarity */
uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
This parameter must be 0: When OCRef clear feature is used with ETR source, ETR prescaler must be off */
This parameter must be 0: When OCRef clear feature is used with ETR source,
ETR prescaler must be off */
uint32_t ClearInputFilter; /*!< TIM Clear Input filter
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
} TIM_ClearInputConfigTypeDef;
@ -264,22 +266,22 @@ typedef struct
*/
typedef struct
{
uint32_t OffStateRunMode; /*!< TIM off state in run mode
This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode
This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
uint32_t LockLevel; /*!< TIM Lock level
This parameter can be a value of @ref TIM_Lock_level */
uint32_t DeadTime; /*!< TIM dead Time
This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
uint32_t BreakState; /*!< TIM Break State
This parameter can be a value of @ref TIM_Break_Input_enable_disable */
uint32_t BreakPolarity; /*!< TIM Break input polarity
This parameter can be a value of @ref TIM_Break_Polarity */
uint32_t BreakFilter; /*!< Specifies the break input filter.
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state
This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
uint32_t OffStateRunMode; /*!< TIM off state in run mode, This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode, This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
uint32_t LockLevel; /*!< TIM Lock level, This parameter can be a value of @ref TIM_Lock_level */
uint32_t DeadTime; /*!< TIM dead Time, This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
uint32_t BreakState; /*!< TIM Break State, This parameter can be a value of @ref TIM_Break_Input_enable_disable */
uint32_t BreakPolarity; /*!< TIM Break input polarity, This parameter can be a value of @ref TIM_Break_Polarity */
uint32_t BreakFilter; /*!< Specifies the break input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state, This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
} TIM_BreakDeadTimeConfigTypeDef;
/**
@ -294,6 +296,26 @@ typedef enum
HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */
} HAL_TIM_StateTypeDef;
/**
* @brief TIM Channel States definition
*/
typedef enum
{
HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /*!< TIM Channel initial state */
HAL_TIM_CHANNEL_STATE_READY = 0x01U, /*!< TIM Channel ready for use */
HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, /*!< An internal process is ongoing on the TIM channel */
} HAL_TIM_ChannelStateTypeDef;
/**
* @brief DMA Burst States definition
*/
typedef enum
{
HAL_DMA_BURST_STATE_RESET = 0x00U, /*!< DMA Burst initial state */
HAL_DMA_BURST_STATE_READY = 0x01U, /*!< DMA Burst ready for use */
HAL_DMA_BURST_STATE_BUSY = 0x02U, /*!< Ongoing DMA Burst */
} HAL_TIM_DMABurstStateTypeDef;
/**
* @brief HAL Active channel structures definition
*/
@ -315,13 +337,16 @@ typedef struct __TIM_HandleTypeDef
typedef struct
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
{
TIM_TypeDef *Instance; /*!< Register base address */
TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
HAL_TIM_ActiveChannel Channel; /*!< Active channel */
DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
This array is accessed by a @ref DMA_Handle_index */
HAL_LockTypeDef Lock; /*!< Locking object */
__IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
TIM_TypeDef *Instance; /*!< Register base address */
TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
HAL_TIM_ActiveChannel Channel; /*!< Active channel */
DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
This array is accessed by a @ref DMA_Handle_index */
HAL_LockTypeDef Lock; /*!< Locking object */
__IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
__IO HAL_TIM_ChannelStateTypeDef ChannelState[4]; /*!< TIM channel operation state */
__IO HAL_TIM_ChannelStateTypeDef ChannelNState[4]; /*!< TIM complementary channel operation state */
__IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /*!< DMA burst operation state */
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */
@ -360,34 +385,34 @@ typedef struct
*/
typedef enum
{
HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */
,HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */
,HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */
,HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */
,HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */
,HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */
,HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */
,HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */
,HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */
,HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */
,HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */
,HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */
,HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */
,HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */
,HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */
,HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */
,HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */
,HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */
HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */
, HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */
, HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */
, HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */
, HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */
, HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */
, HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */
, HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */
, HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */
, HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */
, HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */
, HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */
, HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */
, HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */
, HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */
, HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */
, HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */
, HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */
,HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */
,HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */
,HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */
,HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */
,HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */
,HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */
,HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */
,HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */
,HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */
, HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */
, HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */
, HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */
, HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */
, HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */
, HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */
, HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */
, HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */
, HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */
} HAL_TIM_CallbackIDTypeDef;
/**
@ -593,13 +618,20 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
* @}
*/
/** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity
* @{
*/
#define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity */
#define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge polarity */
/**
* @}
*/
/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
* @{
*/
#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be
connected to IC1, IC2, IC3 or IC4, respectively */
#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be
connected to IC2, IC1, IC4 or IC3, respectively */
#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively */
#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively */
#define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
/**
* @}
@ -673,6 +705,15 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
* @}
*/
/** @defgroup TIM_CC_DMA_Request CCx DMA request selection
* @{
*/
#define TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when capture or compare match event occurs */
#define TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */
/**
* @}
*/
/** @defgroup TIM_Flag_definition TIM Flag Definition
* @{
*/
@ -707,16 +748,16 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
/** @defgroup TIM_Clock_Source TIM Clock Source
* @{
*/
#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */
#define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */
#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */
#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */
#define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */
#define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */
#define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */
#define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */
#define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */
#define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */
#define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */
#define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */
#define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */
#define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */
#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */
/**
* @}
*/
@ -814,8 +855,7 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
* @{
*/
#define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event
(if none of the break inputs BRK and BRK2 is active) */
#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) */
/**
* @}
*/
@ -922,24 +962,24 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
* @{
*/
#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
/**
* @}
*/
@ -984,25 +1024,45 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
* @retval None
*/
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
(__HANDLE__)->State = HAL_TIM_STATE_RESET; \
(__HANDLE__)->Base_MspInitCallback = NULL; \
(__HANDLE__)->Base_MspDeInitCallback = NULL; \
(__HANDLE__)->IC_MspInitCallback = NULL; \
(__HANDLE__)->IC_MspDeInitCallback = NULL; \
(__HANDLE__)->OC_MspInitCallback = NULL; \
(__HANDLE__)->OC_MspDeInitCallback = NULL; \
(__HANDLE__)->PWM_MspInitCallback = NULL; \
(__HANDLE__)->PWM_MspDeInitCallback = NULL; \
(__HANDLE__)->OnePulse_MspInitCallback = NULL; \
(__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \
(__HANDLE__)->Encoder_MspInitCallback = NULL; \
(__HANDLE__)->Encoder_MspDeInitCallback = NULL; \
(__HANDLE__)->HallSensor_MspInitCallback = NULL; \
(__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \
#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
(__HANDLE__)->State = HAL_TIM_STATE_RESET; \
(__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \
(__HANDLE__)->Base_MspInitCallback = NULL; \
(__HANDLE__)->Base_MspDeInitCallback = NULL; \
(__HANDLE__)->IC_MspInitCallback = NULL; \
(__HANDLE__)->IC_MspDeInitCallback = NULL; \
(__HANDLE__)->OC_MspInitCallback = NULL; \
(__HANDLE__)->OC_MspDeInitCallback = NULL; \
(__HANDLE__)->PWM_MspInitCallback = NULL; \
(__HANDLE__)->PWM_MspDeInitCallback = NULL; \
(__HANDLE__)->OnePulse_MspInitCallback = NULL; \
(__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \
(__HANDLE__)->Encoder_MspInitCallback = NULL; \
(__HANDLE__)->Encoder_MspDeInitCallback = NULL; \
(__HANDLE__)->HallSensor_MspInitCallback = NULL; \
(__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
(__HANDLE__)->State = HAL_TIM_STATE_RESET; \
(__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \
} while(0)
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
/**
@ -1039,7 +1099,8 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
* @brief Disable the TIM main Output.
* @param __HANDLE__ TIM handle
* @retval None
* @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled
* @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been
* disabled
*/
#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
do { \
@ -1200,8 +1261,8 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
* @brief Indicates whether or not the TIM Counter is used as downcounter.
* @param __HANDLE__ TIM handle.
* @retval False (Counter used as upcounter) or True (Counter used as downcounter)
* @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder
mode.
* @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode
* or Encoder mode.
*/
#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
@ -1275,7 +1336,8 @@ mode.
#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
/**
* @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.
* @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel()
* function.
* @param __HANDLE__ TIM handle.
* @param __CHANNEL__ TIM Channels to be configured.
* This parameter can be one of the following values:
@ -1473,6 +1535,17 @@ mode.
TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
}while(0)
/** @brief Select the Capture/compare DMA request source.
* @param __HANDLE__ specifies the TIM Handle.
* @param __CCDMA__ specifies Capture/compare DMA request source
* This parameter can be one of the following values:
* @arg TIM_CCDMAREQUEST_CC: CCx DMA request generated on Capture/Compare event
* @arg TIM_CCDMAREQUEST_UPDATE: CCx DMA request generated on Update event
* @retval None
*/
#define __HAL_TIM_SELECT_CCDMAREQUEST(__HANDLE__, __CCDMA__) \
MODIFY_REG((__HANDLE__)->Instance->CR2, TIM_CR2_CCDS, (__CCDMA__))
/**
* @}
*/
@ -1547,6 +1620,9 @@ mode.
#define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \
((__STATE__) == TIM_OCNIDLESTATE_RESET))
#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \
((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING))
#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \
((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \
((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
@ -1578,20 +1654,22 @@ mode.
#define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
((__CHANNEL__) == TIM_CHANNEL_2))
#define IS_TIM_PERIOD(__PERIOD__) (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0xFFFFU))
#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
((__CHANNEL__) == TIM_CHANNEL_2) || \
((__CHANNEL__) == TIM_CHANNEL_3))
#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))
((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR3))
#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \
((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
@ -1667,13 +1745,13 @@ mode.
((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \
((__MODE__) == TIM_OCMODE_FORCED_INACTIVE))
#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
((__SELECTION__) == TIM_TS_ITR1) || \
((__SELECTION__) == TIM_TS_ITR2) || \
((__SELECTION__) == TIM_TS_ITR3) || \
#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
((__SELECTION__) == TIM_TS_ITR1) || \
((__SELECTION__) == TIM_TS_ITR2) || \
((__SELECTION__) == TIM_TS_ITR3) || \
((__SELECTION__) == TIM_TS_TI1F_ED) || \
((__SELECTION__) == TIM_TS_TI1FP1) || \
((__SELECTION__) == TIM_TS_TI2FP2) || \
((__SELECTION__) == TIM_TS_TI1FP1) || \
((__SELECTION__) == TIM_TS_TI2FP2) || \
((__SELECTION__) == TIM_TS_ETRF))
#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
@ -1698,15 +1776,15 @@ mode.
#define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
@ -1717,6 +1795,8 @@ mode.
((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))
#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))
#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
#define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU)
@ -1742,11 +1822,53 @@ mode.
((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP))) :\
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P)) :\
((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P)))
#define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\
(((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\
((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\
((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\
(__HANDLE__)->ChannelState[3])
#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\
((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)))
#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \
(__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \
(__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \
(__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \
(__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \
} while(0)
#define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\
(((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\
((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\
((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\
(__HANDLE__)->ChannelNState[3])
#define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\
((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__)))
#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \
(__HANDLE__)->ChannelNState[0] = \
(__CHANNEL_STATE__); \
(__HANDLE__)->ChannelNState[1] = \
(__CHANNEL_STATE__); \
(__HANDLE__)->ChannelNState[2] = \
(__CHANNEL_STATE__); \
(__HANDLE__)->ChannelNState[3] = \
(__CHANNEL_STATE__); \
} while(0)
/**
* @}
*/
@ -1776,7 +1898,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length);
HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
/**
* @}
@ -1798,7 +1920,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
uint16_t Length);
HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
/**
* @}
@ -1820,7 +1943,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
uint16_t Length);
HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
/**
* @}
@ -1872,7 +1996,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out
* @{
*/
/* Timer Encoder functions ****************************************************/
HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig);
HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig);
HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
@ -1905,25 +2029,35 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
* @{
*/
/* Control functions *********************************************************/
HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig,
uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig,
uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig,
uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
uint32_t OutputChannel, uint32_t InputChannel);
HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig,
HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
const TIM_ClearInputConfigTypeDef *sClearInputConfig,
uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig);
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig);
HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig);
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig);
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
uint32_t BurstLength, uint32_t DataLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
uint32_t BurstLength, uint32_t DataLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel);
/**
* @}
*/
@ -1960,12 +2094,17 @@ HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Ca
* @{
*/
/* Peripheral State functions ************************************************/
HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim);
HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim);
HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim);
HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim);
HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim);
HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim);
/* Peripheral Channel state functions ************************************************/
HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim);
HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim);
/**
* @}
*/
@ -1979,13 +2118,12 @@ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
/** @defgroup TIM_Private_Functions TIM Private Functions
* @{
*/
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure);
void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);
void TIM_DMAError(DMA_HandleTypeDef *hdma);
void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
@ -2014,5 +2152,3 @@ void TIM_ResetCallback(TIM_HandleTypeDef *htim);
#endif
#endif /* STM32F1xx_HAL_TIM_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

30
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h
Wyświetl plik

@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@ -111,7 +110,7 @@ typedef struct
* @{
*/
/* Timer Hall Sensor functions **********************************************/
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig);
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig);
HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
@ -144,7 +143,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
uint16_t Length);
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
/**
* @}
@ -163,7 +163,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
uint16_t Length);
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
/**
* @}
@ -197,9 +198,9 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
uint32_t CommutationSource);
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
TIM_MasterConfigTypeDef *sMasterConfig);
const TIM_MasterConfigTypeDef *sMasterConfig);
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
/**
* @}
@ -222,7 +223,8 @@ void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
* @{
*/
/* Extended Peripheral State functions ***************************************/
HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim);
HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim, uint32_t ChannelN);
/**
* @}
*/
@ -233,7 +235,7 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
/* End of exported functions -------------------------------------------------*/
/* Private functions----------------------------------------------------------*/
/** @addtogroup TIMEx_Private_Functions TIMEx Private Functions
/** @addtogroup TIMEx_Private_Functions TIM Extended Private Functions
* @{
*/
void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
@ -257,5 +259,3 @@ void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma);
#endif /* STM32F1xx_HAL_TIM_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h 100644
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Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_cortex.h 100644
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/**
******************************************************************************
* @file stm32f1xx_ll_cortex.h
* @author MCD Application Team
* @brief Header file of CORTEX LL module.
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The LL CORTEX driver contains a set of generic APIs that can be
used by user:
(+) SYSTICK configuration used by LL_mDelay and LL_Init1msTick
functions
(+) Low power mode configuration (SCB register of Cortex-MCU)
(+) MPU API to configure and enable regions
(MPU services provided only on some devices)
(+) API to access to MCU info (CPUID register)
(+) API to enable fault handler (SHCSR accesses)
@endverbatim
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file in
* the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_LL_CORTEX_H
#define __STM32F1xx_LL_CORTEX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx.h"
/** @addtogroup STM32F1xx_LL_Driver
* @{
*/
/** @defgroup CORTEX_LL CORTEX
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
* @{
*/
/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
* @{
*/
#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/
#define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
* @{
*/
#define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */
#define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */
#define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */
/**
* @}
*/
#if __MPU_PRESENT
/** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
* @{
*/
#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U /*!< Disable NMI and privileged SW access */
#define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
#define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */
#define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_REGION MPU Region Number
* @{
*/
#define LL_MPU_REGION_NUMBER0 0x00U /*!< REGION Number 0 */
#define LL_MPU_REGION_NUMBER1 0x01U /*!< REGION Number 1 */
#define LL_MPU_REGION_NUMBER2 0x02U /*!< REGION Number 2 */
#define LL_MPU_REGION_NUMBER3 0x03U /*!< REGION Number 3 */
#define LL_MPU_REGION_NUMBER4 0x04U /*!< REGION Number 4 */
#define LL_MPU_REGION_NUMBER5 0x05U /*!< REGION Number 5 */
#define LL_MPU_REGION_NUMBER6 0x06U /*!< REGION Number 6 */
#define LL_MPU_REGION_NUMBER7 0x07U /*!< REGION Number 7 */
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
* @{
*/
#define LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
* @{
*/
#define LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos) /*!< No access*/
#define LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/
#define LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */
#define LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */
#define LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/
#define LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
* @{
*/
#define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
#define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
#define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
#define LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
* @{
*/
#define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U /*!< Instruction fetches enabled */
#define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
* @{
*/
#define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */
#define LL_MPU_ACCESS_NOT_SHAREABLE 0x00U /*!< Not Shareable memory attribute */
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
* @{
*/
#define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */
#define LL_MPU_ACCESS_NOT_CACHEABLE 0x00U /*!< Not Cacheable memory attribute */
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
* @{
*/
#define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */
#define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U /*!< Not Bufferable memory attribute */
/**
* @}
*/
#endif /* __MPU_PRESENT */
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
* @{
*/
/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
* @{
*/
/**
* @brief This function checks if the Systick counter flag is active or not.
* @note It can be used in timeout function on application side.
* @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
{
return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk));
}
/**
* @brief Configures the SysTick clock source
* @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
* @param Source This parameter can be one of the following values:
* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
* @retval None
*/
__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
{
if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
{
SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
}
else
{
CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
}
}
/**
* @brief Get the SysTick clock source
* @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
* @retval Returned value can be one of the following values:
* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
*/
__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
{
return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
}
/**
* @brief Enable SysTick exception request
* @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
* @retval None
*/
__STATIC_INLINE void LL_SYSTICK_EnableIT(void)
{
SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
}
/**
* @brief Disable SysTick exception request
* @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
* @retval None
*/
__STATIC_INLINE void LL_SYSTICK_DisableIT(void)
{
CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
}
/**
* @brief Checks if the SYSTICK interrupt is enabled or disabled.
* @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
{
return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk));
}
/**
* @}
*/
/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
* @{
*/
/**
* @brief Processor uses sleep as its low power mode
* @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
* @retval None
*/
__STATIC_INLINE void LL_LPM_EnableSleep(void)
{
/* Clear SLEEPDEEP bit of Cortex System Control Register */
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
}
/**
* @brief Processor uses deep sleep as its low power mode
* @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
* @retval None
*/
__STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
{
/* Set SLEEPDEEP bit of Cortex System Control Register */
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
}
/**
* @brief Configures sleep-on-exit when returning from Handler mode to Thread mode.
* @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
* empty main application.
* @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
* @retval None
*/
__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
{
/* Set SLEEPONEXIT bit of Cortex System Control Register */
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
}
/**
* @brief Do not sleep when returning to Thread mode.
* @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
* @retval None
*/
__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
{
/* Clear SLEEPONEXIT bit of Cortex System Control Register */
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
}
/**
* @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the
* processor.
* @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
* @retval None
*/
__STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
{
/* Set SEVEONPEND bit of Cortex System Control Register */
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
}
/**
* @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are
* excluded
* @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
* @retval None
*/
__STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
{
/* Clear SEVEONPEND bit of Cortex System Control Register */
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
}
/**
* @}
*/
/** @defgroup CORTEX_LL_EF_HANDLER HANDLER
* @{
*/
/**
* @brief Enable a fault in System handler control register (SHCSR)
* @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault
* @param Fault This parameter can be a combination of the following values:
* @arg @ref LL_HANDLER_FAULT_USG
* @arg @ref LL_HANDLER_FAULT_BUS
* @arg @ref LL_HANDLER_FAULT_MEM
* @retval None
*/
__STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
{
/* Enable the system handler fault */
SET_BIT(SCB->SHCSR, Fault);
}
/**
* @brief Disable a fault in System handler control register (SHCSR)
* @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault
* @param Fault This parameter can be a combination of the following values:
* @arg @ref LL_HANDLER_FAULT_USG
* @arg @ref LL_HANDLER_FAULT_BUS
* @arg @ref LL_HANDLER_FAULT_MEM
* @retval None
*/
__STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
{
/* Disable the system handler fault */
CLEAR_BIT(SCB->SHCSR, Fault);
}
/**
* @}
*/
/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
* @{
*/
/**
* @brief Get Implementer code
* @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
* @retval Value should be equal to 0x41 for ARM
*/
__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
{
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
}
/**
* @brief Get Variant number (The r value in the rnpn product revision identifier)
* @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
* @retval Value between 0 and 255 (0x1: revision 1, 0x2: revision 2)
*/
__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
{
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
}
/**
* @brief Get Constant number
* @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant
* @retval Value should be equal to 0xF for Cortex-M3 devices
*/
__STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)
{
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
}
/**
* @brief Get Part number
* @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
* @retval Value should be equal to 0xC23 for Cortex-M3
*/
__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
{
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
}
/**
* @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
* @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
* @retval Value between 0 and 255 (0x0: patch 0, 0x1: patch 1)
*/
__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
{
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
}
/**
* @}
*/
#if __MPU_PRESENT
/** @defgroup CORTEX_LL_EF_MPU MPU
* @{
*/
/**
* @brief Enable MPU with input options
* @rmtoll MPU_CTRL ENABLE LL_MPU_Enable
* @param Options This parameter can be one of the following values:
* @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
* @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
* @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
* @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
* @retval None
*/
__STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
{
/* Enable the MPU*/
WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
/* Ensure MPU settings take effects */
__DSB();
/* Sequence instruction fetches using update settings */
__ISB();
}
/**
* @brief Disable MPU
* @rmtoll MPU_CTRL ENABLE LL_MPU_Disable
* @retval None
*/
__STATIC_INLINE void LL_MPU_Disable(void)
{
/* Make sure outstanding transfers are done */
__DMB();
/* Disable MPU*/
WRITE_REG(MPU->CTRL, 0U);
}
/**
* @brief Check if MPU is enabled or not
* @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
{
return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk));
}
/**
* @brief Enable a MPU region
* @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion
* @param Region This parameter can be one of the following values:
* @arg @ref LL_MPU_REGION_NUMBER0
* @arg @ref LL_MPU_REGION_NUMBER1
* @arg @ref LL_MPU_REGION_NUMBER2
* @arg @ref LL_MPU_REGION_NUMBER3
* @arg @ref LL_MPU_REGION_NUMBER4
* @arg @ref LL_MPU_REGION_NUMBER5
* @arg @ref LL_MPU_REGION_NUMBER6
* @arg @ref LL_MPU_REGION_NUMBER7
* @retval None
*/
__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
{
/* Set Region number */
WRITE_REG(MPU->RNR, Region);
/* Enable the MPU region */
SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
}
/**
* @brief Configure and enable a region
* @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n
* MPU_RBAR REGION LL_MPU_ConfigRegion\n
* MPU_RBAR ADDR LL_MPU_ConfigRegion\n
* MPU_RASR XN LL_MPU_ConfigRegion\n
* MPU_RASR AP LL_MPU_ConfigRegion\n
* MPU_RASR S LL_MPU_ConfigRegion\n
* MPU_RASR C LL_MPU_ConfigRegion\n
* MPU_RASR B LL_MPU_ConfigRegion\n
* MPU_RASR SIZE LL_MPU_ConfigRegion
* @param Region This parameter can be one of the following values:
* @arg @ref LL_MPU_REGION_NUMBER0
* @arg @ref LL_MPU_REGION_NUMBER1
* @arg @ref LL_MPU_REGION_NUMBER2
* @arg @ref LL_MPU_REGION_NUMBER3
* @arg @ref LL_MPU_REGION_NUMBER4
* @arg @ref LL_MPU_REGION_NUMBER5
* @arg @ref LL_MPU_REGION_NUMBER6
* @arg @ref LL_MPU_REGION_NUMBER7
* @param Address Value of region base address
* @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
* @param Attributes This parameter can be a combination of the following values:
* @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
* or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
* or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
* or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
* or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
* or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
* @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
* or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
* @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
* @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
* @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
* @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
* @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
* @retval None
*/
__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
{
/* Set Region number */
WRITE_REG(MPU->RNR, Region);
/* Set base address */
WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
/* Configure MPU */
WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos));
}
/**
* @brief Disable a region
* @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n
* MPU_RASR ENABLE LL_MPU_DisableRegion
* @param Region This parameter can be one of the following values:
* @arg @ref LL_MPU_REGION_NUMBER0
* @arg @ref LL_MPU_REGION_NUMBER1
* @arg @ref LL_MPU_REGION_NUMBER2
* @arg @ref LL_MPU_REGION_NUMBER3
* @arg @ref LL_MPU_REGION_NUMBER4
* @arg @ref LL_MPU_REGION_NUMBER5
* @arg @ref LL_MPU_REGION_NUMBER6
* @arg @ref LL_MPU_REGION_NUMBER7
* @retval None
*/
__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
{
/* Set Region number */
WRITE_REG(MPU->RNR, Region);
/* Disable the MPU region */
CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
}
/**
* @}
*/
#endif /* __MPU_PRESENT */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32F1xx_LL_CORTEX_H */

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Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_exti.h 100644
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/**
******************************************************************************
* @file stm32f1xx_ll_exti.h
* @author MCD Application Team
* @brief Header file of EXTI LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F1xx_LL_EXTI_H
#define STM32F1xx_LL_EXTI_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx.h"
/** @addtogroup STM32F1xx_LL_Driver
* @{
*/
#if defined (EXTI)
/** @defgroup EXTI_LL EXTI
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private Macros ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros
* @{
*/
/**
* @}
*/
#endif /*USE_FULL_LL_DRIVER*/
/* Exported types ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure
* @{
*/
typedef struct
{
uint32_t Line_0_31; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31
This parameter can be any combination of @ref EXTI_LL_EC_LINE */
FunctionalState LineCommand; /*!< Specifies the new state of the selected EXTI lines.
This parameter can be set either to ENABLE or DISABLE */
uint8_t Mode; /*!< Specifies the mode for the EXTI lines.
This parameter can be a value of @ref EXTI_LL_EC_MODE. */
uint8_t Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */
} LL_EXTI_InitTypeDef;
/**
* @}
*/
#endif /*USE_FULL_LL_DRIVER*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants
* @{
*/
/** @defgroup EXTI_LL_EC_LINE LINE
* @{
*/
#define LL_EXTI_LINE_0 EXTI_IMR_IM0 /*!< Extended line 0 */
#define LL_EXTI_LINE_1 EXTI_IMR_IM1 /*!< Extended line 1 */
#define LL_EXTI_LINE_2 EXTI_IMR_IM2 /*!< Extended line 2 */
#define LL_EXTI_LINE_3 EXTI_IMR_IM3 /*!< Extended line 3 */
#define LL_EXTI_LINE_4 EXTI_IMR_IM4 /*!< Extended line 4 */
#define LL_EXTI_LINE_5 EXTI_IMR_IM5 /*!< Extended line 5 */
#define LL_EXTI_LINE_6 EXTI_IMR_IM6 /*!< Extended line 6 */
#define LL_EXTI_LINE_7 EXTI_IMR_IM7 /*!< Extended line 7 */
#define LL_EXTI_LINE_8 EXTI_IMR_IM8 /*!< Extended line 8 */
#define LL_EXTI_LINE_9 EXTI_IMR_IM9 /*!< Extended line 9 */
#define LL_EXTI_LINE_10 EXTI_IMR_IM10 /*!< Extended line 10 */
#define LL_EXTI_LINE_11 EXTI_IMR_IM11 /*!< Extended line 11 */
#define LL_EXTI_LINE_12 EXTI_IMR_IM12 /*!< Extended line 12 */
#define LL_EXTI_LINE_13 EXTI_IMR_IM13 /*!< Extended line 13 */
#define LL_EXTI_LINE_14 EXTI_IMR_IM14 /*!< Extended line 14 */
#define LL_EXTI_LINE_15 EXTI_IMR_IM15 /*!< Extended line 15 */
#if defined(EXTI_IMR_IM16)
#define LL_EXTI_LINE_16 EXTI_IMR_IM16 /*!< Extended line 16 */
#endif
#define LL_EXTI_LINE_17 EXTI_IMR_IM17 /*!< Extended line 17 */
#if defined(EXTI_IMR_IM18)
#define LL_EXTI_LINE_18 EXTI_IMR_IM18 /*!< Extended line 18 */
#endif
#if defined(EXTI_IMR_IM19)
#define LL_EXTI_LINE_19 EXTI_IMR_IM19 /*!< Extended line 19 */
#endif
#if defined(EXTI_IMR_IM20)
#define LL_EXTI_LINE_20 EXTI_IMR_IM20 /*!< Extended line 20 */
#endif
#if defined(EXTI_IMR_IM21)
#define LL_EXTI_LINE_21 EXTI_IMR_IM21 /*!< Extended line 21 */
#endif
#if defined(EXTI_IMR_IM22)
#define LL_EXTI_LINE_22 EXTI_IMR_IM22 /*!< Extended line 22 */
#endif
#if defined(EXTI_IMR_IM23)
#define LL_EXTI_LINE_23 EXTI_IMR_IM23 /*!< Extended line 23 */
#endif
#if defined(EXTI_IMR_IM24)
#define LL_EXTI_LINE_24 EXTI_IMR_IM24 /*!< Extended line 24 */
#endif
#if defined(EXTI_IMR_IM25)
#define LL_EXTI_LINE_25 EXTI_IMR_IM25 /*!< Extended line 25 */
#endif
#if defined(EXTI_IMR_IM26)
#define LL_EXTI_LINE_26 EXTI_IMR_IM26 /*!< Extended line 26 */
#endif
#if defined(EXTI_IMR_IM27)
#define LL_EXTI_LINE_27 EXTI_IMR_IM27 /*!< Extended line 27 */
#endif
#if defined(EXTI_IMR_IM28)
#define LL_EXTI_LINE_28 EXTI_IMR_IM28 /*!< Extended line 28 */
#endif
#if defined(EXTI_IMR_IM29)
#define LL_EXTI_LINE_29 EXTI_IMR_IM29 /*!< Extended line 29 */
#endif
#if defined(EXTI_IMR_IM30)
#define LL_EXTI_LINE_30 EXTI_IMR_IM30 /*!< Extended line 30 */
#endif
#if defined(EXTI_IMR_IM31)
#define LL_EXTI_LINE_31 EXTI_IMR_IM31 /*!< Extended line 31 */
#endif
#define LL_EXTI_LINE_ALL_0_31 EXTI_IMR_IM /*!< All Extended line not reserved*/
#define LL_EXTI_LINE_ALL (0xFFFFFFFFU) /*!< All Extended line */
#if defined(USE_FULL_LL_DRIVER)
#define LL_EXTI_LINE_NONE (0x00000000U) /*!< None Extended line */
#endif /*USE_FULL_LL_DRIVER*/
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup EXTI_LL_EC_MODE Mode
* @{
*/
#define LL_EXTI_MODE_IT ((uint8_t)0x00) /*!< Interrupt Mode */
#define LL_EXTI_MODE_EVENT ((uint8_t)0x01) /*!< Event Mode */
#define LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02) /*!< Interrupt & Event Mode */
/**
* @}
*/
/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger
* @{
*/
#define LL_EXTI_TRIGGER_NONE ((uint8_t)0x00) /*!< No Trigger Mode */
#define LL_EXTI_TRIGGER_RISING ((uint8_t)0x01) /*!< Trigger Rising Mode */
#define LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02) /*!< Trigger Falling Mode */
#define LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03) /*!< Trigger Rising & Falling Mode */
/**
* @}
*/
#endif /*USE_FULL_LL_DRIVER*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros
* @{
*/
/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros
* @{
*/
/**
* @brief Write a value in EXTI register
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__))
/**
* @brief Read a value in EXTI register
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions
* @{
*/
/** @defgroup EXTI_LL_EF_IT_Management IT_Management
* @{
*/
/**
* @brief Enable ExtiLine Interrupt request for Lines in range 0 to 31
* @note The reset value for the direct or internal lines (see RM)
* is set to 1 in order to enable the interrupt by default.
* Bits are set automatically at Power on.
* @rmtoll IMR IMx LL_EXTI_EnableIT_0_31
* @param ExtiLine This parameter can be one of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @arg @ref LL_EXTI_LINE_ALL_0_31
* @note Please check each device line mapping for EXTI Line availability
* @retval None
*/
__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine)
{
SET_BIT(EXTI->IMR, ExtiLine);
}
/**
* @brief Disable ExtiLine Interrupt request for Lines in range 0 to 31
* @note The reset value for the direct or internal lines (see RM)
* is set to 1 in order to enable the interrupt by default.
* Bits are set automatically at Power on.
* @rmtoll IMR IMx LL_EXTI_DisableIT_0_31
* @param ExtiLine This parameter can be one of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @arg @ref LL_EXTI_LINE_ALL_0_31
* @note Please check each device line mapping for EXTI Line availability
* @retval None
*/
__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine)
{
CLEAR_BIT(EXTI->IMR, ExtiLine);
}
/**
* @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31
* @note The reset value for the direct or internal lines (see RM)
* is set to 1 in order to enable the interrupt by default.
* Bits are set automatically at Power on.
* @rmtoll IMR IMx LL_EXTI_IsEnabledIT_0_31
* @param ExtiLine This parameter can be one of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @arg @ref LL_EXTI_LINE_ALL_0_31
* @note Please check each device line mapping for EXTI Line availability
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine)
{
return (READ_BIT(EXTI->IMR, ExtiLine) == (ExtiLine));
}
/**
* @}
*/
/** @defgroup EXTI_LL_EF_Event_Management Event_Management
* @{
*/
/**
* @brief Enable ExtiLine Event request for Lines in range 0 to 31
* @rmtoll EMR EMx LL_EXTI_EnableEvent_0_31
* @param ExtiLine This parameter can be one of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @arg @ref LL_EXTI_LINE_ALL_0_31
* @note Please check each device line mapping for EXTI Line availability
* @retval None
*/
__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine)
{
SET_BIT(EXTI->EMR, ExtiLine);
}
/**
* @brief Disable ExtiLine Event request for Lines in range 0 to 31
* @rmtoll EMR EMx LL_EXTI_DisableEvent_0_31
* @param ExtiLine This parameter can be one of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @arg @ref LL_EXTI_LINE_ALL_0_31
* @note Please check each device line mapping for EXTI Line availability
* @retval None
*/
__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine)
{
CLEAR_BIT(EXTI->EMR, ExtiLine);
}
/**
* @brief Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31
* @rmtoll EMR EMx LL_EXTI_IsEnabledEvent_0_31
* @param ExtiLine This parameter can be one of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @arg @ref LL_EXTI_LINE_ALL_0_31
* @note Please check each device line mapping for EXTI Line availability
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine)
{
return (READ_BIT(EXTI->EMR, ExtiLine) == (ExtiLine));
}
/**
* @}
*/
/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management
* @{
*/
/**
* @brief Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
* @note The configurable wakeup lines are edge-triggered. No glitch must be
* generated on these lines. If a rising edge on a configurable interrupt
* line occurs during a write operation in the EXTI_RTSR register, the
* pending bit is not set.
* Rising and falling edge triggers can be set for
* the same interrupt line. In this case, both generate a trigger
* condition.
* @rmtoll RTSR RTx LL_EXTI_EnableRisingTrig_0_31
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @note Please check each device line mapping for EXTI Line availability
* @retval None
*/
__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine)
{
SET_BIT(EXTI->RTSR, ExtiLine);
}
/**
* @brief Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
* @note The configurable wakeup lines are edge-triggered. No glitch must be
* generated on these lines. If a rising edge on a configurable interrupt
* line occurs during a write operation in the EXTI_RTSR register, the
* pending bit is not set.
* Rising and falling edge triggers can be set for
* the same interrupt line. In this case, both generate a trigger
* condition.
* @rmtoll RTSR RTx LL_EXTI_DisableRisingTrig_0_31
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @note Please check each device line mapping for EXTI Line availability
* @retval None
*/
__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine)
{
CLEAR_BIT(EXTI->RTSR, ExtiLine);
}
/**
* @brief Check if rising edge trigger is enabled for Lines in range 0 to 31
* @rmtoll RTSR RTx LL_EXTI_IsEnabledRisingTrig_0_31
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @note Please check each device line mapping for EXTI Line availability
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine)
{
return (READ_BIT(EXTI->RTSR, ExtiLine) == (ExtiLine));
}
/**
* @}
*/
/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management
* @{
*/
/**
* @brief Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
* @note The configurable wakeup lines are edge-triggered. No glitch must be
* generated on these lines. If a falling edge on a configurable interrupt
* line occurs during a write operation in the EXTI_FTSR register, the
* pending bit is not set.
* Rising and falling edge triggers can be set for
* the same interrupt line. In this case, both generate a trigger
* condition.
* @rmtoll FTSR FTx LL_EXTI_EnableFallingTrig_0_31
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @note Please check each device line mapping for EXTI Line availability
* @retval None
*/
__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine)
{
SET_BIT(EXTI->FTSR, ExtiLine);
}
/**
* @brief Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
* @note The configurable wakeup lines are edge-triggered. No glitch must be
* generated on these lines. If a Falling edge on a configurable interrupt
* line occurs during a write operation in the EXTI_FTSR register, the
* pending bit is not set.
* Rising and falling edge triggers can be set for the same interrupt line.
* In this case, both generate a trigger condition.
* @rmtoll FTSR FTx LL_EXTI_DisableFallingTrig_0_31
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @note Please check each device line mapping for EXTI Line availability
* @retval None
*/
__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine)
{
CLEAR_BIT(EXTI->FTSR, ExtiLine);
}
/**
* @brief Check if falling edge trigger is enabled for Lines in range 0 to 31
* @rmtoll FTSR FTx LL_EXTI_IsEnabledFallingTrig_0_31
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @note Please check each device line mapping for EXTI Line availability
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine)
{
return (READ_BIT(EXTI->FTSR, ExtiLine) == (ExtiLine));
}
/**
* @}
*/
/** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management
* @{
*/
/**
* @brief Generate a software Interrupt Event for Lines in range 0 to 31
* @note If the interrupt is enabled on this line in the EXTI_IMR, writing a 1 to
* this bit when it is at '0' sets the corresponding pending bit in EXTI_PR
* resulting in an interrupt request generation.
* This bit is cleared by clearing the corresponding bit in the EXTI_PR
* register (by writing a 1 into the bit)
* @rmtoll SWIER SWIx LL_EXTI_GenerateSWI_0_31
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @note Please check each device line mapping for EXTI Line availability
* @retval None
*/
__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine)
{
SET_BIT(EXTI->SWIER, ExtiLine);
}
/**
* @}
*/
/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management
* @{
*/
/**
* @brief Check if the ExtLine Flag is set or not for Lines in range 0 to 31
* @note This bit is set when the selected edge event arrives on the interrupt
* line. This bit is cleared by writing a 1 to the bit.
* @rmtoll PR PIFx LL_EXTI_IsActiveFlag_0_31
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @note Please check each device line mapping for EXTI Line availability
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine)
{
return (READ_BIT(EXTI->PR, ExtiLine) == (ExtiLine));
}
/**
* @brief Read ExtLine Combination Flag for Lines in range 0 to 31
* @note This bit is set when the selected edge event arrives on the interrupt
* line. This bit is cleared by writing a 1 to the bit.
* @rmtoll PR PIFx LL_EXTI_ReadFlag_0_31
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @note Please check each device line mapping for EXTI Line availability
* @retval @note This bit is set when the selected edge event arrives on the interrupt
*/
__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine)
{
return (uint32_t)(READ_BIT(EXTI->PR, ExtiLine));
}
/**
* @brief Clear ExtLine Flags for Lines in range 0 to 31
* @note This bit is set when the selected edge event arrives on the interrupt
* line. This bit is cleared by writing a 1 to the bit.
* @rmtoll PR PIFx LL_EXTI_ClearFlag_0_31
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @note Please check each device line mapping for EXTI Line availability
* @retval None
*/
__STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine)
{
WRITE_REG(EXTI->PR, ExtiLine);
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions
* @{
*/
uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct);
uint32_t LL_EXTI_DeInit(void);
void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
/**
* @}
*/
#endif /* EXTI */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32F1xx_LL_EXTI_H */

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Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h 100644
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Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_pwr.h 100644
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/**
******************************************************************************
* @file stm32f1xx_ll_pwr.h
* @author MCD Application Team
* @brief Header file of PWR LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_LL_PWR_H
#define __STM32F1xx_LL_PWR_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx.h"
/** @addtogroup STM32F1xx_LL_Driver
* @{
*/
#if defined(PWR)
/** @defgroup PWR_LL PWR
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
* @{
*/
/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
* @brief Flags defines which can be used with LL_PWR_WriteReg function
* @{
*/
#define LL_PWR_CR_CSBF PWR_CR_CSBF /*!< Clear standby flag */
#define LL_PWR_CR_CWUF PWR_CR_CWUF /*!< Clear wakeup flag */
/**
* @}
*/
/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
* @brief Flags defines which can be used with LL_PWR_ReadReg function
* @{
*/
#define LL_PWR_CSR_WUF PWR_CSR_WUF /*!< Wakeup flag */
#define LL_PWR_CSR_SBF PWR_CSR_SBF /*!< Standby flag */
#define LL_PWR_CSR_PVDO PWR_CSR_PVDO /*!< Power voltage detector output flag */
#define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP /*!< Enable WKUP pin 1 */
/**
* @}
*/
/** @defgroup PWR_LL_EC_MODE_PWR Mode Power
* @{
*/
#define LL_PWR_MODE_STOP_MAINREGU 0x00000000U /*!< Enter Stop mode when the CPU enters deepsleep */
#define LL_PWR_MODE_STOP_LPREGU (PWR_CR_LPDS) /*!< Enter Stop mode (with low power Regulator ON) when the CPU enters deepsleep */
#define LL_PWR_MODE_STANDBY (PWR_CR_PDDS) /*!< Enter Standby mode when the CPU enters deepsleep */
/**
* @}
*/
/** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode
* @{
*/
#define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /*!< Voltage Regulator in main mode during deepsleep mode */
#define LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS) /*!< Voltage Regulator in low-power mode during deepsleep mode */
/**
* @}
*/
/** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level
* @{
*/
#define LL_PWR_PVDLEVEL_0 (PWR_CR_PLS_LEV0) /*!< Voltage threshold detected by PVD 2.2 V */
#define LL_PWR_PVDLEVEL_1 (PWR_CR_PLS_LEV1) /*!< Voltage threshold detected by PVD 2.3 V */
#define LL_PWR_PVDLEVEL_2 (PWR_CR_PLS_LEV2) /*!< Voltage threshold detected by PVD 2.4 V */
#define LL_PWR_PVDLEVEL_3 (PWR_CR_PLS_LEV3) /*!< Voltage threshold detected by PVD 2.5 V */
#define LL_PWR_PVDLEVEL_4 (PWR_CR_PLS_LEV4) /*!< Voltage threshold detected by PVD 2.6 V */
#define LL_PWR_PVDLEVEL_5 (PWR_CR_PLS_LEV5) /*!< Voltage threshold detected by PVD 2.7 V */
#define LL_PWR_PVDLEVEL_6 (PWR_CR_PLS_LEV6) /*!< Voltage threshold detected by PVD 2.8 V */
#define LL_PWR_PVDLEVEL_7 (PWR_CR_PLS_LEV7) /*!< Voltage threshold detected by PVD 2.9 V */
/**
* @}
*/
/** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins
* @{
*/
#define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP) /*!< WKUP pin 1 : PA0 */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
* @{
*/
/** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros
* @{
*/
/**
* @brief Write a value in PWR register
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
/**
* @brief Read a value in PWR register
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
* @{
*/
/** @defgroup PWR_LL_EF_Configuration Configuration
* @{
*/
/**
* @brief Enable access to the backup domain
* @rmtoll CR DBP LL_PWR_EnableBkUpAccess
* @retval None
*/
__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
{
SET_BIT(PWR->CR, PWR_CR_DBP);
}
/**
* @brief Disable access to the backup domain
* @rmtoll CR DBP LL_PWR_DisableBkUpAccess
* @retval None
*/
__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
{
CLEAR_BIT(PWR->CR, PWR_CR_DBP);
}
/**
* @brief Check if the backup domain is enabled
* @rmtoll CR DBP LL_PWR_IsEnabledBkUpAccess
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
{
return (READ_BIT(PWR->CR, PWR_CR_DBP) == (PWR_CR_DBP));
}
/**
* @brief Set voltage Regulator mode during deep sleep mode
* @rmtoll CR LPDS LL_PWR_SetRegulModeDS
* @param RegulMode This parameter can be one of the following values:
* @arg @ref LL_PWR_REGU_DSMODE_MAIN
* @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
* @retval None
*/
__STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode)
{
MODIFY_REG(PWR->CR, PWR_CR_LPDS, RegulMode);
}
/**
* @brief Get voltage Regulator mode during deep sleep mode
* @rmtoll CR LPDS LL_PWR_GetRegulModeDS
* @retval Returned value can be one of the following values:
* @arg @ref LL_PWR_REGU_DSMODE_MAIN
* @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
*/
__STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void)
{
return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPDS));
}
/**
* @brief Set Power Down mode when CPU enters deepsleep
* @rmtoll CR PDDS LL_PWR_SetPowerMode\n
* @rmtoll CR LPDS LL_PWR_SetPowerMode
* @param PDMode This parameter can be one of the following values:
* @arg @ref LL_PWR_MODE_STOP_MAINREGU
* @arg @ref LL_PWR_MODE_STOP_LPREGU
* @arg @ref LL_PWR_MODE_STANDBY
* @retval None
*/
__STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode)
{
MODIFY_REG(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS), PDMode);
}
/**
* @brief Get Power Down mode when CPU enters deepsleep
* @rmtoll CR PDDS LL_PWR_GetPowerMode\n
* @rmtoll CR LPDS LL_PWR_GetPowerMode
* @retval Returned value can be one of the following values:
* @arg @ref LL_PWR_MODE_STOP_MAINREGU
* @arg @ref LL_PWR_MODE_STOP_LPREGU
* @arg @ref LL_PWR_MODE_STANDBY
*/
__STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
{
return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS)));
}
/**
* @brief Configure the voltage threshold detected by the Power Voltage Detector
* @rmtoll CR PLS LL_PWR_SetPVDLevel
* @param PVDLevel This parameter can be one of the following values:
* @arg @ref LL_PWR_PVDLEVEL_0
* @arg @ref LL_PWR_PVDLEVEL_1
* @arg @ref LL_PWR_PVDLEVEL_2
* @arg @ref LL_PWR_PVDLEVEL_3
* @arg @ref LL_PWR_PVDLEVEL_4
* @arg @ref LL_PWR_PVDLEVEL_5
* @arg @ref LL_PWR_PVDLEVEL_6
* @arg @ref LL_PWR_PVDLEVEL_7
* @retval None
*/
__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
{
MODIFY_REG(PWR->CR, PWR_CR_PLS, PVDLevel);
}
/**
* @brief Get the voltage threshold detection
* @rmtoll CR PLS LL_PWR_GetPVDLevel
* @retval Returned value can be one of the following values:
* @arg @ref LL_PWR_PVDLEVEL_0
* @arg @ref LL_PWR_PVDLEVEL_1
* @arg @ref LL_PWR_PVDLEVEL_2
* @arg @ref LL_PWR_PVDLEVEL_3
* @arg @ref LL_PWR_PVDLEVEL_4
* @arg @ref LL_PWR_PVDLEVEL_5
* @arg @ref LL_PWR_PVDLEVEL_6
* @arg @ref LL_PWR_PVDLEVEL_7
*/
__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
{
return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PLS));
}
/**
* @brief Enable Power Voltage Detector
* @rmtoll CR PVDE LL_PWR_EnablePVD
* @retval None
*/
__STATIC_INLINE void LL_PWR_EnablePVD(void)
{
SET_BIT(PWR->CR, PWR_CR_PVDE);
}
/**
* @brief Disable Power Voltage Detector
* @rmtoll CR PVDE LL_PWR_DisablePVD
* @retval None
*/
__STATIC_INLINE void LL_PWR_DisablePVD(void)
{
CLEAR_BIT(PWR->CR, PWR_CR_PVDE);
}
/**
* @brief Check if Power Voltage Detector is enabled
* @rmtoll CR PVDE LL_PWR_IsEnabledPVD
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
{
return (READ_BIT(PWR->CR, PWR_CR_PVDE) == (PWR_CR_PVDE));
}
/**
* @brief Enable the WakeUp PINx functionality
* @rmtoll CSR EWUP LL_PWR_EnableWakeUpPin
* @param WakeUpPin This parameter can be one of the following values:
* @arg @ref LL_PWR_WAKEUP_PIN1
* @retval None
*/
__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
{
SET_BIT(PWR->CSR, WakeUpPin);
}
/**
* @brief Disable the WakeUp PINx functionality
* @rmtoll CSR EWUP LL_PWR_DisableWakeUpPin
* @param WakeUpPin This parameter can be one of the following values:
* @arg @ref LL_PWR_WAKEUP_PIN1
* @retval None
*/
__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
{
CLEAR_BIT(PWR->CSR, WakeUpPin);
}
/**
* @brief Check if the WakeUp PINx functionality is enabled
* @rmtoll CSR EWUP LL_PWR_IsEnabledWakeUpPin
* @param WakeUpPin This parameter can be one of the following values:
* @arg @ref LL_PWR_WAKEUP_PIN1
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
{
return (READ_BIT(PWR->CSR, WakeUpPin) == (WakeUpPin));
}
/**
* @}
*/
/** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
* @{
*/
/**
* @brief Get Wake-up Flag
* @rmtoll CSR WUF LL_PWR_IsActiveFlag_WU
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU(void)
{
return (READ_BIT(PWR->CSR, PWR_CSR_WUF) == (PWR_CSR_WUF));
}
/**
* @brief Get Standby Flag
* @rmtoll CSR SBF LL_PWR_IsActiveFlag_SB
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
{
return (READ_BIT(PWR->CSR, PWR_CSR_SBF) == (PWR_CSR_SBF));
}
/**
* @brief Indicate whether VDD voltage is below the selected PVD threshold
* @rmtoll CSR PVDO LL_PWR_IsActiveFlag_PVDO
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
{
return (READ_BIT(PWR->CSR, PWR_CSR_PVDO) == (PWR_CSR_PVDO));
}
/**
* @brief Clear Standby Flag
* @rmtoll CR CSBF LL_PWR_ClearFlag_SB
* @retval None
*/
__STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
{
SET_BIT(PWR->CR, PWR_CR_CSBF);
}
/**
* @brief Clear Wake-up Flags
* @rmtoll CR CWUF LL_PWR_ClearFlag_WU
* @retval None
*/
__STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
{
SET_BIT(PWR->CR, PWR_CR_CWUF);
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup PWR_LL_EF_Init De-initialization function
* @{
*/
ErrorStatus LL_PWR_DeInit(void);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
/**
* @}
*/
#endif /* defined(PWR) */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32F1xx_LL_PWR_H */

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Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h 100644
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Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h 100644
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/**
******************************************************************************
* @file stm32f1xx_ll_system.h
* @author MCD Application Team
* @brief Header file of SYSTEM LL module.
*
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The LL SYSTEM driver contains a set of generic APIs that can be
used by user:
(+) Some of the FLASH features need to be handled in the SYSTEM file.
(+) Access to DBGCMU registers
(+) Access to SYSCFG registers
@endverbatim
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_LL_SYSTEM_H
#define __STM32F1xx_LL_SYSTEM_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx.h"
/** @addtogroup STM32F1xx_LL_Driver
* @{
*/
#if defined (FLASH) || defined (DBGMCU)
/** @defgroup SYSTEM_LL SYSTEM
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
* @{
*/
/** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
* @{
*/
#define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRACE pins not assigned (default state) */
#define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */
#define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */
#define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */
#define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */
/**
* @}
*/
/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
* @{
*/
#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_CR_DBG_TIM2_STOP /*!< TIM2 counter stopped when core is halted */
#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_CR_DBG_TIM3_STOP /*!< TIM3 counter stopped when core is halted */
#define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_CR_DBG_TIM4_STOP /*!< TIM4 counter stopped when core is halted */
#if defined(DBGMCU_CR_DBG_TIM5_STOP)
#define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_CR_DBG_TIM5_STOP /*!< TIM5 counter stopped when core is halted */
#endif /* DBGMCU_CR_DBG_TIM5_STOP */
#if defined(DBGMCU_CR_DBG_TIM6_STOP)
#define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_CR_DBG_TIM6_STOP /*!< TIM6 counter stopped when core is halted */
#endif /* DBGMCU_CR_DBG_TIM6_STOP */
#if defined(DBGMCU_CR_DBG_TIM7_STOP)
#define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_CR_DBG_TIM7_STOP /*!< TIM7 counter stopped when core is halted */
#endif /* DBGMCU_CR_DBG_TIM7_STOP */
#if defined(DBGMCU_CR_DBG_TIM12_STOP)
#define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_CR_DBG_TIM12_STOP /*!< TIM12 counter stopped when core is halted */
#endif /* DBGMCU_CR_DBG_TIM12_STOP */
#if defined(DBGMCU_CR_DBG_TIM13_STOP)
#define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_CR_DBG_TIM13_STOP /*!< TIM13 counter stopped when core is halted */
#endif /* DBGMCU_CR_DBG_TIM13_STOP */
#if defined(DBGMCU_CR_DBG_TIM14_STOP)
#define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_CR_DBG_TIM14_STOP /*!< TIM14 counter stopped when core is halted */
#endif /* DBGMCU_CR_DBG_TIM14_STOP */
#define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_CR_DBG_WWDG_STOP /*!< Debug Window Watchdog stopped when Core is halted */
#define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_CR_DBG_IWDG_STOP /*!< Debug Independent Watchdog stopped when Core is halted */
#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
#if defined(DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
#define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
#endif /* DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT */
#if defined(DBGMCU_CR_DBG_CAN1_STOP)
#define LL_DBGMCU_APB1_GRP1_CAN1_STOP DBGMCU_CR_DBG_CAN1_STOP /*!< CAN1 debug stopped when Core is halted */
#endif /* DBGMCU_CR_DBG_CAN1_STOP */
#if defined(DBGMCU_CR_DBG_CAN2_STOP)
#define LL_DBGMCU_APB1_GRP1_CAN2_STOP DBGMCU_CR_DBG_CAN2_STOP /*!< CAN2 debug stopped when Core is halted */
#endif /* DBGMCU_CR_DBG_CAN2_STOP */
/**
* @}
*/
/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
* @{
*/
#define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_CR_DBG_TIM1_STOP /*!< TIM1 counter stopped when core is halted */
#if defined(DBGMCU_CR_DBG_TIM8_STOP)
#define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_CR_DBG_TIM8_STOP /*!< TIM8 counter stopped when core is halted */
#endif /* DBGMCU_CR_DBG_CAN1_STOP */
#if defined(DBGMCU_CR_DBG_TIM9_STOP)
#define LL_DBGMCU_APB2_GRP1_TIM9_STOP DBGMCU_CR_DBG_TIM9_STOP /*!< TIM9 counter stopped when core is halted */
#endif /* DBGMCU_CR_DBG_TIM9_STOP */
#if defined(DBGMCU_CR_DBG_TIM10_STOP)
#define LL_DBGMCU_APB2_GRP1_TIM10_STOP DBGMCU_CR_DBG_TIM10_STOP /*!< TIM10 counter stopped when core is halted */
#endif /* DBGMCU_CR_DBG_TIM10_STOP */
#if defined(DBGMCU_CR_DBG_TIM11_STOP)
#define LL_DBGMCU_APB2_GRP1_TIM11_STOP DBGMCU_CR_DBG_TIM11_STOP /*!< TIM11 counter stopped when core is halted */
#endif /* DBGMCU_CR_DBG_TIM11_STOP */
#if defined(DBGMCU_CR_DBG_TIM15_STOP)
#define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_CR_DBG_TIM15_STOP /*!< TIM15 counter stopped when core is halted */
#endif /* DBGMCU_CR_DBG_TIM15_STOP */
#if defined(DBGMCU_CR_DBG_TIM16_STOP)
#define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_CR_DBG_TIM16_STOP /*!< TIM16 counter stopped when core is halted */
#endif /* DBGMCU_CR_DBG_TIM16_STOP */
#if defined(DBGMCU_CR_DBG_TIM17_STOP)
#define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_CR_DBG_TIM17_STOP /*!< TIM17 counter stopped when core is halted */
#endif /* DBGMCU_CR_DBG_TIM17_STOP */
/**
* @}
*/
/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
* @{
*/
#if defined(FLASH_ACR_LATENCY)
#define LL_FLASH_LATENCY_0 0x00000000U /*!< FLASH Zero Latency cycle */
#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /*!< FLASH One Latency cycle */
#define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two wait states */
#else
#endif /* FLASH_ACR_LATENCY */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
* @{
*/
/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
* @{
*/
/**
* @brief Return the device identifier
* @note For Low Density devices, the device ID is 0x412
* @note For Medium Density devices, the device ID is 0x410
* @note For High Density devices, the device ID is 0x414
* @note For XL Density devices, the device ID is 0x430
* @note For Connectivity Line devices, the device ID is 0x418
* @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
* @retval Values between Min_Data=0x00 and Max_Data=0xFFF
*/
__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
{
return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
}
/**
* @brief Return the device revision identifier
* @note This field indicates the revision of the device.
For example, it is read as revA -> 0x1000,for Low Density devices
For example, it is read as revA -> 0x0000, revB -> 0x2000, revZ -> 0x2001, rev1,2,3,X or Y -> 0x2003,for Medium Density devices
For example, it is read as revA or 1 -> 0x1000, revZ -> 0x1001,rev1,2,3,X or Y -> 0x1003,for Medium Density devices
For example, it is read as revA or 1 -> 0x1003,for XL Density devices
For example, it is read as revA -> 0x1000, revZ -> 0x1001 for Connectivity line devices
* @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
* @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
*/
__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
{
return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
}
/**
* @brief Enable the Debug Module during SLEEP mode
* @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
{
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
}
/**
* @brief Disable the Debug Module during SLEEP mode
* @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
{
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
}
/**
* @brief Enable the Debug Module during STOP mode
* @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
{
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
}
/**
* @brief Disable the Debug Module during STOP mode
* @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
{
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
}
/**
* @brief Enable the Debug Module during STANDBY mode
* @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
{
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
}
/**
* @brief Disable the Debug Module during STANDBY mode
* @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
{
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
}
/**
* @brief Set Trace pin assignment control
* @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n
* DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment
* @param PinAssignment This parameter can be one of the following values:
* @arg @ref LL_DBGMCU_TRACE_NONE
* @arg @ref LL_DBGMCU_TRACE_ASYNCH
* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)
{
MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment);
}
/**
* @brief Get Trace pin assignment control
* @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n
* DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment
* @retval Returned value can be one of the following values:
* @arg @ref LL_DBGMCU_TRACE_NONE
* @arg @ref LL_DBGMCU_TRACE_ASYNCH
* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
*/
__STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)
{
return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE));
}
/**
* @brief Freeze APB1 peripherals (group1 peripherals)
* @rmtoll DBGMCU_CR_APB1 DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
* DBGMCU_CR_APB1 DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
* DBGMCU_CR_APB1 DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
* DBGMCU_CR_APB1 DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
* DBGMCU_CR_APB1 DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
* DBGMCU_CR_APB1 DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
* DBGMCU_CR_APB1 DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
* DBGMCU_CR_APB1 DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
* DBGMCU_CR_APB1 DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
* DBGMCU_CR_APB1 DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
* DBGMCU_CR_APB1 DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
* DBGMCU_CR_APB1 DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
* DBGMCU_CR_APB1 DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
* DBGMCU_CR_APB1 DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
* DBGMCU_CR_APB1 DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
* DBGMCU_CR_APB1 DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
* @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*)
* @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
{
SET_BIT(DBGMCU->CR, Periphs);
}
/**
* @brief Unfreeze APB1 peripherals (group1 peripherals)
* @rmtoll DBGMCU_CR_APB1 DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
* DBGMCU_CR_APB1 DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
* DBGMCU_CR_APB1 DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
* DBGMCU_CR_APB1 DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
* DBGMCU_CR_APB1 DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
* DBGMCU_CR_APB1 DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
* DBGMCU_CR_APB1 DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
* DBGMCU_CR_APB1 DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
* DBGMCU_CR_APB1 DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
* DBGMCU_CR_APB1 DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
* DBGMCU_CR_APB1 DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
* DBGMCU_CR_APB1 DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
* DBGMCU_CR_APB1 DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
* DBGMCU_CR_APB1 DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
* DBGMCU_CR_APB1 DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
* DBGMCU_CR_APB1 DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
* @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*)
* @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
{
CLEAR_BIT(DBGMCU->CR, Periphs);
}
/**
* @brief Freeze APB2 peripherals
* @rmtoll DBGMCU_CR_APB2 DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
* DBGMCU_CR_APB2 DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
* DBGMCU_CR_APB2 DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
* DBGMCU_CR_APB2 DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
* DBGMCU_CR_APB2 DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
* DBGMCU_CR_APB2 DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
* DBGMCU_CR_APB2 DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
* DBGMCU_CR_APB2 DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*)
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*)
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*)
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP (*)
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP (*)
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*)
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
{
SET_BIT(DBGMCU->CR, Periphs);
}
/**
* @brief Unfreeze APB2 peripherals
* @rmtoll DBGMCU_CR_APB2 DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
* DBGMCU_CR_APB2 DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
* DBGMCU_CR_APB2 DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
* DBGMCU_CR_APB2 DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
* DBGMCU_CR_APB2 DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
* DBGMCU_CR_APB2 DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
* DBGMCU_CR_APB2 DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
* DBGMCU_CR_APB2 DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*)
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*)
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*)
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP (*)
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP (*)
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*)
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
{
CLEAR_BIT(DBGMCU->CR, Periphs);
}
/**
* @}
*/
#if defined(FLASH_ACR_LATENCY)
/** @defgroup SYSTEM_LL_EF_FLASH FLASH
* @{
*/
/**
* @brief Set FLASH Latency
* @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency
* @param Latency This parameter can be one of the following values:
* @arg @ref LL_FLASH_LATENCY_0
* @arg @ref LL_FLASH_LATENCY_1
* @arg @ref LL_FLASH_LATENCY_2
* @retval None
*/
__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
{
MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
}
/**
* @brief Get FLASH Latency
* @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency
* @retval Returned value can be one of the following values:
* @arg @ref LL_FLASH_LATENCY_0
* @arg @ref LL_FLASH_LATENCY_1
* @arg @ref LL_FLASH_LATENCY_2
*/
__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
{
return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
}
/**
* @brief Enable Prefetch
* @rmtoll FLASH_ACR PRFTBE LL_FLASH_EnablePrefetch
* @retval None
*/
__STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
{
SET_BIT(FLASH->ACR, FLASH_ACR_PRFTBE);
}
/**
* @brief Disable Prefetch
* @rmtoll FLASH_ACR PRFTBE LL_FLASH_DisablePrefetch
* @retval None
*/
__STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
{
CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTBE);
}
/**
* @brief Check if Prefetch buffer is enabled
* @rmtoll FLASH_ACR PRFTBS LL_FLASH_IsPrefetchEnabled
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
{
return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTBS) == (FLASH_ACR_PRFTBS));
}
#endif /* FLASH_ACR_LATENCY */
/**
* @brief Enable Flash Half Cycle Access
* @rmtoll FLASH_ACR HLFCYA LL_FLASH_EnableHalfCycleAccess
* @retval None
*/
__STATIC_INLINE void LL_FLASH_EnableHalfCycleAccess(void)
{
SET_BIT(FLASH->ACR, FLASH_ACR_HLFCYA);
}
/**
* @brief Disable Flash Half Cycle Access
* @rmtoll FLASH_ACR HLFCYA LL_FLASH_DisableHalfCycleAccess
* @retval None
*/
__STATIC_INLINE void LL_FLASH_DisableHalfCycleAccess(void)
{
CLEAR_BIT(FLASH->ACR, FLASH_ACR_HLFCYA);
}
/**
* @brief Check if Flash Half Cycle Access is enabled or not
* @rmtoll FLASH_ACR HLFCYA LL_FLASH_IsHalfCycleAccessEnabled
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_FLASH_IsHalfCycleAccessEnabled(void)
{
return (READ_BIT(FLASH->ACR, FLASH_ACR_HLFCYA) == (FLASH_ACR_HLFCYA));
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* defined (FLASH) || defined (DBGMCU) */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32F1xx_LL_SYSTEM_H */

411
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_usb.h
Wyświetl plik

@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@ -23,7 +22,7 @@
#ifdef __cplusplus
extern "C" {
#endif
#endif /* __cplusplus */
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal_def.h"
@ -42,13 +41,12 @@ extern "C" {
/**
* @brief USB Mode definition
*/
#if defined (USB_OTG_FS)
typedef enum
{
USB_DEVICE_MODE = 0,
USB_HOST_MODE = 1,
USB_DRD_MODE = 2
USB_DEVICE_MODE = 0,
USB_HOST_MODE = 1,
USB_DRD_MODE = 2
} USB_ModeTypeDef;
/**
@ -62,7 +60,7 @@ typedef enum
URB_NYET,
URB_ERROR,
URB_STALL
} USB_OTG_URBStateTypeDef;
} USB_URBStateTypeDef;
/**
* @brief Host channel States definition
@ -72,16 +70,18 @@ typedef enum
HC_IDLE = 0,
HC_XFRC,
HC_HALTED,
HC_ACK,
HC_NAK,
HC_NYET,
HC_STALL,
HC_XACTERR,
HC_BBLERR,
HC_DATATGLERR
} USB_OTG_HCStateTypeDef;
} USB_HCStateTypeDef;
/**
* @brief USB OTG Initialization Structure definition
* @brief USB Instance Initialization Structure definition
*/
typedef struct
{
@ -89,34 +89,40 @@ typedef struct
This parameter depends on the used USB core.
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
#if defined (USB_OTG_FS)
uint32_t Host_channels; /*!< Host Channels number.
This parameter Depends on the used USB core.
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
uint32_t speed; /*!< USB Core speed.
This parameter can be any value of @ref USB_Core_Speed_ */
uint32_t dma_enable; /*!< USB DMA state.
If DMA is not supported this parameter shall be set by default to zero */
#endif /* defined (USB_OTG_FS) */
uint32_t dma_enable; /*!< Enable or disable of the USB embedded DMA used only for OTG HS. */
uint32_t speed; /*!< USB Core speed.
This parameter can be any value of @ref PCD_Speed/HCD_Speed
(HCD_SPEED_xxx, HCD_SPEED_xxx) */
uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */
uint32_t phy_itface; /*!< Select the used PHY interface.
This parameter can be any value of @ref USB_Core_PHY_ */
This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module */
uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */
uint32_t low_power_enable; /*!< Enable or disable the low power mode. */
uint32_t low_power_enable; /*!< Enable or disable the low Power Mode. */
uint32_t lpm_enable; /*!< Enable or disable Link Power Management. */
uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */
#if defined (USB_OTG_FS)
uint32_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */
uint32_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */
uint32_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */
} USB_OTG_CfgTypeDef;
#endif /* defined (USB_OTG_FS) */
} USB_CfgTypeDef;
typedef struct
{
@ -129,33 +135,62 @@ typedef struct
uint8_t is_stall; /*!< Endpoint stall condition
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
#if defined (USB_OTG_FS)
uint8_t is_iso_incomplete; /*!< Endpoint isoc condition
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
#endif /* defined (USB_OTG_FS) */
uint8_t type; /*!< Endpoint type
This parameter can be any value of @ref USB_EP_Type_ */
This parameter can be any value of @ref USB_LL_EP_Type */
uint8_t data_pid_start; /*!< Initial data PID
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
uint8_t even_odd_frame; /*!< IFrame parity
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
#if defined (USB)
uint16_t pmaadress; /*!< PMA Address
This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
uint16_t tx_fifo_num; /*!< Transmission FIFO number
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
uint16_t pmaaddr0; /*!< PMA Address0
This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
uint16_t pmaaddr1; /*!< PMA Address1
This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
uint8_t doublebuffer; /*!< Double buffer enable
This parameter can be 0 or 1 */
#endif /* defined (USB) */
uint32_t maxpacket; /*!< Endpoint Max packet size
This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
uint8_t *xfer_buff; /*!< Pointer to transfer buffer */
uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address */
uint32_t xfer_len; /*!< Current transfer length */
uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */
} USB_OTG_EPTypeDef;
#if defined (USB_OTG_FS)
uint8_t even_odd_frame; /*!< IFrame parity
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
uint16_t tx_fifo_num; /*!< Transmission FIFO number
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address */
uint32_t xfer_size; /*!< requested transfer size */
#endif /* defined (USB_OTG_FS) */
#if defined (USB)
uint32_t xfer_len_db; /*!< double buffer transfer length used with bulk double buffer in */
uint8_t xfer_fill_db; /*!< double buffer Need to Fill new buffer used with bulk_in */
#endif /* defined (USB) */
} USB_EPTypeDef;
typedef struct
{
uint8_t dev_addr ; /*!< USB device address.
uint8_t dev_addr; /*!< USB device address.
This parameter must be a number between Min_Data = 1 and Max_Data = 255 */
uint8_t ch_num; /*!< Host channel number.
@ -167,15 +202,17 @@ typedef struct
uint8_t ep_is_in; /*!< Endpoint direction
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
uint8_t speed; /*!< USB Host speed.
This parameter can be any value of @ref USB_Core_Speed_ */
uint8_t speed; /*!< USB Host Channel speed.
This parameter can be any value of @ref HCD_Device_Speed:
(HCD_DEVICE_SPEED_xxx) */
uint8_t do_ping; /*!< Enable or disable the use of the PING protocol for HS mode. */
uint8_t process_ping; /*!< Execute the PING protocol for HS mode. */
uint8_t hub_port_nbr; /*!< USB HUB port number */
uint8_t hub_addr; /*!< USB HUB address */
uint8_t ep_type; /*!< Endpoint Type.
This parameter can be any value of @ref USB_EP_Type_ */
This parameter can be any value of @ref USB_LL_EP_Type */
uint16_t max_packet; /*!< Endpoint Max packet size.
This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
@ -185,6 +222,8 @@ typedef struct
uint8_t *xfer_buff; /*!< Pointer to transfer buffer. */
uint32_t XferSize; /*!< OTG Channel transfer size. */
uint32_t xfer_len; /*!< Current transfer length. */
uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer. */
@ -197,94 +236,24 @@ typedef struct
uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address. */
uint32_t ErrCnt; /*!< Host channel error count.*/
uint32_t ErrCnt; /*!< Host channel error count. */
USB_OTG_URBStateTypeDef urb_state; /*!< URB state.
This parameter can be any value of @ref USB_OTG_URBStateTypeDef */
USB_URBStateTypeDef urb_state; /*!< URB state.
This parameter can be any value of @ref USB_URBStateTypeDef */
USB_OTG_HCStateTypeDef state; /*!< Host Channel state.
This parameter can be any value of @ref USB_OTG_HCStateTypeDef */
} USB_OTG_HCTypeDef;
USB_HCStateTypeDef state; /*!< Host Channel state.
This parameter can be any value of @ref USB_HCStateTypeDef */
} USB_HCTypeDef;
#if defined (USB_OTG_FS)
typedef USB_ModeTypeDef USB_OTG_ModeTypeDef;
typedef USB_CfgTypeDef USB_OTG_CfgTypeDef;
typedef USB_EPTypeDef USB_OTG_EPTypeDef;
typedef USB_URBStateTypeDef USB_OTG_URBStateTypeDef;
typedef USB_HCStateTypeDef USB_OTG_HCStateTypeDef;
typedef USB_HCTypeDef USB_OTG_HCTypeDef;
#endif /* defined (USB_OTG_FS) */
#if defined (USB)
typedef enum
{
USB_DEVICE_MODE = 0
} USB_ModeTypeDef;
/**
* @brief USB Initialization Structure definition
*/
typedef struct
{
uint32_t dev_endpoints; /*!< Device Endpoints number.
This parameter depends on the used USB core.
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
uint32_t speed; /*!< USB Core speed.
This parameter can be any value of @ref USB_Core_Speed */
uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */
uint32_t phy_itface; /*!< Select the used PHY interface.
This parameter can be any value of @ref USB_Core_PHY */
uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */
uint32_t low_power_enable; /*!< Enable or disable Low Power mode */
uint32_t lpm_enable; /*!< Enable or disable Battery charging. */
uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */
} USB_CfgTypeDef;
typedef struct
{
uint8_t num; /*!< Endpoint number
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
uint8_t is_in; /*!< Endpoint direction
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
uint8_t is_stall; /*!< Endpoint stall condition
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
uint8_t type; /*!< Endpoint type
This parameter can be any value of @ref USB_EP_Type */
uint8_t data_pid_start; /*!< Initial data PID
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
uint16_t pmaadress; /*!< PMA Address
This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
uint16_t pmaaddr0; /*!< PMA Address0
This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
uint16_t pmaaddr1; /*!< PMA Address1
This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
uint8_t doublebuffer; /*!< Double buffer enable
This parameter can be 0 or 1 */
uint16_t tx_fifo_num; /*!< This parameter is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral
This parameter is added to ensure compatibility across USB peripherals */
uint32_t maxpacket; /*!< Endpoint Max packet size
This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
uint8_t *xfer_buff; /*!< Pointer to transfer buffer */
uint32_t xfer_len; /*!< Current transfer length */
uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */
} USB_EPTypeDef;
#endif /* defined (USB) */
/* Exported constants --------------------------------------------------------*/
/** @defgroup PCD_Exported_Constants PCD Exported Constants
@ -311,15 +280,6 @@ typedef struct
* @}
*/
/** @defgroup USB_LL Device Speed
* @{
*/
#define USBD_FS_SPEED 2U
#define USBH_FS_SPEED 1U
/**
* @}
*/
/** @defgroup USB_LL_Core_Speed USB Low Layer Core Speed
* @{
*/
@ -331,7 +291,6 @@ typedef struct
/** @defgroup USB_LL_Core_PHY USB Low Layer Core PHY
* @{
*/
#define USB_OTG_ULPI_PHY 1U
#define USB_OTG_EMBEDDED_PHY 2U
/**
* @}
@ -341,8 +300,8 @@ typedef struct
* @{
*/
#ifndef USBD_FS_TRDT_VALUE
#define USBD_FS_TRDT_VALUE 5U
#define USBD_DEFAULT_TRDT_VALUE 9U
#define USBD_FS_TRDT_VALUE 5U
#define USBD_DEFAULT_TRDT_VALUE 9U
#endif /* USBD_HS_TRDT_VALUE */
/**
* @}
@ -351,8 +310,8 @@ typedef struct
/** @defgroup USB_LL_Core_MPS USB Low Layer Core MPS
* @{
*/
#define USB_OTG_FS_MAX_PACKET_SIZE 64U
#define USB_OTG_MAX_EP0_SIZE 64U
#define USB_OTG_FS_MAX_PACKET_SIZE 64U
#define USB_OTG_MAX_EP0_SIZE 64U
/**
* @}
*/
@ -377,24 +336,14 @@ typedef struct
/**
* @}
*/
#endif /* defined (USB_OTG_FS) */
/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS
* @{
*/
#define DEP0CTL_MPS_64 0U
#define DEP0CTL_MPS_32 1U
#define DEP0CTL_MPS_16 2U
#define DEP0CTL_MPS_8 3U
/**
* @}
*/
/** @defgroup USB_LL_EP_Speed USB Low Layer EP Speed
* @{
*/
#define EP_SPEED_LOW 0U
#define EP_SPEED_FULL 1U
#define EP_SPEED_HIGH 2U
#define EP_MPS_64 0U
#define EP_MPS_32 1U
#define EP_MPS_16 2U
#define EP_MPS_8 3U
/**
* @}
*/
@ -411,6 +360,37 @@ typedef struct
* @}
*/
/** @defgroup USB_LL_EP_Speed USB Low Layer EP Speed
* @{
*/
#define EP_SPEED_LOW 0U
#define EP_SPEED_FULL 1U
#define EP_SPEED_HIGH 2U
/**
* @}
*/
/** @defgroup USB_LL_CH_PID_Type USB Low Layer Channel PID Type
* @{
*/
#define HC_PID_DATA0 0U
#define HC_PID_DATA2 1U
#define HC_PID_DATA1 2U
#define HC_PID_SETUP 3U
/**
* @}
*/
/** @defgroup USB_LL Device Speed
* @{
*/
#define USBD_FS_SPEED 2U
#define USBH_FSLS_SPEED 1U
/**
* @}
*/
#if defined (USB_OTG_FS)
/** @defgroup USB_LL_STS_Defines USB Low Layer STS Defines
* @{
*/
@ -433,6 +413,16 @@ typedef struct
* @}
*/
/** @defgroup USB_LL_HFIR_Defines USB Low Layer frame interval Defines
* @{
*/
#define HFIR_6_MHZ 6000U
#define HFIR_60_MHZ 60000U
#define HFIR_48_MHZ 48000U
/**
* @}
*/
/** @defgroup USB_LL_HPRT0_PRTSPD_SPEED_Defines USB Low Layer HPRT0 PRTSPD Speed Defines
* @{
*/
@ -448,69 +438,51 @@ typedef struct
#define HCCHAR_BULK 2U
#define HCCHAR_INTR 3U
#define HC_PID_DATA0 0U
#define HC_PID_DATA2 1U
#define HC_PID_DATA1 2U
#define HC_PID_SETUP 3U
#define GRXSTS_PKTSTS_IN 2U
#define GRXSTS_PKTSTS_IN_XFER_COMP 3U
#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5U
#define GRXSTS_PKTSTS_CH_HALTED 7U
#define CLEAR_INTERRUPT_MASK 0xFFFFFFFFU
#define HC_MAX_PKT_CNT 256U
#define USBx_PCGCCTL *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_PCGCCTL_BASE)
#define USBx_HPRT0 *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_HOST_PORT_BASE)
#define USBx_DEVICE ((USB_OTG_DeviceTypeDef *)(USBx_BASE + USB_OTG_DEVICE_BASE))
#define USBx_INEP(i) ((USB_OTG_INEndpointTypeDef *)(USBx_BASE + USB_OTG_IN_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))
#define USBx_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)(USBx_BASE + USB_OTG_OUT_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))
#define USBx_INEP(i) ((USB_OTG_INEndpointTypeDef *)(USBx_BASE\
+ USB_OTG_IN_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))
#define USBx_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)(USBx_BASE\
+ USB_OTG_OUT_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))
#define USBx_DFIFO(i) *(__IO uint32_t *)(USBx_BASE + USB_OTG_FIFO_BASE + ((i) * USB_OTG_FIFO_SIZE))
#define USBx_HOST ((USB_OTG_HostTypeDef *)(USBx_BASE + USB_OTG_HOST_BASE))
#define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)(USBx_BASE + USB_OTG_HOST_CHANNEL_BASE + ((i) * USB_OTG_HOST_CHANNEL_SIZE)))
#endif /* defined (USB_OTG_FS) */
#define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)(USBx_BASE\
+ USB_OTG_HOST_CHANNEL_BASE\
+ ((i) * USB_OTG_HOST_CHANNEL_SIZE)))
#if defined (USB)
/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS
* @{
*/
#define DEP0CTL_MPS_64 0U
#define DEP0CTL_MPS_32 1U
#define DEP0CTL_MPS_16 2U
#define DEP0CTL_MPS_8 3U
/**
* @}
*/
/** @defgroup USB_LL_EP_Type USB Low Layer EP Type
* @{
*/
#define EP_TYPE_CTRL 0U
#define EP_TYPE_ISOC 1U
#define EP_TYPE_BULK 2U
#define EP_TYPE_INTR 3U
#define EP_TYPE_MSK 3U
/**
* @}
*/
/** @defgroup USB_LL Device Speed
* @{
*/
#define USBD_FS_SPEED 2U
/**
* @}
*/
#define BTABLE_ADDRESS 0x000U
#define PMA_ACCESS 2U
#endif /* defined (USB) */
#if defined (USB_OTG_FS)
#define EP_ADDR_MSK 0xFU
#endif /* defined (USB_OTG_FS) */
#if defined (USB)
#define BTABLE_ADDRESS 0x000U
#define PMA_ACCESS 2U
#ifndef USB_EP_RX_STRX
#define USB_EP_RX_STRX (0x3U << 12)
#endif /* USB_EP_RX_STRX */
#define EP_ADDR_MSK 0x7U
#ifndef USE_USB_DOUBLE_BUFFER
#define USE_USB_DOUBLE_BUFFER 1U
#endif /* USE_USB_DOUBLE_BUFFER */
#endif /* defined (USB) */
/**
* @}
*/
@ -549,11 +521,13 @@ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EP
HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len);
HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src,
uint8_t ch_ep_num, uint16_t len);
void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len);
HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
HAL_StatusTypeDef USB_EPStopXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address);
HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx);
@ -562,7 +536,8 @@ HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t *psetup);
uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx);
uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx);
uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx);
uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef const *USBx);
uint32_t USB_ReadChInterrupts(USB_OTG_GlobalTypeDef *USBx, uint8_t chnum);
uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx);
uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum);
uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx);
@ -573,16 +548,14 @@ HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c
HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq);
HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state);
uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx);
uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,
uint8_t ch_num,
uint8_t epnum,
uint8_t dev_address,
uint8_t speed,
uint8_t ep_type,
uint16_t mps);
HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc);
uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef const *USBx);
uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef const *USBx);
HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num,
uint8_t epnum, uint8_t dev_address, uint8_t speed,
uint8_t ep_type, uint16_t mps);
HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx,
USB_OTG_HCTypeDef *hc);
uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num);
HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num);
@ -598,31 +571,43 @@ HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode);
HAL_StatusTypeDef USB_SetDevSpeed(USB_TypeDef *USBx, uint8_t speed);
HAL_StatusTypeDef USB_FlushRxFifo(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_FlushTxFifo(USB_TypeDef *USBx, uint32_t num);
HAL_StatusTypeDef USB_FlushRxFifo(USB_TypeDef const *USBx);
HAL_StatusTypeDef USB_FlushTxFifo(USB_TypeDef const *USBx, uint32_t num);
#if defined (HAL_PCD_MODULE_ENABLED)
HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep);
HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep);
HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep);
HAL_StatusTypeDef USB_WritePacket(USB_TypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len);
void *USB_ReadPacket(USB_TypeDef *USBx, uint8_t *dest, uint16_t len);
HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep);
HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep);
HAL_StatusTypeDef USB_EPStopXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep);
#endif /* defined (HAL_PCD_MODULE_ENABLED) */
HAL_StatusTypeDef USB_SetDevAddress(USB_TypeDef *USBx, uint8_t address);
HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_EP0_OutStart(USB_TypeDef *USBx, uint8_t *psetup);
uint32_t USB_ReadInterrupts(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_WritePacket(USB_TypeDef *USBx, uint8_t *src,
uint8_t ch_ep_num, uint16_t len);
void *USB_ReadPacket(USB_TypeDef *USBx, uint8_t *dest, uint16_t len);
uint32_t USB_ReadInterrupts(USB_TypeDef const *USBx);
uint32_t USB_ReadDevAllOutEpInterrupt(USB_TypeDef *USBx);
uint32_t USB_ReadDevOutEPInterrupt(USB_TypeDef *USBx, uint8_t epnum);
uint32_t USB_ReadDevAllInEpInterrupt(USB_TypeDef *USBx);
uint32_t USB_ReadDevInEPInterrupt(USB_TypeDef *USBx, uint8_t epnum);
void USB_ClearInterrupts(USB_TypeDef *USBx, uint32_t interrupt);
HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx);
void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
void USB_WritePMA(USB_TypeDef const *USBx, uint8_t *pbUsrBuf,
uint16_t wPMABufAddr, uint16_t wNBytes);
void USB_ReadPMA(USB_TypeDef const *USBx, uint8_t *pbUsrBuf,
uint16_t wPMABufAddr, uint16_t wNBytes);
#endif /* defined (USB) */
/**
* @}
@ -643,9 +628,7 @@ void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, ui
#ifdef __cplusplus
}
#endif
#endif /* __cplusplus */
#endif /* STM32F1xx_LL_USB_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

270
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_utils.h 100644
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@ -0,0 +1,270 @@
/**
******************************************************************************
* @file stm32f1xx_ll_utils.h
* @author MCD Application Team
* @brief Header file of UTILS LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The LL UTILS driver contains a set of generic APIs that can be
used by user:
(+) Device electronic signature
(+) Timing functions
(+) PLL configuration functions
@endverbatim
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_LL_UTILS_H
#define __STM32F1xx_LL_UTILS_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx.h"
/** @addtogroup STM32F1xx_LL_Driver
* @{
*/
/** @defgroup UTILS_LL UTILS
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
* @{
*/
/* Max delay can be used in LL_mDelay */
#define LL_MAX_DELAY 0xFFFFFFFFU
/**
* @brief Unique device ID register base address
*/
#define UID_BASE_ADDRESS UID_BASE
/**
* @brief Flash size data register base address
*/
#define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
* @{
*/
/**
* @}
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
* @{
*/
/**
* @brief UTILS PLL structure definition
*/
typedef struct
{
uint32_t PLLMul; /*!< Multiplication factor for PLL VCO input clock.
This parameter can be a value of @ref RCC_LL_EC_PLL_MUL
This feature can be modified afterwards using unitary function
@ref LL_RCC_PLL_ConfigDomain_SYS(). */
uint32_t Prediv; /*!< Division factor for HSE used as PLL clock source.
This parameter can be a value of @ref RCC_LL_EC_PREDIV_DIV
This feature can be modified afterwards using unitary function
@ref LL_RCC_PLL_ConfigDomain_SYS(). */
} LL_UTILS_PLLInitTypeDef;
/**
* @brief UTILS System, AHB and APB buses clock configuration structure definition
*/
typedef struct
{
uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
This feature can be modified afterwards using unitary function
@ref LL_RCC_SetAHBPrescaler(). */
uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
This feature can be modified afterwards using unitary function
@ref LL_RCC_SetAPB1Prescaler(). */
uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
This parameter can be a value of @ref RCC_LL_EC_APB2_DIV
This feature can be modified afterwards using unitary function
@ref LL_RCC_SetAPB2Prescaler(). */
} LL_UTILS_ClkInitTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
* @{
*/
/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
* @{
*/
#define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */
#define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
* @{
*/
/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
* @{
*/
/**
* @brief Get Word0 of the unique device identifier (UID based on 96 bits)
* @retval UID[31:0]
*/
__STATIC_INLINE uint32_t LL_GetUID_Word0(void)
{
return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
}
/**
* @brief Get Word1 of the unique device identifier (UID based on 96 bits)
* @retval UID[63:32]
*/
__STATIC_INLINE uint32_t LL_GetUID_Word1(void)
{
return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
}
/**
* @brief Get Word2 of the unique device identifier (UID based on 96 bits)
* @retval UID[95:64]
*/
__STATIC_INLINE uint32_t LL_GetUID_Word2(void)
{
return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
}
/**
* @brief Get Flash memory size
* @note This bitfield indicates the size of the device Flash memory expressed in
* Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
* @retval FLASH_SIZE[15:0]: Flash memory size
*/
__STATIC_INLINE uint32_t LL_GetFlashSize(void)
{
return (uint16_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)));
}
/**
* @}
*/
/** @defgroup UTILS_LL_EF_DELAY DELAY
* @{
*/
/**
* @brief This function configures the Cortex-M SysTick source of the time base.
* @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
* @note When a RTOS is used, it is recommended to avoid changing the SysTick
* configuration by calling this function, for a delay use rather osDelay RTOS service.
* @param Ticks Number of ticks
* @retval None
*/
__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
{
/* Configure the SysTick to have interrupt in 1ms time base */
SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */
}
void LL_Init1msTick(uint32_t HCLKFrequency);
void LL_mDelay(uint32_t Delay);
/**
* @}
*/
/** @defgroup UTILS_EF_SYSTEM SYSTEM
* @{
*/
void LL_SetSystemCoreClock(uint32_t HCLKFrequency);
#if defined(FLASH_ACR_LATENCY)
ErrorStatus LL_SetFlashLatency(uint32_t Frequency);
#endif /* FLASH_ACR_LATENCY */
ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
#if defined(RCC_PLL2_SUPPORT)
ErrorStatus LL_PLL_ConfigSystemClock_PLL2(uint32_t HSEFrequency, uint32_t HSEBypass, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
LL_UTILS_PLLInitTypeDef *UTILS_PLL2InitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
#endif /* RCC_PLL2_SUPPORT */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32F1xx_LL_UTILS_H */

6
Drivers/STM32F1xx_HAL_Driver/LICENSE.txt 100644
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@ -0,0 +1,6 @@
This software component is provided to you as part of a software package and
applicable license terms are in the Package_license file. If you received this
software component outside of a package or without applicable license terms,
the terms of the BSD-3-Clause license shall apply.
You may obtain a copy of the BSD-3-Clause at:
https://opensource.org/licenses/BSD-3-Clause

45
Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c
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@ -5,6 +5,17 @@
* @brief HAL module driver.
* This is the common part of the HAL initialization
*
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@ -19,17 +30,6 @@
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@ -53,11 +53,11 @@
* @{
*/
/**
* @brief STM32F1xx HAL Driver version number V1.1.4
* @brief STM32F1xx HAL Driver version number
*/
#define __STM32F1xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define __STM32F1xx_HAL_VERSION_SUB1 (0x01U) /*!< [23:16] sub1 version */
#define __STM32F1xx_HAL_VERSION_SUB2 (0x04U) /*!< [15:8] sub2 version */
#define __STM32F1xx_HAL_VERSION_SUB2 (0x09U) /*!< [15:8] sub2 version */
#define __STM32F1xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32F1xx_HAL_VERSION ((__STM32F1xx_HAL_VERSION_MAIN << 24)\
|(__STM32F1xx_HAL_VERSION_SUB1 << 16)\
@ -322,15 +322,25 @@ uint32_t HAL_GetTickPrio(void)
HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)
{
HAL_StatusTypeDef status = HAL_OK;
HAL_TickFreqTypeDef prevTickFreq;
assert_param(IS_TICKFREQ(Freq));
if (uwTickFreq != Freq)
{
/* Back up uwTickFreq frequency */
prevTickFreq = uwTickFreq;
/* Update uwTickFreq global variable used by HAL_InitTick() */
uwTickFreq = Freq;
/* Apply the new tick Freq */
status = HAL_InitTick(uwTickPrio);
if (status == HAL_OK)
if (status != HAL_OK)
{
uwTickFreq = Freq;
/* Restore previous tick frequency */
uwTickFreq = prevTickFreq;
}
}
@ -339,7 +349,8 @@ HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)
/**
* @brief Return tick frequency.
* @retval tick period in Hz
* @retval Tick frequency.
* Value of @ref HAL_TickFreqTypeDef.
*/
HAL_TickFreqTypeDef HAL_GetTickFreq(void)
{
@ -593,4 +604,4 @@ void HAL_DBGMCU_DisableDBGStandbyMode(void)
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

12
Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c
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@ -68,13 +68,12 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
* This software is licensed under terms that can be found in the LICENSE file in
* the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@ -502,4 +501,3 @@ __weak void HAL_SYSTICK_Callback(void)
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

20
Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c
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@ -70,13 +70,12 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
* This software is licensed under terms that can be found in the LICENSE file in
* the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@ -684,9 +683,9 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
* @brief Register callbacks
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @param CallbackID: User Callback identifer
* @param CallbackID: User Callback identifier
* a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
* @param pCallback: pointer to private callbacsk function which has pointer to
* @param pCallback: pointer to private callback function which has pointer to
* a DMA_HandleTypeDef structure as parameter.
* @retval HAL status
*/
@ -737,7 +736,7 @@ HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Call
* @brief UnRegister callbacks
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @param CallbackID: User Callback identifer
* @param CallbackID: User Callback identifier
* a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
* @retval HAL status
*/
@ -812,7 +811,7 @@ HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Ca
*/
/**
* @brief Return the DMA hande state.
* @brief Return the DMA handle state.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval HAL state
@ -896,4 +895,3 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

54
Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c
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@ -8,6 +8,17 @@
* + Initialization and de-initialization functions
* + IO operation functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### EXTI Peripheral features #####
@ -53,7 +64,7 @@
(++) Provide exiting handle as parameter.
(++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter.
(#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine().
(#) Clear Exti configuration of a dedicated line using HAL_EXTI_ClearConfigLine().
(++) Provide exiting handle as parameter.
(#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback().
@ -64,23 +75,11 @@
(#) Get interrupt pending bit using HAL_EXTI_GetPending().
(#) Clear interrupt pending bit using HAL_EXTI_GetPending().
(#) Clear interrupt pending bit using HAL_EXTI_ClearPending().
(#) Generate software interrupt using HAL_EXTI_GenerateSWI().
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@ -276,6 +275,10 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT
pExtiConfig->Mode |= EXTI_MODE_EVENT;
}
/* Get default Trigger and GPIOSel configuration */
pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
pExtiConfig->GPIOSel = 0x00u;
/* 2] Get trigger for configurable lines : rising */
if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
{
@ -284,10 +287,6 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT
{
pExtiConfig->Trigger = EXTI_TRIGGER_RISING;
}
else
{
pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
}
/* Get falling configuration */
/* Check if configuration of selected line is enable */
@ -302,18 +301,8 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT
assert_param(IS_EXTI_GPIO_PIN(linepos));
regval = AFIO->EXTICR[linepos >> 2u];
pExtiConfig->GPIOSel = ((regval << (AFIO_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 24);
pExtiConfig->GPIOSel = (regval >> (AFIO_EXTICR1_EXTI1_Pos * (linepos & 0x03u))) & AFIO_EXTICR1_EXTI0;
}
else
{
pExtiConfig->GPIOSel = 0x00u;
}
}
else
{
/* No Trigger selected */
pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
pExtiConfig->GPIOSel = 0x00u;
}
return HAL_OK;
@ -485,6 +474,9 @@ uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
assert_param(IS_EXTI_PENDING_EDGE(Edge));
/* Prevent unused argument compilation warning */
UNUSED(Edge);
/* Compute line mask */
linepos = (hexti->Line & EXTI_PIN_MASK);
maskline = (1uL << linepos);
@ -512,6 +504,9 @@ void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
assert_param(IS_EXTI_PENDING_EDGE(Edge));
/* Prevent unused argument compilation warning */
UNUSED(Edge);
/* Compute line mask */
maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
@ -556,4 +551,3 @@ void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti)
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

13
Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c
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@ -70,14 +70,12 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file in
* the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
@ -964,4 +962,3 @@ static void FLASH_SetErrorCode(void)
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

21
Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c
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@ -28,14 +28,12 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file in
* the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
@ -125,15 +123,15 @@ static uint8_t FLASH_OB_GetUser(void);
==============================================================================
[..] The FLASH Memory Erasing functions, includes the following functions:
(+) @ref HAL_FLASHEx_Erase: return only when erase has been done
(+) @ref HAL_FLASHEx_Erase_IT: end of erase is done when @ref HAL_FLASH_EndOfOperationCallback
(+) HAL_FLASHEx_Erase: return only when erase has been done
(+) HAL_FLASHEx_Erase_IT: end of erase is done when HAL_FLASH_EndOfOperationCallback
is called with parameter 0xFFFFFFFF
[..] Any operation of erase should follow these steps:
(#) Call the @ref HAL_FLASH_Unlock() function to enable the flash control register and
(#) Call the HAL_FLASH_Unlock() function to enable the flash control register and
program memory access.
(#) Call the desired function to erase page.
(#) Call the @ref HAL_FLASH_Lock() to disable the flash program memory access
(#) Call the HAL_FLASH_Lock() to disable the flash program memory access
(recommended to protect the FLASH memory against possible unwanted operation).
@endverbatim
@ -1124,4 +1122,3 @@ void FLASH_PageErase(uint32_t PageAddress)
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

86
Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c
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@ -8,6 +8,17 @@
* + Initialization and de-initialization functions
* + IO operation functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### GPIO Peripheral features #####
@ -88,17 +99,6 @@
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@ -295,26 +295,6 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
AFIO->EXTICR[position >> 2u] = temp;
/* Configure the interrupt mask */
if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
{
SET_BIT(EXTI->IMR, iocurrent);
}
else
{
CLEAR_BIT(EXTI->IMR, iocurrent);
}
/* Configure the event mask */
if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
{
SET_BIT(EXTI->EMR, iocurrent);
}
else
{
CLEAR_BIT(EXTI->EMR, iocurrent);
}
/* Enable or disable the rising trigger */
if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
{
@ -334,6 +314,26 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
CLEAR_BIT(EXTI->FTSR, iocurrent);
}
/* Configure the event mask */
if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
{
SET_BIT(EXTI->EMR, iocurrent);
}
else
{
CLEAR_BIT(EXTI->EMR, iocurrent);
}
/* Configure the interrupt mask */
if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
{
SET_BIT(EXTI->IMR, iocurrent);
}
else
{
CLEAR_BIT(EXTI->IMR, iocurrent);
}
}
}
@ -375,16 +375,16 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
tmp &= 0x0FuL << (4u * (position & 0x03u));
if (tmp == (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u))))
{
tmp = 0x0FuL << (4u * (position & 0x03u));
CLEAR_BIT(AFIO->EXTICR[position >> 2u], tmp);
/* Clear EXTI line configuration */
CLEAR_BIT(EXTI->IMR, (uint32_t)iocurrent);
CLEAR_BIT(EXTI->EMR, (uint32_t)iocurrent);
/* Clear Rising Falling edge configuration */
CLEAR_BIT(EXTI->RTSR, (uint32_t)iocurrent);
CLEAR_BIT(EXTI->FTSR, (uint32_t)iocurrent);
CLEAR_BIT(EXTI->RTSR, (uint32_t)iocurrent);
tmp = 0x0FuL << (4u * (position & 0x03u));
CLEAR_BIT(AFIO->EXTICR[position >> 2u], tmp);
}
/*------------------------- GPIO Mode Configuration --------------------*/
/* Check if the current bit belongs to first half or last half of the pin count number
@ -486,17 +486,16 @@ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState Pin
*/
void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
uint32_t odr;
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
if ((GPIOx->ODR & GPIO_Pin) != 0x00u)
{
GPIOx->BRR = (uint32_t)GPIO_Pin;
}
else
{
GPIOx->BSRR = (uint32_t)GPIO_Pin;
}
/* get current Output Data Register value */
odr = GPIOx->ODR;
/* Set selected pins that were at low level, and reset ones that were high */
GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
}
/**
@ -585,4 +584,3 @@ __weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

23
Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c
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@ -7,6 +7,17 @@
* functionalities of the General Purpose Input/Output (GPIO) extension peripheral.
* + Extended features functions
*
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### GPIO Peripheral extension features #####
@ -23,17 +34,6 @@
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@ -124,4 +124,3 @@ void HAL_GPIOEx_DisableEventout(void)
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

871
Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd.c
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27
Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd_ex.c
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@ -10,13 +10,12 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@ -49,7 +48,7 @@
/** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
* @brief PCDEx control functions
*
*
@verbatim
===============================================================================
##### Extended features functions #####
@ -135,10 +134,8 @@ HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd,
uint16_t ep_addr,
uint16_t ep_kind,
uint32_t pmaadress)
HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr,
uint16_t ep_kind, uint32_t pmaadress)
{
PCD_EPTypeDef *ep;
@ -160,6 +157,7 @@ HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd,
/* Configure the PMA */
ep->pmaadress = (uint16_t)pmaadress;
}
#if (USE_USB_DOUBLE_BUFFER == 1U)
else /* USB_DBL_BUF */
{
/* Double Buffer Endpoint */
@ -168,6 +166,7 @@ HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd,
ep->pmaaddr0 = (uint16_t)(pmaadress & 0xFFFFU);
ep->pmaaddr1 = (uint16_t)((pmaadress & 0xFFFF0000U) >> 16);
}
#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
return HAL_OK;
}
@ -176,8 +175,8 @@ HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd,
* @brief Software Device Connection,
* this function is not required by USB OTG FS peripheral, it is used
* only by USB Device FS peripheral.
* @param hpcd: PCD handle
* @param state: connection state (0 : disconnected / 1: connected)
* @param hpcd PCD handle
* @param state connection state (0 : disconnected / 1: connected)
* @retval None
*/
__weak void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state)
@ -242,5 +241,3 @@ __weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef m
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

13
Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c
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@ -12,13 +12,12 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@ -617,5 +616,3 @@ __weak void HAL_PWR_PVDCallback(void)
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

25
Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c
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@ -48,14 +48,12 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file in
* the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
@ -155,7 +153,7 @@ static void RCC_Delay(uint32_t mdelay);
on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
from AHB clock through configurable prescalers and used to clock
the peripherals mapped on these buses. You can use
"@ref HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
"HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
-@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
(+@) RTC: RTC clock can be derived either from the LSI, LSE or HSE clock
@ -1082,14 +1080,14 @@ void HAL_RCC_DisableCSS(void)
uint32_t HAL_RCC_GetSysClockFreq(void)
{
#if defined(RCC_CFGR2_PREDIV1SRC)
const uint8_t aPLLMULFactorTable[14] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13};
const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
static const uint8_t aPLLMULFactorTable[14U] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13};
static const uint8_t aPredivFactorTable[16U] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
#else
const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
static const uint8_t aPLLMULFactorTable[16U] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
#if defined(RCC_CFGR2_PREDIV1)
const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
static const uint8_t aPredivFactorTable[16U] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
#else
const uint8_t aPredivFactorTable[2] = {1, 2};
static const uint8_t aPredivFactorTable[2U] = {1, 2};
#endif /*RCC_CFGR2_PREDIV1*/
#endif
@ -1400,4 +1398,3 @@ __weak void HAL_RCC_CSSCallback(void)
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

25
Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c
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@ -10,14 +10,12 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file in
* the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
@ -110,11 +108,11 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/*------------------------------- RTC/LCD Configuration ------------------------*/
if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
{
FlagStatus pwrclkchanged = RESET;
/* check for RTC Parameters used to output RTCCLK */
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
FlagStatus pwrclkchanged = RESET;
/* As soon as function is called to change RTC clock source, activation of the
power domain is done. */
/* Requires to enable write access to Backup Domain of necessary */
@ -387,16 +385,16 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
{
#if defined(STM32F105xC) || defined(STM32F107xC)
const uint8_t aPLLMULFactorTable[14] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13};
const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
static const uint8_t aPLLMULFactorTable[14U] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13};
static const uint8_t aPredivFactorTable[16U] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U;
uint32_t pll2mul = 0U, pll3mul = 0U, prediv2 = 0U;
#endif /* STM32F105xC || STM32F107xC */
#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || \
defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
const uint8_t aPredivFactorTable[2] = {1, 2};
static const uint8_t aPLLMULFactorTable[16U] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
static const uint8_t aPredivFactorTable[2U] = {1, 2};
uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U;
#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
@ -859,5 +857,4 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void)
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

2070
Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c
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828
Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c
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1206
Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_usb.c
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1419
EWARM/F103C8T6_DIGI_USB.ewd
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1138
EWARM/F103C8T6_DIGI_USB.ewp
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7
EWARM/Project.eww
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@ -1,7 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<workspace>
<project>
<path>$WS_DIR$\F103C8T6_DIGI_USB.ewp</path>
</project>
<batchBuild />
</workspace>

393
EWARM/startup_stm32f103xb.s
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@ -1,393 +0,0 @@
;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
;* File Name : startup_stm32f103xb.s
;* Author : MCD Application Team
;* Description : STM32F103xB Performance Line Devices vector table for
;* EWARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Configure the clock system
;* - Set the initial PC == __iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;*******************************************************************************
;* @attention
;*
;* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
;* All rights reserved.</center></h2>
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;*
;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
PVD_IRQHandler
B PVD_IRQHandler
PUBWEAK TAMPER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TAMPER_IRQHandler
B TAMPER_IRQHandler
PUBWEAK RTC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_IRQHandler
B RTC_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC1_2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ADC1_2_IRQHandler
B ADC1_2_IRQHandler
PUBWEAK USB_HP_CAN1_TX_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USB_HP_CAN1_TX_IRQHandler
B USB_HP_CAN1_TX_IRQHandler
PUBWEAK USB_LP_CAN1_RX0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USB_LP_CAN1_RX0_IRQHandler
B USB_LP_CAN1_RX0_IRQHandler
PUBWEAK CAN1_RX1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_RX1_IRQHandler
B CAN1_RX1_IRQHandler
PUBWEAK CAN1_SCE_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_SCE_IRQHandler
B CAN1_SCE_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_BRK_IRQHandler
B TIM1_BRK_IRQHandler
PUBWEAK TIM1_UP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_UP_IRQHandler
B TIM1_UP_IRQHandler
PUBWEAK TIM1_TRG_COM_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_TRG_COM_IRQHandler
B TIM1_TRG_COM_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK TIM4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM4_IRQHandler
B TIM4_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK USBWakeUp_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USBWakeUp_IRQHandler
B USBWakeUp_IRQHandler
END
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

31
EWARM/stm32f103xb_flash.icf
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@ -1,31 +0,0 @@
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000 ;
define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
define symbol __ICFEDIT_region_RAM_end__ = 0x20004FFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x400;
define symbol __ICFEDIT_size_heap__ = 0x200;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };

31
EWARM/stm32f103xb_sram.icf
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@ -1,31 +0,0 @@
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x20000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x20000000 ;
define symbol __ICFEDIT_region_ROM_end__ = 0x200013FF;
define symbol __ICFEDIT_region_RAM_start__ = 0x20001400;
define symbol __ICFEDIT_region_RAM_end__ = 0x20004FFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x400;
define symbol __ICFEDIT_size_heap__ = 0x200;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };

35
F103C8T6_DIGI_USB Debug.cfg
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# This is an F103C8T6_DIGI_USB board with a single STM32F103C8Tx chip
#
# Generated by System Workbench for STM32
# Take care that such file, as generated, may be overridden without any early notice. Please have a look to debug launch configuration setup(s)
source [find interface/stlink.cfg]
set WORKAREASIZE 0x5000
transport select "hla_swd"
set CHIPNAME STM32F103C8Tx
set BOARDNAME F103C8T6_DIGI_USB
# CHIPNAMES state
set CHIPNAME_CPU0_ACTIVATED 1
# Enable debug when in low power modes
set ENABLE_LOW_POWER 1
# Stop Watchdog counters when halt
set STOP_WATCHDOG 1
# STlink Debug clock frequency
set CLOCK_FREQ 8000
# use software system reset
reset_config none
set CONNECT_UNDER_RESET 0
# BCTM CPU variables
source [find target/stm32f1x.cfg]

35
F103C8T6_DIGI_USB Release.cfg
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@ -1,35 +0,0 @@
# This is an F103C8T6_DIGI_USB board with a single STM32F103C8Tx chip
#
# Generated by System Workbench for STM32
# Take care that such file, as generated, may be overridden without any early notice. Please have a look to debug launch configuration setup(s)
source [find interface/stlink.cfg]
set WORKAREASIZE 0x5000
transport select "hla_swd"
set CHIPNAME STM32F103C8Tx
set BOARDNAME F103C8T6_DIGI_USB
# CHIPNAMES state
set CHIPNAME_CPU0_ACTIVATED 1
# Enable debug when in low power modes
set ENABLE_LOW_POWER 1
# Stop Watchdog counters when halt
set STOP_WATCHDOG 1
# STlink Debug clock frequency
set CLOCK_FREQ 8000
# use software system reset
reset_config none
set CONNECT_UNDER_RESET 0
# BCTM CPU variables
source [find target/stm32f1x.cfg]

2
F103C8T6_DIGI_USB.xml
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@ -12,7 +12,7 @@
<targetDefinitions>
<board id="f103c8t6_digi_usb">
<name>F103C8T6_DIGI_USB</name>
<dbgIF>JTAG</dbgIF>
<dbgIF>SWD</dbgIF>
<dbgDEV>ST-Link</dbgDEV>
<mcuId>stm32f103c8tx</mcuId>
</board>

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