Increased PWM frequency for TX envelope and speaker outputs.

QCX-SSB.ino

@@ -378,7 +378,7 @@ enum dsp_cap_t { ANALOG, DSP, SDR };
 static uint8_t dsp_cap = 0;
 static uint8_t ssb_cap = 0;
 volatile uint8_t att = 0;
-const char* att_label[] = { "0dB", "-6dB", "-20dB", "-26dB" };
+const char* att_label[] = { "0dB", "-13dB", "-20dB", "-33dB" };
 //#define PROFILING  1
 #ifdef PROFILING
 volatile uint32_t numSamples = 0;
@@ -949,13 +949,10 @@ void timer1_start(uint32_t fs)
 {  // Timer 1: OC1A and OC1B in PWM mode
   TCCR1A = 0;
   TCCR1B = 0;
-  TCCR1A |= (1 << COM1A1) | (1 << COM1B1); // Clear OC1A,OC1B on Compare Match when upcounting. Set OC1A,OC1B on Compare Match when downcounting.
-  TCCR1B |= ((1 << CS10) | (1 << WGM13)); // WGM13: Mode 8 - PWM, Phase and Frequency Correct;  CS10: clkI/O/1 (No prescaling)
-  ICR1H = 0x00;  // TOP. This sets the PWM frequency: PWM_FREQ=312.500kHz ICR=0x1F bit_depth=5; PWM_FREQ=156.250kHz ICR=0x3F bit_depth=6; PWM_FREQ=78.125kHz  ICR=0x7F bit_depth=7; PWM_FREQ=39.250kHz  ICR=0xFF bit_depth=8
-  //ICR1L = 0xFF;  // Fpwm = F_CPU / (2 * Prescaler * TOP) :   PWM_FREQ = 39.25kHz, bit-depth=8
-  //ICR1L = 160;   // Fpwm = F_CPU / (2 * Prescaler * TOP) :   PWM_FREQ = 62.500kHz, bit-depth=7.8
-  //ICR1L = 0x7F;  // Fpwm = F_CPU / (2 * Prescaler * TOP) :   PWM_FREQ = 78.125kHz, bit-depth=7
-  ICR1L = (float)F_CPU / (float)2 / (float)fs + 0.5;  // PWM value range (determines bit-depth and PWM frequency):  Fpwm = F_CPU / (2 * Prescaler * TOP)
+  TCCR1A |= (1 << COM1A1) | (1 << COM1B1) | (1 << WGM11); // Clear OC1A,OC1B on Compare Match when upcounting. Set OC1A,OC1B on Compare Match when downcounting.
+  TCCR1B |= (1 << CS10) | (1 << WGM13) | (1 << WGM12); // WGM13: Mode 14 - Fast PWM;  CS10: clkI/O/1 (No prescaling)
+  ICR1H = 0x00;
+  ICR1L = (float)F_CPU / (float)fs - 0.5;  // PWM value range (determines bit-depth and PWM frequency):  Fpwm = F_CPU / Prescaler * (1 + TOP)
   OCR1AH = 0x00;
   OCR1AL = 0x00;  // OC1A (SIDETONE) PWM duty-cycle (span defined by ICR).
   OCR1BH = 0x00;
@@ -1371,7 +1368,7 @@ public:
       adc_start(0, false, F_ADC_CONV); admux[0] = ADMUX; admux[1] = ADMUX;
     }
     timer2_start(F_SAMP_RX);
-    timer1_start(F_SAMP_RX);
+    timer1_start(78125);
   }
   
   void start_tx()
@@ -1385,7 +1382,7 @@ public:
     amp = 0;  // initialize
     adc_start(2, true, F_ADC_CONV);
     timer2_start(F_SAMP_TX);
-    timer1_start(39250);
+    timer1_start(78125);
     //if(!vox_enable) txen(true);
   }
 

README.md

@@ -25,7 +25,7 @@ pe1nnz@amsat.org
 - **Multiband** support <sup>[note 1](#note1)</sup>
 - Software-based **VOX** that can be used as **fast Full Break-In** (QSK operation) or assist in RX/TX switching for operating digital modes (no CAT or PTT interface required)
 - **Simple easy to install modification** with only **6 component changes and 4 wires** to implement a basic SSB transceiver
-- Firmware is **open source** through an Arduino Sketch, it allows experimentation, new features can be easily added, contributions can be shared via Github repository QCX-SSB
+- Firmware is **open source** through an Arduino Sketch, it allows experimentation, new features can be easily added, contributions can be shared via Github repository QCX-SSB, about 2000 lines of code
 - Completely **digital and software-based** SSB transmit-stage (**no additional circuitry needed**, except for the audio-in circuit)
 - **ATMEGA328P signal processing:** samples audio-input and reconstruct a SSB-signal by controlling the _phase of the SI5351 PLL_ (through tiny frequency changes over 800kbits/s I2C) and the _amplitude of the PA_ (through PWM of the PA key-shaping circuit).
 - **Lean and low-cost SSB transceiver design**: because of the EER/Polar-transmitter class-E stage it is **highly power-efficient** (no bulky heatsinks required), and has a **simple design** (no complex balanced linear power amplifier required)
@@ -33,7 +33,7 @@ pe1nnz@amsat.org
 - Possibility to extend the QCX analog phasing stage with a **DSP stage**
 - Could replace the QCX analog phasing stage completely with a **digital SDR receiver stage**, taking away the need for the manual side-band rejection adjustment procedure and delivering DSP features such as the joy of having a **AGC, adjustable CW/SSB filters**.
 - A theoretical **digital receiver dynamic range of 83dB** at 2.4kHz BW.  (1 dB) Compression point (at -126dBm sensitivity): -44dBm/1mV (for in-band signal); -4dBm/160mV (for signal at 15kHz offset); 19dBm/2V (for signal at 100kHz offset or more).
-- Switchable attenuator steps: 0dB, -13dB, -20dB, -33dB
+- Switchable RF/IF attenuator steps: 0dB, -13dB, -20dB, -33dB
 - SDR implementation **simplifies** the receiver heaviliy and **shaves off roughly 30% of the components** from the original QCX design while adding new and improving existing features. On a new QCX build: 46 components less to be installed, 8 component design changes, 9 additional wires.
 - Can be used as alternate firmware on an unmodified QCX.