Added (draw.io) block-diagram.

README.md

@@ -144,7 +144,8 @@ On startup, the transceiver is performing a self-test. It is checking the supply
 
 
 ## Technical Description:
-The principle of operation is depicted in the following video-fragment: [Opzij] (in Dutch; [lyrics])
+The principle of operation is depicted in the following video-fragment: [Opzij] (in Dutch; [lyrics])... :-)  jokes aside; below the block diagram of the QCX-SSB and SDR transceiver:
+![block diagram](block.png)
 
 For SSB reception, the QCX analog phasing receiver stage is replaced with a digital SDR stage; this means that the phase shifting op-amp IC6 is changed into a regular amplifier and whereby the individual I and Q outputs are directly fed into the ATMEGA328P ADC inputs for signal processing. The ATMEGA328P will over-sample the ADC input at a 32kHz sample-rate and perform a phase-shift by means of a Hilbert-transform and summing the result to obtain side-band rejection; it will also perform CW or SSB filtering and provide an AGC function. Since the phase-shifting network and analog CW filter are no used, about 30% of the components can be left out; by combining the function of IC7B into IC6A another op-amp can be saved. The ADC inputs are low-pass filtered (-40dB/decade roll-off at 1.5kHz cut-off) to prevent aliasing and input are biased with a 1.1V analog reference voltage to obtain additional sensitivity and dynamic range. With the 10-bit ADCs and a 4x over-sampling rate, a theoretical dynamic range of 72dB can be obtained in 2.4kHz SSB bandwidth. LSB/USB mode switching is done by changing the 90 degree phase shift on the CLK1/CLK2 signals of the SI5351 PLL.