kopia lustrzana https://github.com/kamocat/uSDX
73 wiersze
2.2 KiB
C
73 wiersze
2.2 KiB
C
/*
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* si5351.h
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*
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* Created on: Jul 8, 2020
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* Author: marshal
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*/
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#ifndef SI5351_H_
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#define SI5351_H_
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#include "hal.h"
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struct synth{
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float carrier; //< in Hz
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int32_t baseband; //< 15.16 fixed-point, in Hz
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struct { //< Calculated values for setting registers
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uint64_t pll:38; //< 11.27 fixed-point for PLL multipler
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uint64_t synth:38; //< 11.27 fixed-point for Synth Divider
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uint8_t divide:2; //< 4-bit field for extra divider settings
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int8_t shift; //< Shift value for scaling the baseband frequency
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}reg;
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uint8_t channel:2; //< Supports four channels - increase bit width if more are desired
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uint8_t PLLx:1; //< 0 is PLLA, 1 is PLLB
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uint8_t phase:7; //< Phase offset, in increments of 1/(vxco*4) seconds
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};
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/** Sets the PLL and Clock in the synth config
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*
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* Does not reset the clock setup
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*/
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void synthInit(struct synth * cfg, uint8_t channel, uint8_t pll);
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/** Starts the clock output
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*
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*/
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void synthStart(struct synth * cfg);
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/** Sets the clock to the desired frequency
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*
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* Calls synthWriteConfig internally
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*/
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void synthSetCarrier(struct synth * cfg, float carrier);
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/** Adjusts the clock by a certain frequency
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*
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* This is much faster than synthSetCarrier, but has limited range.
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* Also, the frequency may have error due to linearization.
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*
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* @param baseband 15.16 fixed-point value, in Hz
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*/
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void synthSetBaseband(struct synth * cfg, int32_t baseband);
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/** Writes a and b parameters for a pll multiplier or divider
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*/
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void synthWriteParam(uint8_t reg, uint64_t val, uint8_t div);
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/** Writes config to device
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*
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* This may be useful for restoring configurations without recalculating
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*/
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void synthWriteConfig(struct synth * cfg);
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/** Sets the initial phase offset
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*
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* Note that this has limited resolution and range. The maximum delay is 31.75x the PLL clock period,
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* which means you will have a difficult time getting a 90-degree phase shift on the 80m band.
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*/
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void synthSetPhase(struct synth * cfg, float degrees);
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/** Stops the clock output
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*
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* This may be helpful for power saving
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* Unless otherwise configured, clock output will be held low while stopped
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*/
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void synthStop(struct synth * cfg);
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#endif /* SI5351_H_ */
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