kopia lustrzana https://github.com/kamocat/uSDX
116 wiersze
3.4 KiB
C
116 wiersze
3.4 KiB
C
/*
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* si5351.c
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*
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* Created on: Jul 7, 2020
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* Author: marshal
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*/
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#include "si5351.h"
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#include "../trig.h"
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const uint8_t si5351 = 0x60; // i2c address
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void pll_reset(uint8_t PLLx){
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uint8_t buf[2];
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buf[0]=177;
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buf[1]=PLLx ? 0x80 : 0x20;
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i2cMasterTransmitTimeout(&I2CD1, si5351, buf, 2, NULL, 0, TIME_MS2I(100));
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}
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void synthStart(struct synth * cfg){
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uint8_t buf[2];
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buf[0]=cfg->channel+16;
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buf[1]=cfg->PLLx ? 0x2F : 0x1F;
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i2cMasterTransmitTimeout(&I2CD1, si5351, buf, 2, NULL, 0, TIME_MS2I(100));
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pll_reset(cfg->PLLx);
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}
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void synthStop(struct synth * cfg){
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uint8_t buf[2];
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buf[0]=cfg->channel+16;
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buf[1]=0x80;
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i2cMasterTransmitTimeout(&I2CD1, si5351, buf, 2, NULL, 0, TIME_MS2I(100));
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}
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void synthSetPhase(struct synth * cfg, float degrees){
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if(degrees < 0)
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degrees += 360; // Only allow positive delay
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//FIXME: If more than 180 degrees, we should use the clock invert feature
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// Since the delay is before the divider, we scale by the divide ratio
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degrees *= ((1./360)*(cfg->reg.synth))/(1<<25);
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cfg->phase = degrees > 127 ? 127 : degrees;
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uint8_t buf[2];
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buf[0]=cfg->channel+165;
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buf[1]=cfg->phase;
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i2cMasterTransmitTimeout(&I2CD1, si5351, buf, 2, NULL, 0, TIME_MS2I(100));
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pll_reset(cfg->PLLx);
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}
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void synthWriteParam(uint8_t reg, uint64_t val, uint8_t div){
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uint8_t buf[9];
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buf[0]=reg*8+26;
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buf[1]=0xFF; // denominator is always 0xFFFFF
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buf[2]=0xFF;
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buf[3]=val>>36 & 0x03;
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buf[3]|=div<<4;
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buf[4]=val>>28;
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buf[5]=val>>20;
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buf[6]=val>>16 | 0xF0;
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buf[7]=val>>8;
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buf[8]=val;
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i2cMasterTransmitTimeout(&I2CD1, si5351, buf, 9, NULL, 0, TIME_MS2I(100));
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}
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void synthWriteConfig(struct synth * cfg){
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synthWriteParam(cfg->PLLx, cfg->reg.pll, 0);
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synthWriteParam(cfg->channel+2, cfg->reg.synth, cfg->reg.divide);
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}
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void synthSetCarrier(struct synth * cfg, float carrier){
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// Calculate PLL and Multisynth values
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const double xtal = 27e6;
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double pll = 27; // Good starting value to put vxco at 750MHz
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double div = xtal * pll / carrier;
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double delta = div - (xtal*pll)/(carrier+1); // Linearized change per Hz
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int8_t delta_shift = round(log2(delta)); // round to nearest power of 2
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double delta2 = (0x40000000>>delta_shift)*(1.0/0x40000000U); // (Computing a negative power of 2)
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div *= delta2/delta;
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div = round(div/2)*2+1; // Minimize chance of rollover
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pll = carrier * div / xtal; // Adjust pll to match
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// If desired frequency is very low, we need to use the additional divider register
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uint8_t div2;
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for(div2=0; div>2048; ++div2){
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div *= 0.5;
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--delta_shift;
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}
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// Store values into config
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const uint32_t fixed_shift = 1<<27; //For shifting values to fixed-point
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cfg->reg.pll = pll * fixed_shift;
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cfg->reg.synth = div * fixed_shift;
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cfg->reg.shift = delta_shift;
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cfg->reg.divide = div2;
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synthWriteConfig(cfg);
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}
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void synthSetBaseband(struct synth * cfg, int32_t baseband){
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int32_t diff = baseband - cfg->baseband;
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diff >>= cfg->reg.shift;
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cfg->reg.synth -= diff;
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uint32_t val = cfg->reg.synth;
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uint8_t buf[5];
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/* This could potentially be sped up by dropping the last byte */
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buf[0]=8*(cfg->channel)+46;
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buf[1]=val>>20;
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buf[2]=(val>>16) | 0xF0;
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buf[3]=val>>8;
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buf[4]=val;
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i2cMasterTransmitTimeout(&I2CD1, si5351, buf, 5, NULL, 0, TIME_MS2I(100));
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}
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void synthInit(struct synth * cfg, uint8_t channel, uint8_t pll){
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cfg->channel = channel;
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cfg->PLLx = pll;
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}
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