kopia lustrzana https://github.com/ArjanteMarvelde/uWFG-Pico
212 wiersze
10 KiB
C
212 wiersze
10 KiB
C
/*
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* gen.c
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*
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* Created: Dec 2021
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* Author: Arjan te Marvelde
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*
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* The generation of the output.
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*
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* The output is generated by simply taking an array of samples which is repeatedly output on a set of GPIO pins.
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* To accomplish highest speed, the generator utilizes the Pico PIO feature, which enables outputting new data
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* every system clock cycle.
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* A PIO consists of common instruction memory, that may contain several PIO programs at different offsets. These
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* programs can then be executed by each of 4 statemachines contained in the PIO. Each SM has its own I/O FIFOs to
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* the system, its own GPIO interfacing and a set of internal registers to let the program do its work.
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* The SM clock rate is derived from the system clock by means of a divider, [1.0 - 65536.0], in 1/256 steps.
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*
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* For the waveform generator, a simple PIO program is defined that moves a word from the SM TX fifo into the SM output
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* shift register (OSR), and then clocks out one byte on the designated pins on every SM clock tick.
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* A separate SM is allocated for each output channel, thus providing two independent outputs.
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*
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* Two DMA channels are used for each output, chained in a loop to keep the flow going.
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* The dma_data channel transfers from *buffer to the PIO TX FIFO (paced by the PIO DREQ signal), chained to dma_ctrl channel.
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* The dma_ctrl channel transfers the buffer address back into the dma_data channel read_addr, and chains back to dma_data.
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From RP2040 datasheet, DMA Control / Status word layout:
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0x80000000 [31] : AHB_ERROR (0): Logical OR of the READ_ERROR and WRITE_ERROR flags
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0x40000000 [30] : READ_ERROR (0): If 1, the channel received a read bus error
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0x20000000 [29] : WRITE_ERROR (0): If 1, the channel received a write bus error
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0x01000000 [24] : BUSY (0): This flag goes high when the channel starts a new transfer sequence, and low when the...
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0x00800000 [23] : SNIFF_EN (0): If 1, this channel's data transfers are visible to the sniff hardware, and each...
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0x00400000 [22] : BSWAP (0): Apply byte-swap transformation to DMA data
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0x00200000 [21] : IRQ_QUIET (0): In QUIET mode, the channel does not generate IRQs at the end of every transfer block
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0x001f8000 [20:15] : TREQ_SEL (0): Select a Transfer Request signal
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0x00007800 [14:11] : CHAIN_TO (0): When this channel completes, it will trigger the channel indicated by CHAIN_TO
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0x00000400 [10] : RING_SEL (0): Select whether RING_SIZE applies to read or write addresses
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0x000003c0 [9:6] : RING_SIZE (0): Size of address wrap region
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0x00000020 [5] : INCR_WRITE (0): If 1, the write address increments with each transfer
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0x00000010 [4] : INCR_READ (0): If 1, the read address increments with each transfer
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0x0000000c [3:2] : DATA_SIZE (0): Set the size of each bus transfer (byte/halfword/word)
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0x00000002 [1] : HIGH_PRIORITY (0): HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in...
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0x00000001 [0] : EN (0): DMA Channel Enable
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* DMA channel CTRL words, assuming DMA CH0..3 and PIO0 fifo TX0 and TX1:
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* CH0: 0x0020081f (IRQ_QUIET=0x1, TREQ_SEL=0x00, CHAIN_TO=1, INCR_WRITE=0, INCR_READ=1, DATA_SIZE=2, HIGH_PRIORITY=1, EN=1)
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* CH1: 0x003f800f (IRQ_QUIET=0x1, TREQ_SEL=0x3f, CHAIN_TO=0, INCR_WRITE=0, INCR_READ=0, DATA_SIZE=2, HIGH_PRIORITY=1, EN=1)
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* CH2: 0x0020981f (IRQ_QUIET=0x1, TREQ_SEL=0x01, CHAIN_TO=3, INCR_WRITE=0, INCR_READ=1, DATA_SIZE=2, HIGH_PRIORITY=1, EN=1)
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* CH3: 0x003f900f (IRQ_QUIET=0x1, TREQ_SEL=0x3f, CHAIN_TO=2, INCR_WRITE=0, INCR_READ=0, DATA_SIZE=2, HIGH_PRIORITY=1, EN=1)
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*/
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#include <stdio.h>
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#include <string.h>
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#include <math.h>
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#include "pico/stdlib.h"
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#include "pico/sem.h"
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#include "hardware/i2c.h"
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#include "hardware/gpio.h"
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#include "hardware/timer.h"
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#include "hardware/clocks.h"
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#include "hardware/irq.h"
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#include "hardware/pio.h"
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#include "hardware/dma.h"
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#include "wfgout.pio.h"
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#include "gen.h"
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#define FSYS 1.25e8f
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/*
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* Global variables that hold the active parameters for both channels
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*/
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uint a_sm = 0, b_sm = 1; // PIO0 state machine numbers
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uint32_t *a_buffer, *b_buffer; // Buffer address
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uint32_t a_buflen, b_buflen; // Buffer length (in 32bit words)
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float a_freq, b_freq; // Buffer frequency
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/*
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* DMA channel definitions
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*/
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#define DMA_ADATA 0
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#define DMA_ACTRL 1
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#define DMA_BDATA 2
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#define DMA_BCTRL 3
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#define DMA_ADATA_C 0x0020081f
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#define DMA_ACTRL_C 0x003f800f
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#define DMA_BDATA_C 0x0020981f
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#define DMA_BCTRL_C 0x003f900f
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/*
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* Define initial waveforms
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*/
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#define A_FREQ 1.0e6f
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#define A_BUFLEN 4
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uint32_t a_buf[A_BUFLEN] = {0x00000000, 0x00000000, 0xffffffff, 0xffffffff};
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#define B_FREQ 1.0e6f
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#define B_BUFLEN 4
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uint32_t b_buf[B_BUFLEN] = {0x00000000, 0x00000000, 0xffffffff, 0xffffffff};
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/*
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* Unit initialization, only call this once!
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* This function initializes the WFG parameters, the PIO statemachines and teh DMA channels.
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*/
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void wfg_init()
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{
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float fsam;
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float div;
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uint i;
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uint offset;
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for (i=0; i<8; i++) // Initialize the used pins
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{
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gpio_set_function(PINA+i, GPIO_FUNC_PIO0); // Function: PIO
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gpio_set_slew_rate(PINA+i, GPIO_SLEW_RATE_FAST); // No slewrate limiting
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gpio_set_drive_strength(PINA+i, GPIO_DRIVE_STRENGTH_8MA); // Drive 8mA (might increase to 12)
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gpio_set_function(PINB+i, GPIO_FUNC_PIO0);
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gpio_set_slew_rate(PINB+i, GPIO_SLEW_RATE_FAST);
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gpio_set_drive_strength(PINB+i, GPIO_DRIVE_STRENGTH_8MA);
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}
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a_buffer = &a_buf[0]; // Initialize active parameters
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a_buflen = A_BUFLEN;
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a_freq = A_FREQ;
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b_buffer = &b_buf[0];
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b_buflen = B_BUFLEN;
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b_freq = B_FREQ;
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offset = pio_add_program(pio0, &wfgout_program); // Move program to PIO space and obtain offset
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fsam = a_freq * 4.0 * (float)a_buflen; // Required sample rate = samples in buffer * freq
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div = FSYS / fsam; // Ratio FSYS and sampleclock
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if (div < 1.0) div=1.0; // Cannot get higher than FSYS
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wfgout_program_init(pio0, a_sm, offset, (uint)PINA, (uint)8, div); // Invoke PIO initializer (see wfgout.pio.h)
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fsam = b_freq * 4.0 * (float)b_buflen; // Required sample rate = samples in buffer * freq
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div = FSYS / fsam; // Ratio FSYS and sampleclock
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if (div < 1.0) div=1.0; // Cannot get higher than FSYS
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wfgout_program_init(pio0, b_sm, offset, (uint)PINB, (uint)8, div); // Invoke PIO initializer (see wfgout.pio.h)
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dma_hw->ch[DMA_ADATA].read_addr = (io_rw_32)a_buffer; // Read from waveform buffer
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dma_hw->ch[DMA_ADATA].write_addr = (io_rw_32)&pio0->txf[a_sm]; // Write to PIO TX fifo
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dma_hw->ch[DMA_ADATA].transfer_count = a_buflen; // Nr of 32 bit words to transfer
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dma_hw->ch[DMA_ADATA].al1_ctrl = DMA_ADATA_C; // Write ctrl word without starting the DMA
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dma_hw->ch[DMA_ACTRL].read_addr = (io_rw_32)&a_buffer; // Read from waveform buffer address reference
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dma_hw->ch[DMA_ACTRL].write_addr = (io_rw_32)&dma_hw->ch[DMA_ADATA].read_addr; // Write to data channel read address
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dma_hw->ch[DMA_ACTRL].transfer_count = 1; // One word to transfer
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dma_hw->ch[DMA_ACTRL].ctrl_trig = DMA_ACTRL_C; // Write ctrl word and start DMA
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dma_hw->ch[DMA_BDATA].read_addr = (io_rw_32)b_buffer; // Read from waveform buffer
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dma_hw->ch[DMA_BDATA].write_addr = (io_rw_32)&pio0->txf[b_sm]; // Write to PIO TX fifo
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dma_hw->ch[DMA_BDATA].transfer_count = b_buflen; // Nr of 32 bit words to transfer
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dma_hw->ch[DMA_BDATA].al1_ctrl = DMA_BDATA_C; // Write ctrl word without starting the DMA
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dma_hw->ch[DMA_BCTRL].read_addr = (io_rw_32)&b_buffer; // Read from waveform buffer address reference
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dma_hw->ch[DMA_BCTRL].write_addr = (io_rw_32)&dma_hw->ch[DMA_BDATA].read_addr; // Write to data channel read address
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dma_hw->ch[DMA_BCTRL].transfer_count = 1; // One word to transfer
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dma_hw->ch[DMA_BCTRL].ctrl_trig = DMA_BCTRL_C; // Write ctrl word and start DMA
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}
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/*
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* This function is the main API of the generator.
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* Parameters are a waveform samples buffer, its length and a desired frequency.
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* It is assumed that the buffer contains one wave, and the frequency will be maximized at Fsys/buflen
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*/
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void wfg_play(int output, wfg_t *wave)
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{
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uint32_t clkdiv; // 31:16 int part, 15:8 frac part (in 1/256)
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float div;
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div = FSYS/((wave->freq)*(wave->len)*4.0); // Calculate divider
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if (div < 1.0) div=1.0;
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clkdiv = (uint32_t)div; // Extract integer part
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div = (div - clkdiv)*256; // Fraction x 256
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clkdiv = (clkdiv << 8) + (uint32_t)div; // Add 8bit integer part of fraction
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clkdiv = clkdiv << 8; // Final shift to match required format
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if (output)
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{
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b_buffer = wave->buf;
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b_buflen = wave->len;
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b_freq = wave->freq;
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dma_hw->ch[DMA_BDATA].read_addr = (io_rw_32)b_buffer; // Read from waveform buffer
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dma_hw->ch[DMA_BDATA].write_addr = (io_rw_32)&pio0->txf[b_sm]; // Write to PIO TX fifo
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dma_hw->ch[DMA_BDATA].transfer_count = b_buflen; // Nr of 32 bit words to transfer
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dma_hw->ch[DMA_BDATA].al1_ctrl = DMA_BDATA_C; // Write ctrl word without starting the DMA
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dma_hw->ch[DMA_BCTRL].read_addr = (io_rw_32)&b_buffer; // Read from waveform buffer address reference
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dma_hw->ch[DMA_BCTRL].write_addr = (io_rw_32)&dma_hw->ch[DMA_BDATA].read_addr; // Write to data channel read address
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dma_hw->ch[DMA_BCTRL].transfer_count = 1; // One word to transfer
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dma_hw->ch[DMA_BCTRL].ctrl_trig = DMA_BCTRL_C; // Write ctrl word and start DMA
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pio0_hw->sm[b_sm].clkdiv = (io_rw_32)clkdiv; // Set new value
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pio_sm_clkdiv_restart(pio0, b_sm); // Restart clock
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}
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else
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{
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a_buffer = wave->buf;
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a_buflen = wave->len;
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a_freq = wave->freq;
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dma_hw->ch[DMA_ADATA].read_addr = (io_rw_32)a_buffer; // Read from waveform buffer
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dma_hw->ch[DMA_ADATA].write_addr = (io_rw_32)&pio0->txf[a_sm]; // Write to PIO TX fifo
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dma_hw->ch[DMA_ADATA].transfer_count = a_buflen; // Nr of 32 bit words to transfer
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dma_hw->ch[DMA_ADATA].al1_ctrl = DMA_ADATA_C; // Write ctrl word without starting the DMA
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dma_hw->ch[DMA_ACTRL].read_addr = (io_rw_32)&a_buffer; // Read from waveform buffer address reference
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dma_hw->ch[DMA_ACTRL].write_addr = (io_rw_32)&dma_hw->ch[DMA_ADATA].read_addr; // Write to data channel read address
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dma_hw->ch[DMA_ACTRL].transfer_count = 1; // One word to transfer
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dma_hw->ch[DMA_ACTRL].ctrl_trig = DMA_ACTRL_C; // Write ctrl word and start DMA
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pio0_hw->sm[a_sm].clkdiv = (io_rw_32)clkdiv; // Set new value
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pio_sm_clkdiv_restart(pio0, a_sm); // Restart clock
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}
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}
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