kopia lustrzana https://github.com/ArjanteMarvelde/uSDR-pico
AGC added
ArjanteMarvelde
rodzic
2701751e00
commit
9e4cda73a0
190
dsp.c
190
dsp.c
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@ -46,10 +46,10 @@
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* ADC is 12 bit, so resolution is by definition 4096
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* To eliminate undefined behavior we clip off the upper 4 sample bits.
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*/
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#define DAC_RANGE 250
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#define DAC_BIAS DAC_RANGE/2
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#define DAC_RANGE 256
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#define DAC_BIAS (DAC_RANGE/2)
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#define ADC_RANGE 4096
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#define ADC_BIAS ADC_RANGE/2
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#define ADC_BIAS (ADC_RANGE/2)
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/*
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* Callback timeout and inter-core FIFO commands.
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@ -62,9 +62,18 @@
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#define DSP_RX 2
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/*
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* AGC reference level is log2(64) = 6, where 64 is the MSB of half DAC_RANGE
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* 1/AGC_DECAY and 1/AGC_ATTACK are multipliers before agc_gain value integrator
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* These values should ultimately be set by the HMI.
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*/
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#define AGC_REF 6
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#define AGC_DECAY 1024
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#define AGC_ATTACK 128
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/*
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* Low pass filters Fc=3, 7 and 15 kHz (see http://t-filter.engineerjs.com/)
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* for sample rates 62.500 , 31.250 or 15.625 kHz , stopband is appr -40dB
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* Settings: sample rates 62500, 31250 or 15625 Hz, stopband -40dB, passband ripple 5dB
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* Note: 8 bit precision, so divide sum by 256
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*/
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int16_t lpf3_62[15] = { 3, 3, 5, 7, 9, 10, 11, 11, 11, 10, 9, 7, 5, 3, 3}; // Pass: 0-3000, Stop: 6000-31250
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@ -79,6 +88,12 @@ volatile uint32_t fifo_overrun, fifo_rx, fifo_tx, fifo_xx, fifo_incnt;
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volatile bool tx_enabled;
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/*
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* Some macro's
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* See Alpha Max plus Beta Min algorithm for MAG (vector length)
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*/
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#define ABS(x) ((x)<0?-(x):(x))
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#define MAG(i,q) (ABS(i)>ABS(q) ? ABS(i)+((3*ABS(q))>>3) : ABS(q)+((3*ABS(i))>>3))
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/*
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@ -88,61 +103,85 @@ volatile bool tx_enabled;
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*/
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volatile uint16_t adc_result[3];
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volatile int adc_next; // Remember which ADC the result is from
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uint32_t adc_count=0;
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uint32_t adc_count=0; // Debugging
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void adcfifo_handler(void)
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{
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adc_result[adc_next] = adc_fifo_get();
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adc_next = adc_hw->cs;
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adc_next = (adc_next >> ADC_CS_AINSEL_LSB) & 3; // Only 0, 1 and are valid
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adc_result[adc_next] = adc_fifo_get(); // Get result from fifo
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adc_next = adc_hw->cs; // Update adc_next with HW CS register
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adc_next = (adc_next >> ADC_CS_AINSEL_LSB) & 3; // Shift and Mask: Only 0, 1 and 2 are valid numbers
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adc_count++;
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}
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/*
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* CORE1:
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* Execute RX branch signal processing, max time to spend is <16us !
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* No ADC sample interleaving, take both I and Q channels.
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* Execute RX branch signal processing, max time to spend is <16us, i.e. rate is 62.5 kHz
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* No ADC sample interleaving, read both I and Q channels.
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* The delay is only 2us per conversion, which causes less distortion than interpolation of samples.
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*/
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volatile int16_t i_s_raw[15], q_s_raw[15]; // Raw I/Q samples minus DC bias
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volatile uint16_t peak=0; // Peak detector running value
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volatile int16_t agc_gain=0, agc_accu=0; // AGC gain (shift value), log peak level integrator
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volatile int16_t i_s[15], q_s[15]; // Filtered I/Q samples
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volatile int16_t i_dc, q_dc; // DC bias for I/Q channel
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volatile int rx_cnt=0; // Decimation counter
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bool rx(void)
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{
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int16_t q_sample, i_sample;
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int16_t q_sample, i_sample, a_sample;
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int32_t q_accu, i_accu;
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int16_t qh;
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int i;
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uint16_t i;
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int16_t k;
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/*** SAMPLING ***/
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i_sample = adc_result[0]; // Take last ADC 0 result
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q_sample = adc_result[1]; // Take last ADC 1 result
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/*
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* Shift in I and Q raw samples
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* Remove DC and store new sample
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* IIR filter: dc = a*sample + (1-a)*dc where a = 1/128
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* Amplitude of samples should fit inside [-2048, 2047]
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*/
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q_sample = (q_sample&0x0fff) - ADC_BIAS; // Clip to 12 bits and subtract mid-range
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q_dc += (q_sample>>7) - (q_dc>>7); // then IIR running average
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q_sample -= q_dc; // and subtract DC
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i_sample = (i_sample&0x0fff) - ADC_BIAS; // Same for I sample
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i_dc += (i_sample>>7) - (i_dc>>7);
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i_sample -= i_dc;
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/*
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* Shift with AGC feedback from AUDIO GENERATION stage
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* This behavior in essence is exponential, complementing the logarithmic peak detector
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*/
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if (agc_gain > 0)
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{
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q_sample <<= agc_gain;
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i_sample <<= agc_gain;
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}
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else if (agc_gain < 0)
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{
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q_sample >>= -agc_gain;
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i_sample >>= -agc_gain;
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}
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/*
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* Shift-in I and Q raw samples
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*/
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for (i=0; i<14; i++)
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{
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q_s_raw[i] = q_s_raw[i+1]; // Q raw samples shift register
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i_s_raw[i] = i_s_raw[i+1]; // I raw samples shift register
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}
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q_s_raw[14] = q_sample; // Store in shift registers
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i_s_raw[14] = i_sample;
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/*
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* Remove DC and store new sample
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* IIR filter: dc = a*sample + (1-a)*dc where a = 1/128
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*/
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q_sample = (q_sample&0x0fff) - ADC_BIAS; // Clip and subtract mid-range
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q_dc += (q_sample>>7) - (q_dc>>7); // then IIR running average
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q_s_raw[14] = q_sample - q_dc; // and subtract DC, store in shift register
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i_sample = (i_sample&0x0fff) - ADC_BIAS;
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i_dc += (i_sample>>7) - (i_dc>>7);
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i_s_raw[14] = i_sample - i_dc;
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/*
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* Low pass filter + decimation
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*/
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rx_cnt = (rx_cnt+1)&3; // Calculate only every fourth sample
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if (rx_cnt>0) return true;
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if (rx_cnt>0) return (true); // So net sample time is 64us or 15.625 kHz
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for (i=0; i<14; i++) // Shift decimated samples
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{
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@ -153,50 +192,68 @@ bool rx(void)
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i_accu = 0;
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for (i=0; i<15; i++) // Low pass FIR filter
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{
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q_accu += (int32_t)q_s_raw[i]*lpf3_62[i]; // Fc=3kHz, at 62.5 kHz sampling
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i_accu += (int32_t)i_s_raw[i]*lpf3_62[i]; // Fc=3kHz, at 62.5 kHz sampling
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q_accu += (int32_t)q_s_raw[i]*lpf3_62[i]; // Fc=3kHz, at 62.5 kHz raw sampling
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i_accu += (int32_t)i_s_raw[i]*lpf3_62[i]; // Fc=3kHz, at 62.5 kHz raw sampling
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}
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q_s[14] = q_accu >> 8;
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i_s[14] = q_accu >> 8;
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q_accu >>= 8;
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i_accu >>= 8;
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q_s[14] = q_accu;
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i_s[14] = i_accu;
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/*** DEMODULATION ***/
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/*
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* From here things get dependent on receive mode.
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* We assume USB for now, e.g. supporting FT8
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*/
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/*
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* Classic Hilbert transform 15 taps, 12 bits (see Iowa Hills)
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* USB demodulate: I[7] - Qh,
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* Qh is Classic Hilbert transform 15 taps, 12 bits (see Iowa Hills calculator)
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*/
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q_accu = (q_s[0]-q_s[14])*315L + (q_s[2]-q_s[12])*440L + (q_s[4]-q_s[10])*734L + (q_s[6]-q_s[ 8])*2202L;
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qh = q_accu >> 12;
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a_sample = i_s[7] - qh;
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/*
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* SSB demodulate: I[7] - Qh
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* Add DAC_BIAS offset, Clip to DAC_RANGE and send to audio DAC output
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* AM demodulate: sqrt(sqr(i)+sqr(q))
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* Approximated with MAG(i,q)
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*/
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q_sample = ((i_s[7] - qh)/2)+DAC_BIAS;
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q_sample = (q_sample>DAC_RANGE)?DAC_RANGE:((q_sample<0)?0:q_sample);
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pwm_set_chan_level(dac_audio, PWM_CHAN_A, q_sample);
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// a_sample = MAG(i_s[14], q_s[14]);
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/*** AUDIO GENERATION ***/
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/*
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* AGC, peak detector
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* Sample speed is still 15625 per second
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*/
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peak = (127*peak + (ABS(a_sample)))>>7; // Running average level detect, a=1/128
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k=0; i=peak; // Logarithmic peak detection
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if (i&0xff00) {k+=8; i>>=8;} // k=log2(peak), find highest bit set
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if (i&0x00f0) {k+=4; i>>=4;}
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if (i&0x000c) {k+=2; i>>=2;}
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if (i&0x0002) {k+=1;}
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agc_accu += (k - AGC_REF); // Add difference with target to integrator (Acc += Xn - R)
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if (agc_accu > AGC_ATTACK) // Attack time, gain correction in case of high level
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{
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agc_gain--; // Decrease gain
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agc_accu -= AGC_ATTACK; // Reset integrator
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} else if (agc_accu < -(AGC_DECAY)) // Decay time, gain correction in case of low level
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{
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agc_gain++; // Increase gain
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agc_accu += AGC_DECAY; // Reset integrator
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}
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/*
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* Scale and clip output,
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* Send to audio DAC output
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*/
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a_sample += DAC_BIAS; // Add bias level
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if (a_sample > DAC_RANGE) // Clip to DAC range
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a_sample = DAC_RANGE;
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else if (a_sample<0)
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a_sample = 0;
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pwm_set_chan_level(dac_audio, PWM_CHAN_A, a_sample);
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/* AGC ALGORITHM
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if(m_Peak>m_AttackAve) //if power is rising (use m_AttackRiseAlpha time constant)
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m_AttackAve = (1.0-m_AttackRiseAlpha)*m_AttackAve + m_AttackRiseAlpha*m_Peak;
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else //else magnitude is falling (use m_AttackFallAlpha time constant)
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m_AttackAve = (1.0-m_AttackFallAlpha)*m_AttackAve + m_AttackFallAlpha*m_Peak;
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if(m_Peak>m_DecayAve) //if magnitude is rising (use m_DecayRiseAlpha time constant)
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{
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m_DecayAve = (1.0-m_DecayRiseAlpha)*m_DecayAve + m_DecayRiseAlpha*m_Peak;
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m_HangTimer = 0; //reset hang timer
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}
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else
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{ //here if decreasing signal
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if(m_HangTimer<m_HangTime)
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m_HangTimer++; //just inc and hold current m_DecayAve
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else //else decay with m_DecayFallAlpha which is RELEASE_TIMECONST
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m_DecayAve = (1.0-m_DecayFallAlpha)*m_DecayAve + m_DecayFallAlpha*m_Peak;
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}
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*/
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return true;
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}
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@ -290,13 +347,13 @@ void dsp_loop()
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gpio_set_function(21, GPIO_FUNC_PWM); // GP21 is PWM for Q DAC (Slice 2, Channel B)
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dac_iq = pwm_gpio_to_slice_num(20); // Get PWM slice for GP20 (Same for GP21)
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pwm_set_clkdiv_int_frac (dac_iq, 1, 0); // clock divide by 1
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pwm_set_wrap(dac_iq, DAC_RANGE); // Set cycle length
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pwm_set_wrap(dac_iq, DAC_RANGE-1); // Set cycle length
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pwm_set_enabled(dac_iq, true); // Set the PWM running
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gpio_set_function(22, GPIO_FUNC_PWM); // GP22 is PWM for Audio DAC (Slice 3, Channel A)
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dac_audio = pwm_gpio_to_slice_num(22); // Find PWM slice for GP22
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pwm_set_clkdiv_int_frac (dac_audio, 1, 0); // clock divide by 1
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pwm_set_wrap(dac_audio, DAC_RANGE); // Set cycle length
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pwm_set_wrap(dac_audio, DAC_RANGE-1); // Set cycle length
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pwm_set_enabled(dac_audio, true); // Set the PWM running
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/* Initialize ADCs */
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@ -309,7 +366,7 @@ void dsp_loop()
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adc_next = 0;
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adc_set_round_robin(1+2+4); // Sequence ADC 0-1-2 free running
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adc_fifo_setup(true,false,1,false,false); // IRQ for every result (threshold = 1)
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adc_fifo_setup(true,false,1,false,false); // IRQ for every result (fifo threshold = 1)
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irq_set_exclusive_handler(ADC0_IRQ_FIFO, adcfifo_handler);
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adc_irq_set_enabled(true);
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irq_set_enabled(ADC0_IRQ_FIFO, true);
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@ -359,7 +416,18 @@ bool dsp_callback(struct repeating_timer *t)
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/*
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* CORE0:
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* Initialize dsp context and spawn core1 process
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* Initialize dsp context and spawn CORE1 process
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*
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* Some CORE1 code parts should not run from Flash, but be loaded in SRAM at boot
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* See platform.h for function qualifier macro's
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* for example:
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* void __not_in_flash_func(funcname)(int arg1, float arg2)
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* {
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* }
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*
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* Need to set BUS_PRIORITY of Core 1 to high
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* #include bus_ctrl.h
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* bus_ctrl_hw->priority = BUSCTRL_BUS_PRIORITY_PROC1_BITS; // Set Core 1 prio high
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*/
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void dsp_init()
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{
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2
hmi.c
2
hmi.c
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@ -310,7 +310,7 @@ void hmi_evaluate(void)
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{
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char s[20];
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sprintf(s, "%s %7.1f %c%3d", hmi_o_mode[hmi_sub[HMI_S_MODE]], (double)hmi_freq/1000.0, (tx_enabled?126:127),920);
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sprintf(s, "%s %7.1f %c%3d", hmi_o_mode[hmi_sub[HMI_S_MODE]], (double)hmi_freq/1000.0, (tx_enabled?'T':'R'),920);
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lcd_writexy(0,0,s);
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switch (hmi_state)
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{
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9
si5351.c
9
si5351.c
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@ -53,8 +53,11 @@ MSi: target for mid-band, i.e. Fvco=750MHz
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MSN = MSi*Ri*Fout/Fxtal (should be between 24 and 36)
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Only use MSi even-integers, i.e. d=[4, 6, 8..126], e=0 and f=100000, and set INT bits in reg 22, 23.
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Phase offset MS0 (reg 165) must be 0, MS1 (reg 166) must be equal to MS1 for 90 deg. Set INV bit in reg 17 to add 180 deg.
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NOTE: Phase offsets only work when Ri = 1, this means minimum Fout is 4.762MHz at Fvco = 600MHz
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Quadrature Phase offsets (i.e. delay):
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- Offset for MS0 (reg 165) must be 0 (cosine),
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- Offset for MS1 (reg 166) must be equal to divider MS1 for 90 deg (sine),
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- Set INV bit (reg 17) to add 180 deg.
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NOTE: Phase offsets only work when Ri = 1, this means minimum Fout is 4.762MHz at Fvco = 600MHz. Additional flip/flop dividers are needed to get 80m band frequencies, or Fvco must be tuned below spec.
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@ -265,7 +268,7 @@ void si_setmsi(uint8_t i)
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data[1] = vfo[0].msi;
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i2c_write_blocking(i2c1, I2C_VFO, data, 2, false);
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}
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else
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else // Phase is 0 or 180 deg
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{
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data[0] = SI_CLK1_PHOFF;
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data[1] = 0;
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Reference in New Issue