vtcsec_summit
Conor Patrick 2015-12-31 14:33:04 -05:00
rodzic d7018f1a6f
commit 6a7ac4636e
1 zmienionych plików z 0 dodań i 226 usunięć

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<?xml version="1.0" encoding="utf-8"?>
<!DOCTYPE eagle SYSTEM "eagle.dtd">
<eagle version="6.6.0">
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<description>Silicon Laboratories&lt;p&gt;
Source: http://www.silabs.com&lt;p&gt;
&lt;author&gt;Created by fbleikamp@web.de&lt;/author&gt;</description>
<packages>
<package name="QFN20-C">
<description>&lt;b&gt;QFN20-C with corner pads&lt;/b&gt;&lt;p&gt;
Source: www.silabs.com .. EFM8UB1_DataSheet.pdf</description>
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<symbol name="EFM8UB1X">
<description>&lt;b&gt;EFM8UB1X-QFN20-C with corner pads&lt;/b&gt;&lt;p&gt;
Source: www.silabs.com .. EFM8UB1_DataSheet.pdf</description>
<wire x1="-12.7" y1="22.86" x2="-12.7" y2="-22.86" width="0.254" layer="94"/>
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<text x="-12.7" y="24.13" size="1.778" layer="95">&gt;NAME</text>
<text x="-12.7" y="-25.4" size="1.778" layer="96">&gt;VALUE</text>
<text x="-10.16" y="-18.542" size="1.524" layer="95">GND</text>
<text x="-10.16" y="-21.082" size="1.524" layer="95">GND</text>
<pin name="GND" x="-15.24" y="-15.24" length="short" direction="pwr"/>
<pin name="VDD" x="-15.24" y="15.24" length="short"/>
<pin name="!RST/C2CK" x="-15.24" y="-7.62" length="short" direction="in"/>
<pin name="P0.1" x="12.7" y="17.78" length="short" rot="R180"/>
<pin name="GND@1" x="-15.24" y="-17.78" visible="pad" length="short" direction="pwr"/>
<pin name="GND@2" x="-15.24" y="-20.32" visible="pad" length="short" direction="pwr"/>
<pin name="P0.2" x="12.7" y="15.24" length="short" rot="R180"/>
<pin name="P0.3" x="12.7" y="12.7" length="short" rot="R180"/>
<pin name="P0.4" x="12.7" y="10.16" length="short" rot="R180"/>
<pin name="P0.5" x="12.7" y="7.62" length="short" rot="R180"/>
<pin name="P0.6" x="12.7" y="5.08" length="short" rot="R180"/>
<pin name="P0.7" x="12.7" y="2.54" length="short" rot="R180"/>
<pin name="P1.0" x="12.7" y="-2.54" length="short" rot="R180"/>
<pin name="P0.0" x="12.7" y="20.32" length="short" rot="R180"/>
<pin name="P1.1" x="12.7" y="-5.08" length="short" rot="R180"/>
<pin name="P1.2" x="12.7" y="-7.62" length="short" rot="R180"/>
<pin name="VREGIN" x="-15.24" y="20.32" length="short" direction="pwr"/>
<pin name="P3.1/VBUS" x="12.7" y="-17.78" length="short" rot="R180"/>
<pin name="D+" x="-15.24" y="7.62" length="short"/>
<pin name="D-" x="-15.24" y="2.54" length="short"/>
<pin name="P2.0/C2D" x="12.7" y="-12.7" length="short" rot="R180"/>
</symbol>
</symbols>
<devicesets>
<deviceset name="EFM8UB1-QFN20" prefix="IC" uservalue="yes">
<description>&lt;b&gt;EFM8UB1X-QFN20-C with corner pads&lt;/b&gt;&lt;p&gt;
Source: www.silabs.com .. EFM8UB1_DataSheet.pdf</description>
<gates>
<gate name="G$1" symbol="EFM8UB1X" x="0" y="0"/>
</gates>
<devices>
<device name="" package="QFN20-C">
<connects>
<connect gate="G$1" pin="!RST/C2CK" pad="9"/>
<connect gate="G$1" pin="D+" pad="4"/>
<connect gate="G$1" pin="D-" pad="5"/>
<connect gate="G$1" pin="GND" pad="3"/>
<connect gate="G$1" pin="GND@1" pad="12"/>
<connect gate="G$1" pin="GND@2" pad="TH"/>
<connect gate="G$1" pin="P0.0" pad="2"/>
<connect gate="G$1" pin="P0.1" pad="1"/>
<connect gate="G$1" pin="P0.2" pad="20"/>
<connect gate="G$1" pin="P0.3" pad="19"/>
<connect gate="G$1" pin="P0.4" pad="18"/>
<connect gate="G$1" pin="P0.5" pad="17"/>
<connect gate="G$1" pin="P0.6" pad="16"/>
<connect gate="G$1" pin="P0.7" pad="15"/>
<connect gate="G$1" pin="P1.0" pad="14"/>
<connect gate="G$1" pin="P1.1" pad="13"/>
<connect gate="G$1" pin="P1.2" pad="11"/>
<connect gate="G$1" pin="P2.0/C2D" pad="10"/>
<connect gate="G$1" pin="P3.1/VBUS" pad="8"/>
<connect gate="G$1" pin="VDD" pad="6"/>
<connect gate="G$1" pin="VREGIN" pad="7"/>
</connects>
<technologies>
<technology name=""/>
</technologies>
</device>
</devices>
</deviceset>
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