diff --git a/EFM8UB1_setup_board/EFM8UB1_setup_board.bak b/EFM8UB1_setup_board/EFM8UB1_setup_board.bak new file mode 100644 index 0000000..4718016 --- /dev/null +++ b/EFM8UB1_setup_board/EFM8UB1_setup_board.bak @@ -0,0 +1,307 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:siliconlabs +LIBS:discrete +LIBS:atmel_cryptoauth +LIBS:EFM8UB1_setup_board-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L EFM8UB1 E1 +U 1 1 568B0ED8 +P 5250 3500 +F 0 "E1" H 4850 4100 60 0000 C CNN +F 1 "EFM8UB1" H 4700 4200 60 0000 C CNN +F 2 "footprints:EFM8UB1" H 4750 4000 60 0000 C CNN +F 3 "" H 4750 4000 60 0000 C CNN + 1 5250 3500 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR01 +U 1 1 568B0F0F +P 6100 4500 +F 0 "#PWR01" H 6100 4250 50 0001 C CNN +F 1 "GND" H 6100 4350 50 0000 C CNN +F 2 "" H 6100 4500 50 0000 C CNN +F 3 "" H 6100 4500 50 0000 C CNN + 1 6100 4500 + 1 0 0 -1 +$EndComp +Text GLabel 6100 4350 0 60 Input ~ 0 +GND +Text GLabel 6100 3700 2 60 Input ~ 0 +GND +Text GLabel 4400 3450 0 60 Input ~ 0 +GND +$Comp +L ATECC508A A1 +U 1 1 568B10D2 +P 7750 3700 +F 0 "A1" H 8050 4000 60 0000 C CNN +F 1 "ATECC508A" H 7650 4000 60 0000 C CNN +F 2 "SMD_Packages:SOIC-8-N" H 7350 3950 60 0000 C CNN +F 3 "" H 7350 3950 60 0000 C CNN + 1 7750 3700 + -1 0 0 1 +$EndComp +Wire Wire Line + 6100 4500 6100 4350 +Wire Wire Line + 7150 3550 6100 3550 +Wire Wire Line + 7150 3650 6500 3650 +Wire Wire Line + 6500 3650 6500 3850 +Wire Wire Line + 6500 3850 6100 3850 +Text GLabel 8350 3550 2 60 Input ~ 0 +GND +$Comp +L PWR_FLAG #FLG02 +U 1 1 568B121C +P 4950 5250 +F 0 "#FLG02" H 4950 5345 50 0001 C CNN +F 1 "PWR_FLAG" H 4950 5430 50 0000 C CNN +F 2 "" H 4950 5250 50 0000 C CNN +F 3 "" H 4950 5250 50 0000 C CNN + 1 4950 5250 + -1 0 0 1 +$EndComp +Text GLabel 5250 4300 3 60 Input ~ 0 +C2CK +Text GLabel 5400 4300 3 60 Input ~ 0 +C2D +Wire Wire Line + 4950 4300 4950 5250 +Text GLabel 4950 5150 0 60 Input ~ 0 +PWR +$Comp +L C C1 +U 1 1 568B12B0 +P 4050 4350 +F 0 "C1" H 4075 4450 50 0000 L CNN +F 1 "0.1uF" H 4075 4250 50 0000 L CNN +F 2 "Capacitors_SMD:C_0402" H 4088 4200 50 0000 C CNN +F 3 "" H 4050 4350 50 0000 C CNN + 1 4050 4350 + 0 1 1 0 +$EndComp +$Comp +L C C2 +U 1 1 568B131F +P 4050 4650 +F 0 "C2" H 4075 4750 50 0000 L CNN +F 1 "4.7uF" H 4075 4550 50 0000 L CNN +F 2 "Capacitors_SMD:C_0603" H 4088 4500 50 0000 C CNN +F 3 "" H 4050 4650 50 0000 C CNN + 1 4050 4650 + 0 1 1 0 +$EndComp +Wire Wire Line + 4200 4650 4500 4650 +Wire Wire Line + 4500 4650 4500 4350 +Wire Wire Line + 4200 4350 4800 4350 +Wire Wire Line + 4800 4350 4800 4300 +Connection ~ 4500 4350 +Wire Wire Line + 3700 4650 3900 4650 +Wire Wire Line + 3700 4350 3700 4650 +Wire Wire Line + 3700 4350 3900 4350 +Wire Wire Line + 3700 4500 3600 4500 +Connection ~ 3700 4500 +Text GLabel 3600 4500 0 60 Input ~ 0 +GND +$Comp +L C C3 +U 1 1 568B141B +P 5500 4900 +F 0 "C3" H 5525 5000 50 0000 L CNN +F 1 "0.1uF" H 5525 4800 50 0000 L CNN +F 2 "Capacitors_SMD:C_0402" H 5538 4750 50 0000 C CNN +F 3 "" H 5500 4900 50 0000 C CNN + 1 5500 4900 + 0 1 1 0 +$EndComp +$Comp +L C C4 +U 1 1 568B1462 +P 5500 5200 +F 0 "C4" H 5525 5300 50 0000 L CNN +F 1 "4.7uF" H 5525 5100 50 0000 L CNN +F 2 "Capacitors_SMD:C_0603" H 5538 5050 50 0000 C CNN +F 3 "" H 5500 5200 50 0000 C CNN + 1 5500 5200 + 0 1 1 0 +$EndComp +Wire Wire Line + 4950 5000 5250 5000 +Wire Wire Line + 5250 4900 5250 5200 +Wire Wire Line + 5250 4900 5350 4900 +Connection ~ 4950 5000 +Wire Wire Line + 5250 5200 5350 5200 +Connection ~ 5250 5000 +Wire Wire Line + 5850 5200 5650 5200 +Wire Wire Line + 5850 4900 5850 5200 +Wire Wire Line + 5850 4900 5650 4900 +Wire Wire Line + 5850 5050 6000 5050 +Connection ~ 5850 5050 +Text GLabel 6000 5050 2 60 Input ~ 0 +GND +Text GLabel 4500 4650 2 60 Input ~ 0 ++3.3V +Text GLabel 7150 3850 0 60 Input ~ 0 ++3.3V +$Comp +L CA_RGB RGB1 +U 1 1 568B1744 +P 6150 2500 +F 0 "RGB1" H 6400 2650 60 0000 C CNN +F 1 "CA_RGB" H 6050 2650 60 0000 C CNN +F 2 "footprints:LED-0606" H 6150 2550 60 0000 C CNN +F 3 "" H 6150 2550 60 0000 C CNN + 1 6150 2500 + 1 0 0 1 +$EndComp +$Comp +L R R1 +U 1 1 568B17C3 +P 6900 2550 +F 0 "R1" V 6980 2550 50 0000 C CNN +F 1 "100" V 6900 2550 50 0000 C CNN +F 2 "Resistors_SMD:R_0603" V 6830 2550 50 0000 C CNN +F 3 "" H 6900 2550 50 0000 C CNN + 1 6900 2550 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6650 2300 6900 2300 +Wire Wire Line + 6900 2300 6900 2400 +Wire Wire Line + 6900 2700 6900 2800 +Text GLabel 6900 2800 0 60 Input ~ 0 +PWR +Wire Wire Line + 5700 2450 5600 2450 +Wire Wire Line + 5600 2450 5600 2700 +Wire Wire Line + 5450 2700 5450 2300 +Wire Wire Line + 5450 2300 5700 2300 +Wire Wire Line + 5700 2150 5300 2150 +Wire Wire Line + 5300 2150 5300 2700 +NoConn ~ 5100 4300 +NoConn ~ 4400 3750 +NoConn ~ 4400 3600 +NoConn ~ 4400 3300 +NoConn ~ 4400 3150 +NoConn ~ 5000 2700 +NoConn ~ 5150 2700 +NoConn ~ 6100 3400 +NoConn ~ 7150 3750 +NoConn ~ 8350 3850 +NoConn ~ 8350 3750 +NoConn ~ 8350 3650 +$Comp +L CONN_01X05 P1 +U 1 1 568B1E1F +P 7300 5000 +F 0 "P1" H 7300 5300 50 0000 C CNN +F 1 "CONN_01X05" V 7400 5000 50 0000 C CNN +F 2 "Connect:bornier5" H 7300 5000 50 0000 C CNN +F 3 "" H 7300 5000 50 0000 C CNN + 1 7300 5000 + 0 1 1 0 +$EndComp +Text GLabel 7500 4800 1 60 Input ~ 0 +GND +Wire Wire Line + 7100 4800 6550 4800 +Wire Wire Line + 6550 4800 6550 4650 +Wire Wire Line + 7200 4800 7200 4750 +Wire Wire Line + 7200 4750 6850 4750 +Wire Wire Line + 6850 4750 6850 4650 +Wire Wire Line + 7300 4800 7300 4700 +Wire Wire Line + 7300 4700 7100 4700 +Wire Wire Line + 7100 4700 7100 4650 +Wire Wire Line + 7400 4800 7400 4650 +Wire Wire Line + 7400 4650 7300 4650 +Wire Wire Line + 7300 4650 7300 4600 +Text GLabel 6550 4650 1 60 Input ~ 0 +C2D +Text GLabel 6850 4650 1 60 Input ~ 0 +C2CK +Text GLabel 7300 4600 1 60 Input ~ 0 +PWR +Text GLabel 6100 3250 2 60 Input ~ 0 +GPIO1 +Text GLabel 7100 4650 1 60 Input ~ 0 +GPIO1 +$EndSCHEMATC diff --git a/EFM8UB1_setup_board/EFM8UB1_setup_board.kicad_pcb-bak b/EFM8UB1_setup_board/EFM8UB1_setup_board.kicad_pcb-bak new file mode 100644 index 0000000..3a51e5a --- /dev/null +++ b/EFM8UB1_setup_board/EFM8UB1_setup_board.kicad_pcb-bak @@ -0,0 +1,559 @@ +(kicad_pcb (version 4) (host pcbnew 4.0.1-3.201512221402+6198~38~ubuntu15.04.1-stable) + + (general + (links 23) + (no_connects 11) + (area 155.424999 76.424999 202.575001 118.575001) + (thickness 1.6) + (drawings 10) + (tracks 80) + (zones 0) + (modules 9) + (nets 25) + ) + + (page A4) + (layers + (0 F.Cu signal) + (31 B.Cu signal) + (32 B.Adhes user) + (33 F.Adhes user) + (34 B.Paste user) + (35 F.Paste user) + (36 B.SilkS user) + (37 F.SilkS user) + (38 B.Mask user) + (39 F.Mask user) + (40 Dwgs.User user) + (41 Cmts.User user) + (42 Eco1.User user) + (43 Eco2.User user) + (44 Edge.Cuts user) + (45 Margin user) + (46 B.CrtYd user) + (47 F.CrtYd user) + (48 B.Fab user) + (49 F.Fab user) + ) + + (setup + (last_trace_width 0.25) + (trace_clearance 0.2) + (zone_clearance 0.508) + (zone_45_only no) + (trace_min 0.2) + (segment_width 0.2) + (edge_width 0.15) + (via_size 0.6) + (via_drill 0.4) + (via_min_size 0.4) + (via_min_drill 0.3) + (uvia_size 0.3) + (uvia_drill 0.1) + (uvias_allowed no) + (uvia_min_size 0.2) + (uvia_min_drill 0.1) + (pcb_text_width 0.3) + (pcb_text_size 1.5 1.5) + (mod_edge_width 0.15) + (mod_text_size 1 1) + (mod_text_width 0.15) + (pad_size 3.81 3.81) + (pad_drill 1.524) + (pad_to_mask_clearance 0.2) + (aux_axis_origin 0 0) + (visible_elements FFFFFF7F) + (pcbplotparams + (layerselection 0x010f0_80000001) + (usegerberextensions false) + (excludeedgelayer true) + (linewidth 0.100000) + (plotframeref false) + (viasonmask false) + (mode 1) + (useauxorigin false) + (hpglpennumber 1) + (hpglpenspeed 20) + (hpglpendiameter 15) + (hpglpenoverlay 2) + (psnegative false) + (psa4output false) + (plotreference true) + (plotvalue true) + (plotinvisibletext false) + (padsonsilk false) + (subtractmaskfromsilk false) + (outputformat 1) + (mirror false) + (drillshape 0) + (scaleselection 1) + (outputdirectory gerbers/)) + ) + + (net 0 "") + (net 1 +3.3V) + (net 2 "Net-(A1-Pad7)") + (net 3 "Net-(A1-Pad6)") + (net 4 "Net-(A1-Pad5)") + (net 5 GND) + (net 6 "Net-(A1-Pad3)") + (net 7 "Net-(A1-Pad2)") + (net 8 "Net-(A1-Pad1)") + (net 9 PWR) + (net 10 "Net-(E1-Pad1)") + (net 11 "Net-(E1-Pad2)") + (net 12 "Net-(E1-Pad4)") + (net 13 "Net-(E1-Pad5)") + (net 14 "Net-(E1-Pad8)") + (net 15 C2CK) + (net 16 C2D) + (net 17 "Net-(E1-Pad14)") + (net 18 GPIO1) + (net 19 "Net-(E1-Pad16)") + (net 20 "Net-(E1-Pad17)") + (net 21 "Net-(E1-Pad18)") + (net 22 "Net-(E1-Pad19)") + (net 23 "Net-(E1-Pad20)") + (net 24 "Net-(R1-Pad1)") + + (net_class Default "This is the default net class." + (clearance 0.2) + (trace_width 0.25) + (via_dia 0.6) + (via_drill 0.4) + (uvia_dia 0.3) + (uvia_drill 0.1) + (add_net +3.3V) + (add_net C2CK) + (add_net C2D) + (add_net GND) + (add_net GPIO1) + (add_net "Net-(A1-Pad1)") + (add_net "Net-(A1-Pad2)") + (add_net "Net-(A1-Pad3)") + (add_net "Net-(A1-Pad5)") + (add_net "Net-(A1-Pad6)") + (add_net "Net-(A1-Pad7)") + (add_net "Net-(E1-Pad1)") + (add_net "Net-(E1-Pad14)") + (add_net "Net-(E1-Pad16)") + (add_net "Net-(E1-Pad17)") + (add_net "Net-(E1-Pad18)") + (add_net "Net-(E1-Pad19)") + (add_net "Net-(E1-Pad2)") + (add_net "Net-(E1-Pad20)") + (add_net "Net-(E1-Pad4)") + (add_net "Net-(E1-Pad5)") + (add_net "Net-(E1-Pad8)") + (add_net "Net-(R1-Pad1)") + (add_net PWR) + ) + + (module SMD_Packages:SOIC-8-N (layer F.Cu) (tedit 0) (tstamp 568B17AB) + (at 192.65 91 90) + (descr "Module Narrow CMS SOJ 8 pins large") + (tags "CMS SOJ") + (path /568B10D2) + (attr smd) + (fp_text reference A1 (at 0 -1.27 90) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value ATECC508A (at 0 1.27 90) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -2.54 -2.286) (end 2.54 -2.286) (layer F.SilkS) (width 0.15)) + (fp_line (start 2.54 -2.286) (end 2.54 2.286) (layer F.SilkS) (width 0.15)) + (fp_line (start 2.54 2.286) (end -2.54 2.286) (layer F.SilkS) (width 0.15)) + (fp_line (start -2.54 2.286) (end -2.54 -2.286) (layer F.SilkS) (width 0.15)) + (fp_line (start -2.54 -0.762) (end -2.032 -0.762) (layer F.SilkS) (width 0.15)) + (fp_line (start -2.032 -0.762) (end -2.032 0.508) (layer F.SilkS) (width 0.15)) + (fp_line (start -2.032 0.508) (end -2.54 0.508) (layer F.SilkS) (width 0.15)) + (pad 8 smd rect (at -1.905 -3.175 90) (size 0.508 1.143) (layers F.Cu F.Paste F.Mask) + (net 1 +3.3V)) + (pad 7 smd rect (at -0.635 -3.175 90) (size 0.508 1.143) (layers F.Cu F.Paste F.Mask) + (net 2 "Net-(A1-Pad7)")) + (pad 6 smd rect (at 0.635 -3.175 90) (size 0.508 1.143) (layers F.Cu F.Paste F.Mask) + (net 3 "Net-(A1-Pad6)")) + (pad 5 smd rect (at 1.905 -3.175 90) (size 0.508 1.143) (layers F.Cu F.Paste F.Mask) + (net 4 "Net-(A1-Pad5)")) + (pad 4 smd rect (at 1.905 3.175 90) (size 0.508 1.143) (layers F.Cu F.Paste F.Mask) + (net 5 GND)) + (pad 3 smd rect (at 0.635 3.175 90) (size 0.508 1.143) (layers F.Cu F.Paste F.Mask) + (net 6 "Net-(A1-Pad3)")) + (pad 2 smd rect (at -0.635 3.175 90) (size 0.508 1.143) (layers F.Cu F.Paste F.Mask) + (net 7 "Net-(A1-Pad2)")) + (pad 1 smd rect (at -1.905 3.175 90) (size 0.508 1.143) (layers F.Cu F.Paste F.Mask) + (net 8 "Net-(A1-Pad1)")) + (model SMD_Packages.3dshapes/SOIC-8-N.wrl + (at (xyz 0 0 0)) + (scale (xyz 0.5 0.38 0.5)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Capacitors_SMD:C_0402 (layer F.Cu) (tedit 568B1E20) (tstamp 568B17B1) + (at 170.1 96.95) + (descr "Capacitor SMD 0402, reflow soldering, AVX (see smccp.pdf)") + (tags "capacitor 0402") + (path /568B12B0) + (attr smd) + (fp_text reference C1 (at -2.8 0.05) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value 0.1uF (at 0 1.7) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -1.15 -0.6) (end 1.15 -0.6) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.15 0.6) (end 1.15 0.6) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.15 -0.6) (end -1.15 0.6) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.15 -0.6) (end 1.15 0.6) (layer F.CrtYd) (width 0.05)) + (fp_line (start 0.25 -0.475) (end -0.25 -0.475) (layer F.SilkS) (width 0.15)) + (fp_line (start -0.25 0.475) (end 0.25 0.475) (layer F.SilkS) (width 0.15)) + (pad 1 smd rect (at -0.55 0) (size 0.6 0.5) (layers F.Cu F.Paste F.Mask) + (net 1 +3.3V)) + (pad 2 smd rect (at 0.55 0) (size 0.6 0.5) (layers F.Cu F.Paste F.Mask) + (net 5 GND)) + (model Capacitors_SMD.3dshapes/C_0402.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Capacitors_SMD:C_0603 (layer F.Cu) (tedit 568B1E23) (tstamp 568B17B7) + (at 170.2 94.45) + (descr "Capacitor SMD 0603, reflow soldering, AVX (see smccp.pdf)") + (tags "capacitor 0603") + (path /568B131F) + (attr smd) + (fp_text reference C2 (at -3.1 -0.05) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value 4.7uF (at 0 1.9) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -1.45 -0.75) (end 1.45 -0.75) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.45 0.75) (end 1.45 0.75) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.45 -0.75) (end -1.45 0.75) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.45 -0.75) (end 1.45 0.75) (layer F.CrtYd) (width 0.05)) + (fp_line (start -0.35 -0.6) (end 0.35 -0.6) (layer F.SilkS) (width 0.15)) + (fp_line (start 0.35 0.6) (end -0.35 0.6) (layer F.SilkS) (width 0.15)) + (pad 1 smd rect (at -0.75 0) (size 0.8 0.75) (layers F.Cu F.Paste F.Mask) + (net 1 +3.3V)) + (pad 2 smd rect (at 0.75 0) (size 0.8 0.75) (layers F.Cu F.Paste F.Mask) + (net 5 GND)) + (model Capacitors_SMD.3dshapes/C_0603.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Capacitors_SMD:C_0402 (layer F.Cu) (tedit 568B1E31) (tstamp 568B17BD) + (at 180.65 100 180) + (descr "Capacitor SMD 0402, reflow soldering, AVX (see smccp.pdf)") + (tags "capacitor 0402") + (path /568B141B) + (attr smd) + (fp_text reference C3 (at 2.7 0.05 180) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value 0.1uF (at 0 1.7 180) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -1.15 -0.6) (end 1.15 -0.6) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.15 0.6) (end 1.15 0.6) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.15 -0.6) (end -1.15 0.6) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.15 -0.6) (end 1.15 0.6) (layer F.CrtYd) (width 0.05)) + (fp_line (start 0.25 -0.475) (end -0.25 -0.475) (layer F.SilkS) (width 0.15)) + (fp_line (start -0.25 0.475) (end 0.25 0.475) (layer F.SilkS) (width 0.15)) + (pad 1 smd rect (at -0.55 0 180) (size 0.6 0.5) (layers F.Cu F.Paste F.Mask) + (net 5 GND)) + (pad 2 smd rect (at 0.55 0 180) (size 0.6 0.5) (layers F.Cu F.Paste F.Mask) + (net 9 PWR)) + (model Capacitors_SMD.3dshapes/C_0402.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Capacitors_SMD:C_0603 (layer F.Cu) (tedit 568B1E2E) (tstamp 568B17C3) + (at 180.45 95.5 180) + (descr "Capacitor SMD 0603, reflow soldering, AVX (see smccp.pdf)") + (tags "capacitor 0603") + (path /568B1462) + (attr smd) + (fp_text reference C4 (at 3 0.1 180) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value 4.7uF (at 0 1.9 180) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -1.45 -0.75) (end 1.45 -0.75) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.45 0.75) (end 1.45 0.75) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.45 -0.75) (end -1.45 0.75) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.45 -0.75) (end 1.45 0.75) (layer F.CrtYd) (width 0.05)) + (fp_line (start -0.35 -0.6) (end 0.35 -0.6) (layer F.SilkS) (width 0.15)) + (fp_line (start 0.35 0.6) (end -0.35 0.6) (layer F.SilkS) (width 0.15)) + (pad 1 smd rect (at -0.75 0 180) (size 0.8 0.75) (layers F.Cu F.Paste F.Mask) + (net 5 GND)) + (pad 2 smd rect (at 0.75 0 180) (size 0.8 0.75) (layers F.Cu F.Paste F.Mask) + (net 9 PWR)) + (model Capacitors_SMD.3dshapes/C_0603.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module footprints:EFM8UB1 (layer F.Cu) (tedit 5686C774) (tstamp 568B17E1) + (at 175.015001 88.95) + (descr 13) + (path /568B0ED8) + (fp_text reference E1 (at 0 -1.5) (layer F.SilkS) + (effects (font (size 0.5 0.5) (thickness 0.1))) + ) + (fp_text value EFM8UB1 (at 3 -1.5) (layer F.Fab) hide + (effects (font (size 0.5 0.5) (thickness 0.1))) + ) + (fp_circle (center -0.5 -0.5) (end -0.4 -0.6) (layer F.SilkS) (width 0.03)) + (fp_line (start -1 -1) (end 3.5 -1) (layer F.SilkS) (width 0.03)) + (fp_line (start 3.5 -1) (end 3.5 3.5) (layer F.SilkS) (width 0.03)) + (fp_line (start 3.5 3.5) (end -1 3.5) (layer F.SilkS) (width 0.03)) + (fp_line (start -1 3.5) (end -1 -1) (layer F.SilkS) (width 0.03)) + (pad 6 smd rect (at 0 2.5) (size 0.3 0.3) (layers F.Cu F.Paste F.Mask) + (net 1 +3.3V)) + (pad 1 smd rect (at 0 0) (size 0.3 0.3) (layers F.Cu F.Paste F.Mask) + (net 10 "Net-(E1-Pad1)")) + (pad 2 smd rect (at 0 0.5 90) (size 0.3 0.9) (drill (offset 0 -0.3)) (layers F.Cu F.Paste F.Mask) + (net 11 "Net-(E1-Pad2)")) + (pad 3 smd rect (at 0 1 90) (size 0.3 0.9) (drill (offset 0 -0.3)) (layers F.Cu F.Paste F.Mask) + (net 5 GND)) + (pad 4 smd rect (at 0 1.5 90) (size 0.3 0.9) (drill (offset 0 -0.3)) (layers F.Cu F.Paste F.Mask) + (net 12 "Net-(E1-Pad4)")) + (pad 5 smd rect (at 0 2 90) (size 0.3 0.9) (drill (offset 0 -0.3)) (layers F.Cu F.Paste F.Mask) + (net 13 "Net-(E1-Pad5)")) + (pad 7 smd rect (at 0.5 2.5) (size 0.3 0.9) (drill (offset 0 0.3)) (layers F.Cu F.Paste F.Mask) + (net 9 PWR)) + (pad 8 smd rect (at 1 2.5) (size 0.3 0.9) (drill (offset 0 0.3)) (layers F.Cu F.Paste F.Mask) + (net 14 "Net-(E1-Pad8)")) + (pad 9 smd rect (at 1.5 2.5) (size 0.3 0.9) (drill (offset 0 0.3)) (layers F.Cu F.Paste F.Mask) + (net 15 C2CK)) + (pad 10 smd rect (at 2 2.5) (size 0.3 0.9) (drill (offset 0 0.3)) (layers F.Cu F.Paste F.Mask) + (net 16 C2D)) + (pad 11 smd rect (at 2.5 2.5) (size 0.3 0.3) (layers F.Cu F.Paste F.Mask) + (net 3 "Net-(A1-Pad6)")) + (pad 12 smd rect (at 2.5 2 90) (size 0.3 0.9) (drill (offset 0 0.3)) (layers F.Cu F.Paste F.Mask) + (net 5 GND)) + (pad 13 smd rect (at 2.5 1.5 90) (size 0.3 0.9) (drill (offset 0 0.3)) (layers F.Cu F.Paste F.Mask) + (net 4 "Net-(A1-Pad5)")) + (pad 14 smd rect (at 2.5 1 90) (size 0.3 0.9) (drill (offset 0 0.3)) (layers F.Cu F.Paste F.Mask) + (net 17 "Net-(E1-Pad14)")) + (pad 15 smd rect (at 2.5 0.5 90) (size 0.3 0.9) (drill (offset 0 0.3)) (layers F.Cu F.Paste F.Mask) + (net 18 GPIO1)) + (pad 16 smd rect (at 2.5 0 90) (size 0.3 0.3) (layers F.Cu F.Paste F.Mask) + (net 19 "Net-(E1-Pad16)")) + (pad 17 smd rect (at 2 0 180) (size 0.3 0.9) (drill (offset 0 0.3)) (layers F.Cu F.Paste F.Mask) + (net 20 "Net-(E1-Pad17)")) + (pad 18 smd rect (at 1.5 0 180) (size 0.3 0.9) (drill (offset 0 0.3)) (layers F.Cu F.Paste F.Mask) + (net 21 "Net-(E1-Pad18)")) + (pad 19 smd rect (at 1 0 180) (size 0.3 0.9) (drill (offset 0 0.3)) (layers F.Cu F.Paste F.Mask) + (net 22 "Net-(E1-Pad19)")) + (pad 20 smd rect (at 0.5 0 180) (size 0.3 0.9) (drill (offset 0 0.3)) (layers F.Cu F.Paste F.Mask) + (net 23 "Net-(E1-Pad20)")) + (pad 21 smd rect (at 1.25 1.25 180) (size 1.8 1.8) (layers F.Cu F.Paste F.Mask)) + ) + + (module Resistors_SMD:R_0603 (layer F.Cu) (tedit 5415CC62) (tstamp 568B17F5) + (at 162.5 83.25 270) + (descr "Resistor SMD 0603, reflow soldering, Vishay (see dcrcw.pdf)") + (tags "resistor 0603") + (path /568B17C3) + (attr smd) + (fp_text reference R1 (at 0 -1.9 270) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value 100 (at 0 1.9 270) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -1.3 -0.8) (end 1.3 -0.8) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.3 0.8) (end 1.3 0.8) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.3 -0.8) (end -1.3 0.8) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.3 -0.8) (end 1.3 0.8) (layer F.CrtYd) (width 0.05)) + (fp_line (start 0.5 0.675) (end -0.5 0.675) (layer F.SilkS) (width 0.15)) + (fp_line (start -0.5 -0.675) (end 0.5 -0.675) (layer F.SilkS) (width 0.15)) + (pad 1 smd rect (at -0.75 0 270) (size 0.5 0.9) (layers F.Cu F.Paste F.Mask) + (net 24 "Net-(R1-Pad1)")) + (pad 2 smd rect (at 0.75 0 270) (size 0.5 0.9) (layers F.Cu F.Paste F.Mask) + (net 9 PWR)) + (model Resistors_SMD.3dshapes/R_0603.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module footprints:LED-0606 (layer F.Cu) (tedit 5686CF1E) (tstamp 568B1801) + (at 169.05 82.3 270) + (path /568B1744) + (fp_text reference RGB1 (at 0.50546 -1.18872 270) (layer F.SilkS) + (effects (font (size 0.4 0.4) (thickness 0.1))) + ) + (fp_text value CA_RGB (at 0.4445 2.42824 270) (layer F.Fab) hide + (effects (font (size 0.4 0.4) (thickness 0.1))) + ) + (fp_line (start -0.508 -0.635) (end 1.397 -0.635) (layer F.SilkS) (width 0.03)) + (fp_line (start 1.397 -0.635) (end 1.397 2.032) (layer F.SilkS) (width 0.03)) + (fp_line (start 1.397 2.032) (end -0.508 2.032) (layer F.SilkS) (width 0.03)) + (fp_line (start -0.508 2.032) (end -0.508 -0.635) (layer F.SilkS) (width 0.03)) + (pad 1 smd rect (at 0 0 270) (size 0.65 0.85) (layers F.Cu F.Paste F.Mask) + (net 19 "Net-(E1-Pad16)")) + (pad 2 smd rect (at 0.85 0 270) (size 0.65 0.85) (layers F.Cu F.Paste F.Mask) + (net 20 "Net-(E1-Pad17)")) + (pad 3 smd rect (at 0.85 1.45 270) (size 0.65 0.85) (layers F.Cu F.Paste F.Mask) + (net 21 "Net-(E1-Pad18)")) + (pad 4 smd rect (at 0 1.45 270) (size 0.65 0.85) (layers F.Cu F.Paste F.Mask) + (net 24 "Net-(R1-Pad1)")) + ) + + (module footprints:header5pin (layer F.Cu) (tedit 568B2542) (tstamp 568B2690) + (at 175.7 111.7) + (path /568B1E1F) + (fp_text reference P1 (at -10.16 0) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value CONN_01X05 (at -5.08 -2.54) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -8.89 -1.27) (end 3.81 -1.27) (layer F.SilkS) (width 0.15)) + (fp_line (start 3.81 -1.27) (end 3.81 1.27) (layer F.SilkS) (width 0.15)) + (fp_line (start 3.81 1.27) (end -8.89 1.27) (layer F.SilkS) (width 0.15)) + (fp_line (start -8.89 1.27) (end -8.89 -1.27) (layer F.SilkS) (width 0.15)) + (pad 1 thru_hole rect (at -7.62 0) (size 1.524 1.524) (drill 1) (layers *.Cu *.Mask F.SilkS) + (net 5 GND)) + (pad 2 thru_hole circle (at -5.08 0) (size 1.524 1.524) (drill 1) (layers *.Cu *.Mask F.SilkS) + (net 9 PWR)) + (pad 3 thru_hole circle (at -2.54 0) (size 1.524 1.524) (drill 1) (layers *.Cu *.Mask F.SilkS) + (net 18 GPIO1)) + (pad 4 thru_hole circle (at 0 0) (size 1.524 1.524) (drill 1) (layers *.Cu *.Mask F.SilkS) + (net 15 C2CK)) + (pad 5 thru_hole circle (at 2.54 0) (size 1.524 1.524) (drill 1) (layers *.Cu *.Mask F.SilkS) + (net 16 C2D)) + ) + + (gr_line (start 155.5 118.5) (end 155.5 76.5) (angle 90) (layer Edge.Cuts) (width 0.15)) + (gr_line (start 202.5 118.5) (end 155.5 118.5) (angle 90) (layer Edge.Cuts) (width 0.15)) + (gr_line (start 202.5 76.5) (end 202.5 118.5) (angle 90) (layer Edge.Cuts) (width 0.15)) + (gr_line (start 155.5 76.5) (end 202.5 76.5) (angle 90) (layer Edge.Cuts) (width 0.15)) + (gr_text "U2F-ZERO Setup" (at 188 79.5) (layer F.SilkS) + (effects (font (size 1.5 1.5) (thickness 0.3))) + ) + (gr_text GND (at 162.75 105 90) (layer F.SilkS) + (effects (font (size 1.5 1.5) (thickness 0.3))) + ) + (gr_text C2D (at 183.25 104.75 90) (layer F.SilkS) + (effects (font (size 1.5 1.5) (thickness 0.3))) + ) + (gr_text C2CK (at 178.25 104.5 90) (layer F.SilkS) + (effects (font (size 1.5 1.5) (thickness 0.3))) + ) + (gr_text GPIO (at 173 104.75 90) (layer F.SilkS) + (effects (font (size 1.5 1.5) (thickness 0.3))) + ) + (gr_text VCC (at 168 105 90) (layer F.SilkS) + (effects (font (size 1.5 1.5) (thickness 0.3))) + ) + + (segment (start 189.475 92.975) (end 189.475 92.905) (width 0.25) (layer F.Cu) (net 1) (tstamp 568B1B05)) + (segment (start 189.475 92.975) (end 189.5 93) (width 0.25) (layer F.Cu) (net 1) (tstamp 568B1B04)) + (via (at 189.5 93) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 1)) + (segment (start 173.25 93) (end 189.5 93) (width 0.25) (layer B.Cu) (net 1) (tstamp 568B1AF7)) + (segment (start 173.25 93) (end 172.75 92.5) (width 0.25) (layer B.Cu) (net 1) (tstamp 568B1AF6)) + (via (at 172.75 92.5) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 1)) + (segment (start 172.75 92.5) (end 173.965001 92.5) (width 0.25) (layer F.Cu) (net 1) (tstamp 568B1AF3)) + (segment (start 169.55 96.95) (end 169.55 94.55) (width 0.25) (layer F.Cu) (net 1)) + (segment (start 169.55 94.55) (end 171.6 92.5) (width 0.25) (layer F.Cu) (net 1) (tstamp 568B1A6F)) + (segment (start 171.6 92.5) (end 172.75 92.5) (width 0.25) (layer F.Cu) (net 1) (tstamp 568B1A70)) + (segment (start 173.965001 92.5) (end 175.015001 91.45) (width 0.25) (layer F.Cu) (net 1) (tstamp 568B1A72)) + (via (at 189.475 90.365) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 3)) + (segment (start 177.515001 91.45) (end 178.015001 91.95) (width 0.25) (layer F.Cu) (net 3) (tstamp 568B1D62)) + (segment (start 179.2 91.95) (end 178.015001 91.95) (width 0.25) (layer F.Cu) (net 3) (tstamp 568B1D60)) + (segment (start 179.4 91.75) (end 179.2 91.95) (width 0.25) (layer F.Cu) (net 3) (tstamp 568B1D5F)) + (via (at 179.4 91.75) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 3)) + (segment (start 188.09 91.75) (end 179.4 91.75) (width 0.25) (layer B.Cu) (net 3) (tstamp 568B1D55)) + (segment (start 188.09 91.75) (end 189.475 90.365) (width 0.25) (layer B.Cu) (net 3) (tstamp 568B1D54)) + (segment (start 189.475 89.095) (end 182.655 89.095) (width 0.25) (layer F.Cu) (net 4)) + (segment (start 181.3 90.45) (end 177.515001 90.45) (width 0.25) (layer F.Cu) (net 4) (tstamp 568B1ACD)) + (segment (start 182.655 89.095) (end 181.3 90.45) (width 0.25) (layer F.Cu) (net 4) (tstamp 568B1AC5)) + (segment (start 175.015001 89.95) (end 173.05 89.95) (width 0.25) (layer F.Cu) (net 5)) + (segment (start 177.515001 90.95) (end 183 90.95) (width 0.25) (layer F.Cu) (net 5)) + (segment (start 167.92 111.75) (end 162.67 100.15) (width 0.25) (layer B.Cu) (net 5) (status 10)) + (segment (start 162.82 100) (end 162.67 100.15) (width 0.25) (layer B.Cu) (net 5) (tstamp 568B1CBB)) + (via (at 162.67 100.15) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 5)) + (segment (start 180.1 100) (end 180 100) (width 0.25) (layer F.Cu) (net 9) (tstamp 568B1CBF)) + (via (at 180 100) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 9)) + (segment (start 162.82 100) (end 180 100) (width 0.25) (layer B.Cu) (net 9) (tstamp 568B1CBC)) + (segment (start 162.67 100.15) (end 162.67 84.17) (width 0.25) (layer F.Cu) (net 9) (tstamp 568B1CB8)) + (segment (start 162.67 84.17) (end 162.5 84) (width 0.25) (layer F.Cu) (net 9) (tstamp 568B1A96)) + (segment (start 179.7 95.5) (end 177.75 95.5) (width 0.25) (layer F.Cu) (net 9)) + (segment (start 175.515001 93.265001) (end 175.515001 91.45) (width 0.25) (layer F.Cu) (net 9) (tstamp 568B1A84)) + (segment (start 177.75 95.5) (end 175.515001 93.265001) (width 0.25) (layer F.Cu) (net 9) (tstamp 568B1A82)) + (segment (start 180.1 100) (end 180.1 98.1) (width 0.25) (layer F.Cu) (net 9)) + (segment (start 179.7 97.7) (end 179.7 95.5) (width 0.25) (layer F.Cu) (net 9) (tstamp 568B1A7F)) + (segment (start 180.1 98.1) (end 179.7 97.7) (width 0.25) (layer F.Cu) (net 9) (tstamp 568B1A7E)) + (segment (start 176.515001 93.065001) (end 176.515001 91.45) (width 0.25) (layer F.Cu) (net 15) (tstamp 568B1C8D)) + (segment (start 178.08 111.75) (end 178.08 107.37) (width 0.25) (layer F.Cu) (net 16) (status 10)) + (segment (start 185.2 100.25) (end 185.2 96.75) (width 0.25) (layer F.Cu) (net 16) (tstamp 568B1C84)) + (segment (start 185.2 96.75) (end 181.9 93.45) (width 0.25) (layer F.Cu) (net 16) (tstamp 568B1C86)) + (segment (start 181.9 93.45) (end 176.9 93.45) (width 0.25) (layer F.Cu) (net 16) (tstamp 568B1C88)) + (segment (start 176.9 93.45) (end 176.515001 93.065001) (width 0.25) (layer F.Cu) (net 16) (tstamp 568B1C8C)) + (segment (start 178.08 107.37) (end 185.2 100.25) (width 0.25) (layer F.Cu) (net 16) (tstamp 568B2007)) + (segment (start 183.16 111.75) (end 183.16 105.54) (width 0.25) (layer F.Cu) (net 16) (status 10)) + (segment (start 188.2 100.5) (end 188.2 96.9) (width 0.25) (layer F.Cu) (net 16) (tstamp 568B1C4E)) + (segment (start 188.2 96.9) (end 184 92.7) (width 0.25) (layer F.Cu) (net 16) (tstamp 568B1C50)) + (segment (start 184 92.7) (end 177.1 92.7) (width 0.25) (layer F.Cu) (net 16) (tstamp 568B1C52)) + (segment (start 177.1 92.7) (end 177.015001 92.615001) (width 0.25) (layer F.Cu) (net 16) (tstamp 568B1C58)) + (segment (start 177.015001 92.615001) (end 177.015001 91.45) (width 0.25) (layer F.Cu) (net 16) (tstamp 568B1C5B)) + (segment (start 183.16 105.54) (end 188.2 100.5) (width 0.25) (layer F.Cu) (net 16) (tstamp 568B2024)) + (segment (start 173 111.75) (end 173 109.5) (width 0.25) (layer B.Cu) (net 18)) + (via (at 188 106) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 18)) + (segment (start 188 106) (end 188.001578 106.001578) (width 0.25) (layer F.Cu) (net 18) (tstamp 568B1BFE)) + (segment (start 188.001578 106.001578) (end 188.001578 106.001684) (width 0.25) (layer F.Cu) (net 18) (tstamp 568B1BFF)) + (segment (start 188.001578 106.001684) (end 187.953262 106.05) (width 0.25) (layer F.Cu) (net 18) (tstamp 568B1C00)) + (segment (start 187.953262 106.05) (end 187.95 106.05) (width 0.25) (layer F.Cu) (net 18) (tstamp 568B1C01)) + (segment (start 180.35 89.45) (end 177.515001 89.45) (width 0.25) (layer F.Cu) (net 18)) + (segment (start 199.5 99.25) (end 187.95 106.05) (width 0.25) (layer F.Cu) (net 18) (tstamp 568B1BBB)) + (segment (start 199.5 86.1) (end 199.5 99.25) (width 0.25) (layer F.Cu) (net 18) (tstamp 568B1BB8)) + (segment (start 197.6 85.15) (end 199.5 86.1) (width 0.25) (layer F.Cu) (net 18) (tstamp 568B1BB6)) + (segment (start 184.65 85.15) (end 197.6 85.15) (width 0.25) (layer F.Cu) (net 18) (tstamp 568B1BB4)) + (segment (start 180.35 89.45) (end 184.65 85.15) (width 0.25) (layer F.Cu) (net 18) (tstamp 568B1BAB)) + (segment (start 176.5 106) (end 188 106) (width 0.25) (layer B.Cu) (net 18) (tstamp 568B20A0)) + (segment (start 173 109.5) (end 176.5 106) (width 0.25) (layer B.Cu) (net 18) (tstamp 568B209C)) + (via (at 173 111.75) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 18) (status 30)) + (segment (start 169.05 82.3) (end 174.3 82.3) (width 0.25) (layer F.Cu) (net 19)) + (segment (start 177.515001 85.515001) (end 177.515001 88.95) (width 0.25) (layer F.Cu) (net 19) (tstamp 568B1AB4)) + (segment (start 174.3 82.3) (end 177.515001 85.515001) (width 0.25) (layer F.Cu) (net 19) (tstamp 568B1AB2)) + (segment (start 169.05 83.15) (end 174.15 83.15) (width 0.25) (layer F.Cu) (net 20)) + (segment (start 177.015001 86.015001) (end 177.015001 88.95) (width 0.25) (layer F.Cu) (net 20) (tstamp 568B1AAE)) + (segment (start 174.15 83.15) (end 177.015001 86.015001) (width 0.25) (layer F.Cu) (net 20) (tstamp 568B1AAA)) + (segment (start 167.6 83.15) (end 167.6 84.1) (width 0.25) (layer F.Cu) (net 21)) + (segment (start 176.515001 86.765001) (end 176.515001 88.95) (width 0.25) (layer F.Cu) (net 21) (tstamp 568B1AA6)) + (segment (start 176.5 86.75) (end 176.515001 86.765001) (width 0.25) (layer F.Cu) (net 21) (tstamp 568B1AA4)) + (segment (start 170.25 86.75) (end 176.5 86.75) (width 0.25) (layer F.Cu) (net 21) (tstamp 568B1AA0)) + (segment (start 167.6 84.1) (end 170.25 86.75) (width 0.25) (layer F.Cu) (net 21) (tstamp 568B1A9E)) + (segment (start 162.5 82.5) (end 165 82.5) (width 0.25) (layer F.Cu) (net 24)) + (segment (start 165.2 82.3) (end 167.6 82.3) (width 0.25) (layer F.Cu) (net 24) (tstamp 568B1A9A)) + (segment (start 165 82.5) (end 165.2 82.3) (width 0.25) (layer F.Cu) (net 24) (tstamp 568B1A99)) + + (zone (net 5) (net_name GND) (layer F.Cu) (tstamp 568B2153) (hatch edge 0.508) + (connect_pads (clearance 0.508)) + (min_thickness 0.254) + (fill (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508)) + (polygon + (pts + (xy 202 118) (xy 156 118) (xy 156 77) (xy 202 77) (xy 202 118) + ) + ) + ) +) diff --git a/library/atmel_cryptoauth.bak b/library/atmel_cryptoauth.bak new file mode 100644 index 0000000..2ca3938 --- /dev/null +++ b/library/atmel_cryptoauth.bak @@ -0,0 +1,24 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# ATECC508A +# +DEF ATECC508A A 0 40 Y Y 1 F N +F0 "A" 300 300 60 H V C CNN +F1 "ATECC508A" -100 300 60 H V C CNN +F2 "" -400 250 60 H V C CNN +F3 "" -400 250 60 H V C CNN +DRAW +S -350 250 350 -250 1 1 4 N +X NC 1 -600 150 276 R 39 39 1 1 P +X NC 2 -600 50 276 R 39 39 1 1 P +X NC 3 -600 -50 276 R 39 39 1 1 P +X GND 4 -600 -150 276 R 39 39 1 1 w +X SDA 5 600 -150 276 L 39 39 1 1 P +X SCL 6 600 -50 276 L 39 39 1 1 P +X NC 7 600 50 276 L 39 39 1 1 P +X VCC 8 600 150 276 L 39 39 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/discrete.bak b/library/discrete.bak new file mode 100644 index 0000000..11dbca6 --- /dev/null +++ b/library/discrete.bak @@ -0,0 +1,49 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# CA_RGB +# +DEF CA_RGB RGB 0 40 Y Y 1 F N +F0 "RGB" 250 150 60 H V C CNN +F1 "CA_RGB" -100 150 60 H V C CNN +F2 "" 0 50 60 H V C CNN +F3 "" 0 50 60 H V C CNN +DRAW +S -250 100 300 -500 0 1 0 N +P 2 0 1 0 -100 -350 -150 -350 N +P 2 0 1 0 -100 -300 -100 -400 N +P 2 0 1 0 -100 -200 -150 -200 N +P 2 0 1 0 -100 -150 -100 -250 N +P 2 0 1 0 -100 -50 -150 -50 N +P 2 0 1 0 -100 0 -100 -100 N +P 2 0 1 0 50 -200 0 -200 N +P 2 0 1 0 50 -200 100 -200 N +P 4 0 1 0 -100 -350 0 -300 0 -400 -100 -350 N +P 4 0 1 0 -100 -200 0 -150 0 -250 -100 -200 N +P 4 0 1 0 -100 -50 0 0 0 -100 -100 -50 N +P 5 0 1 0 0 -50 50 -50 50 -350 0 -350 50 -350 N +X R 1 -450 -50 200 R 50 50 1 1 P +X G 2 -450 -200 200 R 50 50 1 1 P +X B 3 -450 -350 200 R 50 50 1 1 P +X VCC 4 500 -200 200 L 50 50 1 1 P +ENDDRAW +ENDDEF +# +# DF5A5.6JE +# +DEF DF5A5.6JE Z 0 40 Y Y 1 F N +F0 "Z" -400 50 60 H V C CNN +F1 "DF5A5.6JE" -550 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 200 300 -200 0 1 0 N +X C1 1 -200 300 79 D 50 50 1 1 I +X GND 2 0 300 79 D 50 50 1 1 w +X C2 3 200 300 79 D 50 50 1 1 I +X C3 4 -150 -300 79 U 50 50 1 1 I +X C4 5 150 -300 79 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/siliconlabs.bak b/library/siliconlabs.bak new file mode 100644 index 0000000..ae1860b --- /dev/null +++ b/library/siliconlabs.bak @@ -0,0 +1,37 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# EFM8UB1 +# +DEF EFM8UB1 E 0 40 Y Y 1 F N +F0 "E" -400 600 60 H V C CNN +F1 "EFM8UB1" -550 700 60 H V C CNN +F2 "" -500 500 60 H V C CNN +F3 "" -500 500 60 H V C CNN +DRAW +C -300 250 71 0 1 4 N +S -550 550 550 -500 0 1 4 N +X P0.1 1 -850 350 276 R 39 39 1 1 P +X P0.0 2 -850 200 276 R 39 39 1 1 P +X GND 3 -850 50 276 R 39 39 1 1 B +X D+ 4 -850 -100 276 R 39 39 1 1 P +X D- 5 -850 -250 276 R 39 39 1 1 P +X VDD 6 -450 -800 276 U 39 39 1 1 P +X VREGIN 7 -300 -800 276 U 39 39 1 1 P +X P3.1/VBUS 8 -150 -800 276 U 39 39 1 1 P +X RSTb/C2CK 9 0 -800 276 U 39 39 1 1 P +X P2.0/C2D 10 150 -800 276 U 39 39 1 1 P +X P0.2 20 -250 800 276 D 39 39 1 1 P +X P1.2/SCL 11 850 -350 276 L 39 39 1 1 P +X GND 12 850 -200 276 L 39 39 1 1 W +X P1.1/SDA 13 850 -50 276 L 39 39 1 1 P +X P1.0 14 850 100 276 L 39 39 1 1 P +X P0.7 15 850 250 276 L 39 39 1 1 P +X P0.6 16 350 800 276 D 39 39 1 1 P +X P0.5 17 200 800 276 D 39 39 1 1 P +X P0.4 18 50 800 276 D 39 39 1 1 P +X P0.3 19 -100 800 276 D 39 39 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/u2f-zero-rescue.bak b/u2f-zero-rescue.bak new file mode 100644 index 0000000..05c4c65 --- /dev/null +++ b/u2f-zero-rescue.bak @@ -0,0 +1,52 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# ATECC508A-RESCUE-u2f-zero +# +DEF ATECC508A-RESCUE-u2f-zero A 0 40 Y Y 1 F N +F0 "A" 300 300 60 H V C CNN +F1 "ATECC508A-RESCUE-u2f-zero" -100 300 60 H V C CNN +F2 "" -400 250 60 H V C CNN +F3 "" -400 250 60 H V C CNN +DRAW +S -350 250 350 -250 1 1 4 N +X NC 1 -600 150 276 R 39 39 1 1 P +X NC 2 -600 50 276 R 39 39 1 1 P +X NC 3 -600 -50 276 R 39 39 1 1 P +X GND 4 -600 -150 276 R 39 39 1 1 P +X SDA 5 600 -150 276 L 39 39 1 1 P +X SCL 6 600 -50 276 L 39 39 1 1 P +X NC 7 600 50 276 L 39 39 1 1 P +X VCC 8 600 150 276 L 39 39 1 1 P +ENDDRAW +ENDDEF +# +# CA_RGB-RESCUE-u2f-zero +# +DEF CA_RGB-RESCUE-u2f-zero RGB 0 40 Y Y 1 F N +F0 "RGB" 250 150 60 H V C CNN +F1 "CA_RGB-RESCUE-u2f-zero" -100 150 60 H V C CNN +F2 "" 0 50 60 H V C CNN +F3 "" 0 50 60 H V C CNN +DRAW +S -250 100 300 -500 0 1 0 N +P 2 0 1 0 -100 -350 -150 -350 N +P 2 0 1 0 -100 -300 -100 -400 N +P 2 0 1 0 -100 -200 -150 -200 N +P 2 0 1 0 -100 -150 -100 -250 N +P 2 0 1 0 -100 -50 -150 -50 N +P 2 0 1 0 -100 0 -100 -100 N +P 2 0 1 0 50 -200 0 -200 N +P 2 0 1 0 50 -200 100 -200 N +P 4 0 1 0 -100 -350 0 -300 0 -400 -100 -350 N +P 4 0 1 0 -100 -200 0 -150 0 -250 -100 -200 N +P 4 0 1 0 -100 -50 0 0 0 -100 -100 -50 N +P 5 0 1 0 0 -50 50 -50 50 -350 0 -350 50 -350 N +X R 1 -450 -50 200 R 50 50 1 1 I +X G 2 -450 -200 200 R 50 50 1 1 I +X B 3 -450 -350 200 R 50 50 1 1 I +X GND 4 500 -200 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/u2f-zero.bak b/u2f-zero.bak new file mode 100644 index 0000000..085e6da --- /dev/null +++ b/u2f-zero.bak @@ -0,0 +1,316 @@ +EESchema Schematic File Version 2 +LIBS:u2f-zero-rescue +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:siliconlabs +LIBS:atmel_cryptoauth +LIBS:discrete +LIBS:u2f-zero-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L EFM8UB1 E1 +U 1 1 56857441 +P 5200 4500 +F 0 "E1" H 4800 5100 60 0000 C CNN +F 1 "EFM8UB1" H 4650 5200 60 0000 C CNN +F 2 "footprints:EFM8UB1" H 4700 5000 60 0001 C CNN +F 3 "" H 4700 5000 60 0000 C CNN + 1 5200 4500 + 1 0 0 -1 +$EndComp +NoConn ~ 7600 4650 +$Comp +L ATECC508A-RESCUE-u2f-zero A1 +U 1 1 56857313 +P 7000 4700 +F 0 "A1" H 7300 5000 60 0000 C CNN +F 1 "ATECC508A" H 6900 5000 60 0000 C CNN +F 2 "SMD_Packages:SOIC-8-N" H 6600 4950 60 0001 C CNN +F 3 "" H 6600 4950 60 0000 C CNN + 1 7000 4700 + -1 0 0 1 +$EndComp +NoConn ~ 7600 4750 +Text Label 4350 4450 2 60 ~ 0 +GND +NoConn ~ 7600 4850 +NoConn ~ 6400 4750 +NoConn ~ 6050 4400 +NoConn ~ 6050 4250 +Text Label 7850 5050 0 60 ~ 0 +GND +Text Label 6400 5150 0 60 ~ 0 ++3.3V +Text Label 6050 4700 0 60 ~ 0 +GND +$Comp +L C C3 +U 1 1 56857DEB +P 5350 5600 +F 0 "C3" H 5375 5700 50 0000 L CNN +F 1 "0.1uF" H 5375 5500 50 0000 L CNN +F 2 "Capacitors_SMD:C_0402" H 5388 5450 50 0001 C CNN +F 3 "" H 5350 5600 50 0000 C CNN + 1 5350 5600 + 0 -1 1 0 +$EndComp +$Comp +L C C4 +U 1 1 56857E44 +P 5350 5950 +F 0 "C4" H 5375 6050 50 0000 L CNN +F 1 "4.7uF" H 5375 5850 50 0000 L CNN +F 2 "Capacitors_SMD:C_0603" H 5388 5800 50 0001 C CNN +F 3 "" H 5350 5950 50 0000 C CNN + 1 5350 5950 + 0 1 1 0 +$EndComp +$Comp +L C C1 +U 1 1 56858041 +P 4400 5600 +F 0 "C1" H 4425 5700 50 0000 L CNN +F 1 "0.1uF" H 4425 5500 50 0000 L CNN +F 2 "Capacitors_SMD:C_0402" H 4438 5450 50 0001 C CNN +F 3 "" H 4400 5600 50 0000 C CNN + 1 4400 5600 + 0 1 1 0 +$EndComp +$Comp +L C C2 +U 1 1 5685809E +P 4400 5950 +F 0 "C2" H 4425 6050 50 0000 L CNN +F 1 "4.7uF" H 4425 5850 50 0000 L CNN +F 2 "Capacitors_SMD:C_0603" H 4438 5800 50 0001 C CNN +F 3 "" H 4400 5950 50 0000 C CNN + 1 4400 5950 + 0 1 1 0 +$EndComp +Text Label 4050 6100 3 60 ~ 0 +GND +Text Label 4750 5450 2 60 ~ 0 ++3.3V +Text Label 7350 3600 0 60 ~ 0 ++5V +NoConn ~ 4350 4150 +NoConn ~ 4350 4300 +$Comp +L DF5A5.6JE Z1 +U 1 1 56857EAF +P 3450 4300 +F 0 "Z1" H 3050 4350 60 0000 C CNN +F 1 "DF5A5.6JE" H 2900 4450 60 0000 C CNN +F 2 "TO_SOT_Packages_SMD:SOT-553" H 3450 4300 60 0001 C CNN +F 3 "" H 3450 4300 60 0000 C CNN + 1 3450 4300 + 1 0 0 -1 +$EndComp +Text Label 5900 5600 0 60 ~ 0 +GND +Text Label 4900 6150 0 60 ~ 0 ++5V +Text Label 3650 3900 2 60 ~ 0 ++5V +Text Label 3450 3900 2 60 ~ 0 +GND +Text Label 3750 4600 0 60 ~ 0 +HD- +Text Label 3950 4750 2 60 ~ 0 +HD+ +Text Label 4350 3400 2 60 ~ 0 +GND +$Comp +L R R1 +U 1 1 56857B9B +P 7050 3450 +F 0 "R1" V 7130 3450 50 0000 C CNN +F 1 "100" V 7050 3450 50 0000 C CNN +F 2 "Resistors_SMD:R_0603" V 6980 3450 50 0001 C CNN +F 3 "" H 7050 3450 50 0000 C CNN + 1 7050 3450 + 0 1 1 0 +$EndComp +NoConn ~ 5050 5300 +NoConn ~ 5200 5300 +NoConn ~ 5350 5300 +Text Notes 3050 3750 0 60 ~ 0 +Protect from ESD +Text Notes 3350 4900 0 60 ~ 0 +Host USB data +Text Notes 6500 4350 0 60 ~ 0 +Secure element for EC +$Comp +L CA_RGB-RESCUE-u2f-zero RGB1 +U 1 1 5686DEFD +P 6250 3650 +F 0 "RGB1" H 6500 3800 60 0000 C CNN +F 1 "CA_RGB" H 6150 3800 60 0000 C CNN +F 2 "footprints:LED-0606" H 7050 3700 60 0001 C CNN +F 3 "" H 6250 3700 60 0000 C CNN + 1 6250 3650 + 1 0 0 1 +$EndComp +$Comp +L GND #PWR01 +U 1 1 5686E5B0 +P 6550 5850 +F 0 "#PWR01" H 6550 5600 50 0001 C CNN +F 1 "GND" H 6550 5700 50 0000 C CNN +F 2 "" H 6550 5850 50 0000 C CNN +F 3 "" H 6550 5850 50 0000 C CNN + 1 6550 5850 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG02 +U 1 1 5686E60B +P 6850 5850 +F 0 "#FLG02" H 6850 5945 50 0001 C CNN +F 1 "PWR_FLAG" H 6850 6030 50 0000 C CNN +F 2 "" H 6850 5850 50 0000 C CNN +F 3 "" H 6850 5850 50 0000 C CNN + 1 6850 5850 + -1 0 0 1 +$EndComp +Wire Wire Line + 6050 4850 6300 4850 +Wire Wire Line + 6300 4850 6300 4650 +Wire Wire Line + 6300 4650 6400 4650 +Wire Wire Line + 6400 4550 6050 4550 +Wire Wire Line + 6400 4850 6400 5150 +Wire Wire Line + 7600 4550 7850 4550 +Wire Wire Line + 7850 4550 7850 5050 +Wire Wire Line + 7200 3450 7350 3450 +Wire Wire Line + 7350 3450 7350 3600 +Wire Wire Line + 4900 5300 4900 6150 +Wire Wire Line + 4900 5950 5200 5950 +Wire Wire Line + 4900 5600 5200 5600 +Connection ~ 4900 5950 +Wire Wire Line + 5500 5950 5750 5950 +Wire Wire Line + 5750 5950 5750 5600 +Connection ~ 5750 5600 +Connection ~ 4900 5600 +Wire Wire Line + 4750 5300 4750 5950 +Wire Wire Line + 4750 5600 4550 5600 +Connection ~ 4750 5600 +Wire Wire Line + 4050 5600 4250 5600 +Wire Wire Line + 4750 5950 4550 5950 +Wire Wire Line + 4050 5600 4050 6100 +Wire Wire Line + 4050 5950 4250 5950 +Connection ~ 4050 5950 +Wire Wire Line + 5500 5600 5900 5600 +Wire Wire Line + 5100 3400 5100 3700 +Wire Wire Line + 4500 3400 4350 3400 +Wire Wire Line + 6900 3450 6750 3450 +Wire Wire Line + 5550 3700 5550 3600 +Wire Wire Line + 5550 3600 5800 3600 +Wire Wire Line + 5800 3450 5400 3450 +Wire Wire Line + 5400 3450 5400 3700 +Wire Wire Line + 5250 3700 5250 3300 +Wire Wire Line + 5250 3300 5800 3300 +Wire Wire Line + 6850 5850 6850 5650 +Wire Wire Line + 6550 5650 6550 5850 +Text Label 6850 5650 0 60 ~ 0 ++5V +Text Label 6550 5650 0 60 ~ 0 +GND +$Comp +L SW_PUSH SW1 +U 1 1 5685E9F9 +P 4800 3400 +F 0 "SW1" H 4950 3510 50 0000 C CNN +F 1 "SW_PUSH" H 4800 3320 50 0000 C CNN +F 2 "footprints:MJTP1230" H 4800 3400 50 0001 C CNN +F 3 "" H 4800 3400 50 0000 C CNN + 1 4800 3400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4950 3700 4950 3650 +Wire Wire Line + 4950 3650 5100 3650 +Connection ~ 5100 3650 +Wire Wire Line + 3300 4600 3300 4750 +Wire Wire Line + 3300 4750 4350 4750 +Wire Wire Line + 3600 4600 4350 4600 +NoConn ~ 3250 4000 +Wire Wire Line + 3450 4000 3450 3900 +Wire Wire Line + 3650 4000 3650 3900 +$EndSCHEMATC