2016-03-29 04:35:26 +00:00
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/*
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2016-06-18 14:40:01 +00:00
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* Copyright (c) 2016, Conor Patrick
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* All rights reserved.
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2016-03-29 04:35:26 +00:00
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*
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2016-06-18 14:40:01 +00:00
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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2016-03-29 04:35:26 +00:00
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*/
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#ifndef ATECC508A_H_
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#define ATECC508A_H_
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#define ATECC508A_ADDR 0xc0
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#define ATECC_CMD_COUNTER 0x24
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// P1
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#define ATECC_COUNTER_READ 0
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#define ATECC_COUNTER_INC 1
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// P2
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#define ATECC_COUNTER0 0
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#define ATECC_COUNTER1 1
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#define ATECC_CMD_RNG 0x1B
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#define ATECC_RNG_P1 0
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#define ATECC_RNG_P2 0
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#define ATECC_CMD_SHA 0x47
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// P1
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#define ATECC_SHA_START 0x0
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#define ATECC_SHA_UPDATE 0x1
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#define ATECC_SHA_END 0x2
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2017-01-28 03:07:19 +00:00
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#define ATECC_SHA_HMACSTART 0x4
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#define ATECC_SHA_HMACEND 0x5
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// P2 is keyslot ID for hmac and message length otherwise
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2016-03-29 04:35:26 +00:00
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#define ATECC_CMD_READ 0x02
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// P1
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#define ATECC_RW_CONFIG 0x00
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#define ATECC_RW_OTP 0x01
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#define ATECC_RW_DATA 0x02
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#define ATECC_RW_EXT 0x80
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// P2 read addr
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#define ATECC_CMD_WRITE 0x12
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2017-01-28 03:07:19 +00:00
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// P1 same as for read
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2016-03-29 04:35:26 +00:00
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// P2 write addr
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#define ATECC_EEPROM_SLOT(x) (0x5 + ((x)>>1))
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#define ATECC_EEPROM_SLOT_OFFSET(x) ( (x) & 1 ? 2 : 0 )
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#define ATECC_EEPROM_SLOT_SIZE 0x2
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#define ATECC_EEPROM_KEY(x) (24 + ((x)>>1))
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#define ATECC_EEPROM_KEY_OFFSET(x) ( (x) & 1 ? 2 : 0 )
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#define ATECC_EEPROM_KEY_SIZE 0x2
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2017-01-28 03:07:19 +00:00
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#define ATECC_EEPROM_DATA_SLOT(x) (x<<3)
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2016-03-29 04:35:26 +00:00
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#define ATECC_EEPROM_B2A(b) ((b)>>2)
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#define ATECC_EEPROM_B2O(b) ((b)&0x3)
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#define ATECC_CMD_LOCK 0x17
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// P1 flags
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#define ATECC_LOCK_CONFIG 0x00
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#define ATECC_LOCK_DATA_OTP 0x01
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#define ATECC_LOCK_SLOT 0x02
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#define ATECC_LOCK_SLOTNUM(x) (((x)&0xf)<<2)
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#define ATECC_LOCK_IGNORE_SUMMARY 0x08
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// P2 is CRC or 0
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#define ATECC_CMD_GENKEY 0x40
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// P1
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#define ATECC_GENKEY_PRIVATE 0x04
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2017-01-28 03:07:19 +00:00
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#define ATECC_GENKEY_PUBLIC 0x00
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2016-03-29 04:35:26 +00:00
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#define ATECC_GENKEY_PUBDIGEST 0x08
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#define ATECC_GENKEY_PUBDIGEST2 0x10
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// P2 is keyid
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#define ATECC_CMD_NONCE 0x16
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// P1
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#define ATECC_NONCE_RNG_UPDATE 0x0
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#define ATECC_NONCE_TEMP_UPDATE 0x3
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// P2 is 0
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#define ATECC_CMD_SIGN 0x41
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// P1
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#define ATECC_SIGN_INTERNAL 0x00
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#define ATECC_SIGN_EXTERNAL 0x80
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// P2 is keyid
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2017-01-28 03:07:19 +00:00
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#define ATECC_CMD_GENDIG 0x15
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// P1 same as for read
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// P2 is keyid
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#define ATECC_CMD_INFO 0x30
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// P1 same as for read
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#define ATECC_INFO_REVISION 0x00
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#define ATECC_INFO_KEYVALID 0x01
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#define ATECC_INFO_STATE 0x02
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#define ATECC_INFO_GPIO 0x03
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// P2 is keyid
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#define ATECC_CMD_PRIVWRITE 0x46
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// P1
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#define ATECC_PRIVWRITE_ENC 0x40
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// P2 is keyid
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2016-03-29 04:35:26 +00:00
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struct atecc_response
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{
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// length of payload
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uint8_t len;
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// payload
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uint8_t* buf;
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};
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struct atecc_slot_config
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{
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uint8_t readkey : 4;
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uint8_t nomac : 1;
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uint8_t limiteduse : 1;
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uint8_t encread : 1;
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uint8_t secret : 1;
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uint8_t writekey : 4;
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uint8_t writeconfig : 4;
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};
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struct atecc_key_config
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{
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uint8_t private : 1;
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uint8_t pubinfo : 1;
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uint8_t keytype : 3;
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uint8_t lockable : 1;
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uint8_t reqrandom : 1;
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uint8_t reqauth : 1;
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uint8_t authkey : 4;
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uint8_t intrusiondisable : 1;
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uint8_t rfu : 1;
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uint8_t x509id : 2;
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};
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void atecc_idle();
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void atecc_wake();
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void atecc_sleep();
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int8_t atecc_send(uint8_t cmd, uint8_t p1, uint16_t p2,
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uint8_t * buf, uint8_t len);
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int8_t atecc_recv(uint8_t * buf, uint8_t buflen, struct atecc_response* res);
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int8_t atecc_send_recv(uint8_t cmd, uint8_t p1, uint16_t p2,
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uint8_t* tx, uint8_t txlen, uint8_t * rx,
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uint8_t rxlen, struct atecc_response* res);
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int8_t atecc_write_eeprom(uint8_t base, uint8_t offset, uint8_t* srcbuf, uint8_t len);
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#endif /* ATECC508A_H_ */
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