kopia lustrzana https://github.com/stlink-org/stlink
426 wiersze
14 KiB
C
426 wiersze
14 KiB
C
/*
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* File: stlink-common.h
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* Bulk import from stlink-hw.h
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*
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* This should contain all the common top level stlink interfaces, regardless
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* of how the backend does the work....
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*/
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#ifndef STLINK_COMMON_H
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#define STLINK_COMMON_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdint.h>
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// Max data transfer size.
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// 6kB = max mem32_read block, 8kB sram
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//#define Q_BUF_LEN 96
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#define Q_BUF_LEN (1024 * 100)
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// st-link vendor cmd's
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#define USB_ST_VID 0x0483
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#define USB_STLINK_PID 0x3744
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#define USB_STLINK_32L_PID 0x3748
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// STLINK_DEBUG_RESETSYS, etc:
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#define STLINK_OK 0x80
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#define STLINK_FALSE 0x81
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#define STLINK_CORE_RUNNING 0x80
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#define STLINK_CORE_HALTED 0x81
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#define STLINK_CORE_STAT_UNKNOWN -1
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#define STLINK_GET_VERSION 0xf1
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#define STLINK_GET_CURRENT_MODE 0xf5
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#define STLINK_DEBUG_COMMAND 0xF2
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#define STLINK_DFU_COMMAND 0xF3
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#define STLINK_DFU_EXIT 0x07
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// enter dfu could be 0x08?
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// STLINK_GET_CURRENT_MODE
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#define STLINK_DEV_DFU_MODE 0x00
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#define STLINK_DEV_MASS_MODE 0x01
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#define STLINK_DEV_DEBUG_MODE 0x02
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#define STLINK_DEV_UNKNOWN_MODE -1
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// jtag mode cmds
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#define STLINK_DEBUG_ENTER 0x20
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#define STLINK_DEBUG_EXIT 0x21
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#define STLINK_DEBUG_READCOREID 0x22
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#define STLINK_DEBUG_GETSTATUS 0x01
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#define STLINK_DEBUG_FORCEDEBUG 0x02
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#define STLINK_DEBUG_RESETSYS 0x03
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#define STLINK_DEBUG_READALLREGS 0x04
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#define STLINK_DEBUG_READREG 0x05
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#define STLINK_DEBUG_WRITEREG 0x06
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#define STLINK_DEBUG_READMEM_32BIT 0x07
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#define STLINK_DEBUG_WRITEMEM_32BIT 0x08
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#define STLINK_DEBUG_RUNCORE 0x09
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#define STLINK_DEBUG_STEPCORE 0x0a
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#define STLINK_DEBUG_SETFP 0x0b
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#define STLINK_DEBUG_WRITEMEM_8BIT 0x0d
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#define STLINK_DEBUG_CLEARFP 0x0e
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#define STLINK_DEBUG_WRITEDEBUGREG 0x0f
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#define STLINK_DEBUG_ENTER_SWD 0xa3
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#define STLINK_DEBUG_ENTER_JTAG 0x00
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// TODO - possible poor names...
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#define STLINK_SWD_ENTER 0x30
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#define STLINK_SWD_READCOREID 0x32 // TBD
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#define STLINK_JTAG_WRITEDEBUG_32BIT 0x35
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#define STLINK_JTAG_READDEBUG_32BIT 0x36
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#define STLINK_JTAG_DRIVE_NRST 0x3c
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#define STLINK_JTAG_DRIVE_NRST 0x3c
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// cortex m3 technical reference manual
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#define CM3_REG_CPUID 0xE000ED00
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#define CM3_REG_FP_CTRL 0xE0002000
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#define CM3_REG_FP_COMP0 0xE0002008
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/* cortex core ids */
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// TODO clean this up...
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#define STM32VL_CORE_ID 0x1ba01477
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#define STM32L_CORE_ID 0x2ba01477
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#define STM32F4_CORE_ID 0x2ba01477
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#define CORE_M3_R1 0x1BA00477
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#define CORE_M3_R2 0x4BA00477
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#define CORE_M4_R0 0x2BA01477
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/*
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* Chip IDs are explained in the appropriate programming manual for the
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* DBGMCU_IDCODE register (0xE0042000)
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*/
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// stm32 chipids, only lower 12 bits..
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#define STM32_CHIPID_F1_MEDIUM 0x410
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#define STM32_CHIPID_F2 0x411
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#define STM32_CHIPID_F1_LOW 0x412
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#define STM32_CHIPID_F4 0x413
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#define STM32_CHIPID_F1_HIGH 0x414
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#define STM32_CHIPID_L1_MEDIUM 0x416
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#define STM32_CHIPID_F1_CONN 0x418
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#define STM32_CHIPID_F1_VL_MEDIUM 0x420
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#define STM32_CHIPID_F1_VL_HIGH 0x428
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#define STM32_CHIPID_F1_XL 0x430
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// Constant STM32 memory map figures
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#define STM32_FLASH_BASE 0x08000000
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#define STM32_SRAM_BASE 0x20000000
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/* Cortex™-M3 Technical Reference Manual */
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/* Debug Halting Control and Status Register */
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#define DHCSR 0xe000edf0
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#define DCRSR 0xe000edf4
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#define DCRDR 0xe000edf8
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#define DBGKEY 0xa05f0000
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/* Enough space to hold both a V2 command or a V1 command packaged as generic scsi*/
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#define C_BUF_LEN 32
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typedef struct chip_params_ {
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uint32_t chip_id;
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char* description;
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uint32_t flash_size_reg;
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uint32_t flash_pagesize;
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uint32_t sram_size;
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uint32_t bootrom_base, bootrom_size;
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} chip_params_t;
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// These maps are from a combination of the Programming Manuals, and
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// also the Reference manuals. (flash size reg is normally in ref man)
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static const chip_params_t devices[] = {
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{ // table 2, PM0063
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.chip_id = 0x410,
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.description = "F1 Medium-density device",
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.flash_size_reg = 0x1ffff7e0,
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.flash_pagesize = 0x400,
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.sram_size = 0x5000,
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.bootrom_base = 0x1ffff000,
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.bootrom_size = 0x800
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},
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{ // table 1, PM0059
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.chip_id = 0x411,
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.description = "F2 device",
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.flash_size_reg = 0, /* no flash size reg found in the docs! */
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.flash_pagesize = 0x20000,
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.sram_size = 0x20000,
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.bootrom_base = 0x1fff0000,
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.bootrom_size = 0x7800
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},
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{ // PM0063
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.chip_id = 0x412,
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.description = "F1 Low-density device",
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.flash_size_reg = 0x1ffff7e0,
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.flash_pagesize = 0x400,
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.sram_size = 0x2800,
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.bootrom_base = 0x1ffff000,
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.bootrom_size = 0x800
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},
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{
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.chip_id = 0x413,
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.description = "F4 device",
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.flash_size_reg = 0x1FFF7A10, //RM0090 error same as unique ID
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.flash_pagesize = 0x4000,
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.sram_size = 0x30000,
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.bootrom_base = 0x1fff0000,
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.bootrom_size = 0x7800
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},
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{
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.chip_id = 0x414,
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.description = "F1 High-density device",
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.flash_size_reg = 0x1ffff7e0,
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.flash_pagesize = 0x800,
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.sram_size = 0x10000,
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.bootrom_base = 0x1ffff000,
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.bootrom_size = 0x800
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},
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{
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// This ignores the EEPROM! (and uses the page erase size,
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// not the sector write protection...)
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.chip_id = 0x416,
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.description = "L1 Med-density device",
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.flash_size_reg = 0x1ff8004c,
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.flash_pagesize = 0x100,
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.sram_size = 0x4000,
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.bootrom_base = 0x1ff00000,
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.bootrom_size = 0x1000
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},
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{
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.chip_id = 0x418,
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.description = "F1 Connectivity line device",
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.flash_size_reg = 0x1ffff7e0,
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.flash_pagesize = 0x800,
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.sram_size = 0x10000,
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.bootrom_base = 0x1fffb000,
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.bootrom_size = 0x4800
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},
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{
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.chip_id = 0x420,
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.description = "F1 Medium-density Value Line device",
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.flash_size_reg = 0x1ffff7e0,
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.flash_pagesize = 0x400,
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.sram_size = 0x2000,
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.bootrom_base = 0x1ffff000,
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.bootrom_size = 0x800
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},
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{
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.chip_id = 0x428,
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.description = "F1 High-density value line device",
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.flash_size_reg = 0x1ffff7e0,
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.flash_pagesize = 0x800,
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.sram_size = 0x8000,
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.bootrom_base = 0x1ffff000,
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.bootrom_size = 0x800
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},
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{
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.chip_id = 0x430,
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.description = "F1 XL-density device",
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.flash_size_reg = 0x1ffff7e0,
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.flash_pagesize = 0x800,
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.sram_size = 0x18000,
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.bootrom_base = 0x1fffe000,
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.bootrom_size = 0x1800
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},
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{
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//Use this as an example for mapping future chips:
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//RM0091 document was used to find these paramaters
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.chip_id = 0x440,
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.description = "F0 device",
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.flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735)
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.flash_pagesize = 0x400, // Page sizes listed in Table 4
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.sram_size = 0x2000, // "SRAM" byte size in hex from Table 2
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.bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2
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.bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2
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}
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};
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typedef struct {
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uint32_t r[16];
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uint32_t s[32];
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uint32_t xpsr;
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uint32_t main_sp;
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uint32_t process_sp;
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uint32_t rw;
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uint32_t rw2;
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uint8_t control;
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uint8_t faultmask;
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uint8_t basepri;
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uint8_t primask;
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uint32_t fpscr;
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} reg;
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typedef uint32_t stm32_addr_t;
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typedef struct _cortex_m3_cpuid_ {
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uint16_t implementer_id;
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uint16_t variant;
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uint16_t part;
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uint8_t revision;
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} cortex_m3_cpuid_t;
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typedef struct stlink_version_ {
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uint32_t stlink_v;
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uint32_t jtag_v;
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uint32_t swim_v;
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uint32_t st_vid;
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uint32_t stlink_pid;
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} stlink_version_t;
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typedef struct flash_loader {
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stm32_addr_t loader_addr; /* loader sram adddr */
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stm32_addr_t buf_addr; /* buffer sram address */
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} flash_loader_t;
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enum transport_type {
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TRANSPORT_TYPE_ZERO = 0,
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TRANSPORT_TYPE_LIBSG,
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TRANSPORT_TYPE_LIBUSB,
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TRANSPORT_TYPE_INVALID
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};
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typedef struct _stlink stlink_t;
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typedef struct _stlink_backend {
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void (*close) (stlink_t * sl);
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void (*exit_debug_mode) (stlink_t * sl);
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void (*enter_swd_mode) (stlink_t * sl);
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void (*enter_jtag_mode) (stlink_t * stl);
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void (*exit_dfu_mode) (stlink_t * stl);
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void (*core_id) (stlink_t * stl);
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void (*reset) (stlink_t * stl);
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void (*jtag_reset) (stlink_t * stl, int value);
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void (*run) (stlink_t * stl);
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void (*status) (stlink_t * stl);
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void (*version) (stlink_t *sl);
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uint32_t (*read_debug32) (stlink_t *sl, uint32_t addr);
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void (*read_mem32) (stlink_t *sl, uint32_t addr, uint16_t len);
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void (*write_debug32) (stlink_t *sl, uint32_t addr, uint32_t data);
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void (*write_mem32) (stlink_t *sl, uint32_t addr, uint16_t len);
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void (*write_mem8) (stlink_t *sl, uint32_t addr, uint16_t len);
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void (*read_all_regs) (stlink_t *sl, reg * regp);
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void (*read_reg) (stlink_t *sl, int r_idx, reg * regp);
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void (*read_all_unsupported_regs) (stlink_t *sl, reg *regp);
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void (*read_unsupported_reg) (stlink_t *sl, int r_idx, reg *regp);
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void (*write_unsupported_reg) (stlink_t *sl, uint32_t value, int idx, reg *regp);
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void (*write_reg) (stlink_t *sl, uint32_t reg, int idx);
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void (*step) (stlink_t * stl);
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int (*current_mode) (stlink_t * stl);
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void (*force_debug) (stlink_t *sl);
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} stlink_backend_t;
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struct _stlink {
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struct _stlink_backend *backend;
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void *backend_data;
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// Room for the command header
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unsigned char c_buf[C_BUF_LEN];
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// Data transferred from or to device
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unsigned char q_buf[Q_BUF_LEN];
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int q_len;
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// transport layer verboseness: 0 for no debug info, 10 for lots
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int verbose;
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uint32_t core_id;
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uint32_t chip_id;
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int core_stat;
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#define STM32_FLASH_PGSZ 1024
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#define STM32L_FLASH_PGSZ 256
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#define STM32F4_FLASH_PGSZ 16384
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#define STM32F4_FLASH_SIZE (128 * 1024 * 8)
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stm32_addr_t flash_base;
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size_t flash_size;
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size_t flash_pgsz;
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/* sram settings */
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#define STM32_SRAM_SIZE (8 * 1024)
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#define STM32L_SRAM_SIZE (16 * 1024)
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stm32_addr_t sram_base;
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size_t sram_size;
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// bootloader
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stm32_addr_t sys_base;
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size_t sys_size;
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struct stlink_version_ version;
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};
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//stlink_t* stlink_quirk_open(const char *dev_name, const int verbose);
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// delegated functions...
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void stlink_enter_swd_mode(stlink_t *sl);
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void stlink_enter_jtag_mode(stlink_t *sl);
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void stlink_exit_debug_mode(stlink_t *sl);
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void stlink_exit_dfu_mode(stlink_t *sl);
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void stlink_close(stlink_t *sl);
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uint32_t stlink_core_id(stlink_t *sl);
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void stlink_reset(stlink_t *sl);
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void stlink_jtag_reset(stlink_t *sl, int value);
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void stlink_run(stlink_t *sl);
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void stlink_status(stlink_t *sl);
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void stlink_version(stlink_t *sl);
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uint32_t stlink_read_debug32(stlink_t *sl, uint32_t addr);
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void stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len);
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void stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data);
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void stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len);
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void stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len);
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void stlink_read_all_regs(stlink_t *sl, reg *regp);
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void stlink_read_all_unsupported_regs(stlink_t *sl, reg *regp);
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void stlink_read_reg(stlink_t *sl, int r_idx, reg *regp);
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void stlink_read_unsupported_reg(stlink_t *sl, int r_idx, reg *regp);
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void stlink_write_unsupported_reg(stlink_t *sl, uint32_t value, int r_idx, reg *regp);
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void stlink_write_reg(stlink_t *sl, uint32_t reg, int idx);
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void stlink_step(stlink_t *sl);
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int stlink_current_mode(stlink_t *sl);
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void stlink_force_debug(stlink_t *sl);
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// unprocessed
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int stlink_erase_flash_mass(stlink_t* sl);
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int stlink_write_flash(stlink_t* sl, stm32_addr_t address, uint8_t* data, unsigned length);
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int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr);
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int stlink_fwrite_sram(stlink_t *sl, const char* path, stm32_addr_t addr);
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int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, unsigned length);
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// PUBLIC
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uint32_t stlink_chip_id(stlink_t *sl);
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void stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid);
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// privates, publics, the rest....
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// TODO sort what is private, and what is not
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int stlink_erase_flash_page(stlink_t* sl, stm32_addr_t flashaddr);
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uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr);
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uint16_t read_uint16(const unsigned char *c, const int pt);
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void stlink_core_stat(stlink_t *sl);
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void stlink_print_data(stlink_t *sl);
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unsigned int is_bigendian(void);
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uint32_t read_uint32(const unsigned char *c, const int pt);
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void write_uint32(unsigned char* buf, uint32_t ui);
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void write_uint16(unsigned char* buf, uint16_t ui);
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unsigned int is_core_halted(stlink_t *sl);
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int write_buffer_to_sram(stlink_t *sl, flash_loader_t* fl, const uint8_t* buf, size_t size);
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int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size);
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int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size);
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int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size);
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int stlink_load_device_params(stlink_t *sl);
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#include "stlink-sg.h"
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#include "stlink-usb.h"
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#ifdef __cplusplus
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}
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#endif
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#endif /* STLINK_COMMON_H */
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