kopia lustrzana https://github.com/stlink-org/stlink
207 wiersze
6.6 KiB
C
207 wiersze
6.6 KiB
C
/*
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* File: test_main.c
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*
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* main() ripped out of old stlink-hw.c
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*/
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <stlink.h>
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static void __attribute__((unused)) mark_buf(stlink_t *sl) {
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memset(sl->q_buf, 0, sizeof(sl->q_buf));
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sl->q_buf[0] = 0xaa;
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sl->q_buf[1] = 0xbb;
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sl->q_buf[2] = 0xcc;
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sl->q_buf[3] = 0xdd;
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sl->q_buf[4] = 0x11;
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sl->q_buf[15] = 0x22;
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sl->q_buf[16] = 0x33;
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sl->q_buf[63] = 0x44;
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sl->q_buf[64] = 0x69;
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sl->q_buf[1024 * 6 - 1] = 0x42; //6kB
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sl->q_buf[1024 * 8 - 1] = 0x42; //8kB
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}
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int main(void)
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{
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/* Avoid unused parameter warning */
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// set scpi lib debug level: 0 for no debug info, 10 for lots
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fputs(
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"\nUsage: stlink-access-test [anything at all] ...\n"
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"\n*** Notice: The stlink firmware violates the USB standard.\n"
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"*** Because we just use libusb, we can just tell the kernel's\n"
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"*** driver to simply ignore the device...\n"
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"*** Unplug the stlink and execute once as root:\n"
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"modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i\n\n",
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stderr);
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stlink_t *sl = stlink_v1_open(99, 1);
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if (sl == NULL)
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return 0;
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// we are in mass mode, go to swd
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stlink_enter_swd_mode(sl);
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stlink_current_mode(sl);
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stlink_core_id(sl);
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//----------------------------------------------------------------------
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stlink_status(sl);
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//stlink_force_debug(sl);
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stlink_reset(sl);
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stlink_status(sl);
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// core system control block
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stlink_read_mem32(sl, 0xe000ed00, 4);
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DLOG("cpu id base register: SCB_CPUID = got 0x%08x expect 0x411fc231\n", read_uint32(sl->q_buf, 0));
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// no MPU
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stlink_read_mem32(sl, 0xe000ed90, 4);
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DLOG("mpu type register: MPU_TYPER = got 0x%08x expect 0x0\n", read_uint32(sl->q_buf, 0));
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#if 0
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stlink_read_mem32(sl, 0xe000edf0, 4);
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DD(sl, "DHCSR = 0x%08x", read_uint32(sl->q_buf, 0));
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stlink_read_mem32(sl, 0x4001100c, 4);
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DD(sl, "GPIOC_ODR = 0x%08x", read_uint32(sl->q_buf, 0));
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#endif
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#if 0
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// happy new year 2011: let blink all the leds
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// see "RM0041 Reference manual - STM32F100xx advanced ARM-based 32-bit MCUs"
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#define GPIOC 0x40011000 // port C
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#define GPIOC_CRH (GPIOC + 0x04) // port configuration register high
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#define GPIOC_ODR (GPIOC + 0x0c) // port output data register
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#define LED_BLUE (1<<8) // pin 8
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#define LED_GREEN (1<<9) // pin 9
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stlink_read_mem32(sl, GPIOC_CRH, 4);
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uint32_t io_conf = read_uint32(sl->q_buf, 0);
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DLOG("GPIOC_CRH = 0x%08x\n", io_conf);
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// set: general purpose output push-pull, output mode, max speed 10 MHz.
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write_uint32(sl->q_buf, 0x44444411);
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stlink_write_mem32(sl, GPIOC_CRH, 4);
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memset(sl->q_buf, 0, sizeof(sl->q_buf));
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for (int i = 0; i < 100; i++) {
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write_uint32(sl->q_buf, LED_BLUE | LED_GREEN);
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stlink_write_mem32(sl, GPIOC_ODR, 4);
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/* stlink_read_mem32(sl, 0x4001100c, 4); */
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/* DD(sl, "GPIOC_ODR = 0x%08x", read_uint32(sl->q_buf, 0)); */
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usleep(100 * 1000);
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memset(sl->q_buf, 0, sizeof(sl->q_buf));
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stlink_write_mem32(sl, GPIOC_ODR, 4); // PC lo
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usleep(100 * 1000);
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}
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write_uint32(sl->q_buf, io_conf); // set old state
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#endif
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#if 0
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// TODO rtfm: stlink doesn't have flash write routines
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// writing to the flash area confuses the fw for the next read access
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//stlink_read_mem32(sl, 0, 1024*6);
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// flash 0x08000000 128kB
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fputs("++++++++++ read a flash at 0x0800 0000\n", stderr);
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stlink_read_mem32(sl, 0x08000000, 1024 * 6); //max 6kB
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clear_buf(sl);
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stlink_read_mem32(sl, 0x08000c00, 5);
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stlink_read_mem32(sl, 0x08000c00, 4);
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mark_buf(sl);
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stlink_write_mem32(sl, 0x08000c00, 4);
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stlink_read_mem32(sl, 0x08000c00, 256);
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stlink_read_mem32(sl, 0x08000c00, 256);
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#endif
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#if 0
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// sram 0x20000000 8kB
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fputs("\n++++++++++ read/write 8bit, sram at 0x2000 0000 ++++++++++++++++\n\n", stderr);
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memset(sl->q_buf, 0, sizeof(sl->q_buf));
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mark_buf(sl);
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//stlink_write_mem8(sl, 0x20000000, 16);
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//stlink_write_mem8(sl, 0x20000000, 1);
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//stlink_write_mem8(sl, 0x20000001, 1);
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stlink_write_mem8(sl, 0x2000000b, 3);
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stlink_read_mem32(sl, 0x20000000, 16);
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#endif
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#if 0
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// a not aligned mem32 access doesn't work indeed
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fputs("\n++++++++++ read/write 32bit, sram at 0x2000 0000 ++++++++++++++++\n\n", stderr);
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memset(sl->q_buf, 0, sizeof(sl->q_buf));
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mark_buf(sl);
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stlink_write_mem32(sl, 0x20000000, 1);
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stlink_read_mem32(sl, 0x20000000, 16);
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mark_buf(sl);
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stlink_write_mem32(sl, 0x20000001, 1);
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stlink_read_mem32(sl, 0x20000000, 16);
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mark_buf(sl);
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stlink_write_mem32(sl, 0x2000000b, 3);
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stlink_read_mem32(sl, 0x20000000, 16);
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mark_buf(sl);
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stlink_write_mem32(sl, 0x20000000, 17);
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stlink_read_mem32(sl, 0x20000000, 32);
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#endif
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#if 0
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// sram 0x20000000 8kB
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fputs("++++++++++ read/write 32bit, sram at 0x2000 0000 ++++++++++++\n", stderr);
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memset(sl->q_buf, 0, sizeof(sl->q_buf));
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mark_buf(sl);
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stlink_write_mem8(sl, 0x20000000, 64);
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stlink_read_mem32(sl, 0x20000000, 64);
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mark_buf(sl);
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stlink_write_mem32(sl, 0x20000000, 1024 * 8); //8kB
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stlink_read_mem32(sl, 0x20000000, 1024 * 6);
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stlink_read_mem32(sl, 0x20000000 + 1024 * 6, 1024 * 2);
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#endif
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#if 0
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stlink_run(sl);
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stlink_status(sl);
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stlink_force_debug(sl);
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stlink_status(sl);
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#endif
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#if 0 /* read the system bootloader */
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fputs("\n++++++++++ reading bootloader ++++++++++++++++\n\n", stderr);
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stlink_fread(sl, "/tmp/barfoo", sl->sys_base, sl->sys_size);
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#endif
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#if 0 /* read the flash memory */
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fputs("\n+++++++ read flash memory\n\n", stderr);
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/* mark_buf(sl); */
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stlink_read_mem32(sl, 0x08000000, 4);
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#endif
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#if 0 /* flash programming */
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fputs("\n+++++++ program flash memory\n\n", stderr);
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stlink_fwrite_flash(sl, "/tmp/foobar", 0x08000000);
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#endif
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#if 0 /* check file contents */
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fputs("\n+++++++ check flash memory\n\n", stderr);
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{
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const int res = stlink_fcheck_flash(sl, "/tmp/foobar", 0x08000000);
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printf("_____ stlink_fcheck_flash() == %d\n", res);
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}
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#endif
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#if 0
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fputs("\n+++++++ sram write and execute\n\n", stderr);
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stlink_fwrite_sram(sl, "/tmp/foobar", sl->sram_base);
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stlink_run_at(sl, sl->sram_base);
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#endif
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#if 0
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stlink_run(sl);
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stlink_status(sl);
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//----------------------------------------------------------------------
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// back to mass mode, just in case ...
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stlink_exit_debug_mode(sl);
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stlink_current_mode(sl);
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stlink_close(sl);
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#endif
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//fflush(stderr); fflush(stdout);
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return EXIT_SUCCESS;
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}
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