kopia lustrzana https://github.com/stlink-org/stlink
287 wiersze
8.9 KiB
C
287 wiersze
8.9 KiB
C
/*
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* File: stlink.h
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*
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* All common top level stlink interfaces, regardless of how the backend does the work....
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*/
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#ifndef STLINK_H
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#define STLINK_H
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#include <stdint.h>
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#include <stddef.h>
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#include <stdbool.h>
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#include <stm32.h>
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#include <stm32flash.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define STLINK_ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
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/* Max data transfer size */
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// 6kB = max mem32_read block, 8kB sram
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// #define Q_BUF_LEN 96
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#define Q_BUF_LEN (1024 * 100)
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/* Statuses of core */
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enum target_state {
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TARGET_UNKNOWN = 0,
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TARGET_RUNNING = 1,
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TARGET_HALTED = 2,
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TARGET_RESET = 3,
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TARGET_DEBUG_RUNNING = 4,
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};
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#define STLINK_CORE_RUNNING 0x80
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#define STLINK_CORE_HALTED 0x81
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/* STLINK modes */
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#define STLINK_DEV_DFU_MODE 0x00
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#define STLINK_DEV_MASS_MODE 0x01
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#define STLINK_DEV_DEBUG_MODE 0x02
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#define STLINK_DEV_UNKNOWN_MODE -1
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/* NRST pin states */
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#define STLINK_DEBUG_APIV2_DRIVE_NRST_LOW 0x00
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#define STLINK_DEBUG_APIV2_DRIVE_NRST_HIGH 0x01
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/* Baud rate divisors for SWDCLK */
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#define STLINK_SWDCLK_4MHZ_DIVISOR 0
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#define STLINK_SWDCLK_1P8MHZ_DIVISOR 1
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#define STLINK_SWDCLK_1P2MHZ_DIVISOR 2
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#define STLINK_SWDCLK_950KHZ_DIVISOR 3
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#define STLINK_SWDCLK_480KHZ_DIVISOR 7
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#define STLINK_SWDCLK_240KHZ_DIVISOR 15
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#define STLINK_SWDCLK_125KHZ_DIVISOR 31
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#define STLINK_SWDCLK_100KHZ_DIVISOR 40
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#define STLINK_SWDCLK_50KHZ_DIVISOR 79
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#define STLINK_SWDCLK_25KHZ_DIVISOR 158
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#define STLINK_SWDCLK_15KHZ_DIVISOR 265
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#define STLINK_SWDCLK_5KHZ_DIVISOR 798
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#define STLINK_SERIAL_LENGTH 24
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#define STLINK_SERIAL_BUFFER_SIZE (STLINK_SERIAL_LENGTH + 1)
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#define STLINK_V3_MAX_FREQ_NB 10
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#define STLINK_V2_TRACE_BUF_LEN 2048
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#define STLINK_V3_TRACE_BUF_LEN 8192
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#define STLINK_V2_MAX_TRACE_FREQUENCY 2000000
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#define STLINK_V3_MAX_TRACE_FREQUENCY 24000000
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#define STLINK_DEFAULT_TRACE_FREQUENCY 2000000
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/* Map the relevant features, quirks and workaround for specific firmware version of stlink */
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#define STLINK_F_HAS_TRACE (1 << 0)
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#define STLINK_F_HAS_SWD_SET_FREQ (1 << 1)
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#define STLINK_F_HAS_JTAG_SET_FREQ (1 << 2)
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#define STLINK_F_HAS_MEM_16BIT (1 << 3)
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#define STLINK_F_HAS_GETLASTRWSTATUS2 (1 << 4)
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#define STLINK_F_HAS_DAP_REG (1 << 5)
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#define STLINK_F_QUIRK_JTAG_DP_READ (1 << 6)
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#define STLINK_F_HAS_AP_INIT (1 << 7)
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#define STLINK_F_HAS_DPBANKSEL (1 << 8)
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#define STLINK_F_HAS_RW8_512BYTES (1 << 9)
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/* Additional MCU features */
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#define CHIP_F_HAS_DUAL_BANK (1 << 0)
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#define CHIP_F_HAS_SWO_TRACING (1 << 1)
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/* Error code */
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#define STLINK_DEBUG_ERR_OK 0x80
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#define STLINK_DEBUG_ERR_FAULT 0x81
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#define STLINK_DEBUG_ERR_WRITE 0x0c
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#define STLINK_DEBUG_ERR_WRITE_VERIFY 0x0d
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#define STLINK_DEBUG_ERR_AP_WAIT 0x10
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#define STLINK_DEBUG_ERR_AP_FAULT 0x11
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#define STLINK_DEBUG_ERR_AP_ERROR 0x12
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#define STLINK_DEBUG_ERR_DP_WAIT 0x14
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#define STLINK_DEBUG_ERR_DP_FAULT 0x15
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#define STLINK_DEBUG_ERR_DP_ERROR 0x16
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#define CMD_CHECK_NO 0
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#define CMD_CHECK_REP_LEN 1
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#define CMD_CHECK_STATUS 2
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#define CMD_CHECK_RETRY 3 /* check status and retry if wait error */
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#define C_BUF_LEN 32
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struct stlink_reg {
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uint32_t r[16];
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uint32_t s[32];
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uint32_t xpsr;
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uint32_t main_sp;
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uint32_t process_sp;
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uint32_t rw;
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uint32_t rw2;
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uint8_t control;
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uint8_t faultmask;
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uint8_t basepri;
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uint8_t primask;
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uint32_t fpscr;
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};
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typedef uint32_t stm32_addr_t;
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typedef struct flash_loader {
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stm32_addr_t loader_addr; // loader sram addr
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stm32_addr_t buf_addr; // buffer sram address
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uint32_t rcc_dma_bkp; // backup RCC DMA enable state
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uint32_t iwdg_kr; // IWDG key register address
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} flash_loader_t;
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typedef struct _cortex_m3_cpuid_ {
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uint16_t implementer_id;
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uint16_t variant;
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uint16_t part;
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uint8_t revision;
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} cortex_m3_cpuid_t;
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enum stlink_jtag_api_version {
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STLINK_JTAG_API_V1 = 1,
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STLINK_JTAG_API_V2,
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STLINK_JTAG_API_V3,
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};
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typedef struct stlink_version_ {
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uint32_t stlink_v;
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uint32_t jtag_v;
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uint32_t swim_v;
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uint32_t st_vid;
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uint32_t stlink_pid;
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// jtag api version supported
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enum stlink_jtag_api_version jtag_api;
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// one bit for each feature supported. See macros STLINK_F_*
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uint32_t flags;
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} stlink_version_t;
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enum transport_type {
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TRANSPORT_TYPE_ZERO = 0,
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TRANSPORT_TYPE_LIBSG,
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TRANSPORT_TYPE_LIBUSB,
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TRANSPORT_TYPE_INVALID
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};
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enum connect_type {
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CONNECT_HOT_PLUG = 0,
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CONNECT_NORMAL = 1,
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CONNECT_UNDER_RESET = 2,
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};
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enum reset_type {
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RESET_AUTO = 0,
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RESET_HARD = 1,
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RESET_SOFT = 2,
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RESET_SOFT_AND_HALT = 3,
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};
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enum run_type {
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RUN_NORMAL = 0,
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RUN_FLASH_LOADER = 1,
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};
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typedef struct _stlink stlink_t;
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#include <stm32.h>
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#include <backend.h>
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struct _stlink {
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struct _stlink_backend *backend;
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void *backend_data;
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// room for the command header
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unsigned char c_buf[C_BUF_LEN];
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// data transferred from or to device
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unsigned char q_buf[Q_BUF_LEN];
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int32_t q_len;
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// transport layer verboseness: 0 for no debug info, 10 for lots
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int32_t verbose;
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int32_t opt;
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uint32_t core_id; // set by stlink_core_id(), result from STLINK_DEBUGREADCOREID
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uint32_t chip_id; // set by stlink_load_device_params(), used to identify flash and sram
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enum target_state core_stat; // set by stlink_status()
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char serial[STLINK_SERIAL_BUFFER_SIZE];
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int32_t freq; // set by stlink_open_usb(), values: STLINK_SWDCLK_xxx_DIVISOR
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enum stm32_flash_type flash_type;
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// stlink_chipid_params.flash_type, set by stlink_load_device_params(), values: STM32_FLASH_TYPE_xx
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stm32_addr_t flash_base; // STM32_FLASH_BASE, set by stlink_load_device_params()
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uint32_t flash_size; // calculated by stlink_load_device_params()
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uint32_t flash_pgsz; // stlink_chipid_params.flash_pagesize, set by stlink_load_device_params()
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/* sram settings */
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stm32_addr_t sram_base; // STM32_SRAM_BASE, set by stlink_load_device_params()
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uint32_t sram_size; // stlink_chipid_params.sram_size, set by stlink_load_device_params()
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/* option settings */
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stm32_addr_t option_base;
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uint32_t option_size;
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// bootloader
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// sys_base and sys_size are not used by the tools, but are only there to download the bootloader code
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// (see tests/sg.c)
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stm32_addr_t sys_base; // stlink_chipid_params.bootrom_base, set by stlink_load_device_params()
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uint32_t sys_size; // stlink_chipid_params.bootrom_size, set by stlink_load_device_params()
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struct stlink_version_ version;
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uint32_t chip_flags; // stlink_chipid_params.flags, set by stlink_load_device_params(), values: CHIP_F_xxx
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uint32_t max_trace_freq; // set by stlink_open_usb()
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uint32_t otp_base;
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uint32_t otp_size;
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};
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/* Functions defined in common.c */
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int32_t stlink_enter_swd_mode(stlink_t *sl);
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// int32_t stlink_enter_jtag_mode(stlink_t *sl);
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int32_t stlink_exit_debug_mode(stlink_t *sl);
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int32_t stlink_exit_dfu_mode(stlink_t *sl);
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void stlink_close(stlink_t *sl);
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int32_t stlink_core_id(stlink_t *sl);
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int32_t stlink_reset(stlink_t *sl, enum reset_type type);
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int32_t stlink_run(stlink_t *sl, enum run_type type);
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int32_t stlink_status(stlink_t *sl);
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int32_t stlink_version(stlink_t *sl);
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int32_t stlink_step(stlink_t *sl);
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int32_t stlink_current_mode(stlink_t *sl);
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int32_t stlink_force_debug(stlink_t *sl);
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int32_t stlink_target_voltage(stlink_t *sl);
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int32_t stlink_set_swdclk(stlink_t *sl, int32_t freq_khz);
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int32_t stlink_parse_ihex(const char* path, uint8_t erased_pattern, uint8_t* *mem, uint32_t* size, uint32_t* begin);
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uint8_t stlink_get_erased_pattern(stlink_t *sl);
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int32_t stlink_mwrite_sram(stlink_t *sl, uint8_t* data, uint32_t length, stm32_addr_t addr);
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int32_t stlink_fwrite_sram(stlink_t *sl, const char* path, stm32_addr_t addr);
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int32_t stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid);
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uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr);
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//void stlink_core_stat(stlink_t *sl);
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void stlink_print_data(stlink_t *sl);
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uint32_t is_bigendian(void);
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bool stlink_is_core_halted(stlink_t *sl);
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int32_t write_buffer_to_sram(stlink_t *sl, flash_loader_t* fl, const uint8_t* buf, uint16_t size);
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// int32_t write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, uint16_t* size);
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int32_t stlink_fread(stlink_t* sl, const char* path, bool is_ihex, stm32_addr_t addr, uint32_t size);
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int32_t stlink_load_device_params(stlink_t *sl);
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int32_t stlink_target_connect(stlink_t *sl, enum connect_type connect);
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#include <chipid.h>
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#include <commands.h>
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#include <flash_loader.h>
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#include <sg.h>
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#include <usb.h>
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#include <version.h>
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#include <logging.h>
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#ifdef __cplusplus
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}
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#endif
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#endif // STLINK_H
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