kopia lustrzana https://github.com/stlink-org/stlink
262 wiersze
9.3 KiB
C
262 wiersze
9.3 KiB
C
/*
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* File: stlink.h
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*
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* This should contain all the common top level stlink interfaces, regardless
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* of how the backend does the work....
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*/
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#ifndef STLINK_H
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#define STLINK_H
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#include <stdint.h>
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#include <stddef.h>
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#include <stdbool.h>
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#include "stm32.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define STLINK_ARRAY_SIZE(x) (sizeof(x)/sizeof(x[0]))
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// Max data transfer size.
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// 6kB = max mem32_read block, 8kB sram
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//#define Q_BUF_LEN 96
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#define Q_BUF_LEN (1024 * 100)
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// STLINK_DEBUG_RESETSYS, etc:
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#define STLINK_CORE_RUNNING 0x80
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#define STLINK_CORE_HALTED 0x81
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#define STLINK_CORE_STAT_UNKNOWN -1
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#define STLINK_GET_VERSION 0xf1
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#define STLINK_GET_CURRENT_MODE 0xf5
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#define STLINK_GET_TARGET_VOLTAGE 0xF7
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#define STLINK_DEBUG_COMMAND 0xF2
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#define STLINK_DFU_COMMAND 0xF3
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#define STLINK_DFU_EXIT 0x07
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// STLINK_GET_CURRENT_MODE
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#define STLINK_DEV_DFU_MODE 0x00
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#define STLINK_DEV_MASS_MODE 0x01
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#define STLINK_DEV_DEBUG_MODE 0x02
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#define STLINK_DEV_UNKNOWN_MODE -1
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// TODO - possible poor names...
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#define STLINK_SWD_ENTER 0x30
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#define STLINK_SWD_READCOREID 0x32 // TBD
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#define STLINK_JTAG_WRITEDEBUG_32BIT 0x35
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#define STLINK_JTAG_READDEBUG_32BIT 0x36
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#define STLINK_JTAG_DRIVE_NRST 0x3c
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#define STLINK_DEBUG_APIV2_SWD_SET_FREQ 0x43
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#define STLINK_APIV3_SET_COM_FREQ 0x61
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#define STLINK_APIV3_GET_COM_FREQ 0x62
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#define STLINK_APIV3_GET_VERSION_EX 0xFB
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// Baud rate divisors for SWDCLK
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#define STLINK_SWDCLK_4MHZ_DIVISOR 0
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#define STLINK_SWDCLK_1P8MHZ_DIVISOR 1
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#define STLINK_SWDCLK_1P2MHZ_DIVISOR 2
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#define STLINK_SWDCLK_950KHZ_DIVISOR 3
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#define STLINK_SWDCLK_480KHZ_DIVISOR 7
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#define STLINK_SWDCLK_240KHZ_DIVISOR 15
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#define STLINK_SWDCLK_125KHZ_DIVISOR 31
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#define STLINK_SWDCLK_100KHZ_DIVISOR 40
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#define STLINK_SWDCLK_50KHZ_DIVISOR 79
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#define STLINK_SWDCLK_25KHZ_DIVISOR 158
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#define STLINK_SWDCLK_15KHZ_DIVISOR 265
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#define STLINK_SWDCLK_5KHZ_DIVISOR 798
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#define STLINK_SERIAL_MAX_SIZE 64
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#define STLINK_V3_MAX_FREQ_NB 10
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/* Enough space to hold both a V2 command or a V1 command packaged as generic scsi*/
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#define C_BUF_LEN 32
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enum stlink_flash_type {
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STLINK_FLASH_TYPE_UNKNOWN = 0,
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STLINK_FLASH_TYPE_F0, /* used by f0, f1 (except f1xl),f3. */
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STLINK_FLASH_TYPE_F1_XL, /* f0 flash with dual bank, apparently */
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STLINK_FLASH_TYPE_F4, /* used by f2, f4, f7 */
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STLINK_FLASH_TYPE_L0, /* l0, l1 */
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STLINK_FLASH_TYPE_L4, /* l4, l4+ */
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STLINK_FLASH_TYPE_G0,
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STLINK_FLASH_TYPE_G4,
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STLINK_FLASH_TYPE_WB
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};
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struct stlink_reg {
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uint32_t r[16];
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uint32_t s[32];
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uint32_t xpsr;
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uint32_t main_sp;
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uint32_t process_sp;
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uint32_t rw;
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uint32_t rw2;
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uint8_t control;
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uint8_t faultmask;
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uint8_t basepri;
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uint8_t primask;
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uint32_t fpscr;
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};
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typedef uint32_t stm32_addr_t;
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typedef struct flash_loader {
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stm32_addr_t loader_addr; /* loader sram adddr */
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stm32_addr_t buf_addr; /* buffer sram address */
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} flash_loader_t;
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typedef struct _cortex_m3_cpuid_ {
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uint16_t implementer_id;
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uint16_t variant;
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uint16_t part;
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uint8_t revision;
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} cortex_m3_cpuid_t;
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typedef struct stlink_version_ {
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uint32_t stlink_v;
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uint32_t jtag_v;
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uint32_t swim_v;
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uint32_t st_vid;
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uint32_t stlink_pid;
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} stlink_version_t;
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enum transport_type {
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TRANSPORT_TYPE_ZERO = 0,
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TRANSPORT_TYPE_LIBSG,
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TRANSPORT_TYPE_LIBUSB,
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TRANSPORT_TYPE_INVALID
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};
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typedef struct _stlink stlink_t;
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#include "stlink/backend.h"
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struct _stlink {
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struct _stlink_backend *backend;
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void *backend_data;
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// Room for the command header
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unsigned char c_buf[C_BUF_LEN];
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// Data transferred from or to device
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unsigned char q_buf[Q_BUF_LEN];
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int q_len;
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// transport layer verboseness: 0 for no debug info, 10 for lots
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int verbose;
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int opt;
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uint32_t core_id; // set by stlink_core_id(), result from STLINK_DEBUGREADCOREID
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uint32_t chip_id; // set by stlink_load_device_params(), used to identify flash and sram
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int core_stat; // set by stlink_status(), values STLINK_CORE_xxxxx
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char serial[STLINK_SERIAL_MAX_SIZE];
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int serial_size;
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enum stlink_flash_type flash_type; // stlink_chipid_params.flash_type, set by stlink_load_device_params(), values: STLINK_FLASH_TYPE_xxx
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bool has_dual_bank;
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stm32_addr_t flash_base; // STM32_FLASH_BASE, set by stlink_load_device_params()
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size_t flash_size; // calculated by stlink_load_device_params()
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size_t flash_pgsz; // stlink_chipid_params.flash_pagesize, set by stlink_load_device_params()
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/* sram settings */
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stm32_addr_t sram_base; // STM32_SRAM_BASE, set by stlink_load_device_params()
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size_t sram_size; // stlink_chipid_params.sram_size, set by stlink_load_device_params()
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/* option settings */
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stm32_addr_t option_base;
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size_t option_size;
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// bootloader
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// sys_base and sys_size are not used by the tools, but are only there to
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// download the bootloader code (see tests/sg.c)
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stm32_addr_t sys_base; // stlink_chipid_params.bootrom_base, set by stlink_load_device_params()
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size_t sys_size; // stlink_chipid_params.bootrom_size, set by stlink_load_device_params()
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struct stlink_version_ version;
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};
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int stlink_enter_swd_mode(stlink_t *sl);
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int stlink_enter_jtag_mode(stlink_t *sl);
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int stlink_exit_debug_mode(stlink_t *sl);
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int stlink_exit_dfu_mode(stlink_t *sl);
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void stlink_close(stlink_t *sl);
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int stlink_core_id(stlink_t *sl);
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int stlink_reset(stlink_t *sl);
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int stlink_jtag_reset(stlink_t *sl, int value);
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int stlink_run(stlink_t *sl);
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int stlink_status(stlink_t *sl);
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int stlink_version(stlink_t *sl);
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int stlink_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data);
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int stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len);
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int stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data);
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int stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len);
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int stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len);
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int stlink_read_all_regs(stlink_t *sl, struct stlink_reg *regp);
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int stlink_read_all_unsupported_regs(stlink_t *sl, struct stlink_reg *regp);
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int stlink_read_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp);
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int stlink_read_unsupported_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp);
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int stlink_write_unsupported_reg(stlink_t *sl, uint32_t value, int r_idx, struct stlink_reg *regp);
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int stlink_write_reg(stlink_t *sl, uint32_t reg, int idx);
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int stlink_step(stlink_t *sl);
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int stlink_current_mode(stlink_t *sl);
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int stlink_force_debug(stlink_t *sl);
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int stlink_target_voltage(stlink_t *sl);
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int stlink_set_swdclk(stlink_t *sl, uint16_t divisor);
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int stlink_erase_flash_mass(stlink_t* sl);
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int stlink_write_flash(stlink_t* sl, stm32_addr_t address, uint8_t* data, uint32_t length, uint8_t eraseonly);
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int stlink_parse_ihex(const char* path, uint8_t erased_pattern, uint8_t * * mem, size_t * size, uint32_t * begin);
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uint8_t stlink_get_erased_pattern(stlink_t *sl);
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int stlink_mwrite_flash(stlink_t *sl, uint8_t* data, uint32_t length, stm32_addr_t addr);
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int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr);
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int stlink_mwrite_sram(stlink_t *sl, uint8_t* data, uint32_t length, stm32_addr_t addr);
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int stlink_fwrite_sram(stlink_t *sl, const char* path, stm32_addr_t addr);
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int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, uint32_t length);
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int stlink_chip_id(stlink_t *sl, uint32_t *chip_id);
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int stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid);
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int stlink_erase_flash_page(stlink_t* sl, stm32_addr_t flashaddr);
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uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr);
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uint16_t read_uint16(const unsigned char *c, const int pt);
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void stlink_core_stat(stlink_t *sl);
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void stlink_print_data(stlink_t *sl);
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unsigned int is_bigendian(void);
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uint32_t read_uint32(const unsigned char *c, const int pt);
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void write_uint32(unsigned char* buf, uint32_t ui);
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void write_uint16(unsigned char* buf, uint16_t ui);
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bool stlink_is_core_halted(stlink_t *sl);
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int write_buffer_to_sram(stlink_t *sl, flash_loader_t* fl, const uint8_t* buf, size_t size);
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int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size);
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int stlink_fread(stlink_t* sl, const char* path, bool is_ihex, stm32_addr_t addr, size_t size);
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int stlink_load_device_params(stlink_t *sl);
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int stlink_read_option_bytes32(stlink_t *sl, uint32_t* option_byte);
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int stlink_write_option_bytes32(stlink_t *sl, uint32_t option_byte);
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int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len);
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int stlink_fwrite_option_bytes(stlink_t *sl, const char* path, stm32_addr_t addr);
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#include "stlink/sg.h"
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#include "stlink/usb.h"
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#include "stlink/reg.h"
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#include "stlink/commands.h"
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#include "stlink/chipid.h"
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#include "stlink/flash_loader.h"
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#include "stlink/version.h"
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#include "stlink/logging.h"
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#ifdef __cplusplus
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}
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#endif
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#endif /* STLINK_H */
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