kopia lustrzana https://github.com/stlink-org/stlink
Add STM32WLEx support
rodzic
9605d21b5b
commit
fe48a98cb1
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@ -0,0 +1,13 @@
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# Chip-ID file for WLE
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#
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chip_id 0x497
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description WLE
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flash_type 9
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flash_pagesize 0x800
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sram_size 0x10000
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bootrom_base 0x1fff0000
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bootrom_size 0x7000
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option_base 0x0
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option_size 0x0
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flags swo
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@ -847,6 +847,18 @@ static struct stlink_chipid_params devices[] = {
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.bootrom_size = 0x7000,
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.flags = CHIP_F_HAS_SWO_TRACING,
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},
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{
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// STM32WLEx
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.chip_id = STLINK_CHIPID_STM32_WLE,
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.description = "WLEx",
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.flash_type = STLINK_FLASH_TYPE_WB,
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.flash_size_reg = 0x1FFF75E0,
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.flash_pagesize = 0x800, // 2k
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.sram_size = 0x10000,
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.bootrom_base = 0x1fff0000, // see the memory map
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.bootrom_size = 0x7000,
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.flags = CHIP_F_HAS_SWO_TRACING,
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},
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{
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// STM32H742/743/753 (from RM0433)
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.chip_id = STLINK_CHIPID_STM32_H74xxx,
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@ -70,7 +70,8 @@ enum stlink_stm32_chipids {
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STLINK_CHIPID_STM32_G4_CAT4 = 0x479,
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STLINK_CHIPID_STM32_H7Ax = 0x480, /* RM0455, p.2863 */
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STLINK_CHIPID_STM32_H72x = 0x483, /* RM0468, p.3199 */
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STLINK_CHIPID_STM32_WB55 = 0x495
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STLINK_CHIPID_STM32_WB55 = 0x495,
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STLINK_CHIPID_STM32_WLE = 0x497
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};
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#define CHIP_F_HAS_DUAL_BANK (1 << 0)
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