kopia lustrzana https://github.com/stlink-org/stlink
Fix for broken STML0 and STML1
Commitspull/407/head907383da8eande43a737c3cwere causing issues for people with STML0's and STML1's. This commit reverses the changes in these two commits.
Tom de Boer
rodzic
0bb22e9ed6
commit
f5d6cec4c7
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@ -34,29 +34,31 @@
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.global write
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/*
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r0 - source address
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r1 - destination address
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r0 - destination address
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r1 - source address
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r2 - count
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*/
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// Set 0 to r3
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movs r3, #0
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// Go to compare
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b test_done
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b.n test_done
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write_word:
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// Load one word from address in r0, increment by 4
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ldr r4, [r0]
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ldr r4, [r1]
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// Store the word to address in r1, increment by 4
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str r4, [r1]
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// Decrement r2
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subs r2, #1
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str r4, [r0]
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// Increment r3
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adds r3, #1
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adds r1, #4
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// does not matter, only first addr is important
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// next 15 bytes are in sequnce RM0367 page 66
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adds r0, #4
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test_done:
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// Test r2
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cmp r2, #0
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// Compare r3 and r2
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cmp r3, r2
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// Loop if not zero
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bcc.n write_word
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@ -34,25 +34,27 @@
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.global write
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/*
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r0 - source address
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r1 - destination address
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r0 - destination address
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r1 - source address
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r2 - count
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*/
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// Set 0 to r3
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movs r3, #0
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// Go to compare
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b test_done
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b.n test_done
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write_word:
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// Load one word from address in r0, increment by 4
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ldr.w ip, [r0], #4
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ldr.w ip, [r1], #4
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// Store the word to address in r1, increment by 4
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str.w ip, [r1], #4
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// Decrement r2
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subs r2, #1
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str.w ip, [r0], #4
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// Increment r3
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adds r3, #1
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test_done:
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// Test r2
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cmp r2, #0
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// Compare r3 and r2
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cmp r3, r2
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// Loop if not zero
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bcc.n write_word
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91
src/common.c
91
src/common.c
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@ -593,12 +593,6 @@ int stlink_load_device_params(stlink_t *sl) {
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return -1;
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}
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if (params->flash_type == FLASH_TYPE_UNKNOWN) {
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WLOG("Invalid flash type, please check device declaration\n");
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return -1;
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}
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// These are fixed...
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sl->flash_base = STM32_FLASH_BASE;
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sl->sram_base = STM32_SRAM_BASE;
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@ -1511,19 +1505,20 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) {
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static const uint8_t loader_code_stm32l[] = {
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/* openocd.git/contrib/loaders/flash/stm32lx.S
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r0, input, source addr
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r1, input, dest addr
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r0, input, dest addr
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r1, input, source addr
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r2, input, word count
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r2, output, remaining word count
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r3, output, word count
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*/
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0x00, 0x23,
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0x04, 0xe0,
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0x50, 0xf8, 0x04, 0xcb,
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0x41, 0xf8, 0x04, 0xcb,
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0x01, 0x3a,
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0x51, 0xf8, 0x04, 0xcb,
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0x40, 0xf8, 0x04, 0xcb,
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0x01, 0x33,
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0x00, 0x2a,
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0x93, 0x42,
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0xf8, 0xd3,
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0x00, 0xbe
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};
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@ -1531,21 +1526,22 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) {
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static const uint8_t loader_code_stm32l0[] = {
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/*
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r0, input, source addr
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r1, input, dest addr
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r0, input, dest addr
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r1, input, source addr
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r2, input, word count
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r2, output, remaining word count
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r3, output, word count
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*/
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0x00, 0x23,
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0x04, 0xe0,
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0x04, 0x68,
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0x0c, 0x60,
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0x01, 0x3a,
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0x0c, 0x68,
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0x04, 0x60,
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0x01, 0x33,
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0x04, 0x31,
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0x04, 0x30,
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0x00, 0x2a,
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0x93, 0x42,
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0xf8, 0xd3,
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0x00, 0xbe
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};
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@ -1608,7 +1604,7 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) {
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0xfb, 0xd1, // bne.n <wait>
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0x00, 0xf1, 0x08, 0x00, // add.w r0, r0, #8
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0x01, 0xf1, 0x08, 0x01, // add.w r1, r1, #8
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0xa2, 0xf1, 0x01, 0x02, // sub.w r2, r2, #1
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0xa2, 0xf1, 0x02, 0x02, // add.w r2, r2, #2
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0xef, 0xe7, // b.n <next>
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0x00, 0xbe, // done: bkpt 0x0000
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0x00, 0x20, 0x02, 0x40 // flash_base: .word 0x40022000
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@ -2072,8 +2068,8 @@ int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) {
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int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size) {
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reg rr;
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int i = 0;
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size_t count = 0;
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int target_reg, source_reg, i = 0;
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size_t count;
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DLOG("Running flash loader, write address:%#x, size: %zd\n", target, size);
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// FIXME This can never return -1
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@ -2083,23 +2079,36 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons
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return -1;
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}
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if (sl->flash_type == FLASH_TYPE_F0) {
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count = size / sizeof(uint16_t);
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if (size % sizeof(uint16_t))
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++count;
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} else if (sl->flash_type == FLASH_TYPE_F4 || sl->flash_type == FLASH_TYPE_L0) {
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if (sl->flash_type == FLASH_TYPE_L0) {
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count = size / sizeof(uint32_t);
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if (size % sizeof(uint32_t))
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++count;
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} else if (sl->flash_type == FLASH_TYPE_L4) {
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count = size / sizeof(uint64_t);
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if (size % sizeof(uint64_t))
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target_reg = 0;
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source_reg = 1;
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} else if (sl->flash_type == FLASH_TYPE_F0) {
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count = size / sizeof(uint16_t);
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if (size % sizeof(uint16_t))
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++count;
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target_reg = 1;
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source_reg = 0;
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} else if (sl->flash_type == FLASH_TYPE_F4 || sl->flash_type == FLASH_TYPE_L4) {
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count = size / sizeof(uint32_t);
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if (size % sizeof(uint32_t))
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++count;
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if (sl->chip_id == STM32_CHIPID_L4) {
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if (count % 2)
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++count;
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}
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target_reg = 1;
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source_reg = 0;
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} else {
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fprintf(stderr, "unknown coreid 0x%x, don't know what flash loader to use\n", sl->core_id);
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return -1;
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}
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/* setup core */
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stlink_write_reg(sl, fl->buf_addr, 0); /* source */
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stlink_write_reg(sl, target, 1); /* target */
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stlink_write_reg(sl, fl->buf_addr, source_reg); /* source */
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stlink_write_reg(sl, target, target_reg); /* target */
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stlink_write_reg(sl, count, 2); /* count */
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stlink_write_reg(sl, 0, 3); /* flash bank 0 (input), only used on F0, but armless fopr others */
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stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */
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@ -2120,11 +2129,19 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons
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return -1;
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}
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stlink_read_all_regs(sl, &rr);
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/* check written byte count */
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stlink_read_reg(sl, 2, &rr);
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if (rr.r[2] != 0) {
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fprintf(stderr, "write error, count == %u\n", rr.r[2]);
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return -1;
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if (sl->flash_type == FLASH_TYPE_L0) {
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if (rr.r[3] != count) {
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fprintf(stderr, "write error, count == %u\n", rr.r[3]);
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return -1;
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}
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} else {
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if (rr.r[2] != 0) {
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fprintf(stderr, "write error, count == %u\n", rr.r[2]);
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return -1;
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}
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}
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return 0;
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