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Unify chipid naming convention. 

Flag more duplicate variables that need to be removed/combined
pull/54/head
Karl Palsson 2012-02-01 20:55:10 +00:00
rodzic 9aeeca2687
commit f38ff8f912
3 zmienionych plików z 24 dodań i 27 usunięć
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2
gdbserver/gdb-server.c
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@ -219,7 +219,7 @@ char* make_memory_map(stlink_t *sl) {
char* map = malloc(4096); char* map = malloc(4096);
map[0] = '\0'; map[0] = '\0';
if(sl->chip_id==STM32F4_CHIP_ID) { if(sl->chip_id==STM32_CHIPID_F4) {
strcpy(map, memory_map_template_F4); strcpy(map, memory_map_template_F4);
} else { } else {
snprintf(map, 4096, memory_map_template, snprintf(map, 4096, memory_map_template,

28
src/stlink-common.c
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@ -136,7 +136,7 @@ static inline uint32_t read_flash_obr(stlink_t *sl) {
static inline uint32_t read_flash_cr(stlink_t *sl) { static inline uint32_t read_flash_cr(stlink_t *sl) {
uint32_t res; uint32_t res;
if(sl->chip_id==STM32F4_CHIP_ID) if(sl->chip_id==STM32_CHIPID_F4)
res = stlink_read_debug32(sl, FLASH_F4_CR); res = stlink_read_debug32(sl, FLASH_F4_CR);
else else
res = stlink_read_debug32(sl, FLASH_CR); res = stlink_read_debug32(sl, FLASH_CR);
@ -148,7 +148,7 @@ static inline uint32_t read_flash_cr(stlink_t *sl) {
static inline unsigned int is_flash_locked(stlink_t *sl) { static inline unsigned int is_flash_locked(stlink_t *sl) {
/* return non zero for true */ /* return non zero for true */
if(sl->chip_id==STM32F4_CHIP_ID) if(sl->chip_id==STM32_CHIPID_F4)
return read_flash_cr(sl) & (1 << FLASH_F4_CR_LOCK); return read_flash_cr(sl) & (1 << FLASH_F4_CR_LOCK);
else else
return read_flash_cr(sl) & (1 << FLASH_CR_LOCK); return read_flash_cr(sl) & (1 << FLASH_CR_LOCK);
@ -160,7 +160,7 @@ static void unlock_flash(stlink_t *sl) {
an invalid sequence results in a definitive lock of an invalid sequence results in a definitive lock of
the FPEC block until next reset. the FPEC block until next reset.
*/ */
if(sl->chip_id==STM32F4_CHIP_ID) { if(sl->chip_id==STM32_CHIPID_F4) {
stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY1); stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY1);
stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY2); stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY2);
} }
@ -186,7 +186,7 @@ static int unlock_flash_if(stlink_t *sl) {
} }
static void lock_flash(stlink_t *sl) { static void lock_flash(stlink_t *sl) {
if(sl->chip_id==STM32F4_CHIP_ID) { if(sl->chip_id==STM32_CHIPID_F4) {
const uint32_t n = read_flash_cr(sl) | (1 << FLASH_F4_CR_LOCK); const uint32_t n = read_flash_cr(sl) | (1 << FLASH_F4_CR_LOCK);
stlink_write_debug32(sl, FLASH_F4_CR, n); stlink_write_debug32(sl, FLASH_F4_CR, n);
} }
@ -199,7 +199,7 @@ static void lock_flash(stlink_t *sl) {
static void set_flash_cr_pg(stlink_t *sl) { static void set_flash_cr_pg(stlink_t *sl) {
if(sl->chip_id==STM32F4_CHIP_ID) { if(sl->chip_id==STM32_CHIPID_F4) {
uint32_t x = read_flash_cr(sl); uint32_t x = read_flash_cr(sl);
x |= (1 << FLASH_CR_PG); x |= (1 << FLASH_CR_PG);
stlink_write_debug32(sl, FLASH_F4_CR, x); stlink_write_debug32(sl, FLASH_F4_CR, x);
@ -212,7 +212,7 @@ static void set_flash_cr_pg(stlink_t *sl) {
static void __attribute__((unused)) clear_flash_cr_pg(stlink_t *sl) { static void __attribute__((unused)) clear_flash_cr_pg(stlink_t *sl) {
const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_PG); const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_PG);
if(sl->chip_id==STM32F4_CHIP_ID) if(sl->chip_id==STM32_CHIPID_F4)
stlink_write_debug32(sl, FLASH_F4_CR, n); stlink_write_debug32(sl, FLASH_F4_CR, n);
else else
stlink_write_debug32(sl, FLASH_CR, n); stlink_write_debug32(sl, FLASH_CR, n);
@ -229,7 +229,7 @@ static void __attribute__((unused)) clear_flash_cr_per(stlink_t *sl) {
} }
static void set_flash_cr_mer(stlink_t *sl) { static void set_flash_cr_mer(stlink_t *sl) {
if(sl->chip_id == STM32F4_CHIP_ID) if(sl->chip_id == STM32_CHIPID_F4)
stlink_write_debug32(sl, FLASH_F4_CR, stlink_write_debug32(sl, FLASH_F4_CR,
stlink_read_debug32(sl, FLASH_F4_CR) | (1 << FLASH_CR_MER)); stlink_read_debug32(sl, FLASH_F4_CR) | (1 << FLASH_CR_MER));
else else
@ -238,7 +238,7 @@ static void set_flash_cr_mer(stlink_t *sl) {
} }
static void __attribute__((unused)) clear_flash_cr_mer(stlink_t *sl) { static void __attribute__((unused)) clear_flash_cr_mer(stlink_t *sl) {
if(sl->chip_id == STM32F4_CHIP_ID) if(sl->chip_id == STM32_CHIPID_F4)
stlink_write_debug32(sl, FLASH_F4_CR, stlink_write_debug32(sl, FLASH_F4_CR,
stlink_read_debug32(sl, FLASH_F4_CR) & ~(1 << FLASH_CR_MER)); stlink_read_debug32(sl, FLASH_F4_CR) & ~(1 << FLASH_CR_MER));
else else
@ -247,7 +247,7 @@ static void __attribute__((unused)) clear_flash_cr_mer(stlink_t *sl) {
} }
static void set_flash_cr_strt(stlink_t *sl) { static void set_flash_cr_strt(stlink_t *sl) {
if(sl->chip_id == STM32F4_CHIP_ID) if(sl->chip_id == STM32_CHIPID_F4)
{ {
uint32_t x = read_flash_cr(sl); uint32_t x = read_flash_cr(sl);
x |= (1 << FLASH_F4_CR_STRT); x |= (1 << FLASH_F4_CR_STRT);
@ -266,7 +266,7 @@ static inline uint32_t read_flash_acr(stlink_t *sl) {
static inline uint32_t read_flash_sr(stlink_t *sl) { static inline uint32_t read_flash_sr(stlink_t *sl) {
uint32_t res; uint32_t res;
if(sl->chip_id==STM32F4_CHIP_ID) if(sl->chip_id==STM32_CHIPID_F4)
res = stlink_read_debug32(sl, FLASH_F4_SR); res = stlink_read_debug32(sl, FLASH_F4_SR);
else else
res = stlink_read_debug32(sl, FLASH_SR); res = stlink_read_debug32(sl, FLASH_SR);
@ -275,7 +275,7 @@ static inline uint32_t read_flash_sr(stlink_t *sl) {
} }
static inline unsigned int is_flash_busy(stlink_t *sl) { static inline unsigned int is_flash_busy(stlink_t *sl) {
if(sl->chip_id==STM32F4_CHIP_ID) if(sl->chip_id==STM32_CHIPID_F4)
return read_flash_sr(sl) & (1 << FLASH_F4_SR_BSY); return read_flash_sr(sl) & (1 << FLASH_F4_SR_BSY);
else else
return read_flash_sr(sl) & (1 << FLASH_SR_BSY); return read_flash_sr(sl) & (1 << FLASH_SR_BSY);
@ -927,7 +927,7 @@ uint32_t calculate_F4_sectornum(uint32_t flashaddr){
} }
uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){ uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){
if(sl->chip_id == STM32F4_CHIP_ID) { if(sl->chip_id == STM32_CHIPID_F4) {
uint32_t sector=calculate_F4_sectornum(flashaddr); uint32_t sector=calculate_F4_sectornum(flashaddr);
if (sector<4) sl->flash_pgsz=0x4000; if (sector<4) sl->flash_pgsz=0x4000;
else if(sector<5) sl->flash_pgsz=0x10000; else if(sector<5) sl->flash_pgsz=0x10000;
@ -944,7 +944,7 @@ uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){
*/ */
int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr)
{ {
if (sl->chip_id == STM32F4_CHIP_ID) if (sl->chip_id == STM32_CHIPID_F4)
{ {
/* wait for ongoing op to finish */ /* wait for ongoing op to finish */
wait_flash_busy(sl); wait_flash_busy(sl);
@ -1359,7 +1359,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned
ILOG("Finished erasing %d pages of %d (%#x) bytes\n", ILOG("Finished erasing %d pages of %d (%#x) bytes\n",
page_count, sl->flash_pgsz, sl->flash_pgsz); page_count, sl->flash_pgsz, sl->flash_pgsz);
if (sl->chip_id == STM32F4_CHIP_ID) { if (sl->chip_id == STM32_CHIPID_F4) {
/* todo: check write operation */ /* todo: check write operation */
/* First unlock the cr */ /* First unlock the cr */

21
src/stlink-common.h
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@ -81,10 +81,18 @@ extern "C" {
#define CM3_REG_FP_COMP0 0xE0002008 #define CM3_REG_FP_COMP0 0xE0002008
/* cortex core ids */ /* cortex core ids */
// TODO clean this up...
#define STM32VL_CORE_ID 0x1ba01477 #define STM32VL_CORE_ID 0x1ba01477
#define STM32L_CORE_ID 0x2ba01477 #define STM32L_CORE_ID 0x2ba01477
#define STM32F4_CORE_ID 0x2ba01477 #define STM32F4_CORE_ID 0x2ba01477
#define CORE_M3_R1 0x1BA00477
#define CORE_M3_R2 0x4BA00477
#define CORE_M4_R0 0x2BA01477
/*
* Chip IDs are explained in the appropriate programming manual for the
* DBGMCU_IDCODE register (0xE0042000)
*/
// stm32 chipids, only lower 12 bits.. // stm32 chipids, only lower 12 bits..
#define STM32_CHIPID_F1_MEDIUM 0x410 #define STM32_CHIPID_F1_MEDIUM 0x410
#define STM32_CHIPID_F2 0x411 #define STM32_CHIPID_F2 0x411
@ -101,17 +109,6 @@ extern "C" {
#define STM32_FLASH_BASE 0x08000000 #define STM32_FLASH_BASE 0x08000000
#define STM32_SRAM_BASE 0x20000000 #define STM32_SRAM_BASE 0x20000000
/*
* Chip IDs are explained in the appropriate programming manual for the
* DBGMCU_IDCODE register (0xE0042000)
*/
#define CORE_M3_R1 0x1BA00477
#define CORE_M3_R2 0x4BA00477
#define CORE_M4_R0 0x2BA01477
/* using chip id for F4 ident, since core id is same as F1 */
#define STM32F4_CHIP_ID 0x413
/* Cortex™-M3 Technical Reference Manual */ /* Cortex™-M3 Technical Reference Manual */
/* Debug Halting Control and Status Register */ /* Debug Halting Control and Status Register */
#define DHCSR 0xe000edf0 #define DHCSR 0xe000edf0