kopia lustrzana https://github.com/stlink-org/stlink
Core ID reading rework
rodzic
40e9aa22ba
commit
ee2c9f508e
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@ -8,9 +8,10 @@
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#define STM32_H
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/* Cortex core ids */
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#define STM32VL_CORE_ID 0x1ba01477
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#define STM32F7_CORE_ID 0x5ba02477
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#define STM32H7_CORE_ID 0x6ba02477 // STM32H7 JTAG ID Code (RM0433 pg3065)
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#define STM32VL_CORE_ID 0x1ba01477
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#define STM32F7_CORE_ID 0x5ba02477
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#define STM32H7_CORE_ID 0x6ba02477 // STM32H7 SWD ID Code
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#define STM32H7_CORE_ID_JTAG 0x6ba00477 // STM32H7 JTAG ID Code (RM0433 pg3065)
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/* Constant STM32 memory map figures */
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#define STM32_FLASH_BASE ((uint32_t)0x08000000)
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45
src/common.c
45
src/common.c
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@ -1229,20 +1229,43 @@ int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) {
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if (stlink_read_debug32(sl, STLINK_REG_CM3_CPUID, &cpu_id))
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cpu_id = 0;
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// If the chip is an H7, read the chipid from the new address
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if (sl->core_id == STM32H7_CORE_ID && cpu_id == STLINK_REG_CMx_CPUID_CM7) {
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/*
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* the chip_id register in the reference manual have
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* DBGMCU_IDCODE / DBG_IDCODE name
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*
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*/
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uint32_t part_no = STLINK_REG_CM3_CPUID_PARTNO(cpu_id);
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if ((sl->core_id == STM32H7_CORE_ID ||
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sl->core_id == STM32H7_CORE_ID_JTAG) &&
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part_no == STLINK_REG_CMx_CPUID_PARTNO_CM7) {
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// STM32H7 chipid in 0x5c001000 (RM0433 pg3189)
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ret = stlink_read_debug32(sl, 0x5c001000, chip_id);
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}
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if (*chip_id == 0) {
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// default chipid address
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ret = stlink_read_debug32(sl, 0xE0042000, chip_id);
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}
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if (*chip_id == 0) {
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// Try Corex M0 DBGMCU_IDCODE register address
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} else if (part_no == STLINK_REG_CMx_CPUID_PARTNO_CM0) {
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// STM32F0 (RM0091, pg914; RM0360, pg713)
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// STM32L0 (RM0377, pg813; RM0367, pg915; RM0376, pg917)
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// STM32G0 (RM0444, pg1367)
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ret = stlink_read_debug32(sl, 0x40015800, chip_id);
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} else if (part_no == STLINK_REG_CMx_CPUID_PARTNO_CM33) {
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// STM32L5 (RM0438, pg2157)
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ret = stlink_read_debug32(sl, 0xE0044000, chip_id);
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} else /* СM3, СM4, CM7 */ {
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// default chipid address
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// STM32F1 (RM0008, pg1087; RM0041, pg681)
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// STM32F2 (RM0033, pg1326)
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// STM32F3 (RM0316, pg1095; RM0313, pg874)
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// STM32F7 (RM0385, pg1676; RM0410, pg1912)
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// STM32L1 (RM0038, pg861)
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// STM32L4 (RM0351, pg1840; RM0394, pg1560)
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// STM32G4 (RM0440, pg2086)
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// STM32WB (RM0434, pg1406)
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ret = stlink_read_debug32(sl, 0xE0042000, chip_id);
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// Fix chip_id for F4 rev A errata, read CPU ID, as CoreID is the same for F2/F4
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if (*chip_id == 0x411 && (cpu_id & 0xfff0) == 0xc240) {
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*chip_id = 0x413;
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}
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}
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return(ret);
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@ -3,9 +3,12 @@
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#define STLINK_REG_CM3_CPUID 0xE000ED00
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#define STLINK_REG_CMx_CPUID_CM0 0x410CC200
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#define STLINK_REG_CMx_CPUID_CM3 0x412FC230
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#define STLINK_REG_CMx_CPUID_CM7 0x411FC272
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#define STLINK_REG_CM3_CPUID_PARTNO(cpuid) ((cpuid)&STLINK_REG_CMx_CPUID_PARTNO_MASK)
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#define STLINK_REG_CMx_CPUID_PARTNO_MASK 0xFFF0
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#define STLINK_REG_CMx_CPUID_PARTNO_CM0 0xC200
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#define STLINK_REG_CMx_CPUID_PARTNO_CM3 0xC230
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#define STLINK_REG_CMx_CPUID_PARTNO_CM7 0xC270
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#define STLINK_REG_CMx_CPUID_PARTNO_CM33 0xD210
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#define STLINK_REG_CM3_FP_CTRL 0xE0002000 // Flash Patch Control Register
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