kopia lustrzana https://github.com/stlink-org/stlink
Add support for STM32F0-Discovery
Pekka Nikander
rodzic
bfc368c57e
commit
e8b15c0e78
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@ -0,0 +1,32 @@
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/* Adopted from STM AN4065 stm32f0xx_flash.c:FLASH_ProgramWord */
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write:
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ldr r4, STM32_FLASH_BASE
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mov r5, #1 /* FLASH_CR_PG, FLASH_SR_BUSY */
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mov r6, #4 /* PGERR */
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write_half_word:
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ldr r3, [r4, #16] /* FLASH->CR */
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orr r3, r5
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str r3, [r4, #16] /* FLASH->CR |= FLASH_CR_PG */
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ldrh r3, [r0] /* r3 = *sram */
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strh r3, [r1] /* *flash = r3 */
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busy:
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ldr r3, [r4, #12] /* FLASH->SR */
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tst r3, r5 /* FLASH_SR_BUSY */
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beq busy
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tst r3, r6 /* PGERR */
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bne exit
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add r0, r0, #2 /* sram += 2 */
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add r1, r1, #2 /* flash += 2 */
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sub r2, r2, #0x01 /* count-- */
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cmp r2, #0
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bne write_half_word
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exit:
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ldr r3, [r4, #16] /* FLASH->CR */
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bic r3, r5
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str r3, [r4, #16] /* FLASH->CR &= ~FLASH_CR_PG */
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bkpt #0x00
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STM32_FLASH_BASE: .word 0x40022000
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@ -25,6 +25,7 @@
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/* stm32f FPEC flash controller interface, pm0063 manual */
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// TODO - all of this needs to be abstracted out....
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// STM32F05x is identical, based on RM0091 (DM00031936, Doc ID 018940 Rev 2, August 2012)
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#define FLASH_REGS_ADDR 0x40022000
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#define FLASH_REGS_SIZE 0x28
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@ -36,6 +37,7 @@
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#define FLASH_OBR (FLASH_REGS_ADDR + 0x1c)
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#define FLASH_WRPR (FLASH_REGS_ADDR + 0x20)
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// For STM32F05x, the RDPTR_KEY may be wrong, but as it is not used anywhere...
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#define FLASH_RDPTR_KEY 0x00a5
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#define FLASH_KEY1 0x45670123
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#define FLASH_KEY2 0xcdef89ab
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@ -1083,7 +1085,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr)
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val = stlink_read_debug32(sl, STM32L_FLASH_PECR)
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| (1 << 0) | (1 << 1) | (1 << 2);
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stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
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} else if (sl->core_id == STM32VL_CORE_ID) {
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} else if (sl->core_id == STM32VL_CORE_ID || sl->core_id == STM32F0_CORE_ID) {
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/* wait for ongoing op to finish */
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wait_flash_busy(sl);
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@ -1191,6 +1193,54 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) {
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0x00, 0x20, 0x02, 0x40, /* STM32_FLASH_BASE: .word 0x40022000 */
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};
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/* flashloaders/stm32f0.s -- thumb1 only, same sequence as for STM32VL, bank ignored */
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static const uint8_t loader_code_stm32f0[] = {
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#if 1
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/*
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* These two NOPs here are a safety precaution, added by Pekka Nikander
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* while debugging the STM32F05x support. They may not be needed, but
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* there were strange problems with simpler programs, like a program
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* that had just a breakpoint or a program that first moved zero to register r2
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* and then had a breakpoint. So, it appears safest to have these two nops.
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*
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* Feel free to remove them, if you dare, but then please do test the result
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* rigorously. Also, if you remove these, it may be a good idea first to
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* #if 0 them out, with a comment when these were taken out, and to remove
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* these only a few months later... But YMMV.
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*/
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0x00, 0x30, // nop /* add r0,#0 */
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0x00, 0x30, // nop /* add r0,#0 */
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#endif
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0x0A, 0x4C, // ldr r4, STM32_FLASH_BASE
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0x01, 0x25, // mov r5, #1 /* FLASH_CR_PG, FLASH_SR_BUSY */
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0x04, 0x26, // mov r6, #4 /* PGERR */
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// write_half_word:
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0x23, 0x69, // ldr r3, [r4, #16] /* FLASH->CR */
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0x2B, 0x43, // orr r3, r5
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0x23, 0x61, // str r3, [r4, #16] /* FLASH->CR |= FLASH_CR_PG */
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0x03, 0x88, // ldrh r3, [r0] /* r3 = *sram */
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0x0B, 0x80, // strh r3, [r1] /* *flash = r3 */
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// busy:
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0xE3, 0x68, // ldr r3, [r4, #12] /* FLASH->SR */
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0x2B, 0x42, // tst r3, r5 /* FLASH_SR_BUSY */
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0xFC, 0xD0, // beq busy
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0x33, 0x42, // tst r3, r6 /* PGERR */
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0x04, 0xD1, // bne exit
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0x02, 0x30, // add r0, r0, #2 /* sram += 2 */
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0x02, 0x31, // add r1, r1, #2 /* flash += 2 */
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0x01, 0x3A, // sub r2, r2, #0x01 /* count-- */
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0x00, 0x2A, // cmp r2, #0
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0xF0, 0xD1, // bne write_half_word
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// exit:
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0x23, 0x69, // ldr r3, [r4, #16] /* FLASH->CR */
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0xAB, 0x43, // bic r3, r5
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0x23, 0x61, // str r3, [r4, #16] /* FLASH->CR &= ~FLASH_CR_PG */
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0x00, 0xBE, // bkpt #0x00
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0x00, 0x20, 0x02, 0x40, /* STM32_FLASH_BASE: .word 0x40022000 */
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};
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static const uint8_t loader_code_stm32l[] = {
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/* openocd.git/contrib/loaders/flash/stm32lx.S
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@ -1246,6 +1296,9 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) {
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} else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4) {
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loader_code = loader_code_stm32f4;
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loader_size = sizeof(loader_code_stm32f4);
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} else if (sl->chip_id == STM32_CHIPID_F0) {
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loader_code = loader_code_stm32f0;
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loader_size = sizeof(loader_code_stm32f0);
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} else {
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ELOG("unknown coreid, not sure what flash loader to use, aborting!: %x\n", sl->core_id);
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return -1;
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@ -1580,8 +1633,8 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned
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val = stlink_read_debug32(sl, STM32L_FLASH_PECR)
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| (1 << 0) | (1 << 1) | (1 << 2);
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stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
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} else if (sl->core_id == STM32VL_CORE_ID) {
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ILOG("Starting Flash write for VL core id\n");
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} else if (sl->core_id == STM32VL_CORE_ID || sl->core_id == STM32F0_CORE_ID) {
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ILOG("Starting Flash write for VL/F0 core id\n");
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/* flash loader initialization */
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if (init_flash_loader(sl, &fl) == -1) {
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ELOG("init_flash_loader() == -1\n");
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@ -1679,7 +1732,7 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons
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stlink_write_reg(sl, count, 2); /* count (32 bits words) */
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stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */
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} else if (sl->core_id == STM32VL_CORE_ID) {
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} else if (sl->core_id == STM32VL_CORE_ID || sl->core_id == STM32F0_CORE_ID) {
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size_t count = size / sizeof(uint16_t);
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if (size % sizeof(uint16_t)) ++count;
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@ -1734,7 +1787,7 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons
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return -1;
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}
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} else if (sl->core_id == STM32VL_CORE_ID) {
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} else if (sl->core_id == STM32VL_CORE_ID || sl->core_id == STM32F0_CORE_ID) {
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stlink_read_reg(sl, 2, &rr);
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if (rr.r[2] != 0) {
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@ -85,6 +85,7 @@ extern "C" {
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#define STM32VL_CORE_ID 0x1ba01477
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#define STM32L_CORE_ID 0x2ba01477
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#define STM32F4_CORE_ID 0x2ba01477
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#define STM32F0_CORE_ID 0xbb11477
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#define CORE_M3_R1 0x1BA00477
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#define CORE_M3_R2 0x4BA00477
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#define CORE_M4_R0 0x2BA01477
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@ -104,6 +105,7 @@ extern "C" {
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#define STM32_CHIPID_F1_VL_MEDIUM 0x420
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#define STM32_CHIPID_F1_VL_HIGH 0x428
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#define STM32_CHIPID_F1_XL 0x430
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#define STM32_CHIPID_F0 0x440
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// Constant STM32 memory map figures
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#define STM32_FLASH_BASE 0x08000000
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