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[ patch from Uwe Bonnes ] add STM32F42x and F43x-parts (bank handling not yet supported)

pull/183/head
texane 2013-10-14 18:08:42 -05:00
rodzic f15ef16aea
commit e40741e827
2 zmienionych plików z 30 dodań i 20 usunięć
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40
src/stlink-common.c
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@ -144,7 +144,7 @@ static inline uint32_t read_flash_obr(stlink_t *sl) {
static inline uint32_t read_flash_cr(stlink_t *sl) {
uint32_t res;
if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) ||
(sl->chip_id == STM32_CHIPID_F4_LP))
(sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD))
res = stlink_read_debug32(sl, FLASH_F4_CR);
else
res = stlink_read_debug32(sl, FLASH_CR);
@ -157,7 +157,7 @@ static inline uint32_t read_flash_cr(stlink_t *sl) {
static inline unsigned int is_flash_locked(stlink_t *sl) {
/* return non zero for true */
if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) ||
(sl->chip_id == STM32_CHIPID_F4_LP))
(sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD))
return read_flash_cr(sl) & (1 << FLASH_F4_CR_LOCK);
else
return read_flash_cr(sl) & (1 << FLASH_CR_LOCK);
@ -170,7 +170,7 @@ static void unlock_flash(stlink_t *sl) {
the FPEC block until next reset.
*/
if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) ||
(sl->chip_id == STM32_CHIPID_F4_LP)) {
(sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) {
stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY1);
stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY2);
} else {
@ -196,7 +196,7 @@ static int unlock_flash_if(stlink_t *sl) {
static void lock_flash(stlink_t *sl) {
if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) ||
(sl->chip_id == STM32_CHIPID_F4_LP)) {
(sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) {
const uint32_t n = read_flash_cr(sl) | (1 << FLASH_F4_CR_LOCK);
stlink_write_debug32(sl, FLASH_F4_CR, n);
} else {
@ -209,7 +209,7 @@ static void lock_flash(stlink_t *sl) {
static void set_flash_cr_pg(stlink_t *sl) {
if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) ||
(sl->chip_id == STM32_CHIPID_F4_LP)) {
(sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) {
uint32_t x = read_flash_cr(sl);
x |= (1 << FLASH_CR_PG);
stlink_write_debug32(sl, FLASH_F4_CR, x);
@ -222,7 +222,7 @@ static void set_flash_cr_pg(stlink_t *sl) {
static void __attribute__((unused)) clear_flash_cr_pg(stlink_t *sl) {
const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_PG);
if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) ||
(sl->chip_id == STM32_CHIPID_F4_LP))
(sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD))
stlink_write_debug32(sl, FLASH_F4_CR, n);
else
stlink_write_debug32(sl, FLASH_CR, n);
@ -240,7 +240,7 @@ static void __attribute__((unused)) clear_flash_cr_per(stlink_t *sl) {
static void set_flash_cr_mer(stlink_t *sl) {
if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) ||
(sl->chip_id == STM32_CHIPID_F4_LP))
(sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD))
stlink_write_debug32(sl, FLASH_F4_CR,
stlink_read_debug32(sl, FLASH_F4_CR) | (1 << FLASH_CR_MER));
else
@ -250,7 +250,7 @@ static void set_flash_cr_mer(stlink_t *sl) {
static void __attribute__((unused)) clear_flash_cr_mer(stlink_t *sl) {
if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) ||
(sl->chip_id == STM32_CHIPID_F4_LP))
(sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD))
stlink_write_debug32(sl, FLASH_F4_CR,
stlink_read_debug32(sl, FLASH_F4_CR) & ~(1 << FLASH_CR_MER));
else
@ -260,7 +260,7 @@ static void __attribute__((unused)) clear_flash_cr_mer(stlink_t *sl) {
static void set_flash_cr_strt(stlink_t *sl) {
if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) ||
(sl->chip_id == STM32_CHIPID_F4_LP)) {
(sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) {
uint32_t x = read_flash_cr(sl);
x |= (1 << FLASH_F4_CR_STRT);
stlink_write_debug32(sl, FLASH_F4_CR, x);
@ -277,7 +277,7 @@ static inline uint32_t read_flash_acr(stlink_t *sl) {
static inline uint32_t read_flash_sr(stlink_t *sl) {
uint32_t res;
if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) ||
(sl->chip_id == STM32_CHIPID_F4_LP))
(sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD))
res = stlink_read_debug32(sl, FLASH_F4_SR);
else
res = stlink_read_debug32(sl, FLASH_SR);
@ -287,7 +287,7 @@ static inline uint32_t read_flash_sr(stlink_t *sl) {
static inline unsigned int is_flash_busy(stlink_t *sl) {
if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) ||
(sl->chip_id == STM32_CHIPID_F4_LP))
(sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD))
return read_flash_sr(sl) & (1 << FLASH_F4_SR_BSY);
else
return read_flash_sr(sl) & (1 << FLASH_SR_BSY);
@ -1014,7 +1014,7 @@ uint32_t calculate_F4_sectornum(uint32_t flashaddr){
uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){
if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) ||
(sl->chip_id == STM32_CHIPID_F4_LP)) {
(sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) {
uint32_t sector=calculate_F4_sectornum(flashaddr);
if (sector<4) sl->flash_pgsz=0x4000;
else if(sector<5) sl->flash_pgsz=0x10000;
@ -1032,7 +1032,7 @@ uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){
int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr)
{
if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) ||
(sl->chip_id == STM32_CHIPID_F4_LP)) {
(sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) {
/* wait for ongoing op to finish */
wait_flash_busy(sl);
@ -1346,8 +1346,8 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) {
} else if (sl->core_id == STM32VL_CORE_ID || sl->chip_id == STM32_CHIPID_F3 || sl->chip_id == STM32_CHIPID_F37x) {
loader_code = loader_code_stm32vl;
loader_size = sizeof(loader_code_stm32vl);
} else if (sl->chip_id == STM32_CHIPID_F2 ||
sl->chip_id == STM32_CHIPID_F4 || sl->chip_id == STM32_CHIPID_F4_LP) {
} else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4 ||
sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD){
loader_code = loader_code_stm32f4;
loader_size = sizeof(loader_code_stm32f4);
} else if (sl->chip_id == STM32_CHIPID_F0 || sl->chip_id == STM32_CHIPID_F0_SMALL) {
@ -1516,7 +1516,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t
page_count, sl->flash_pgsz, sl->flash_pgsz);
if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) ||
(sl->chip_id == STM32_CHIPID_F4_LP)) {
(sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) {
/* todo: check write operation */
ILOG("Starting Flash write for F2/F4\n");
@ -1802,8 +1802,8 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons
stlink_write_reg(sl, 0, 3); /* flash bank 0 (input) */
stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */
} else if (sl->chip_id == STM32_CHIPID_F2 ||
sl->chip_id == STM32_CHIPID_F4 || sl->chip_id == STM32_CHIPID_F4_LP) {
} else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4 ||
sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD) {
size_t count = size / sizeof(uint32_t);
if (size % sizeof(uint32_t)) ++count;
@ -1856,8 +1856,8 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons
return -1;
}
} else if (sl->chip_id == STM32_CHIPID_F2 ||
sl->chip_id == STM32_CHIPID_F4 || sl->chip_id == STM32_CHIPID_F4_LP) {
} else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4 ||
sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD) {
stlink_read_reg(sl, 2, &rr);
if (rr.r[2] != 0) {

10
src/stlink-common.h
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@ -103,6 +103,7 @@ extern "C" {
#define STM32_CHIPID_F3 0x422
#define STM32_CHIPID_F37x 0x432
#define STM32_CHIPID_F4 0x413
#define STM32_CHIPID_F4_HD 0x419
#define STM32_CHIPID_F4_LP 0x423
#define STM32_CHIPID_F1_HIGH 0x414
#define STM32_CHIPID_L1_MEDIUM 0x416
@ -184,6 +185,15 @@ static const chip_params_t devices[] = {
.bootrom_base = 0x1fff0000,
.bootrom_size = 0x7800
},
{
.chip_id = STM32_CHIPID_F4_HD,
.description = "F42x and F43x device",
.flash_size_reg = 0x1FFF7A22, /* As in rm0090 since Rev 2*/
.flash_pagesize = 0x4000,
.sram_size = 0x30000,
.bootrom_base = 0x1fff0000,
.bootrom_size = 0x7800
},
{
.chip_id = STM32_CHIPID_F4_LP,
.description = "F4 device (low power)",