stm32l1: fix flash, dbgmcu and rcc registers

inc/stm32.h

@@ -167,6 +167,10 @@ enum stm32_chipids {
 #define STM32L0_DBGMCU_APB1_FZ_WWDG_STOP 11
 #define STM32L0_DBGMCU_APB1_FZ_IWDG_STOP 12
 
+#define STM32L1_DBGMCU_APB1_FZ 0xE0042008
+#define STM32L1_DBGMCU_APB1_FZ_WWDG_STOP 11
+#define STM32L1_DBGMCU_APB1_FZ_IWDG_STOP 12
+
 #define STM32H7_DBGMCU_APB1HFZ 0x5C001054
 #define STM32H7_DBGMCU_APB1HFZ_IWDG_STOP 18
 
@@ -189,6 +193,9 @@ enum stm32_chipids {
 #define STM32L0_RCC_AHBENR 0x40021030
 #define STM32L0_RCC_DMAEN 0x00000001 // DMAEN
 
+#define STM32L1_RCC_AHBENR 0x4002381C
+#define STM32L1_RCC_DMAEN 0x30000000 // DMA2EN | DMA1EN
+
 #define STM32H7_RCC_AHB1ENR 0x58024538
 #define STM32H7_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN
 

inc/stm32flash.h

@@ -219,6 +219,10 @@
 #define STM32L0_FLASH_SR_PGAERR 9
 #define STM32L0_FLASH_SR_NOTZEROERR 16
 
+#define STM32L1_FLASH_SR_ERROR_MASK 0x00003F00
+#define STM32L1_FLASH_SR_WRPERR 8
+#define STM32L1_FLASH_SR_PGAERR 9
+
 #define FLASH_ACR_OFF ((uint32_t)0x00)
 #define FLASH_PECR_OFF ((uint32_t)0x04)
 #define FLASH_PDKEYR_OFF ((uint32_t)0x08)

src/common.c

@@ -991,9 +991,15 @@ static void stop_wdg_in_debug(stlink_t *sl) {
     break;
   case STM32_FLASH_TYPE_L0_L1:
   case STM32_FLASH_TYPE_G0:
+    if (get_stm32l0_flash_base(sl) == STM32L_FLASH_REGS_ADDR) {
+      dbgmcu_cr = STM32L1_DBGMCU_APB1_FZ;
+      set = (1 << STM32L1_DBGMCU_APB1_FZ_IWDG_STOP) |
+            (1 << STM32L1_DBGMCU_APB1_FZ_WWDG_STOP);
+    } else {
       dbgmcu_cr = STM32L0_DBGMCU_APB1_FZ;
       set = (1 << STM32L0_DBGMCU_APB1_FZ_IWDG_STOP) |
             (1 << STM32L0_DBGMCU_APB1_FZ_WWDG_STOP);
+    }
     break;
   case STM32_FLASH_TYPE_H7:
     dbgmcu_cr = STM32H7_DBGMCU_APB1HFZ;

src/common_flash.c

@@ -155,7 +155,11 @@ void clear_flash_error(stlink_t *sl) {
     write_flash_sr(sl, BANK_1, STM32Gx_FLASH_SR_ERROR_MASK);
     break;
   case STM32_FLASH_TYPE_L0_L1:
+    if (get_stm32l0_flash_base(sl) == STM32L_FLASH_REGS_ADDR) {
+      write_flash_sr(sl, BANK_1, STM32L1_FLASH_SR_ERROR_MASK);
+    } else {
       write_flash_sr(sl, BANK_1, STM32L0_FLASH_SR_ERROR_MASK);
+    }
     break;
   case STM32_FLASH_TYPE_L4_L4P:
     write_flash_sr(sl, BANK_1, STM32L4_FLASH_SR_ERROR_MASK);
@@ -281,9 +285,14 @@ int check_flash_error(stlink_t *sl) {
     PGAERR = (1 << STM32Gx_FLASH_SR_PGAERR);
     break;
   case STM32_FLASH_TYPE_L0_L1:
-    res = read_flash_sr(sl, BANK_1) & STM32L0_FLASH_SR_ERROR_MASK;
-    WRPERR = (1 << STM32L0_FLASH_SR_WRPERR);
+    res = read_flash_sr(sl, BANK_1);
+    if (get_stm32l0_flash_base(sl) == STM32L_FLASH_REGS_ADDR) {
+      res &= STM32L1_FLASH_SR_ERROR_MASK;
+    } else {
+      res &= STM32L0_FLASH_SR_ERROR_MASK;
       PROGERR = (1 << STM32L0_FLASH_SR_NOTZEROERR);
+    }
+    WRPERR = (1 << STM32L0_FLASH_SR_WRPERR);
     PGAERR = (1 << STM32L0_FLASH_SR_PGAERR);
     break;
   case STM32_FLASH_TYPE_L4_L4P:

src/flashloader.c

@@ -127,8 +127,13 @@ static void set_dma_state(stlink_t *sl, flash_loader_t *fl, int bckpRstr) {
     rcc_dma_mask = STM32G4_RCC_DMAEN;
     break;
   case STM32_FLASH_TYPE_L0_L1:
+    if (get_stm32l0_flash_base(sl) == STM32L_FLASH_REGS_ADDR) {
+      rcc = STM32L1_RCC_AHBENR;
+      rcc_dma_mask = STM32L1_RCC_DMAEN;
+    } else {
       rcc = STM32L0_RCC_AHBENR;
       rcc_dma_mask = STM32L0_RCC_DMAEN;
+    }
     break;
   case STM32_FLASH_TYPE_H7:
     rcc = STM32H7_RCC_AHB1ENR;