kopia lustrzana https://github.com/stlink-org/stlink
Added USB OTG Driver sources
jnosky
rodzic
4856df1aad
commit
c2fa32ce2b
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{mso-style-unhide:no;
|
||||
color:blue;
|
||||
text-decoration:underline;
|
||||
text-underline:single;}
|
||||
p
|
||||
{mso-style-unhide:no;
|
||||
mso-margin-top-alt:auto;
|
||||
margin-right:0in;
|
||||
mso-margin-bottom-alt:auto;
|
||||
margin-left:0in;
|
||||
mso-pagination:widow-orphan;
|
||||
font-size:12.0pt;
|
||||
font-family:"Times New Roman","serif";
|
||||
mso-fareast-font-family:"Times New Roman";}
|
||||
p.MsoAcetate, li.MsoAcetate, div.MsoAcetate
|
||||
{mso-style-unhide:no;
|
||||
mso-style-link:"Balloon Text Char";
|
||||
margin:0in;
|
||||
margin-bottom:.0001pt;
|
||||
mso-pagination:widow-orphan;
|
||||
font-size:8.0pt;
|
||||
font-family:"Tahoma","sans-serif";
|
||||
mso-fareast-font-family:"Times New Roman";}
|
||||
span.Heading1Char
|
||||
{mso-style-name:"Heading 1 Char";
|
||||
mso-style-unhide:no;
|
||||
mso-style-locked:yes;
|
||||
mso-style-link:"Heading 1";
|
||||
mso-ansi-font-size:14.0pt;
|
||||
mso-bidi-font-size:14.0pt;
|
||||
font-family:"Cambria","serif";
|
||||
mso-ascii-font-family:Cambria;
|
||||
mso-ascii-theme-font:major-latin;
|
||||
mso-fareast-font-family:"Times New Roman";
|
||||
mso-fareast-theme-font:major-fareast;
|
||||
mso-hansi-font-family:Cambria;
|
||||
mso-hansi-theme-font:major-latin;
|
||||
mso-bidi-font-family:"Times New Roman";
|
||||
mso-bidi-theme-font:major-bidi;
|
||||
color:#365F91;
|
||||
mso-themecolor:accent1;
|
||||
mso-themeshade:191;
|
||||
font-weight:bold;}
|
||||
span.Heading2Char
|
||||
{mso-style-name:"Heading 2 Char";
|
||||
mso-style-unhide:no;
|
||||
mso-style-locked:yes;
|
||||
mso-style-link:"Heading 2";
|
||||
mso-ansi-font-size:13.0pt;
|
||||
mso-bidi-font-size:13.0pt;
|
||||
font-family:"Cambria","serif";
|
||||
mso-ascii-font-family:Cambria;
|
||||
mso-ascii-theme-font:major-latin;
|
||||
mso-fareast-font-family:"Times New Roman";
|
||||
mso-fareast-theme-font:major-fareast;
|
||||
mso-hansi-font-family:Cambria;
|
||||
mso-hansi-theme-font:major-latin;
|
||||
mso-bidi-font-family:"Times New Roman";
|
||||
mso-bidi-theme-font:major-bidi;
|
||||
color:#4F81BD;
|
||||
mso-themecolor:accent1;
|
||||
font-weight:bold;}
|
||||
span.Heading3Char
|
||||
{mso-style-name:"Heading 3 Char";
|
||||
mso-style-unhide:no;
|
||||
mso-style-locked:yes;
|
||||
mso-style-link:"Heading 3";
|
||||
mso-ansi-font-size:12.0pt;
|
||||
mso-bidi-font-size:12.0pt;
|
||||
font-family:"Cambria","serif";
|
||||
mso-ascii-font-family:Cambria;
|
||||
mso-ascii-theme-font:major-latin;
|
||||
mso-fareast-font-family:"Times New Roman";
|
||||
mso-fareast-theme-font:major-fareast;
|
||||
mso-hansi-font-family:Cambria;
|
||||
mso-hansi-theme-font:major-latin;
|
||||
mso-bidi-font-family:"Times New Roman";
|
||||
mso-bidi-theme-font:major-bidi;
|
||||
color:#4F81BD;
|
||||
mso-themecolor:accent1;
|
||||
font-weight:bold;}
|
||||
span.BalloonTextChar
|
||||
{mso-style-name:"Balloon Text Char";
|
||||
mso-style-unhide:no;
|
||||
mso-style-locked:yes;
|
||||
mso-style-link:"Balloon Text";
|
||||
mso-ansi-font-size:8.0pt;
|
||||
mso-bidi-font-size:8.0pt;
|
||||
font-family:"Tahoma","sans-serif";
|
||||
mso-ascii-font-family:Tahoma;
|
||||
mso-hansi-font-family:Tahoma;
|
||||
mso-bidi-font-family:Tahoma;}
|
||||
.MsoChpDefault
|
||||
{mso-style-type:export-only;
|
||||
mso-default-props:yes;
|
||||
font-size:10.0pt;
|
||||
mso-ansi-font-size:10.0pt;
|
||||
mso-bidi-font-size:10.0pt;}
|
||||
@page WordSection1
|
||||
{size:8.5in 11.0in;
|
||||
margin:1.0in 1.25in 1.0in 1.25in;
|
||||
mso-header-margin:.5in;
|
||||
mso-footer-margin:.5in;
|
||||
mso-paper-source:0;}
|
||||
div.WordSection1
|
||||
{page:WordSection1;}
|
||||
/* List Definitions */
|
||||
@list l0
|
||||
{mso-list-id:62067358;
|
||||
mso-list-template-ids:-174943062;}
|
||||
@list l0:level1
|
||||
{mso-level-number-format:bullet;
|
||||
mso-level-text:\F0B7;
|
||||
mso-level-tab-stop:.5in;
|
||||
mso-level-number-position:left;
|
||||
text-indent:-.25in;
|
||||
mso-ansi-font-size:10.0pt;
|
||||
font-family:Symbol;}
|
||||
@list l0:level2
|
||||
{mso-level-tab-stop:1.0in;
|
||||
mso-level-number-position:left;
|
||||
text-indent:-.25in;}
|
||||
@list l0:level3
|
||||
{mso-level-tab-stop:1.5in;
|
||||
mso-level-number-position:left;
|
||||
text-indent:-.25in;}
|
||||
@list l0:level4
|
||||
{mso-level-tab-stop:2.0in;
|
||||
mso-level-number-position:left;
|
||||
text-indent:-.25in;}
|
||||
@list l0:level5
|
||||
{mso-level-tab-stop:2.5in;
|
||||
mso-level-number-position:left;
|
||||
text-indent:-.25in;}
|
||||
@list l0:level6
|
||||
{mso-level-tab-stop:3.0in;
|
||||
mso-level-number-position:left;
|
||||
text-indent:-.25in;}
|
||||
@list l0:level7
|
||||
{mso-level-tab-stop:3.5in;
|
||||
mso-level-number-position:left;
|
||||
text-indent:-.25in;}
|
||||
@list l0:level8
|
||||
{mso-level-tab-stop:4.0in;
|
||||
mso-level-number-position:left;
|
||||
text-indent:-.25in;}
|
||||
@list l0:level9
|
||||
{mso-level-tab-stop:4.5in;
|
||||
mso-level-number-position:left;
|
||||
text-indent:-.25in;}
|
||||
@list l1
|
||||
{mso-list-id:128015942;
|
||||
mso-list-template-ids:-90681214;}
|
||||
@list l1:level1
|
||||
{mso-level-tab-stop:.5in;
|
||||
mso-level-number-position:left;
|
||||
text-indent:-.25in;}
|
||||
@list l1:level2
|
||||
{mso-level-tab-stop:1.0in;
|
||||
mso-level-number-position:left;
|
||||
text-indent:-.25in;}
|
||||
@list l1:level3
|
||||
{mso-level-tab-stop:1.5in;
|
||||
mso-level-number-position:left;
|
||||
text-indent:-.25in;}
|
||||
@list l1:level4
|
||||
{mso-level-tab-stop:2.0in;
|
||||
mso-level-number-position:left;
|
||||
text-indent:-.25in;}
|
||||
@list l1:level5
|
||||
{mso-level-tab-stop:2.5in;
|
||||
mso-level-number-position:left;
|
||||
text-indent:-.25in;}
|
||||
@list l1:level6
|
||||
{mso-level-tab-stop:3.0in;
|
||||
mso-level-number-position:left;
|
||||
text-indent:-.25in;}
|
||||
@list l1:level7
|
||||
{mso-level-tab-stop:3.5in;
|
||||
mso-level-number-position:left;
|
||||
text-indent:-.25in;}
|
||||
@list l1:level8
|
||||
{mso-level-tab-stop:4.0in;
|
||||
mso-level-number-position:left;
|
||||
text-indent:-.25in;}
|
||||
@list l1:level9
|
||||
{mso-level-tab-stop:4.5in;
|
||||
mso-level-number-position:left;
|
||||
text-indent:-.25in;}
|
||||
@list l2
|
||||
{mso-list-id:216556000;
|
||||
mso-list-template-ids:925924412;}
|
||||
@list l2:level1
|
||||
{mso-level-number-format:bullet;
|
||||
mso-level-text:\F0B7;
|
||||
mso-level-tab-stop:.5in;
|
||||
mso-level-number-position:left;
|
||||
text-indent:-.25in;
|
||||
mso-ansi-font-size:10.0pt;
|
||||
font-family:Symbol;}
|
||||
@list l2:level2
|
||||
{mso-level-number-format:bullet;
|
||||
mso-level-text:\F0B7;
|
||||
mso-level-tab-stop:1.0in;
|
||||
mso-level-number-position:left;
|
||||
text-indent:-.25in;
|
||||
mso-ansi-font-size:10.0pt;
|
||||
font-family:Symbol;}
|
||||
@list l2:level3
|
||||
{mso-level-tab-stop:1.5in;
|
||||
mso-level-number-position:left;
|
||||
text-indent:-.25in;}
|
||||
@list l2:level4
|
||||
{mso-level-tab-stop:2.0in;
|
||||
mso-level-number-position:left;
|
||||
text-indent:-.25in;}
|
||||
@list l2:level5
|
||||
{mso-level-tab-stop:2.5in;
|
||||
mso-level-number-position:left;
|
||||
text-indent:-.25in;}
|
||||
@list l2:level6
|
||||
{mso-level-tab-stop:3.0in;
|
||||
mso-level-number-position:left;
|
||||
text-indent:-.25in;}
|
||||
@list l2:level7
|
||||
{mso-level-tab-stop:3.5in;
|
||||
mso-level-number-position:left;
|
||||
text-indent:-.25in;}
|
||||
@list l2:level8
|
||||
{mso-level-tab-stop:4.0in;
|
||||
mso-level-number-position:left;
|
||||
text-indent:-.25in;}
|
||||
@list l2:level9
|
||||
{mso-level-tab-stop:4.5in;
|
||||
mso-level-number-position:left;
|
||||
text-indent:-.25in;}
|
||||
@list l3
|
||||
{mso-list-id:562446694;
|
||||
mso-list-template-ids:913898366;}
|
||||
@list l3:level1
|
||||
{mso-level-number-format:bullet;
|
||||
mso-level-text:\F0B7;
|
||||
mso-level-tab-stop:.5in;
|
||||
mso-level-number-position:left;
|
||||
text-indent:-.25in;
|
||||
mso-ansi-font-size:10.0pt;
|
||||
font-family:Symbol;}
|
||||
@list l3:level2
|
||||
{mso-level-tab-stop:1.0in;
|
||||
mso-level-number-position:left;
|
||||
text-indent:-.25in;}
|
||||
@list l3:level3
|
||||
{mso-level-tab-stop:1.5in;
|
||||
mso-level-number-position:left;
|
||||
text-indent:-.25in;}
|
||||
@list l3:level4
|
||||
{mso-level-tab-stop:2.0in;
|
||||
mso-level-number-position:left;
|
||||
text-indent:-.25in;}
|
||||
@list l3:level5
|
||||
{mso-level-tab-stop:2.5in;
|
||||
mso-level-number-position:left;
|
||||
text-indent:-.25in;}
|
||||
@list l3:level6
|
||||
{mso-level-tab-stop:3.0in;
|
||||
mso-level-number-position:left;
|
||||
text-indent:-.25in;}
|
||||
@list l3:level7
|
||||
{mso-level-tab-stop:3.5in;
|
||||
mso-level-number-position:left;
|
||||
text-indent:-.25in;}
|
||||
@list l3:level8
|
||||
{mso-level-tab-stop:4.0in;
|
||||
mso-level-number-position:left;
|
||||
text-indent:-.25in;}
|
||||
@list l3:level9
|
||||
{mso-level-tab-stop:4.5in;
|
||||
mso-level-number-position:left;
|
||||
text-indent:-.25in;}
|
||||
@list l4
|
||||
{mso-list-id:797802132;
|
||||
mso-list-template-ids:-1971191336;}
|
||||
@list l4:level1
|
||||
{mso-level-tab-stop:.5in;
|
||||
mso-level-number-position:left;
|
||||
text-indent:-.25in;}
|
||||
@list l4:level2
|
||||
{mso-level-tab-stop:1.0in;
|
||||
mso-level-number-position:left;
|
||||
text-indent:-.25in;}
|
||||
@list l4:level3
|
||||
{mso-level-tab-stop:1.5in;
|
||||
mso-level-number-position:left;
|
||||
text-indent:-.25in;}
|
||||
@list l4:level4
|
||||
{mso-level-tab-stop:2.0in;
|
||||
mso-level-number-position:left;
|
||||
text-indent:-.25in;}
|
||||
@list l4:level5
|
||||
{mso-level-tab-stop:2.5in;
|
||||
mso-level-number-position:left;
|
||||
text-indent:-.25in;}
|
||||
@list l4:level6
|
||||
{mso-level-tab-stop:3.0in;
|
||||
mso-level-number-position:left;
|
||||
text-indent:-.25in;}
|
||||
@list l4:level7
|
||||
{mso-level-tab-stop:3.5in;
|
||||
mso-level-number-position:left;
|
||||
text-indent:-.25in;}
|
||||
@list l4:level8
|
||||
{mso-level-tab-stop:4.0in;
|
||||
mso-level-number-position:left;
|
||||
text-indent:-.25in;}
|
||||
@list l4:level9
|
||||
{mso-level-tab-stop:4.5in;
|
||||
mso-level-number-position:left;
|
||||
text-indent:-.25in;}
|
||||
@list l5
|
||||
{mso-list-id:907304066;
|
||||
mso-list-template-ids:1969781532;}
|
||||
@list l5:level1
|
||||
{mso-level-tab-stop:.5in;
|
||||
mso-level-number-position:left;
|
||||
text-indent:-.25in;}
|
||||
@list l5:level2
|
||||
{mso-level-tab-stop:1.0in;
|
||||
mso-level-number-position:left;
|
||||
text-indent:-.25in;}
|
||||
@list l5:level3
|
||||
{mso-level-tab-stop:1.5in;
|
||||
mso-level-number-position:left;
|
||||
text-indent:-.25in;}
|
||||
@list l5:level4
|
||||
{mso-level-tab-stop:2.0in;
|
||||
mso-level-number-position:left;
|
||||
text-indent:-.25in;}
|
||||
@list l5:level5
|
||||
{mso-level-tab-stop:2.5in;
|
||||
mso-level-number-position:left;
|
||||
text-indent:-.25in;}
|
||||
@list l5:level6
|
||||
{mso-level-tab-stop:3.0in;
|
||||
mso-level-number-position:left;
|
||||
text-indent:-.25in;}
|
||||
@list l5:level7
|
||||
{mso-level-tab-stop:3.5in;
|
||||
mso-level-number-position:left;
|
||||
text-indent:-.25in;}
|
||||
@list l5:level8
|
||||
{mso-level-tab-stop:4.0in;
|
||||
mso-level-number-position:left;
|
||||
text-indent:-.25in;}
|
||||
@list l5:level9
|
||||
{mso-level-tab-stop:4.5in;
|
||||
mso-level-number-position:left;
|
||||
text-indent:-.25in;}
|
||||
@list l6
|
||||
{mso-list-id:1050613616;
|
||||
mso-list-template-ids:-1009886748;}
|
||||
@list l6:level1
|
||||
{mso-level-number-format:bullet;
|
||||
mso-level-text:\F0B7;
|
||||
mso-level-tab-stop:.5in;
|
||||
mso-level-number-position:left;
|
||||
text-indent:-.25in;
|
||||
mso-ansi-font-size:10.0pt;
|
||||
font-family:Symbol;}
|
||||
@list l6:level2
|
||||
{mso-level-number-format:bullet;
|
||||
mso-level-text:\F0B7;
|
||||
mso-level-tab-stop:1.0in;
|
||||
mso-level-number-position:left;
|
||||
text-indent:-.25in;
|
||||
mso-ansi-font-size:10.0pt;
|
||||
font-family:Symbol;}
|
||||
@list l6:level3
|
||||
{mso-level-tab-stop:1.5in;
|
||||
mso-level-number-position:left;
|
||||
text-indent:-.25in;}
|
||||
@list l6:level4
|
||||
{mso-level-tab-stop:2.0in;
|
||||
mso-level-number-position:left;
|
||||
text-indent:-.25in;}
|
||||
@list l6:level5
|
||||
{mso-level-tab-stop:2.5in;
|
||||
mso-level-number-position:left;
|
||||
text-indent:-.25in;}
|
||||
@list l6:level6
|
||||
{mso-level-tab-stop:3.0in;
|
||||
mso-level-number-position:left;
|
||||
text-indent:-.25in;}
|
||||
@list l6:level7
|
||||
{mso-level-tab-stop:3.5in;
|
||||
mso-level-number-position:left;
|
||||
text-indent:-.25in;}
|
||||
@list l6:level8
|
||||
{mso-level-tab-stop:4.0in;
|
||||
mso-level-number-position:left;
|
||||
text-indent:-.25in;}
|
||||
@list l6:level9
|
||||
{mso-level-tab-stop:4.5in;
|
||||
mso-level-number-position:left;
|
||||
text-indent:-.25in;}
|
||||
@list l7
|
||||
{mso-list-id:1234970193;
|
||||
mso-list-template-ids:2055904002;}
|
||||
@list l7:level1
|
||||
{mso-level-number-format:bullet;
|
||||
mso-level-text:\F0B7;
|
||||
mso-level-tab-stop:.5in;
|
||||
mso-level-number-position:left;
|
||||
text-indent:-.25in;
|
||||
mso-ansi-font-size:10.0pt;
|
||||
font-family:Symbol;}
|
||||
@list l7:level2
|
||||
{mso-level-number-format:bullet;
|
||||
mso-level-text:\F0B7;
|
||||
mso-level-tab-stop:1.0in;
|
||||
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|
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
ol
|
||||
{margin-bottom:0in;}
|
||||
ul
|
||||
{margin-bottom:0in;}
|
||||
-->
|
||||
</style><!--[if gte mso 10]>
|
||||
<style>
|
||||
/* Style Definitions */
|
||||
table.MsoNormalTable
|
||||
{mso-style-name:"Table Normal";
|
||||
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|
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|
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|
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|
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|
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|
||||
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|
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|
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mso-pagination:widow-orphan;
|
||||
font-size:10.0pt;
|
||||
font-family:"Times New Roman","serif";}
|
||||
</style>
|
||||
<![endif]--><!--[if gte mso 9]><xml>
|
||||
<o:shapedefaults v:ext="edit" spidmax="7170"/>
|
||||
</xml><![endif]--><!--[if gte mso 9]><xml>
|
||||
<o:shapelayout v:ext="edit">
|
||||
<o:idmap v:ext="edit" data="1"/>
|
||||
</o:shapelayout></xml><![endif]--></head>
|
||||
<body style="" lang="EN-US" link="blue" vlink="blue">
|
||||
|
||||
<div class="WordSection1">
|
||||
|
||||
<p class="MsoNormal"><span style="font-family: "Arial","sans-serif";"><o:p> </o:p></span></p>
|
||||
|
||||
<div align="center">
|
||||
|
||||
<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" cellspacing="0" width="900">
|
||||
<tbody><tr style="">
|
||||
<td style="padding: 0in;" valign="top">
|
||||
<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" cellspacing="0" width="900">
|
||||
<tbody><tr style="">
|
||||
<td style="padding: 0in 5.4pt;" valign="top">
|
||||
<p class="MsoNormal"><span style="font-size: 8pt; font-family: "Arial","sans-serif"; color: blue;"><a href="../../Release_Notes.html">Back to Release page</a></span><span style="font-size: 10pt;"><o:p></o:p></span></p>
|
||||
</td>
|
||||
</tr>
|
||||
<tr style="">
|
||||
<td style="padding: 1.5pt;">
|
||||
<h1 style="margin-bottom: 0.25in; text-align: center;" align="center"><span style="font-size: 20pt; font-family: "Verdana","sans-serif"; color: rgb(51, 102, 255);">Release Notes for STM32F105/7xx and STM32F2xx USB OTG Driver</span><span style="font-size: 20pt; font-family: "Verdana","sans-serif";"><o:p></o:p></span></h1>
|
||||
<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: "Arial","sans-serif"; color: black;">Copyright
|
||||
2011 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>
|
||||
<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: "Arial","sans-serif"; color: black;"><img id="_x0000_i1026" src="../../_htmresc/logo.bmp" border="0" height="65" width="86"></span><span style="font-size: 10pt;"><o:p></o:p></span></p>
|
||||
</td>
|
||||
</tr>
|
||||
</tbody></table>
|
||||
<p class="MsoNormal"><span style="font-family: "Arial","sans-serif"; display: none;"><o:p> </o:p></span></p>
|
||||
<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" width="900">
|
||||
<tbody><tr style="">
|
||||
<td style="padding: 0in;" valign="top">
|
||||
<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><span style="font-size: 12pt; color: white;">Contents<o:p></o:p></span></h2>
|
||||
<ol style="margin-top: 0in;" start="1" type="1">
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><a href="#History">STM32F105/7xx and STM32F2xx USB OTG Driver update History</a><o:p></o:p></span></li>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><a href="#License">License</a><o:p></o:p></span></li>
|
||||
</ol>
|
||||
<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">STM32F105/7xx and STM32F2xx USB OTG Driver update History</span></h2><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 171px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V2.0.0 / 22-July-2011 <o:p></o:p></span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
|
||||
Changes<o:p></o:p></span></u></b></p>
|
||||
<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Second official version supporting <span style="font-weight: bold; font-style: italic;">STM32F105/7</span> and <span style="font-weight: bold; font-style: italic;">STM32F2xx</span> devices</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Rename the Library from "<span style="font-style: italic;">STM32_USB_HOST_Driver</span>" to "<span style="font-style: italic;">STM32_USB_OTG_Driver</span>"</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add support for <span style="font-weight: bold; font-style: italic;">STM32F2xx</span> devices</span><span style="font-size: 10pt; font-family: Verdana;"></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add support for Device and OTG modes</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Change HCD layer to support High speed core</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Change the Low level driver to support multi core support for Host mode</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add Stop mechanism for Host and Device modes</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Change VBUS enabling method, to use the external or the internal VBUS when using the ULPI</span></li></ul><span style="font-size: 10pt; font-family: Verdana;"><br></span><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 171px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0 - 11/29/2010<o:p></o:p></span></h3>
|
||||
<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Created </span></li></ul><h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span></h2>
|
||||
<p class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana; color: black;">The use of this STM32 software is governed by the terms and conditions of the License Agreement </span><span style="font-size: 10pt; font-family: Verdana; color: black;"><span style="font-weight: bold; font-style: italic;">"MCD-ST Liberty SW License Agreement 20Jul2011 v0.1.pdf"</span> </span><span style="font-size: 10pt; font-family: Verdana; color: black;">available in the root of this package.</span><span style="color: black;"><o:p> </o:p></span></p>
|
||||
<div class="MsoNormal" style="text-align: center;" align="center"><span style="color: black;">
|
||||
<hr align="center" size="2" width="100%">
|
||||
</span></div>
|
||||
<p class="MsoNormal" style="margin: 4.5pt 0in 4.5pt 0.25in; text-align: center;" align="center"><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;">For
|
||||
complete documentation on </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">STM32(<span style="color: black;">CORTEX M3) 32-Bit
|
||||
Microcontrollers visit </span><u><span style="color: blue;"><a href="http://www.st.com/stm32" target="_blank">www.st.com/STM32</a></span></u></span><span style="color: black;"><o:p></o:p></span></p>
|
||||
</td>
|
||||
</tr>
|
||||
</tbody></table>
|
||||
<p class="MsoNormal"><span style="font-size: 10pt;"><o:p></o:p></span></p>
|
||||
</td>
|
||||
</tr>
|
||||
</tbody></table>
|
||||
|
||||
</div>
|
||||
|
||||
<p class="MsoNormal"><o:p> </o:p></p>
|
||||
|
||||
</div>
|
||||
|
||||
</body></html>
|
||||
|
|
@ -0,0 +1,97 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file usb_bsp.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.0.0
|
||||
* @date 22-July-2011
|
||||
* @brief Specific api's relative to the used hardware platform
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __USB_BSP__H__
|
||||
#define __USB_BSP__H__
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "usb_core.h"
|
||||
#include "stm32f4_discovery.h"
|
||||
|
||||
/** @addtogroup USB_OTG_DRIVER
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USB_BSP
|
||||
* @brief This file is the
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_BSP_Exported_Defines
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_BSP_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_BSP_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_BSP_Exported_Variables
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_BSP_Exported_FunctionsPrototype
|
||||
* @{
|
||||
*/
|
||||
void BSP_Init(void);
|
||||
|
||||
void USB_OTG_BSP_Init (USB_OTG_CORE_HANDLE *pdev);
|
||||
void USB_OTG_BSP_uDelay (const uint32_t usec);
|
||||
void USB_OTG_BSP_mDelay (const uint32_t msec);
|
||||
void USB_OTG_BSP_EnableInterrupt (USB_OTG_CORE_HANDLE *pdev);
|
||||
#ifdef USE_HOST_MODE
|
||||
void USB_OTG_BSP_ConfigVBUS(USB_OTG_CORE_HANDLE *pdev);
|
||||
void USB_OTG_BSP_DriveVBUS(USB_OTG_CORE_HANDLE *pdev,uint8_t state);
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif //__USB_BSP__H__
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
|
||||
|
|
@ -0,0 +1,287 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file usb_conf.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.0.0
|
||||
* @date 22-July-2011
|
||||
* @brief general low level driver configuration
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __USB_CONF__H__
|
||||
#define __USB_CONF__H__
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f2xx.h"
|
||||
|
||||
|
||||
/** @addtogroup USB_OTG_DRIVER
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USB_CONF
|
||||
* @brief USB low level driver configuration file
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USB_CONF_Exported_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* USB Core and PHY interface configuration.
|
||||
Tip: To avoid modifying these defines each time you need to change the USB
|
||||
configuration, you can declare the needed define in your toolchain
|
||||
compiler preprocessor.
|
||||
*/
|
||||
#ifndef USE_USB_OTG_FS
|
||||
//#define USE_USB_OTG_FS
|
||||
#endif /* USE_USB_OTG_FS */
|
||||
|
||||
#ifndef USE_USB_OTG_HS
|
||||
//#define USE_USB_OTG_HS
|
||||
#endif /* USE_USB_OTG_HS */
|
||||
|
||||
#ifndef USE_ULPI_PHY
|
||||
//#define USE_ULPI_PHY
|
||||
#endif /* USE_ULPI_PHY */
|
||||
|
||||
#ifndef USE_EMBEDDED_PHY
|
||||
//#define USE_EMBEDDED_PHY
|
||||
#endif /* USE_EMBEDDED_PHY */
|
||||
|
||||
#ifndef USE_I2C_PHY
|
||||
//#define USE_I2C_PHY
|
||||
#endif /* USE_I2C_PHY */
|
||||
|
||||
|
||||
#ifdef USE_USB_OTG_FS
|
||||
#define USB_OTG_FS_CORE
|
||||
#endif
|
||||
|
||||
#ifdef USE_USB_OTG_HS
|
||||
#define USB_OTG_HS_CORE
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* FIFO Size Configuration in Device mode
|
||||
*
|
||||
* (i) Receive data FIFO size = RAM for setup packets +
|
||||
* OUT endpoint control information +
|
||||
* data OUT packets + miscellaneous
|
||||
* Space = ONE 32-bits words
|
||||
* --> RAM for setup packets = 10 spaces
|
||||
* (n is the nbr of CTRL EPs the device core supports)
|
||||
* --> OUT EP CTRL info = 1 space
|
||||
* (one space for status information written to the FIFO along with each
|
||||
* received packet)
|
||||
* --> data OUT packets = (Largest Packet Size / 4) + 1 spaces
|
||||
* (MINIMUM to receive packets)
|
||||
* --> OR data OUT packets = at least 2*(Largest Packet Size / 4) + 1 spaces
|
||||
* (if high-bandwidth EP is enabled or multiple isochronous EPs)
|
||||
* --> miscellaneous = 1 space per OUT EP
|
||||
* (one space for transfer complete status information also pushed to the
|
||||
* FIFO with each endpoint's last packet)
|
||||
*
|
||||
* (ii)MINIMUM RAM space required for each IN EP Tx FIFO = MAX packet size for
|
||||
* that particular IN EP. More space allocated in the IN EP Tx FIFO results
|
||||
* in a better performance on the USB and can hide latencies on the AHB.
|
||||
*
|
||||
* (iii) TXn min size = 16 words. (n : Transmit FIFO index)
|
||||
* (iv) When a TxFIFO is not used, the Configuration should be as follows:
|
||||
* case 1 : n > m and Txn is not used (n,m : Transmit FIFO indexes)
|
||||
* --> Txm can use the space allocated for Txn.
|
||||
* case2 : n < m and Txn is not used (n,m : Transmit FIFO indexes)
|
||||
* --> Txn should be configured with the minimum space of 16 words
|
||||
* (v) The FIFO is used optimally when used TxFIFOs are allocated in the top
|
||||
* of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones.
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* FIFO Size Configuration in Host mode
|
||||
*
|
||||
* (i) Receive data FIFO size = (Largest Packet Size / 4) + 1 or
|
||||
* 2x (Largest Packet Size / 4) + 1, If a
|
||||
* high-bandwidth channel or multiple isochronous
|
||||
* channels are enabled
|
||||
*
|
||||
* (ii) For the host nonperiodic Transmit FIFO is the largest maximum packet size
|
||||
* for all supported nonperiodic OUT channels. Typically, a space
|
||||
* corresponding to two Largest Packet Size is recommended.
|
||||
*
|
||||
* (iii) The minimum amount of RAM required for Host periodic Transmit FIFO is
|
||||
* the largest maximum packet size for all supported periodic OUT channels.
|
||||
* If there is at least one High Bandwidth Isochronous OUT endpoint,
|
||||
* then the space must be at least two times the maximum packet size for
|
||||
* that channel.
|
||||
*******************************************************************************/
|
||||
|
||||
/****************** USB OTG HS CONFIGURATION **********************************/
|
||||
#ifdef USB_OTG_HS_CORE
|
||||
#define RX_FIFO_HS_SIZE 512
|
||||
#define TX0_FIFO_HS_SIZE 512
|
||||
#define TX1_FIFO_HS_SIZE 512
|
||||
#define TX2_FIFO_HS_SIZE 0
|
||||
#define TX3_FIFO_HS_SIZE 0
|
||||
#define TX4_FIFO_HS_SIZE 0
|
||||
#define TX5_FIFO_HS_SIZE 0
|
||||
#define TXH_NP_HS_FIFOSIZ 96
|
||||
#define TXH_P_HS_FIFOSIZ 96
|
||||
|
||||
//#define USB_OTG_HS_LOW_PWR_MGMT_SUPPORT
|
||||
//#define USB_OTG_HS_SOF_OUTPUT_ENABLED
|
||||
|
||||
//#define USB_OTG_INTERNAL_VBUS_ENABLED
|
||||
#define USB_OTG_EXTERNAL_VBUS_ENABLED
|
||||
|
||||
#ifdef USE_ULPI_PHY
|
||||
#define USB_OTG_ULPI_PHY_ENABLED
|
||||
#endif
|
||||
#ifdef USE_EMBEDDED_PHY
|
||||
#define USB_OTG_EMBEDDED_PHY_ENABLED
|
||||
#endif
|
||||
#ifdef USE_I2C_PHY
|
||||
#define USB_OTG_I2C_PHY_ENABLED
|
||||
#endif
|
||||
#define USB_OTG_HS_INTERNAL_DMA_ENABLED
|
||||
#define USB_OTG_HS_DEDICATED_EP1_ENABLED
|
||||
#endif
|
||||
|
||||
/****************** USB OTG FS CONFIGURATION **********************************/
|
||||
#ifdef USB_OTG_FS_CORE
|
||||
#define RX_FIFO_FS_SIZE 128
|
||||
#define TX0_FIFO_FS_SIZE 64
|
||||
#define TX1_FIFO_FS_SIZE 128
|
||||
#define TX2_FIFO_FS_SIZE 0
|
||||
#define TX3_FIFO_FS_SIZE 0
|
||||
#define TXH_NP_HS_FIFOSIZ 96
|
||||
#define TXH_P_HS_FIFOSIZ 96
|
||||
|
||||
//#define USB_OTG_FS_LOW_PWR_MGMT_SUPPORT
|
||||
//#define USB_OTG_FS_SOF_OUTPUT_ENABLED
|
||||
#endif
|
||||
|
||||
/****************** USB OTG MODE CONFIGURATION ********************************/
|
||||
//#define USE_HOST_MODE
|
||||
#define USE_DEVICE_MODE
|
||||
//#define USE_OTG_MODE
|
||||
|
||||
|
||||
#ifndef USB_OTG_FS_CORE
|
||||
#ifndef USB_OTG_HS_CORE
|
||||
#error "USB_OTG_HS_CORE or USB_OTG_FS_CORE should be defined"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
#ifndef USE_DEVICE_MODE
|
||||
#ifndef USE_HOST_MODE
|
||||
#error "USE_DEVICE_MODE or USE_HOST_MODE should be defined"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef USE_USB_OTG_HS
|
||||
#ifndef USE_USB_OTG_FS
|
||||
#error "USE_USB_OTG_HS or USE_USB_OTG_FS should be defined"
|
||||
#endif
|
||||
#else //USE_USB_OTG_HS
|
||||
#ifndef USE_ULPI_PHY
|
||||
#ifndef USE_EMBEDDED_PHY
|
||||
#ifndef USE_I2C_PHY
|
||||
#error "USE_ULPI_PHY or USE_EMBEDDED_PHY or USE_I2C_PHY should be defined"
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/****************** C Compilers dependant keywords ****************************/
|
||||
/* In HS mode and when the DMA is used, all variables and data structures dealing
|
||||
with the DMA during the transaction process should be 4-bytes aligned */
|
||||
#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
|
||||
#if defined (__GNUC__) /* GNU Compiler */
|
||||
#define __ALIGN_END __attribute__ ((aligned (4)))
|
||||
#define __ALIGN_BEGIN
|
||||
#else
|
||||
#define __ALIGN_END
|
||||
#if defined (__CC_ARM) /* ARM Compiler */
|
||||
#define __ALIGN_BEGIN __align(4)
|
||||
#elif defined (__ICCARM__) /* IAR Compiler */
|
||||
#define __ALIGN_BEGIN
|
||||
#elif defined (__TASKING__) /* TASKING Compiler */
|
||||
#define __ALIGN_BEGIN __align(4)
|
||||
#endif /* __CC_ARM */
|
||||
#endif /* __GNUC__ */
|
||||
#else
|
||||
#define __ALIGN_BEGIN
|
||||
#define __ALIGN_END
|
||||
#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
|
||||
|
||||
/* __packed keyword used to decrease the data type alignment to 1-byte */
|
||||
#if defined (__CC_ARM) /* ARM Compiler */
|
||||
#define __packed __packed
|
||||
#elif defined (__ICCARM__) /* IAR Compiler */
|
||||
#define __packed __packed
|
||||
#elif defined ( __GNUC__ ) /* GNU Compiler */
|
||||
#define __packed __attribute__ ((__packed__))
|
||||
#elif defined (__TASKING__) /* TASKING Compiler */
|
||||
#define __packed __unaligned
|
||||
#endif /* __CC_ARM */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_CONF_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_CONF_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_CONF_Exported_Variables
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_CONF_Exported_FunctionsPrototype
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#endif //__USB_CONF__H__
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
|
||||
|
|
@ -0,0 +1,408 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file usb_core.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.0.0
|
||||
* @date 22-July-2011
|
||||
* @brief Header of the Core Layer
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __USB_CORE_H__
|
||||
#define __USB_CORE_H__
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "usb_conf.h"
|
||||
#include "usb_regs.h"
|
||||
#include "usb_defines.h"
|
||||
|
||||
|
||||
/** @addtogroup USB_OTG_DRIVER
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USB_CORE
|
||||
* @brief usb otg driver core layer
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_CORE_Exported_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USB_OTG_EP0_IDLE 0
|
||||
#define USB_OTG_EP0_SETUP 1
|
||||
#define USB_OTG_EP0_DATA_IN 2
|
||||
#define USB_OTG_EP0_DATA_OUT 3
|
||||
#define USB_OTG_EP0_STATUS_IN 4
|
||||
#define USB_OTG_EP0_STATUS_OUT 5
|
||||
#define USB_OTG_EP0_STALL 6
|
||||
|
||||
#define USB_OTG_EP_TX_DIS 0x0000
|
||||
#define USB_OTG_EP_TX_STALL 0x0010
|
||||
#define USB_OTG_EP_TX_NAK 0x0020
|
||||
#define USB_OTG_EP_TX_VALID 0x0030
|
||||
|
||||
#define USB_OTG_EP_RX_DIS 0x0000
|
||||
#define USB_OTG_EP_RX_STALL 0x1000
|
||||
#define USB_OTG_EP_RX_NAK 0x2000
|
||||
#define USB_OTG_EP_RX_VALID 0x3000
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#define MAX_DATA_LENGTH 0xFF
|
||||
|
||||
/** @defgroup USB_CORE_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
typedef enum {
|
||||
USB_OTG_OK = 0,
|
||||
USB_OTG_FAIL
|
||||
}USB_OTG_STS;
|
||||
|
||||
typedef enum {
|
||||
HC_IDLE = 0,
|
||||
HC_XFRC,
|
||||
HC_HALTED,
|
||||
HC_NAK,
|
||||
HC_NYET,
|
||||
HC_STALL,
|
||||
HC_XACTERR,
|
||||
HC_BBLERR,
|
||||
HC_DATATGLERR,
|
||||
}HC_STATUS;
|
||||
|
||||
typedef enum {
|
||||
URB_IDLE = 0,
|
||||
URB_DONE,
|
||||
URB_NOTREADY,
|
||||
URB_ERROR,
|
||||
URB_STALL
|
||||
}URB_STATE;
|
||||
|
||||
typedef enum {
|
||||
CTRL_START = 0,
|
||||
CTRL_XFRC,
|
||||
CTRL_HALTED,
|
||||
CTRL_NAK,
|
||||
CTRL_STALL,
|
||||
CTRL_XACTERR,
|
||||
CTRL_BBLERR,
|
||||
CTRL_DATATGLERR,
|
||||
CTRL_FAIL
|
||||
}CTRL_STATUS;
|
||||
|
||||
|
||||
typedef struct USB_OTG_hc
|
||||
{
|
||||
uint8_t dev_addr ;
|
||||
uint8_t ep_num;
|
||||
uint8_t ep_is_in;
|
||||
uint8_t speed;
|
||||
uint8_t do_ping;
|
||||
uint8_t ep_type;
|
||||
uint16_t max_packet;
|
||||
uint8_t data_pid;
|
||||
uint8_t *xfer_buff;
|
||||
uint32_t xfer_len;
|
||||
uint32_t xfer_count;
|
||||
uint8_t toggle_in;
|
||||
uint8_t toggle_out;
|
||||
uint32_t dma_addr;
|
||||
}
|
||||
USB_OTG_HC , *PUSB_OTG_HC;
|
||||
|
||||
typedef struct USB_OTG_ep
|
||||
{
|
||||
uint8_t num;
|
||||
uint8_t is_in;
|
||||
uint8_t is_stall;
|
||||
uint8_t type;
|
||||
uint8_t data_pid_start;
|
||||
uint8_t even_odd_frame;
|
||||
uint16_t tx_fifo_num;
|
||||
uint32_t maxpacket;
|
||||
/* transaction level variables*/
|
||||
uint8_t *xfer_buff;
|
||||
uint32_t dma_addr;
|
||||
uint32_t xfer_len;
|
||||
uint32_t xfer_count;
|
||||
/* Transfer level variables*/
|
||||
uint32_t rem_data_len;
|
||||
uint32_t total_data_len;
|
||||
uint32_t ctl_data_len;
|
||||
|
||||
}
|
||||
|
||||
USB_OTG_EP , *PUSB_OTG_EP;
|
||||
|
||||
|
||||
|
||||
typedef struct USB_OTG_core_cfg
|
||||
{
|
||||
uint8_t host_channels;
|
||||
uint8_t dev_endpoints;
|
||||
uint8_t speed;
|
||||
uint8_t dma_enable;
|
||||
uint16_t mps;
|
||||
uint16_t TotalFifoSize;
|
||||
uint8_t phy_itface;
|
||||
uint8_t Sof_output;
|
||||
uint8_t low_power;
|
||||
uint8_t coreID;
|
||||
|
||||
}
|
||||
USB_OTG_CORE_CFGS, *PUSB_OTG_CORE_CFGS;
|
||||
|
||||
|
||||
|
||||
typedef struct usb_setup_req {
|
||||
|
||||
uint8_t bmRequest;
|
||||
uint8_t bRequest;
|
||||
uint16_t wValue;
|
||||
uint16_t wIndex;
|
||||
uint16_t wLength;
|
||||
} USB_SETUP_REQ;
|
||||
|
||||
typedef struct _Device_TypeDef
|
||||
{
|
||||
uint8_t *(*GetDeviceDescriptor)( uint8_t speed , uint16_t *length);
|
||||
uint8_t *(*GetLangIDStrDescriptor)( uint8_t speed , uint16_t *length);
|
||||
uint8_t *(*GetManufacturerStrDescriptor)( uint8_t speed , uint16_t *length);
|
||||
uint8_t *(*GetProductStrDescriptor)( uint8_t speed , uint16_t *length);
|
||||
uint8_t *(*GetSerialStrDescriptor)( uint8_t speed , uint16_t *length);
|
||||
uint8_t *(*GetConfigurationStrDescriptor)( uint8_t speed , uint16_t *length);
|
||||
uint8_t *(*GetInterfaceStrDescriptor)( uint8_t speed , uint16_t *length);
|
||||
} USBD_DEVICE, *pUSBD_DEVICE;
|
||||
|
||||
typedef struct USB_OTG_hPort
|
||||
{
|
||||
void (*Disconnect) (void *phost);
|
||||
void (*Connect) (void *phost);
|
||||
uint8_t ConnStatus;
|
||||
uint8_t DisconnStatus;
|
||||
uint8_t ConnHandled;
|
||||
uint8_t DisconnHandled;
|
||||
} USB_OTG_hPort_TypeDef;
|
||||
|
||||
typedef struct _Device_cb
|
||||
{
|
||||
uint8_t (*Init) (void *pdev , uint8_t cfgidx);
|
||||
uint8_t (*DeInit) (void *pdev , uint8_t cfgidx);
|
||||
/* Control Endpoints*/
|
||||
uint8_t (*Setup) (void *pdev , USB_SETUP_REQ *req);
|
||||
uint8_t (*EP0_TxSent) (void *pdev );
|
||||
uint8_t (*EP0_RxReady) (void *pdev );
|
||||
/* Class Specific Endpoints*/
|
||||
uint8_t (*DataIn) (void *pdev , uint8_t epnum);
|
||||
uint8_t (*DataOut) (void *pdev , uint8_t epnum);
|
||||
uint8_t (*SOF) (void *pdev);
|
||||
uint8_t (*IsoINIncomplete) (void *pdev);
|
||||
uint8_t (*IsoOUTIncomplete) (void *pdev);
|
||||
|
||||
uint8_t *(*GetConfigDescriptor)( uint8_t speed , uint16_t *length);
|
||||
#ifdef USB_OTG_HS_CORE
|
||||
uint8_t *(*GetOtherConfigDescriptor)( uint8_t speed , uint16_t *length);
|
||||
#endif
|
||||
|
||||
#ifdef USB_SUPPORT_USER_STRING_DESC
|
||||
uint8_t *(*GetUsrStrDescriptor)( uint8_t speed ,uint8_t index, uint16_t *length);
|
||||
#endif
|
||||
|
||||
} USBD_Class_cb_TypeDef;
|
||||
|
||||
|
||||
|
||||
typedef struct _USBD_USR_PROP
|
||||
{
|
||||
void (*Init)(void);
|
||||
void (*DeviceReset)(uint8_t speed);
|
||||
void (*DeviceConfigured)(void);
|
||||
void (*DeviceSuspended)(void);
|
||||
void (*DeviceResumed)(void);
|
||||
|
||||
void (*DeviceConnected)(void);
|
||||
void (*DeviceDisconnected)(void);
|
||||
|
||||
}
|
||||
USBD_Usr_cb_TypeDef;
|
||||
|
||||
typedef struct _DCD
|
||||
{
|
||||
uint8_t device_config;
|
||||
uint8_t device_state;
|
||||
uint8_t device_status;
|
||||
uint8_t device_address;
|
||||
uint32_t DevRemoteWakeup;
|
||||
USB_OTG_EP in_ep [USB_OTG_MAX_TX_FIFOS];
|
||||
USB_OTG_EP out_ep [USB_OTG_MAX_TX_FIFOS];
|
||||
uint8_t setup_packet [8*3];
|
||||
USBD_Class_cb_TypeDef *class_cb;
|
||||
USBD_Usr_cb_TypeDef *usr_cb;
|
||||
USBD_DEVICE *usr_device;
|
||||
uint8_t *pConfig_descriptor;
|
||||
}
|
||||
DCD_DEV , *DCD_PDEV;
|
||||
|
||||
|
||||
typedef struct _HCD
|
||||
{
|
||||
uint8_t Rx_Buffer [MAX_DATA_LENGTH];
|
||||
__IO uint32_t ConnSts;
|
||||
__IO uint32_t ErrCnt[USB_OTG_MAX_TX_FIFOS];
|
||||
__IO uint32_t XferCnt[USB_OTG_MAX_TX_FIFOS];
|
||||
__IO HC_STATUS HC_Status[USB_OTG_MAX_TX_FIFOS];
|
||||
__IO URB_STATE URB_State[USB_OTG_MAX_TX_FIFOS];
|
||||
USB_OTG_HC hc [USB_OTG_MAX_TX_FIFOS];
|
||||
uint16_t channel [USB_OTG_MAX_TX_FIFOS];
|
||||
USB_OTG_hPort_TypeDef *port_cb;
|
||||
}
|
||||
HCD_DEV , *USB_OTG_USBH_PDEV;
|
||||
|
||||
|
||||
typedef struct _OTG
|
||||
{
|
||||
uint8_t OTG_State;
|
||||
uint8_t OTG_PrevState;
|
||||
uint8_t OTG_Mode;
|
||||
}
|
||||
OTG_DEV , *USB_OTG_USBO_PDEV;
|
||||
|
||||
typedef struct USB_OTG_handle
|
||||
{
|
||||
USB_OTG_CORE_CFGS cfg;
|
||||
USB_OTG_CORE_REGS regs;
|
||||
#ifdef USE_DEVICE_MODE
|
||||
DCD_DEV dev;
|
||||
#endif
|
||||
#ifdef USE_HOST_MODE
|
||||
HCD_DEV host;
|
||||
#endif
|
||||
#ifdef USE_OTG_MODE
|
||||
OTG_DEV otg;
|
||||
#endif
|
||||
}
|
||||
USB_OTG_CORE_HANDLE , *PUSB_OTG_CORE_HANDLE;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_CORE_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_CORE_Exported_Variables
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_CORE_Exported_FunctionsPrototype
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
USB_OTG_STS USB_OTG_CoreInit (USB_OTG_CORE_HANDLE *pdev);
|
||||
USB_OTG_STS USB_OTG_SelectCore (USB_OTG_CORE_HANDLE *pdev,
|
||||
USB_OTG_CORE_ID_TypeDef coreID);
|
||||
USB_OTG_STS USB_OTG_EnableGlobalInt (USB_OTG_CORE_HANDLE *pdev);
|
||||
USB_OTG_STS USB_OTG_DisableGlobalInt(USB_OTG_CORE_HANDLE *pdev);
|
||||
void* USB_OTG_ReadPacket (USB_OTG_CORE_HANDLE *pdev ,
|
||||
uint8_t *dest,
|
||||
uint16_t len);
|
||||
USB_OTG_STS USB_OTG_WritePacket (USB_OTG_CORE_HANDLE *pdev ,
|
||||
uint8_t *src,
|
||||
uint8_t ch_ep_num,
|
||||
uint16_t len);
|
||||
USB_OTG_STS USB_OTG_FlushTxFifo (USB_OTG_CORE_HANDLE *pdev , uint32_t num);
|
||||
USB_OTG_STS USB_OTG_FlushRxFifo (USB_OTG_CORE_HANDLE *pdev);
|
||||
|
||||
uint32_t USB_OTG_ReadCoreItr (USB_OTG_CORE_HANDLE *pdev);
|
||||
uint32_t USB_OTG_ReadOtgItr (USB_OTG_CORE_HANDLE *pdev);
|
||||
uint8_t USB_OTG_IsHostMode (USB_OTG_CORE_HANDLE *pdev);
|
||||
uint8_t USB_OTG_IsDeviceMode (USB_OTG_CORE_HANDLE *pdev);
|
||||
uint32_t USB_OTG_GetMode (USB_OTG_CORE_HANDLE *pdev);
|
||||
USB_OTG_STS USB_OTG_PhyInit (USB_OTG_CORE_HANDLE *pdev);
|
||||
USB_OTG_STS USB_OTG_SetCurrentMode (USB_OTG_CORE_HANDLE *pdev,
|
||||
uint8_t mode);
|
||||
|
||||
/*********************** HOST APIs ********************************************/
|
||||
#ifdef USE_HOST_MODE
|
||||
USB_OTG_STS USB_OTG_CoreInitHost (USB_OTG_CORE_HANDLE *pdev);
|
||||
USB_OTG_STS USB_OTG_EnableHostInt (USB_OTG_CORE_HANDLE *pdev);
|
||||
USB_OTG_STS USB_OTG_HC_Init (USB_OTG_CORE_HANDLE *pdev, uint8_t hc_num);
|
||||
USB_OTG_STS USB_OTG_HC_Halt (USB_OTG_CORE_HANDLE *pdev, uint8_t hc_num);
|
||||
USB_OTG_STS USB_OTG_HC_StartXfer (USB_OTG_CORE_HANDLE *pdev, uint8_t hc_num);
|
||||
USB_OTG_STS USB_OTG_HC_DoPing (USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num);
|
||||
uint32_t USB_OTG_ReadHostAllChannels_intr (USB_OTG_CORE_HANDLE *pdev);
|
||||
uint32_t USB_OTG_ResetPort (USB_OTG_CORE_HANDLE *pdev);
|
||||
uint32_t USB_OTG_ReadHPRT0 (USB_OTG_CORE_HANDLE *pdev);
|
||||
void USB_OTG_DriveVbus (USB_OTG_CORE_HANDLE *pdev, uint8_t state);
|
||||
void USB_OTG_InitFSLSPClkSel (USB_OTG_CORE_HANDLE *pdev ,uint8_t freq);
|
||||
uint8_t USB_OTG_IsEvenFrame (USB_OTG_CORE_HANDLE *pdev) ;
|
||||
void USB_OTG_StopHost (USB_OTG_CORE_HANDLE *pdev);
|
||||
#endif
|
||||
/********************* DEVICE APIs ********************************************/
|
||||
#ifdef USE_DEVICE_MODE
|
||||
USB_OTG_STS USB_OTG_CoreInitDev (USB_OTG_CORE_HANDLE *pdev);
|
||||
USB_OTG_STS USB_OTG_EnableDevInt (USB_OTG_CORE_HANDLE *pdev);
|
||||
uint32_t USB_OTG_ReadDevAllInEPItr (USB_OTG_CORE_HANDLE *pdev);
|
||||
enum USB_OTG_SPEED USB_OTG_GetDeviceSpeed (USB_OTG_CORE_HANDLE *pdev);
|
||||
USB_OTG_STS USB_OTG_EP0Activate (USB_OTG_CORE_HANDLE *pdev);
|
||||
USB_OTG_STS USB_OTG_EPActivate (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep);
|
||||
USB_OTG_STS USB_OTG_EPDeactivate(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep);
|
||||
USB_OTG_STS USB_OTG_EPStartXfer (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep);
|
||||
USB_OTG_STS USB_OTG_EP0StartXfer(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep);
|
||||
USB_OTG_STS USB_OTG_EPSetStall (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep);
|
||||
USB_OTG_STS USB_OTG_EPClearStall (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep);
|
||||
uint32_t USB_OTG_ReadDevAllOutEp_itr (USB_OTG_CORE_HANDLE *pdev);
|
||||
uint32_t USB_OTG_ReadDevOutEP_itr (USB_OTG_CORE_HANDLE *pdev , uint8_t epnum);
|
||||
uint32_t USB_OTG_ReadDevAllInEPItr (USB_OTG_CORE_HANDLE *pdev);
|
||||
void USB_OTG_InitDevSpeed (USB_OTG_CORE_HANDLE *pdev , uint8_t speed);
|
||||
uint8_t USBH_IsEvenFrame (USB_OTG_CORE_HANDLE *pdev);
|
||||
void USB_OTG_EP0_OutStart(USB_OTG_CORE_HANDLE *pdev);
|
||||
void USB_OTG_ActiveRemoteWakeup(USB_OTG_CORE_HANDLE *pdev);
|
||||
void USB_OTG_UngateClock(USB_OTG_CORE_HANDLE *pdev);
|
||||
void USB_OTG_StopDevice(USB_OTG_CORE_HANDLE *pdev);
|
||||
void USB_OTG_SetEPStatus (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep , uint32_t Status);
|
||||
uint32_t USB_OTG_GetEPStatus(USB_OTG_CORE_HANDLE *pdev ,USB_OTG_EP *ep);
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* __USB_CORE_H__ */
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
|
||||
|
|
@ -0,0 +1,158 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file usb_dcd.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.0.0
|
||||
* @date 22-July-2011
|
||||
* @brief Peripheral Driver Header file
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __DCD_H__
|
||||
#define __DCD_H__
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "usb_core.h"
|
||||
|
||||
|
||||
/** @addtogroup USB_OTG_DRIVER
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USB_DCD
|
||||
* @brief This file is the
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_DCD_Exported_Defines
|
||||
* @{
|
||||
*/
|
||||
#define USB_OTG_EP_CONTROL 0
|
||||
#define USB_OTG_EP_ISOC 1
|
||||
#define USB_OTG_EP_BULK 2
|
||||
#define USB_OTG_EP_INT 3
|
||||
#define USB_OTG_EP_MASK 3
|
||||
|
||||
/* Device Status */
|
||||
#define USB_OTG_DEFAULT 1
|
||||
#define USB_OTG_ADDRESSED 2
|
||||
#define USB_OTG_CONFIGURED 3
|
||||
#define USB_OTG_SUSPENDED 4
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_DCD_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
/********************************************************************************
|
||||
Data structure type
|
||||
********************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t bLength;
|
||||
uint8_t bDescriptorType;
|
||||
uint8_t bEndpointAddress;
|
||||
uint8_t bmAttributes;
|
||||
uint16_t wMaxPacketSize;
|
||||
uint8_t bInterval;
|
||||
}
|
||||
EP_DESCRIPTOR , *PEP_DESCRIPTOR;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_DCD_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_DCD_Exported_Variables
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_DCD_Exported_FunctionsPrototype
|
||||
* @{
|
||||
*/
|
||||
/********************************************************************************
|
||||
EXPORTED FUNCTION FROM THE USB-OTG LAYER
|
||||
********************************************************************************/
|
||||
void DCD_Init(USB_OTG_CORE_HANDLE *pdev ,
|
||||
USB_OTG_CORE_ID_TypeDef coreID);
|
||||
|
||||
void DCD_DevConnect (USB_OTG_CORE_HANDLE *pdev);
|
||||
void DCD_DevDisconnect (USB_OTG_CORE_HANDLE *pdev);
|
||||
void DCD_EP_SetAddress (USB_OTG_CORE_HANDLE *pdev,
|
||||
uint8_t address);
|
||||
uint32_t DCD_EP_Open(USB_OTG_CORE_HANDLE *pdev ,
|
||||
uint8_t ep_addr,
|
||||
uint16_t ep_mps,
|
||||
uint8_t ep_type);
|
||||
|
||||
uint32_t DCD_EP_Close (USB_OTG_CORE_HANDLE *pdev,
|
||||
uint8_t ep_addr);
|
||||
|
||||
|
||||
uint32_t DCD_EP_PrepareRx ( USB_OTG_CORE_HANDLE *pdev,
|
||||
uint8_t ep_addr,
|
||||
uint8_t *pbuf,
|
||||
uint16_t buf_len);
|
||||
|
||||
uint32_t DCD_EP_Tx (USB_OTG_CORE_HANDLE *pdev,
|
||||
uint8_t ep_addr,
|
||||
uint8_t *pbuf,
|
||||
uint32_t buf_len);
|
||||
uint32_t DCD_EP_Stall (USB_OTG_CORE_HANDLE *pdev,
|
||||
uint8_t epnum);
|
||||
uint32_t DCD_EP_ClrStall (USB_OTG_CORE_HANDLE *pdev,
|
||||
uint8_t epnum);
|
||||
uint32_t DCD_EP_Flush (USB_OTG_CORE_HANDLE *pdev,
|
||||
uint8_t epnum);
|
||||
uint32_t DCD_Handle_ISR(USB_OTG_CORE_HANDLE *pdev);
|
||||
|
||||
uint32_t DCD_GetEPStatus(USB_OTG_CORE_HANDLE *pdev ,
|
||||
uint8_t epnum);
|
||||
|
||||
void DCD_SetEPStatus (USB_OTG_CORE_HANDLE *pdev ,
|
||||
uint8_t epnum ,
|
||||
uint32_t Status);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#endif //__DCD_H__
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
|
||||
|
|
@ -0,0 +1,121 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file usb_dcd_int.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.0.0
|
||||
* @date 22-July-2011
|
||||
* @brief Peripheral Device Interface Layer
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef USB_DCD_INT_H__
|
||||
#define USB_DCD_INT_H__
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "usb_dcd.h"
|
||||
|
||||
|
||||
|
||||
/** @addtogroup USB_OTG_DRIVER
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USB_DCD_INT
|
||||
* @brief This file is the
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_DCD_INT_Exported_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef struct _USBD_DCD_INT
|
||||
{
|
||||
uint8_t (* DataOutStage) (USB_OTG_CORE_HANDLE *pdev , uint8_t epnum);
|
||||
uint8_t (* DataInStage) (USB_OTG_CORE_HANDLE *pdev , uint8_t epnum);
|
||||
uint8_t (* SetupStage) (USB_OTG_CORE_HANDLE *pdev);
|
||||
uint8_t (* SOF) (USB_OTG_CORE_HANDLE *pdev);
|
||||
uint8_t (* Reset) (USB_OTG_CORE_HANDLE *pdev);
|
||||
uint8_t (* Suspend) (USB_OTG_CORE_HANDLE *pdev);
|
||||
uint8_t (* Resume) (USB_OTG_CORE_HANDLE *pdev);
|
||||
uint8_t (* IsoINIncomplete) (USB_OTG_CORE_HANDLE *pdev);
|
||||
uint8_t (* IsoOUTIncomplete) (USB_OTG_CORE_HANDLE *pdev);
|
||||
|
||||
uint8_t (* DevConnected) (USB_OTG_CORE_HANDLE *pdev);
|
||||
uint8_t (* DevDisconnected) (USB_OTG_CORE_HANDLE *pdev);
|
||||
|
||||
}USBD_DCD_INT_cb_TypeDef;
|
||||
|
||||
extern USBD_DCD_INT_cb_TypeDef *USBD_DCD_INT_fops;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_DCD_INT_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_DCD_INT_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CLEAR_IN_EP_INTR(epnum,intr) \
|
||||
diepint.d32=0; \
|
||||
diepint.b.intr = 1; \
|
||||
USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[epnum]->DIEPINT,diepint.d32);
|
||||
|
||||
#define CLEAR_OUT_EP_INTR(epnum,intr) \
|
||||
doepint.d32=0; \
|
||||
doepint.b.intr = 1; \
|
||||
USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[epnum]->DOEPINT,doepint.d32);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_DCD_INT_Exported_Variables
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_DCD_INT_Exported_FunctionsPrototype
|
||||
* @{
|
||||
*/
|
||||
|
||||
uint32_t USBD_OTG_ISR_Handler (USB_OTG_CORE_HANDLE *pdev);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#endif // USB_DCD_INT_H__
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
|
||||
|
|
@ -0,0 +1,244 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file usb_defines.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.0.0
|
||||
* @date 22-July-2011
|
||||
* @brief Header of the Core Layer
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __USB_DEF_H__
|
||||
#define __USB_DEF_H__
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "usb_conf.h"
|
||||
|
||||
/** @addtogroup USB_OTG_DRIVER
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USB_DEFINES
|
||||
* @brief This file is the
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_DEFINES_Exported_Defines
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup _CORE_DEFINES_
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USB_OTG_SPEED_PARAM_HIGH 0
|
||||
#define USB_OTG_SPEED_PARAM_HIGH_IN_FULL 1
|
||||
#define USB_OTG_SPEED_PARAM_FULL 3
|
||||
|
||||
#define USB_OTG_SPEED_HIGH 0
|
||||
#define USB_OTG_SPEED_FULL 1
|
||||
|
||||
#define USB_OTG_ULPI_PHY 1
|
||||
#define USB_OTG_EMBEDDED_PHY 2
|
||||
#define USB_OTG_I2C_PHY 3
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup _GLOBAL_DEFINES_
|
||||
* @{
|
||||
*/
|
||||
#define GAHBCFG_TXFEMPTYLVL_EMPTY 1
|
||||
#define GAHBCFG_TXFEMPTYLVL_HALFEMPTY 0
|
||||
#define GAHBCFG_GLBINT_ENABLE 1
|
||||
#define GAHBCFG_INT_DMA_BURST_SINGLE 0
|
||||
#define GAHBCFG_INT_DMA_BURST_INCR 1
|
||||
#define GAHBCFG_INT_DMA_BURST_INCR4 3
|
||||
#define GAHBCFG_INT_DMA_BURST_INCR8 5
|
||||
#define GAHBCFG_INT_DMA_BURST_INCR16 7
|
||||
#define GAHBCFG_DMAENABLE 1
|
||||
#define GAHBCFG_TXFEMPTYLVL_EMPTY 1
|
||||
#define GAHBCFG_TXFEMPTYLVL_HALFEMPTY 0
|
||||
#define GRXSTS_PKTSTS_IN 2
|
||||
#define GRXSTS_PKTSTS_IN_XFER_COMP 3
|
||||
#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5
|
||||
#define GRXSTS_PKTSTS_CH_HALTED 7
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup _OnTheGo_DEFINES_
|
||||
* @{
|
||||
*/
|
||||
#define MODE_HNP_SRP_CAPABLE 0
|
||||
#define MODE_SRP_ONLY_CAPABLE 1
|
||||
#define MODE_NO_HNP_SRP_CAPABLE 2
|
||||
#define MODE_SRP_CAPABLE_DEVICE 3
|
||||
#define MODE_NO_SRP_CAPABLE_DEVICE 4
|
||||
#define MODE_SRP_CAPABLE_HOST 5
|
||||
#define MODE_NO_SRP_CAPABLE_HOST 6
|
||||
#define A_HOST 1
|
||||
#define A_SUSPEND 2
|
||||
#define A_PERIPHERAL 3
|
||||
#define B_PERIPHERAL 4
|
||||
#define B_HOST 5
|
||||
#define DEVICE_MODE 0
|
||||
#define HOST_MODE 1
|
||||
#define OTG_MODE 2
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup __DEVICE_DEFINES_
|
||||
* @{
|
||||
*/
|
||||
#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0
|
||||
#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1
|
||||
#define DSTS_ENUMSPD_LS_PHY_6MHZ 2
|
||||
#define DSTS_ENUMSPD_FS_PHY_48MHZ 3
|
||||
|
||||
#define DCFG_FRAME_INTERVAL_80 0
|
||||
#define DCFG_FRAME_INTERVAL_85 1
|
||||
#define DCFG_FRAME_INTERVAL_90 2
|
||||
#define DCFG_FRAME_INTERVAL_95 3
|
||||
|
||||
#define DEP0CTL_MPS_64 0
|
||||
#define DEP0CTL_MPS_32 1
|
||||
#define DEP0CTL_MPS_16 2
|
||||
#define DEP0CTL_MPS_8 3
|
||||
|
||||
#define EP_SPEED_LOW 0
|
||||
#define EP_SPEED_FULL 1
|
||||
#define EP_SPEED_HIGH 2
|
||||
|
||||
#define EP_TYPE_CTRL 0
|
||||
#define EP_TYPE_ISOC 1
|
||||
#define EP_TYPE_BULK 2
|
||||
#define EP_TYPE_INTR 3
|
||||
#define EP_TYPE_MSK 3
|
||||
|
||||
#define STS_GOUT_NAK 1
|
||||
#define STS_DATA_UPDT 2
|
||||
#define STS_XFER_COMP 3
|
||||
#define STS_SETUP_COMP 4
|
||||
#define STS_SETUP_UPDT 6
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup __HOST_DEFINES_
|
||||
* @{
|
||||
*/
|
||||
#define HC_PID_DATA0 0
|
||||
#define HC_PID_DATA2 1
|
||||
#define HC_PID_DATA1 2
|
||||
#define HC_PID_SETUP 3
|
||||
|
||||
#define HPRT0_PRTSPD_HIGH_SPEED 0
|
||||
#define HPRT0_PRTSPD_FULL_SPEED 1
|
||||
#define HPRT0_PRTSPD_LOW_SPEED 2
|
||||
|
||||
#define HCFG_30_60_MHZ 0
|
||||
#define HCFG_48_MHZ 1
|
||||
#define HCFG_6_MHZ 2
|
||||
|
||||
#define HCCHAR_CTRL 0
|
||||
#define HCCHAR_ISOC 1
|
||||
#define HCCHAR_BULK 2
|
||||
#define HCCHAR_INTR 3
|
||||
|
||||
#define MIN(a, b) (((a) < (b)) ? (a) : (b))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_DEFINES_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{
|
||||
USB_OTG_HS_CORE_ID = 0,
|
||||
USB_OTG_FS_CORE_ID = 1
|
||||
}USB_OTG_CORE_ID_TypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_DEFINES_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_DEFINES_Exported_Variables
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_DEFINES_Exported_FunctionsPrototype
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup Internal_Macro's
|
||||
* @{
|
||||
*/
|
||||
#define USB_OTG_READ_REG32(reg) (*(__IO uint32_t *)reg)
|
||||
#define USB_OTG_WRITE_REG32(reg,value) (*(__IO uint32_t *)reg = value)
|
||||
#define USB_OTG_MODIFY_REG32(reg,clear_mask,set_mask) \
|
||||
USB_OTG_WRITE_REG32(reg, (((USB_OTG_READ_REG32(reg)) & ~clear_mask) | set_mask ) )
|
||||
|
||||
/********************************************************************************
|
||||
ENUMERATION TYPE
|
||||
********************************************************************************/
|
||||
enum USB_OTG_SPEED {
|
||||
USB_SPEED_UNKNOWN = 0,
|
||||
USB_SPEED_LOW,
|
||||
USB_SPEED_FULL,
|
||||
USB_SPEED_HIGH
|
||||
};
|
||||
|
||||
#endif //__USB_DEFINES__H__
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
|
||||
|
|
@ -0,0 +1,102 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file usb_hcd.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.0.0
|
||||
* @date 22-July-2011
|
||||
* @brief Host layer Header file
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __USB_HCD_H__
|
||||
#define __USB_HCD_H__
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "usb_regs.h"
|
||||
#include "usb_core.h"
|
||||
|
||||
|
||||
/** @addtogroup USB_OTG_DRIVER
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USB_HCD
|
||||
* @brief This file is the
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_HCD_Exported_Defines
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_HCD_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_HCD_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_HCD_Exported_Variables
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_HCD_Exported_FunctionsPrototype
|
||||
* @{
|
||||
*/
|
||||
uint32_t HCD_Init (USB_OTG_CORE_HANDLE *pdev ,
|
||||
USB_OTG_CORE_ID_TypeDef coreID);
|
||||
uint32_t HCD_HC_Init (USB_OTG_CORE_HANDLE *pdev ,
|
||||
uint8_t hc_num);
|
||||
uint32_t HCD_SubmitRequest (USB_OTG_CORE_HANDLE *pdev ,
|
||||
uint8_t hc_num) ;
|
||||
uint32_t HCD_GetCurrentSpeed (USB_OTG_CORE_HANDLE *pdev);
|
||||
uint32_t HCD_ResetPort (USB_OTG_CORE_HANDLE *pdev);
|
||||
uint32_t HCD_IsDeviceConnected (USB_OTG_CORE_HANDLE *pdev);
|
||||
uint32_t HCD_GetCurrentFrame (USB_OTG_CORE_HANDLE *pdev) ;
|
||||
URB_STATE HCD_GetURB_State (USB_OTG_CORE_HANDLE *pdev, uint8_t ch_num);
|
||||
uint32_t HCD_GetXferCnt (USB_OTG_CORE_HANDLE *pdev, uint8_t ch_num);
|
||||
HC_STATUS HCD_GetHCState (USB_OTG_CORE_HANDLE *pdev, uint8_t ch_num) ;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif //__USB_HCD_H__
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
|
||||
|
|
@ -0,0 +1,126 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file usb_hcd_int.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.0.0
|
||||
* @date 22-July-2011
|
||||
* @brief Peripheral Device Interface Layer
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __HCD_INT_H__
|
||||
#define __HCD_INT_H__
|
||||
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "usb_hcd.h"
|
||||
|
||||
|
||||
/** @addtogroup USB_OTG_DRIVER
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USB_HCD_INT
|
||||
* @brief This file is the
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_HCD_INT_Exported_Defines
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_HCD_INT_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_HCD_INT_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CLEAR_HC_INT(HC_REGS, intr) \
|
||||
{\
|
||||
USB_OTG_HCINTn_TypeDef hcint_clear; \
|
||||
hcint_clear.d32 = 0; \
|
||||
hcint_clear.b.intr = 1; \
|
||||
USB_OTG_WRITE_REG32(&((HC_REGS)->HCINT), hcint_clear.d32);\
|
||||
}\
|
||||
|
||||
#define MASK_HOST_INT_CHH(hc_num) { USB_OTG_HCGINTMSK_TypeDef GINTMSK; \
|
||||
GINTMSK.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCGINTMSK); \
|
||||
GINTMSK.b.chhltd = 0; \
|
||||
USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCGINTMSK, GINTMSK.d32);}
|
||||
|
||||
#define UNMASK_HOST_INT_CHH(hc_num) { USB_OTG_HCGINTMSK_TypeDef GINTMSK; \
|
||||
GINTMSK.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCGINTMSK); \
|
||||
GINTMSK.b.chhltd = 1; \
|
||||
USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCGINTMSK, GINTMSK.d32);}
|
||||
|
||||
#define MASK_HOST_INT_ACK(hc_num) { USB_OTG_HCGINTMSK_TypeDef GINTMSK; \
|
||||
GINTMSK.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCGINTMSK); \
|
||||
GINTMSK.b.ack = 0; \
|
||||
USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCGINTMSK, GINTMSK.d32);}
|
||||
|
||||
#define UNMASK_HOST_INT_ACK(hc_num) { USB_OTG_HCGINTMSK_TypeDef GINTMSK; \
|
||||
GINTMSK.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCGINTMSK); \
|
||||
GINTMSK.b.ack = 1; \
|
||||
USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCGINTMSK, GINTMSK.d32);}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_HCD_INT_Exported_Variables
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_HCD_INT_Exported_FunctionsPrototype
|
||||
* @{
|
||||
*/
|
||||
/* Callbacks handler */
|
||||
void ConnectCallback_Handler(USB_OTG_CORE_HANDLE *pdev);
|
||||
void Disconnect_Callback_Handler(USB_OTG_CORE_HANDLE *pdev);
|
||||
void Overcurrent_Callback_Handler(USB_OTG_CORE_HANDLE *pdev);
|
||||
uint32_t USBH_OTG_ISR_Handler (USB_OTG_CORE_HANDLE *pdev);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#endif //__HCD_INT_H__
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
|
||||
|
|
@ -0,0 +1,94 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file usb_otg.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.0.0
|
||||
* @date 22-July-2011
|
||||
* @brief OTG Core Header
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __USB_OTG__
|
||||
#define __USB_OTG__
|
||||
|
||||
|
||||
/** @addtogroup USB_OTG_DRIVER
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USB_OTG
|
||||
* @brief This file is the
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_OTG_Exported_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
void USB_OTG_InitiateSRP(void);
|
||||
void USB_OTG_InitiateHNP(uint8_t state , uint8_t mode);
|
||||
void USB_OTG_Switchback (USB_OTG_CORE_HANDLE *pdev);
|
||||
uint32_t USB_OTG_GetCurrentState (USB_OTG_CORE_HANDLE *pdev);
|
||||
|
||||
uint32_t STM32_USBO_OTG_ISR_Handler(USB_OTG_CORE_HANDLE *pdev);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_OTG_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_OTG_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_OTG_Exported_Variables
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_OTG_Exported_FunctionsPrototype
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#endif //__USB_OTG__
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
|
||||
Plik diff jest za duży
Load Diff
|
|
@ -0,0 +1,200 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file usb_bsp.c
|
||||
* @author MCD Application Team
|
||||
* @version V2.0.0
|
||||
* @date 22-July-2011
|
||||
* @brief This file is responsible to offer board support package and is
|
||||
* configurable by user.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "usb_bsp.h"
|
||||
|
||||
/** @addtogroup USB_OTG_DRIVER
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USB_BSP
|
||||
* @brief This file is responsible to offer board support package
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USB_BSP_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_BSP_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/** @defgroup USB_BSP_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USBH_BSP_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USBH_BSP_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_BSP_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief USB_OTG_BSP_Init
|
||||
* Initilizes BSP configurations
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
void USB_OTG_BSP_Init(void)
|
||||
{
|
||||
|
||||
}
|
||||
/**
|
||||
* @brief USB_OTG_BSP_EnableInterrupt
|
||||
* Enabele USB Global interrupt
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void USB_OTG_BSP_EnableInterrupt(void)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief BSP_Drive_VBUS
|
||||
* Drives the Vbus signal through IO
|
||||
* @param speed : Full, Low
|
||||
* @param state : VBUS states
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
void USB_OTG_BSP_DriveVBUS(uint32_t speed, uint8_t state)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USB_OTG_BSP_ConfigVBUS
|
||||
* Configures the IO for the Vbus and OverCurrent
|
||||
* @param Speed : Full, Low
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
void USB_OTG_BSP_ConfigVBUS(uint32_t speed)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USB_OTG_BSP_TimeInit
|
||||
* Initialises delay unit Systick timer /Timer2
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void USB_OTG_BSP_TimeInit ( void )
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USB_OTG_BSP_uDelay
|
||||
* This function provides delay time in micro sec
|
||||
* @param usec : Value of delay required in micro sec
|
||||
* @retval None
|
||||
*/
|
||||
void USB_OTG_BSP_uDelay (const uint32_t usec)
|
||||
{
|
||||
|
||||
uint32_t count = 0;
|
||||
const uint32_t utime = (120 * usec / 7);
|
||||
do
|
||||
{
|
||||
if ( ++count > utime )
|
||||
{
|
||||
return ;
|
||||
}
|
||||
}
|
||||
while (1);
|
||||
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief USB_OTG_BSP_mDelay
|
||||
* This function provides delay time in milli sec
|
||||
* @param msec : Value of delay required in milli sec
|
||||
* @retval None
|
||||
*/
|
||||
void USB_OTG_BSP_mDelay (const uint32_t msec)
|
||||
{
|
||||
|
||||
USB_OTG_BSP_uDelay(msec * 1000);
|
||||
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief USB_OTG_BSP_TimerIRQ
|
||||
* Time base IRQ
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
void USB_OTG_BSP_TimerIRQ (void)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
Plik diff jest za duży
Load Diff
|
|
@ -0,0 +1,472 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file usb_dcd.c
|
||||
* @author MCD Application Team
|
||||
* @version V2.0.0
|
||||
* @date 22-July-2011
|
||||
* @brief Peripheral Device Interface Layer
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "usb_dcd.h"
|
||||
#include "usb_bsp.h"
|
||||
|
||||
|
||||
/** @addtogroup USB_OTG_DRIVER
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USB_DCD
|
||||
* @brief This file is the interface between EFSL ans Host mass-storage class
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_DCD_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_DCD_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/** @defgroup USB_DCD_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_DCD_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_DCD_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_DCD_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
|
||||
void DCD_Init(USB_OTG_CORE_HANDLE *pdev ,
|
||||
USB_OTG_CORE_ID_TypeDef coreID)
|
||||
{
|
||||
uint32_t i;
|
||||
USB_OTG_EP *ep;
|
||||
|
||||
USB_OTG_SelectCore (pdev , coreID);
|
||||
|
||||
pdev->dev.device_status = USB_OTG_DEFAULT;
|
||||
pdev->dev.device_address = 0;
|
||||
|
||||
/* Init ep structure */
|
||||
for (i = 0; i < pdev->cfg.dev_endpoints ; i++)
|
||||
{
|
||||
ep = &pdev->dev.in_ep[i];
|
||||
/* Init ep structure */
|
||||
ep->is_in = 1;
|
||||
ep->num = i;
|
||||
ep->tx_fifo_num = i;
|
||||
/* Control until ep is actvated */
|
||||
ep->type = EP_TYPE_CTRL;
|
||||
ep->maxpacket = USB_OTG_MAX_EP0_SIZE;
|
||||
ep->xfer_buff = 0;
|
||||
ep->xfer_len = 0;
|
||||
}
|
||||
|
||||
for (i = 0; i < pdev->cfg.dev_endpoints; i++)
|
||||
{
|
||||
ep = &pdev->dev.out_ep[i];
|
||||
/* Init ep structure */
|
||||
ep->is_in = 0;
|
||||
ep->num = i;
|
||||
ep->tx_fifo_num = i;
|
||||
/* Control until ep is activated */
|
||||
ep->type = EP_TYPE_CTRL;
|
||||
ep->maxpacket = USB_OTG_MAX_EP0_SIZE;
|
||||
ep->xfer_buff = 0;
|
||||
ep->xfer_len = 0;
|
||||
}
|
||||
|
||||
USB_OTG_DisableGlobalInt(pdev);
|
||||
|
||||
/*Init the Core (common init.) */
|
||||
USB_OTG_CoreInit(pdev);
|
||||
|
||||
|
||||
/* Force Device Mode*/
|
||||
USB_OTG_SetCurrentMode(pdev, DEVICE_MODE);
|
||||
|
||||
/* Init Device */
|
||||
USB_OTG_CoreInitDev(pdev);
|
||||
|
||||
|
||||
/* Enable USB Global interrupt */
|
||||
USB_OTG_EnableGlobalInt(pdev);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Configure an EP
|
||||
* @param pdev : Device instance
|
||||
* @param epdesc : Endpoint Descriptor
|
||||
* @retval : status
|
||||
*/
|
||||
uint32_t DCD_EP_Open(USB_OTG_CORE_HANDLE *pdev ,
|
||||
uint8_t ep_addr,
|
||||
uint16_t ep_mps,
|
||||
uint8_t ep_type)
|
||||
{
|
||||
USB_OTG_EP *ep;
|
||||
|
||||
if ((ep_addr & 0x80) == 0x80)
|
||||
{
|
||||
ep = &pdev->dev.in_ep[ep_addr & 0x7F];
|
||||
}
|
||||
else
|
||||
{
|
||||
ep = &pdev->dev.out_ep[ep_addr & 0x7F];
|
||||
}
|
||||
ep->num = ep_addr & 0x7F;
|
||||
|
||||
ep->is_in = (0x80 & ep_addr) != 0;
|
||||
ep->maxpacket = ep_mps;
|
||||
ep->type = ep_type;
|
||||
if (ep->is_in)
|
||||
{
|
||||
/* Assign a Tx FIFO */
|
||||
ep->tx_fifo_num = ep->num;
|
||||
}
|
||||
/* Set initial data PID. */
|
||||
if (ep_type == USB_OTG_EP_BULK )
|
||||
{
|
||||
ep->data_pid_start = 0;
|
||||
}
|
||||
USB_OTG_EPActivate(pdev , ep );
|
||||
return 0;
|
||||
}
|
||||
/**
|
||||
* @brief called when an EP is disabled
|
||||
* @param pdev: device instance
|
||||
* @param ep_addr: endpoint address
|
||||
* @retval : status
|
||||
*/
|
||||
uint32_t DCD_EP_Close(USB_OTG_CORE_HANDLE *pdev , uint8_t ep_addr)
|
||||
{
|
||||
USB_OTG_EP *ep;
|
||||
|
||||
if ((ep_addr&0x80) == 0x80)
|
||||
{
|
||||
ep = &pdev->dev.in_ep[ep_addr & 0x7F];
|
||||
}
|
||||
else
|
||||
{
|
||||
ep = &pdev->dev.out_ep[ep_addr & 0x7F];
|
||||
}
|
||||
ep->num = ep_addr & 0x7F;
|
||||
ep->is_in = (0x80 & ep_addr) != 0;
|
||||
USB_OTG_EPDeactivate(pdev , ep );
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief DCD_EP_PrepareRx
|
||||
* @param pdev: device instance
|
||||
* @param ep_addr: endpoint address
|
||||
* @param pbuf: pointer to Rx buffer
|
||||
* @param buf_len: data length
|
||||
* @retval : status
|
||||
*/
|
||||
uint32_t DCD_EP_PrepareRx( USB_OTG_CORE_HANDLE *pdev,
|
||||
uint8_t ep_addr,
|
||||
uint8_t *pbuf,
|
||||
uint16_t buf_len)
|
||||
{
|
||||
USB_OTG_EP *ep;
|
||||
|
||||
ep = &pdev->dev.out_ep[ep_addr & 0x7F];
|
||||
|
||||
/*setup and start the Xfer */
|
||||
ep->xfer_buff = pbuf;
|
||||
ep->xfer_len = buf_len;
|
||||
ep->xfer_count = 0;
|
||||
ep->is_in = 0;
|
||||
ep->num = ep_addr & 0x7F;
|
||||
|
||||
if (pdev->cfg.dma_enable == 1)
|
||||
{
|
||||
ep->dma_addr = (uint32_t)pbuf;
|
||||
}
|
||||
|
||||
if ( ep->num == 0 )
|
||||
{
|
||||
USB_OTG_EP0StartXfer(pdev , ep);
|
||||
}
|
||||
else
|
||||
{
|
||||
USB_OTG_EPStartXfer(pdev, ep );
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Transmit data over USB
|
||||
* @param pdev: device instance
|
||||
* @param ep_addr: endpoint address
|
||||
* @param pbuf: pointer to Tx buffer
|
||||
* @param buf_len: data length
|
||||
* @retval : status
|
||||
*/
|
||||
uint32_t DCD_EP_Tx ( USB_OTG_CORE_HANDLE *pdev,
|
||||
uint8_t ep_addr,
|
||||
uint8_t *pbuf,
|
||||
uint32_t buf_len)
|
||||
{
|
||||
USB_OTG_EP *ep;
|
||||
|
||||
ep = &pdev->dev.in_ep[ep_addr & 0x7F];
|
||||
|
||||
/* Setup and start the Transfer */
|
||||
ep->is_in = 1;
|
||||
ep->num = ep_addr & 0x7F;
|
||||
ep->xfer_buff = pbuf;
|
||||
ep->dma_addr = (uint32_t)pbuf;
|
||||
ep->xfer_count = 0;
|
||||
ep->xfer_len = buf_len;
|
||||
|
||||
if ( ep->num == 0 )
|
||||
{
|
||||
USB_OTG_EP0StartXfer(pdev , ep);
|
||||
}
|
||||
else
|
||||
{
|
||||
USB_OTG_EPStartXfer(pdev, ep );
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Stall an endpoint.
|
||||
* @param pdev: device instance
|
||||
* @param epnum: endpoint address
|
||||
* @retval : status
|
||||
*/
|
||||
uint32_t DCD_EP_Stall (USB_OTG_CORE_HANDLE *pdev, uint8_t epnum)
|
||||
{
|
||||
USB_OTG_EP *ep;
|
||||
if ((0x80 & epnum) == 0x80)
|
||||
{
|
||||
ep = &pdev->dev.in_ep[epnum & 0x7F];
|
||||
}
|
||||
else
|
||||
{
|
||||
ep = &pdev->dev.out_ep[epnum];
|
||||
}
|
||||
|
||||
ep->is_stall = 1;
|
||||
ep->num = epnum & 0x7F;
|
||||
ep->is_in = ((epnum & 0x80) == 0x80);
|
||||
|
||||
USB_OTG_EPSetStall(pdev , ep);
|
||||
return (0);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Clear stall condition on endpoints.
|
||||
* @param pdev: device instance
|
||||
* @param epnum: endpoint address
|
||||
* @retval : status
|
||||
*/
|
||||
uint32_t DCD_EP_ClrStall (USB_OTG_CORE_HANDLE *pdev, uint8_t epnum)
|
||||
{
|
||||
USB_OTG_EP *ep;
|
||||
if ((0x80 & epnum) == 0x80)
|
||||
{
|
||||
ep = &pdev->dev.in_ep[epnum & 0x7F];
|
||||
}
|
||||
else
|
||||
{
|
||||
ep = &pdev->dev.out_ep[epnum];
|
||||
}
|
||||
|
||||
ep->is_stall = 0;
|
||||
ep->num = epnum & 0x7F;
|
||||
ep->is_in = ((epnum & 0x80) == 0x80);
|
||||
|
||||
USB_OTG_EPClearStall(pdev , ep);
|
||||
return (0);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief This Function flushes the FIFOs.
|
||||
* @param pdev: device instance
|
||||
* @param epnum: endpoint address
|
||||
* @retval : status
|
||||
*/
|
||||
uint32_t DCD_EP_Flush (USB_OTG_CORE_HANDLE *pdev , uint8_t epnum)
|
||||
{
|
||||
|
||||
if ((epnum & 0x80) == 0x80)
|
||||
{
|
||||
USB_OTG_FlushTxFifo(pdev, epnum & 0x7F);
|
||||
}
|
||||
else
|
||||
{
|
||||
USB_OTG_FlushRxFifo(pdev);
|
||||
}
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief This Function set USB device address
|
||||
* @param pdev: device instance
|
||||
* @param address: new device address
|
||||
* @retval : status
|
||||
*/
|
||||
void DCD_EP_SetAddress (USB_OTG_CORE_HANDLE *pdev, uint8_t address)
|
||||
{
|
||||
USB_OTG_DCFG_TypeDef dcfg;
|
||||
dcfg.d32 = 0;
|
||||
dcfg.b.devaddr = address;
|
||||
USB_OTG_MODIFY_REG32( &pdev->regs.DREGS->DCFG, 0, dcfg.d32);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Connect device (enable internal pull-up)
|
||||
* @param pdev: device instance
|
||||
* @retval : None
|
||||
*/
|
||||
void DCD_DevConnect (USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
#ifndef USE_OTG_MODE
|
||||
USB_OTG_DCTL_TypeDef dctl;
|
||||
dctl.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DCTL);
|
||||
/* Connect device */
|
||||
dctl.b.sftdiscon = 0;
|
||||
USB_OTG_WRITE_REG32(&pdev->regs.DREGS->DCTL, dctl.d32);
|
||||
USB_OTG_BSP_mDelay(3);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disconnect device (disable internal pull-up)
|
||||
* @param pdev: device instance
|
||||
* @retval : None
|
||||
*/
|
||||
void DCD_DevDisconnect (USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
#ifndef USE_OTG_MODE
|
||||
USB_OTG_DCTL_TypeDef dctl;
|
||||
dctl.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DCTL);
|
||||
/* Disconnect device for 3ms */
|
||||
dctl.b.sftdiscon = 1;
|
||||
USB_OTG_WRITE_REG32(&pdev->regs.DREGS->DCTL, dctl.d32);
|
||||
USB_OTG_BSP_mDelay(3);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief returns the EP Status
|
||||
* @param pdev : Selected device
|
||||
* epnum : endpoint address
|
||||
* @retval : EP status
|
||||
*/
|
||||
|
||||
uint32_t DCD_GetEPStatus(USB_OTG_CORE_HANDLE *pdev ,uint8_t epnum)
|
||||
{
|
||||
USB_OTG_EP *ep;
|
||||
uint32_t Status = 0;
|
||||
|
||||
if ((0x80 & epnum) == 0x80)
|
||||
{
|
||||
ep = &pdev->dev.in_ep[epnum & 0x7F];
|
||||
}
|
||||
else
|
||||
{
|
||||
ep = &pdev->dev.out_ep[epnum];
|
||||
}
|
||||
|
||||
Status = USB_OTG_GetEPStatus(pdev ,ep);
|
||||
|
||||
/* Return the current status */
|
||||
return Status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the EP Status
|
||||
* @param pdev : Selected device
|
||||
* Status : new Status
|
||||
* epnum : EP address
|
||||
* @retval : None
|
||||
*/
|
||||
void DCD_SetEPStatus (USB_OTG_CORE_HANDLE *pdev , uint8_t epnum , uint32_t Status)
|
||||
{
|
||||
USB_OTG_EP *ep;
|
||||
|
||||
if ((0x80 & epnum) == 0x80)
|
||||
{
|
||||
ep = &pdev->dev.in_ep[epnum & 0x7F];
|
||||
}
|
||||
else
|
||||
{
|
||||
ep = &pdev->dev.out_ep[epnum];
|
||||
}
|
||||
|
||||
USB_OTG_SetEPStatus(pdev ,ep , Status);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,886 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file usb_dcd_int.c
|
||||
* @author MCD Application Team
|
||||
* @version V2.0.0
|
||||
* @date 22-July-2011
|
||||
* @brief Peripheral Device interrupt subroutines
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "usb_dcd_int.h"
|
||||
/** @addtogroup USB_OTG_DRIVER
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USB_DCD_INT
|
||||
* @brief This file contains the interrupt subroutines for the Device mode.
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_DCD_INT_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_DCD_INT_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/** @defgroup USB_DCD_INT_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_DCD_INT_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_DCD_INT_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
/* static functions */
|
||||
static uint32_t DCD_ReadDevInEP (USB_OTG_CORE_HANDLE *pdev, uint8_t epnum);
|
||||
|
||||
/* Interrupt Handlers */
|
||||
static uint32_t DCD_HandleInEP_ISR(USB_OTG_CORE_HANDLE *pdev);
|
||||
static uint32_t DCD_HandleOutEP_ISR(USB_OTG_CORE_HANDLE *pdev);
|
||||
static uint32_t DCD_HandleSof_ISR(USB_OTG_CORE_HANDLE *pdev);
|
||||
|
||||
static uint32_t DCD_HandleRxStatusQueueLevel_ISR(USB_OTG_CORE_HANDLE *pdev);
|
||||
static uint32_t DCD_WriteEmptyTxFifo(USB_OTG_CORE_HANDLE *pdev , uint32_t epnum);
|
||||
|
||||
static uint32_t DCD_HandleUsbReset_ISR(USB_OTG_CORE_HANDLE *pdev);
|
||||
static uint32_t DCD_HandleEnumDone_ISR(USB_OTG_CORE_HANDLE *pdev);
|
||||
static uint32_t DCD_HandleResume_ISR(USB_OTG_CORE_HANDLE *pdev);
|
||||
static uint32_t DCD_HandleUSBSuspend_ISR(USB_OTG_CORE_HANDLE *pdev);
|
||||
|
||||
static uint32_t DCD_IsoINIncomplete_ISR(USB_OTG_CORE_HANDLE *pdev);
|
||||
static uint32_t DCD_IsoOUTIncomplete_ISR(USB_OTG_CORE_HANDLE *pdev);
|
||||
#ifdef VBUS_SENSING_ENABLED
|
||||
static uint32_t DCD_SessionRequest_ISR(USB_OTG_CORE_HANDLE *pdev);
|
||||
static uint32_t DCD_OTG_ISR(USB_OTG_CORE_HANDLE *pdev);
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_DCD_INT_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED
|
||||
/**
|
||||
* @brief USBD_OTG_EP1OUT_ISR_Handler
|
||||
* handles all USB Interrupts
|
||||
* @param pdev: device instance
|
||||
* @retval status
|
||||
*/
|
||||
uint32_t USBD_OTG_EP1OUT_ISR_Handler (USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
|
||||
USB_OTG_DOEPINTn_TypeDef doepint;
|
||||
USB_OTG_DEPXFRSIZ_TypeDef deptsiz;
|
||||
|
||||
doepint.d32 = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[1]->DOEPINT);
|
||||
doepint.d32&= USB_OTG_READ_REG32(&pdev->regs.DREGS->DOUTEP1MSK);
|
||||
|
||||
/* Transfer complete */
|
||||
if ( doepint.b.xfercompl )
|
||||
{
|
||||
/* Clear the bit in DOEPINTn for this interrupt */
|
||||
CLEAR_OUT_EP_INTR(1, xfercompl);
|
||||
if (pdev->cfg.dma_enable == 1)
|
||||
{
|
||||
deptsiz.d32 = USB_OTG_READ_REG32(&(pdev->regs.OUTEP_REGS[1]->DOEPTSIZ));
|
||||
/*ToDo : handle more than one single MPS size packet */
|
||||
pdev->dev.out_ep[1].xfer_count = pdev->dev.out_ep[1].maxpacket - \
|
||||
deptsiz.b.xfersize;
|
||||
}
|
||||
/* Inform upper layer: data ready */
|
||||
/* RX COMPLETE */
|
||||
USBD_DCD_INT_fops->DataOutStage(pdev , 1);
|
||||
|
||||
}
|
||||
|
||||
/* Endpoint disable */
|
||||
if ( doepint.b.epdisabled )
|
||||
{
|
||||
/* Clear the bit in DOEPINTn for this interrupt */
|
||||
CLEAR_OUT_EP_INTR(1, epdisabled);
|
||||
}
|
||||
/* AHB Error */
|
||||
if ( doepint.b.ahberr )
|
||||
{
|
||||
CLEAR_OUT_EP_INTR(1, ahberr);
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USBD_OTG_EP1IN_ISR_Handler
|
||||
* handles all USB Interrupts
|
||||
* @param pdev: device instance
|
||||
* @retval status
|
||||
*/
|
||||
uint32_t USBD_OTG_EP1IN_ISR_Handler (USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
|
||||
USB_OTG_DIEPINTn_TypeDef diepint;
|
||||
uint32_t fifoemptymsk, msk, emp;
|
||||
|
||||
msk = USB_OTG_READ_REG32(&pdev->regs.DREGS->DINEP1MSK);
|
||||
emp = USB_OTG_READ_REG32(&pdev->regs.DREGS->DIEPEMPMSK);
|
||||
msk |= ((emp >> 1 ) & 0x1) << 7;
|
||||
diepint.d32 = USB_OTG_READ_REG32(&pdev->regs.INEP_REGS[1]->DIEPINT) & msk;
|
||||
|
||||
if ( diepint.b.xfercompl )
|
||||
{
|
||||
fifoemptymsk = 0x1 << 1;
|
||||
USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DIEPEMPMSK, fifoemptymsk, 0);
|
||||
CLEAR_IN_EP_INTR(1, xfercompl);
|
||||
/* TX COMPLETE */
|
||||
USBD_DCD_INT_fops->DataInStage(pdev , 1);
|
||||
}
|
||||
if ( diepint.b.ahberr )
|
||||
{
|
||||
CLEAR_IN_EP_INTR(1, ahberr);
|
||||
}
|
||||
if ( diepint.b.epdisabled )
|
||||
{
|
||||
CLEAR_IN_EP_INTR(1, epdisabled);
|
||||
}
|
||||
if ( diepint.b.timeout )
|
||||
{
|
||||
CLEAR_IN_EP_INTR(1, timeout);
|
||||
}
|
||||
if (diepint.b.intktxfemp)
|
||||
{
|
||||
CLEAR_IN_EP_INTR(1, intktxfemp);
|
||||
}
|
||||
if (diepint.b.intknepmis)
|
||||
{
|
||||
CLEAR_IN_EP_INTR(1, intknepmis);
|
||||
}
|
||||
if (diepint.b.inepnakeff)
|
||||
{
|
||||
CLEAR_IN_EP_INTR(1, inepnakeff);
|
||||
}
|
||||
if (diepint.b.emptyintr)
|
||||
{
|
||||
DCD_WriteEmptyTxFifo(pdev , 1);
|
||||
CLEAR_IN_EP_INTR(1, emptyintr);
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief STM32_USBF_OTG_ISR_Handler
|
||||
* handles all USB Interrupts
|
||||
* @param pdev: device instance
|
||||
* @retval status
|
||||
*/
|
||||
uint32_t USBD_OTG_ISR_Handler (USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
USB_OTG_GINTSTS_TypeDef gintr_status;
|
||||
uint32_t retval = 0;
|
||||
|
||||
if (USB_OTG_IsDeviceMode(pdev)) /* ensure that we are in device mode */
|
||||
{
|
||||
gintr_status.d32 = USB_OTG_ReadCoreItr(pdev);
|
||||
if (!gintr_status.d32) /* avoid spurious interrupt */
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (gintr_status.b.outepintr)
|
||||
{
|
||||
retval |= DCD_HandleOutEP_ISR(pdev);
|
||||
}
|
||||
|
||||
if (gintr_status.b.inepint)
|
||||
{
|
||||
retval |= DCD_HandleInEP_ISR(pdev);
|
||||
}
|
||||
|
||||
if (gintr_status.b.modemismatch)
|
||||
{
|
||||
USB_OTG_GINTSTS_TypeDef gintsts;
|
||||
|
||||
/* Clear interrupt */
|
||||
gintsts.d32 = 0;
|
||||
gintsts.b.modemismatch = 1;
|
||||
USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32);
|
||||
}
|
||||
|
||||
if (gintr_status.b.wkupintr)
|
||||
{
|
||||
retval |= DCD_HandleResume_ISR(pdev);
|
||||
}
|
||||
|
||||
if (gintr_status.b.usbsuspend)
|
||||
{
|
||||
retval |= DCD_HandleUSBSuspend_ISR(pdev);
|
||||
}
|
||||
if (gintr_status.b.sofintr)
|
||||
{
|
||||
retval |= DCD_HandleSof_ISR(pdev);
|
||||
|
||||
}
|
||||
|
||||
if (gintr_status.b.rxstsqlvl)
|
||||
{
|
||||
retval |= DCD_HandleRxStatusQueueLevel_ISR(pdev);
|
||||
|
||||
}
|
||||
|
||||
if (gintr_status.b.usbreset)
|
||||
{
|
||||
retval |= DCD_HandleUsbReset_ISR(pdev);
|
||||
|
||||
}
|
||||
if (gintr_status.b.enumdone)
|
||||
{
|
||||
retval |= DCD_HandleEnumDone_ISR(pdev);
|
||||
}
|
||||
|
||||
if (gintr_status.b.incomplisoin)
|
||||
{
|
||||
retval |= DCD_IsoINIncomplete_ISR(pdev);
|
||||
}
|
||||
|
||||
if (gintr_status.b.incomplisoout)
|
||||
{
|
||||
retval |= DCD_IsoOUTIncomplete_ISR(pdev);
|
||||
}
|
||||
#ifdef VBUS_SENSING_ENABLED
|
||||
if (gintr_status.b.sessreqintr)
|
||||
{
|
||||
retval |= DCD_SessionRequest_ISR(pdev);
|
||||
}
|
||||
|
||||
if (gintr_status.b.otgintr)
|
||||
{
|
||||
retval |= DCD_OTG_ISR(pdev);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
return retval;
|
||||
}
|
||||
|
||||
#ifdef VBUS_SENSING_ENABLED
|
||||
/**
|
||||
* @brief DCD_SessionRequest_ISR
|
||||
* Indicates that the USB_OTG controller has detected a connection
|
||||
* @param pdev: device instance
|
||||
* @retval status
|
||||
*/
|
||||
static uint32_t DCD_SessionRequest_ISR(USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
USB_OTG_GINTSTS_TypeDef gintsts;
|
||||
USBD_DCD_INT_fops->DevConnected (pdev);
|
||||
|
||||
/* Clear interrupt */
|
||||
gintsts.d32 = 0;
|
||||
gintsts.b.sessreqintr = 1;
|
||||
USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GINTSTS, gintsts.d32);
|
||||
return 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DCD_OTG_ISR
|
||||
* Indicates that the USB_OTG controller has detected an OTG event:
|
||||
* used to detect the end of session i.e. disconnection
|
||||
* @param pdev: device instance
|
||||
* @retval status
|
||||
*/
|
||||
static uint32_t DCD_OTG_ISR(USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
|
||||
USB_OTG_GOTGINT_TypeDef gotgint;
|
||||
|
||||
gotgint.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GOTGINT);
|
||||
|
||||
if (gotgint.b.sesenddet)
|
||||
{
|
||||
USBD_DCD_INT_fops->DevDisconnected (pdev);
|
||||
}
|
||||
/* Clear OTG interrupt */
|
||||
USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GOTGINT, gotgint.d32);
|
||||
return 1;
|
||||
}
|
||||
#endif
|
||||
/**
|
||||
* @brief DCD_HandleResume_ISR
|
||||
* Indicates that the USB_OTG controller has detected a resume or
|
||||
* remote Wake-up sequence
|
||||
* @param pdev: device instance
|
||||
* @retval status
|
||||
*/
|
||||
static uint32_t DCD_HandleResume_ISR(USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
USB_OTG_GINTSTS_TypeDef gintsts;
|
||||
USB_OTG_DCTL_TypeDef devctl;
|
||||
USB_OTG_PCGCCTL_TypeDef power;
|
||||
|
||||
if(pdev->cfg.low_power)
|
||||
{
|
||||
/* un-gate USB Core clock */
|
||||
power.d32 = USB_OTG_READ_REG32(&pdev->regs.PCGCCTL);
|
||||
power.b.gatehclk = 0;
|
||||
power.b.stoppclk = 0;
|
||||
USB_OTG_WRITE_REG32(pdev->regs.PCGCCTL, power.d32);
|
||||
}
|
||||
|
||||
/* Clear the Remote Wake-up Signaling */
|
||||
devctl.d32 = 0;
|
||||
devctl.b.rmtwkupsig = 1;
|
||||
USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DCTL, devctl.d32, 0);
|
||||
|
||||
/* Inform upper layer by the Resume Event */
|
||||
USBD_DCD_INT_fops->Resume (pdev);
|
||||
|
||||
/* Clear interrupt */
|
||||
gintsts.d32 = 0;
|
||||
gintsts.b.wkupintr = 1;
|
||||
USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GINTSTS, gintsts.d32);
|
||||
return 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USB_OTG_HandleUSBSuspend_ISR
|
||||
* Indicates that SUSPEND state has been detected on the USB
|
||||
* @param pdev: device instance
|
||||
* @retval status
|
||||
*/
|
||||
static uint32_t DCD_HandleUSBSuspend_ISR(USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
USB_OTG_GINTSTS_TypeDef gintsts;
|
||||
USB_OTG_PCGCCTL_TypeDef power;
|
||||
USB_OTG_DSTS_TypeDef dsts;
|
||||
|
||||
USBD_DCD_INT_fops->Suspend (pdev);
|
||||
|
||||
dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS);
|
||||
|
||||
/* Clear interrupt */
|
||||
gintsts.d32 = 0;
|
||||
gintsts.b.usbsuspend = 1;
|
||||
USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32);
|
||||
|
||||
if((pdev->cfg.low_power) && (dsts.b.suspsts == 1))
|
||||
{
|
||||
/* switch-off the clocks */
|
||||
power.d32 = 0;
|
||||
power.b.stoppclk = 1;
|
||||
USB_OTG_MODIFY_REG32(pdev->regs.PCGCCTL, 0, power.d32);
|
||||
|
||||
power.b.gatehclk = 1;
|
||||
USB_OTG_MODIFY_REG32(pdev->regs.PCGCCTL, 0, power.d32);
|
||||
|
||||
/* Request to enter Sleep mode after exit from current ISR */
|
||||
SCB->SCR |= (SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk);
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DCD_HandleInEP_ISR
|
||||
* Indicates that an IN EP has a pending Interrupt
|
||||
* @param pdev: device instance
|
||||
* @retval status
|
||||
*/
|
||||
static uint32_t DCD_HandleInEP_ISR(USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
USB_OTG_DIEPINTn_TypeDef diepint;
|
||||
|
||||
uint32_t ep_intr;
|
||||
uint32_t epnum = 0;
|
||||
uint32_t fifoemptymsk;
|
||||
diepint.d32 = 0;
|
||||
ep_intr = USB_OTG_ReadDevAllInEPItr(pdev);
|
||||
|
||||
while ( ep_intr )
|
||||
{
|
||||
if (ep_intr&0x1) /* In ITR */
|
||||
{
|
||||
diepint.d32 = DCD_ReadDevInEP(pdev , epnum); /* Get In ITR status */
|
||||
if ( diepint.b.xfercompl )
|
||||
{
|
||||
fifoemptymsk = 0x1 << epnum;
|
||||
USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DIEPEMPMSK, fifoemptymsk, 0);
|
||||
CLEAR_IN_EP_INTR(epnum, xfercompl);
|
||||
/* TX COMPLETE */
|
||||
USBD_DCD_INT_fops->DataInStage(pdev , epnum);
|
||||
|
||||
if (pdev->cfg.dma_enable == 1)
|
||||
{
|
||||
if((epnum == 0) && (pdev->dev.device_state == USB_OTG_EP0_STATUS_IN))
|
||||
{
|
||||
/* prepare to rx more setup packets */
|
||||
USB_OTG_EP0_OutStart(pdev);
|
||||
}
|
||||
}
|
||||
}
|
||||
if ( diepint.b.ahberr )
|
||||
{
|
||||
CLEAR_IN_EP_INTR(epnum, ahberr);
|
||||
}
|
||||
if ( diepint.b.timeout )
|
||||
{
|
||||
CLEAR_IN_EP_INTR(epnum, timeout);
|
||||
}
|
||||
if (diepint.b.intktxfemp)
|
||||
{
|
||||
CLEAR_IN_EP_INTR(epnum, intktxfemp);
|
||||
}
|
||||
if (diepint.b.intknepmis)
|
||||
{
|
||||
CLEAR_IN_EP_INTR(epnum, intknepmis);
|
||||
}
|
||||
if (diepint.b.inepnakeff)
|
||||
{
|
||||
CLEAR_IN_EP_INTR(epnum, inepnakeff);
|
||||
}
|
||||
if ( diepint.b.epdisabled )
|
||||
{
|
||||
CLEAR_IN_EP_INTR(epnum, epdisabled);
|
||||
}
|
||||
if (diepint.b.emptyintr)
|
||||
{
|
||||
|
||||
DCD_WriteEmptyTxFifo(pdev , epnum);
|
||||
|
||||
CLEAR_IN_EP_INTR(epnum, emptyintr);
|
||||
}
|
||||
}
|
||||
epnum++;
|
||||
ep_intr >>= 1;
|
||||
}
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DCD_HandleOutEP_ISR
|
||||
* Indicates that an OUT EP has a pending Interrupt
|
||||
* @param pdev: device instance
|
||||
* @retval status
|
||||
*/
|
||||
static uint32_t DCD_HandleOutEP_ISR(USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
uint32_t ep_intr;
|
||||
USB_OTG_DOEPINTn_TypeDef doepint;
|
||||
USB_OTG_DEPXFRSIZ_TypeDef deptsiz;
|
||||
uint32_t epnum = 0;
|
||||
|
||||
doepint.d32 = 0;
|
||||
|
||||
/* Read in the device interrupt bits */
|
||||
ep_intr = USB_OTG_ReadDevAllOutEp_itr(pdev);
|
||||
|
||||
while ( ep_intr )
|
||||
{
|
||||
if (ep_intr&0x1)
|
||||
{
|
||||
|
||||
doepint.d32 = USB_OTG_ReadDevOutEP_itr(pdev, epnum);
|
||||
|
||||
/* Transfer complete */
|
||||
if ( doepint.b.xfercompl )
|
||||
{
|
||||
/* Clear the bit in DOEPINTn for this interrupt */
|
||||
CLEAR_OUT_EP_INTR(epnum, xfercompl);
|
||||
if (pdev->cfg.dma_enable == 1)
|
||||
{
|
||||
deptsiz.d32 = USB_OTG_READ_REG32(&(pdev->regs.OUTEP_REGS[epnum]->DOEPTSIZ));
|
||||
/*ToDo : handle more than one single MPS size packet */
|
||||
pdev->dev.out_ep[epnum].xfer_count = pdev->dev.out_ep[epnum].maxpacket - \
|
||||
deptsiz.b.xfersize;
|
||||
}
|
||||
/* Inform upper layer: data ready */
|
||||
/* RX COMPLETE */
|
||||
USBD_DCD_INT_fops->DataOutStage(pdev , epnum);
|
||||
|
||||
if (pdev->cfg.dma_enable == 1)
|
||||
{
|
||||
if((epnum == 0) && (pdev->dev.device_state == USB_OTG_EP0_STATUS_OUT))
|
||||
{
|
||||
/* prepare to rx more setup packets */
|
||||
USB_OTG_EP0_OutStart(pdev);
|
||||
}
|
||||
}
|
||||
}
|
||||
/* Endpoint disable */
|
||||
if ( doepint.b.epdisabled )
|
||||
{
|
||||
/* Clear the bit in DOEPINTn for this interrupt */
|
||||
CLEAR_OUT_EP_INTR(epnum, epdisabled);
|
||||
}
|
||||
/* AHB Error */
|
||||
if ( doepint.b.ahberr )
|
||||
{
|
||||
CLEAR_OUT_EP_INTR(epnum, ahberr);
|
||||
}
|
||||
/* Setup Phase Done (control EPs) */
|
||||
if ( doepint.b.setup )
|
||||
{
|
||||
|
||||
/* inform the upper layer that a setup packet is available */
|
||||
/* SETUP COMPLETE */
|
||||
USBD_DCD_INT_fops->SetupStage(pdev);
|
||||
CLEAR_OUT_EP_INTR(epnum, setup);
|
||||
}
|
||||
}
|
||||
epnum++;
|
||||
ep_intr >>= 1;
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DCD_HandleSof_ISR
|
||||
* Handles the SOF Interrupts
|
||||
* @param pdev: device instance
|
||||
* @retval status
|
||||
*/
|
||||
static uint32_t DCD_HandleSof_ISR(USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
USB_OTG_GINTSTS_TypeDef GINTSTS;
|
||||
|
||||
|
||||
USBD_DCD_INT_fops->SOF(pdev);
|
||||
|
||||
/* Clear interrupt */
|
||||
GINTSTS.d32 = 0;
|
||||
GINTSTS.b.sofintr = 1;
|
||||
USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GINTSTS, GINTSTS.d32);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DCD_HandleRxStatusQueueLevel_ISR
|
||||
* Handles the Rx Status Queue Level Interrupt
|
||||
* @param pdev: device instance
|
||||
* @retval status
|
||||
*/
|
||||
static uint32_t DCD_HandleRxStatusQueueLevel_ISR(USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
USB_OTG_GINTMSK_TypeDef int_mask;
|
||||
USB_OTG_DRXSTS_TypeDef status;
|
||||
USB_OTG_EP *ep;
|
||||
|
||||
/* Disable the Rx Status Queue Level interrupt */
|
||||
int_mask.d32 = 0;
|
||||
int_mask.b.rxstsqlvl = 1;
|
||||
USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, int_mask.d32, 0);
|
||||
|
||||
/* Get the Status from the top of the FIFO */
|
||||
status.d32 = USB_OTG_READ_REG32( &pdev->regs.GREGS->GRXSTSP );
|
||||
|
||||
ep = &pdev->dev.out_ep[status.b.epnum];
|
||||
|
||||
switch (status.b.pktsts)
|
||||
{
|
||||
case STS_GOUT_NAK:
|
||||
break;
|
||||
case STS_DATA_UPDT:
|
||||
if (status.b.bcnt)
|
||||
{
|
||||
USB_OTG_ReadPacket(pdev,ep->xfer_buff, status.b.bcnt);
|
||||
ep->xfer_buff += status.b.bcnt;
|
||||
ep->xfer_count += status.b.bcnt;
|
||||
}
|
||||
break;
|
||||
case STS_XFER_COMP:
|
||||
break;
|
||||
case STS_SETUP_COMP:
|
||||
break;
|
||||
case STS_SETUP_UPDT:
|
||||
/* Copy the setup packet received in FIFO into the setup buffer in RAM */
|
||||
USB_OTG_ReadPacket(pdev , pdev->dev.setup_packet, 8);
|
||||
ep->xfer_count += status.b.bcnt;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
/* Enable the Rx Status Queue Level interrupt */
|
||||
USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, 0, int_mask.d32);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DCD_WriteEmptyTxFifo
|
||||
* check FIFO for the next packet to be loaded
|
||||
* @param pdev: device instance
|
||||
* @retval status
|
||||
*/
|
||||
static uint32_t DCD_WriteEmptyTxFifo(USB_OTG_CORE_HANDLE *pdev, uint32_t epnum)
|
||||
{
|
||||
USB_OTG_DTXFSTSn_TypeDef txstatus;
|
||||
USB_OTG_EP *ep;
|
||||
uint32_t len = 0;
|
||||
uint32_t len32b;
|
||||
txstatus.d32 = 0;
|
||||
|
||||
ep = &pdev->dev.in_ep[epnum];
|
||||
|
||||
len = ep->xfer_len - ep->xfer_count;
|
||||
|
||||
if (len > ep->maxpacket)
|
||||
{
|
||||
len = ep->maxpacket;
|
||||
}
|
||||
|
||||
len32b = (len + 3) / 4;
|
||||
txstatus.d32 = USB_OTG_READ_REG32( &pdev->regs.INEP_REGS[epnum]->DTXFSTS);
|
||||
|
||||
|
||||
|
||||
while (txstatus.b.txfspcavail > len32b &&
|
||||
ep->xfer_count < ep->xfer_len &&
|
||||
ep->xfer_len != 0)
|
||||
{
|
||||
/* Write the FIFO */
|
||||
len = ep->xfer_len - ep->xfer_count;
|
||||
|
||||
if (len > ep->maxpacket)
|
||||
{
|
||||
len = ep->maxpacket;
|
||||
}
|
||||
len32b = (len + 3) / 4;
|
||||
|
||||
USB_OTG_WritePacket (pdev , ep->xfer_buff, epnum, len);
|
||||
|
||||
ep->xfer_buff += len;
|
||||
ep->xfer_count += len;
|
||||
|
||||
txstatus.d32 = USB_OTG_READ_REG32(&pdev->regs.INEP_REGS[epnum]->DTXFSTS);
|
||||
}
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DCD_HandleUsbReset_ISR
|
||||
* This interrupt occurs when a USB Reset is detected
|
||||
* @param pdev: device instance
|
||||
* @retval status
|
||||
*/
|
||||
static uint32_t DCD_HandleUsbReset_ISR(USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
USB_OTG_DAINT_TypeDef daintmsk;
|
||||
USB_OTG_DOEPMSK_TypeDef doepmsk;
|
||||
USB_OTG_DIEPMSK_TypeDef diepmsk;
|
||||
USB_OTG_DCFG_TypeDef dcfg;
|
||||
USB_OTG_DCTL_TypeDef dctl;
|
||||
USB_OTG_GINTSTS_TypeDef gintsts;
|
||||
uint32_t i;
|
||||
|
||||
dctl.d32 = 0;
|
||||
daintmsk.d32 = 0;
|
||||
doepmsk.d32 = 0;
|
||||
diepmsk.d32 = 0;
|
||||
dcfg.d32 = 0;
|
||||
gintsts.d32 = 0;
|
||||
|
||||
/* Clear the Remote Wake-up Signaling */
|
||||
dctl.b.rmtwkupsig = 1;
|
||||
USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DCTL, dctl.d32, 0 );
|
||||
|
||||
/* Flush the Tx FIFO */
|
||||
USB_OTG_FlushTxFifo(pdev , 0 );
|
||||
|
||||
for (i = 0; i < pdev->cfg.dev_endpoints ; i++)
|
||||
{
|
||||
USB_OTG_WRITE_REG32( &pdev->regs.INEP_REGS[i]->DIEPINT, 0xFF);
|
||||
USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[i]->DOEPINT, 0xFF);
|
||||
}
|
||||
USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINT, 0xFFFFFFFF );
|
||||
|
||||
daintmsk.ep.in = 1;
|
||||
daintmsk.ep.out = 1;
|
||||
USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINTMSK, daintmsk.d32 );
|
||||
|
||||
doepmsk.b.setup = 1;
|
||||
doepmsk.b.xfercompl = 1;
|
||||
doepmsk.b.ahberr = 1;
|
||||
doepmsk.b.epdisabled = 1;
|
||||
USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DOEPMSK, doepmsk.d32 );
|
||||
#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED
|
||||
USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DOUTEP1MSK, doepmsk.d32 );
|
||||
#endif
|
||||
diepmsk.b.xfercompl = 1;
|
||||
diepmsk.b.timeout = 1;
|
||||
diepmsk.b.epdisabled = 1;
|
||||
diepmsk.b.ahberr = 1;
|
||||
diepmsk.b.intknepmis = 1;
|
||||
USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DIEPMSK, diepmsk.d32 );
|
||||
#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED
|
||||
USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DINEP1MSK, diepmsk.d32 );
|
||||
#endif
|
||||
/* Reset Device Address */
|
||||
dcfg.d32 = USB_OTG_READ_REG32( &pdev->regs.DREGS->DCFG);
|
||||
dcfg.b.devaddr = 0;
|
||||
USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DCFG, dcfg.d32);
|
||||
|
||||
|
||||
/* setup EP0 to receive SETUP packets */
|
||||
USB_OTG_EP0_OutStart(pdev);
|
||||
|
||||
/* Clear interrupt */
|
||||
gintsts.d32 = 0;
|
||||
gintsts.b.usbreset = 1;
|
||||
USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GINTSTS, gintsts.d32);
|
||||
|
||||
/*Reset internal state machine */
|
||||
USBD_DCD_INT_fops->Reset(pdev);
|
||||
return 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DCD_HandleEnumDone_ISR
|
||||
* Read the device status register and set the device speed
|
||||
* @param pdev: device instance
|
||||
* @retval status
|
||||
*/
|
||||
static uint32_t DCD_HandleEnumDone_ISR(USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
USB_OTG_GINTSTS_TypeDef gintsts;
|
||||
USB_OTG_GUSBCFG_TypeDef gusbcfg;
|
||||
|
||||
USB_OTG_EP0Activate(pdev);
|
||||
|
||||
/* Set USB turn-around time based on device speed and PHY interface. */
|
||||
gusbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG);
|
||||
|
||||
/* Full or High speed */
|
||||
if ( USB_OTG_GetDeviceSpeed(pdev) == USB_SPEED_HIGH)
|
||||
{
|
||||
pdev->cfg.speed = USB_OTG_SPEED_HIGH;
|
||||
pdev->cfg.mps = USB_OTG_HS_MAX_PACKET_SIZE ;
|
||||
gusbcfg.b.usbtrdtim = 9;
|
||||
}
|
||||
else
|
||||
{
|
||||
pdev->cfg.speed = USB_OTG_SPEED_FULL;
|
||||
pdev->cfg.mps = USB_OTG_FS_MAX_PACKET_SIZE ;
|
||||
gusbcfg.b.usbtrdtim = 5;
|
||||
}
|
||||
|
||||
USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GUSBCFG, gusbcfg.d32);
|
||||
|
||||
/* Clear interrupt */
|
||||
gintsts.d32 = 0;
|
||||
gintsts.b.enumdone = 1;
|
||||
USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GINTSTS, gintsts.d32 );
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief DCD_IsoINIncomplete_ISR
|
||||
* handle the ISO IN incomplete interrupt
|
||||
* @param pdev: device instance
|
||||
* @retval status
|
||||
*/
|
||||
static uint32_t DCD_IsoINIncomplete_ISR(USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
USB_OTG_GINTSTS_TypeDef gintsts;
|
||||
|
||||
gintsts.d32 = 0;
|
||||
|
||||
USBD_DCD_INT_fops->IsoINIncomplete (pdev);
|
||||
|
||||
/* Clear interrupt */
|
||||
gintsts.b.incomplisoin = 1;
|
||||
USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DCD_IsoOUTIncomplete_ISR
|
||||
* handle the ISO OUT incomplete interrupt
|
||||
* @param pdev: device instance
|
||||
* @retval status
|
||||
*/
|
||||
static uint32_t DCD_IsoOUTIncomplete_ISR(USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
USB_OTG_GINTSTS_TypeDef gintsts;
|
||||
|
||||
gintsts.d32 = 0;
|
||||
|
||||
USBD_DCD_INT_fops->IsoOUTIncomplete (pdev);
|
||||
|
||||
/* Clear interrupt */
|
||||
gintsts.b.incomplisoout = 1;
|
||||
USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32);
|
||||
return 1;
|
||||
}
|
||||
/**
|
||||
* @brief DCD_ReadDevInEP
|
||||
* Reads ep flags
|
||||
* @param pdev: device instance
|
||||
* @retval status
|
||||
*/
|
||||
static uint32_t DCD_ReadDevInEP (USB_OTG_CORE_HANDLE *pdev, uint8_t epnum)
|
||||
{
|
||||
uint32_t v, msk, emp;
|
||||
msk = USB_OTG_READ_REG32(&pdev->regs.DREGS->DIEPMSK);
|
||||
emp = USB_OTG_READ_REG32(&pdev->regs.DREGS->DIEPEMPMSK);
|
||||
msk |= ((emp >> epnum) & 0x1) << 7;
|
||||
v = USB_OTG_READ_REG32(&pdev->regs.INEP_REGS[epnum]->DIEPINT) & msk;
|
||||
return v;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,256 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file usb_hcd.c
|
||||
* @author MCD Application Team
|
||||
* @version V2.0.0
|
||||
* @date 22-July-2011
|
||||
* @brief Host Interface Layer
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "usb_core.h"
|
||||
#include "usb_hcd.h"
|
||||
#include "usb_conf.h"
|
||||
#include "usb_bsp.h"
|
||||
|
||||
|
||||
/** @addtogroup USB_OTG_DRIVER
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USB_HCD
|
||||
* @brief This file is the interface between EFSL ans Host mass-storage class
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_HCD_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_HCD_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/** @defgroup USB_HCD_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_HCD_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_HCD_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_HCD_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief HCD_Init
|
||||
* Initialize the HOST portion of the driver.
|
||||
* @param pdev: Selected device
|
||||
* @param base_address: OTG base address
|
||||
* @retval Status
|
||||
*/
|
||||
uint32_t HCD_Init(USB_OTG_CORE_HANDLE *pdev ,
|
||||
USB_OTG_CORE_ID_TypeDef coreID)
|
||||
{
|
||||
uint8_t i = 0;
|
||||
pdev->host.ConnSts = 0;
|
||||
|
||||
for (i= 0; i< USB_OTG_MAX_TX_FIFOS; i++)
|
||||
{
|
||||
pdev->host.ErrCnt[i] = 0;
|
||||
pdev->host.XferCnt[i] = 0;
|
||||
pdev->host.HC_Status[i] = HC_IDLE;
|
||||
}
|
||||
pdev->host.hc[0].max_packet = 8;
|
||||
|
||||
USB_OTG_SelectCore(pdev, coreID);
|
||||
#ifndef DUAL_ROLE_MODE_ENABLED
|
||||
USB_OTG_DisableGlobalInt(pdev);
|
||||
USB_OTG_CoreInit(pdev);
|
||||
|
||||
/* Force Host Mode*/
|
||||
USB_OTG_SetCurrentMode(pdev , HOST_MODE);
|
||||
USB_OTG_CoreInitHost(pdev);
|
||||
USB_OTG_EnableGlobalInt(pdev);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief HCD_GetCurrentSpeed
|
||||
* Get Current device Speed.
|
||||
* @param pdev : Selected device
|
||||
* @retval Status
|
||||
*/
|
||||
|
||||
uint32_t HCD_GetCurrentSpeed (USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
USB_OTG_HPRT0_TypeDef HPRT0;
|
||||
HPRT0.d32 = USB_OTG_READ_REG32(pdev->regs.HPRT0);
|
||||
|
||||
return HPRT0.b.prtspd;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief HCD_ResetPort
|
||||
* Issues the reset command to device
|
||||
* @param pdev : Selected device
|
||||
* @retval Status
|
||||
*/
|
||||
uint32_t HCD_ResetPort(USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
/*
|
||||
Before starting to drive a USB reset, the application waits for the OTG
|
||||
interrupt triggered by the debounce done bit (DBCDNE bit in OTG_FS_GOTGINT),
|
||||
which indicates that the bus is stable again after the electrical debounce
|
||||
caused by the attachment of a pull-up resistor on DP (FS) or DM (LS).
|
||||
*/
|
||||
|
||||
USB_OTG_ResetPort(pdev);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief HCD_IsDeviceConnected
|
||||
* Check if the device is connected.
|
||||
* @param pdev : Selected device
|
||||
* @retval Device connection status. 1 -> connected and 0 -> disconnected
|
||||
*
|
||||
*/
|
||||
uint32_t HCD_IsDeviceConnected(USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
return (pdev->host.ConnSts);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief HCD_GetCurrentFrame
|
||||
* This function returns the frame number for sof packet
|
||||
* @param pdev : Selected device
|
||||
* @retval Frame number
|
||||
*
|
||||
*/
|
||||
uint32_t HCD_GetCurrentFrame (USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
return (USB_OTG_READ_REG32(&pdev->regs.HREGS->HFNUM) & 0xFFFF) ;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief HCD_GetURB_State
|
||||
* This function returns the last URBstate
|
||||
* @param pdev: Selected device
|
||||
* @retval URB_STATE
|
||||
*
|
||||
*/
|
||||
URB_STATE HCD_GetURB_State (USB_OTG_CORE_HANDLE *pdev , uint8_t ch_num)
|
||||
{
|
||||
return pdev->host.URB_State[ch_num] ;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief HCD_GetXferCnt
|
||||
* This function returns the last URBstate
|
||||
* @param pdev: Selected device
|
||||
* @retval No. of data bytes transferred
|
||||
*
|
||||
*/
|
||||
uint32_t HCD_GetXferCnt (USB_OTG_CORE_HANDLE *pdev, uint8_t ch_num)
|
||||
{
|
||||
return pdev->host.XferCnt[ch_num] ;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief HCD_GetHCState
|
||||
* This function returns the HC Status
|
||||
* @param pdev: Selected device
|
||||
* @retval HC_STATUS
|
||||
*
|
||||
*/
|
||||
HC_STATUS HCD_GetHCState (USB_OTG_CORE_HANDLE *pdev , uint8_t ch_num)
|
||||
{
|
||||
return pdev->host.HC_Status[ch_num] ;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief HCD_HC_Init
|
||||
* This function prepare a HC and start a transfer
|
||||
* @param pdev: Selected device
|
||||
* @param hc_num: Channel number
|
||||
* @retval status
|
||||
*/
|
||||
uint32_t HCD_HC_Init (USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num)
|
||||
{
|
||||
return USB_OTG_HC_Init(pdev, hc_num);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief HCD_SubmitRequest
|
||||
* This function prepare a HC and start a transfer
|
||||
* @param pdev: Selected device
|
||||
* @param hc_num: Channel number
|
||||
* @retval status
|
||||
*/
|
||||
uint32_t HCD_SubmitRequest (USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num)
|
||||
{
|
||||
|
||||
pdev->host.URB_State[hc_num] = URB_IDLE;
|
||||
pdev->host.hc[hc_num].xfer_count = 0 ;
|
||||
return USB_OTG_HC_StartXfer(pdev, hc_num);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,832 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file usb_hcd_int.c
|
||||
* @author MCD Application Team
|
||||
* @version V2.0.0
|
||||
* @date 22-July-2011
|
||||
* @brief Host driver interrupt subroutines
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "usb_core.h"
|
||||
#include "usb_defines.h"
|
||||
#include "usb_hcd_int.h"
|
||||
|
||||
#if defined (__CC_ARM) /*!< ARM Compiler */
|
||||
#pragma O0
|
||||
#elif defined ( __ICCARM__ ) /*!< IAR Compiler */
|
||||
#pragma O0
|
||||
#elif defined (__GNUC__) /*!< GNU Compiler */
|
||||
#pragma GCC optimize ("O0")
|
||||
#elif defined (__TASKING__) /*!< TASKING Compiler */
|
||||
#pragma optimize=0
|
||||
|
||||
#endif /* __CC_ARM */
|
||||
|
||||
/** @addtogroup USB_OTG_DRIVER
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USB_HCD_INT
|
||||
* @brief This file contains the interrupt subroutines for the Host mode.
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_HCD_INT_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_HCD_INT_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/** @defgroup USB_HCD_INT_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_HCD_INT_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_HCD_INT_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
static uint32_t USB_OTG_USBH_handle_sof_ISR(USB_OTG_CORE_HANDLE *pdev);
|
||||
static uint32_t USB_OTG_USBH_handle_port_ISR(USB_OTG_CORE_HANDLE *pdev);
|
||||
static uint32_t USB_OTG_USBH_handle_hc_ISR (USB_OTG_CORE_HANDLE *pdev);
|
||||
static uint32_t USB_OTG_USBH_handle_hc_n_In_ISR (USB_OTG_CORE_HANDLE *pdev ,
|
||||
uint32_t num);
|
||||
static uint32_t USB_OTG_USBH_handle_hc_n_Out_ISR (USB_OTG_CORE_HANDLE *pdev ,
|
||||
uint32_t num);
|
||||
static uint32_t USB_OTG_USBH_handle_rx_qlvl_ISR (USB_OTG_CORE_HANDLE *pdev);
|
||||
static uint32_t USB_OTG_USBH_handle_nptxfempty_ISR (USB_OTG_CORE_HANDLE *pdev);
|
||||
static uint32_t USB_OTG_USBH_handle_ptxfempty_ISR (USB_OTG_CORE_HANDLE *pdev);
|
||||
static uint32_t USB_OTG_USBH_handle_Disconnect_ISR (USB_OTG_CORE_HANDLE *pdev);
|
||||
static uint32_t USB_OTG_USBH_handle_IncompletePeriodicXfer_ISR (USB_OTG_CORE_HANDLE *pdev);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_HCD_INT_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief HOST_Handle_ISR
|
||||
* This function handles all USB Host Interrupts
|
||||
* @param pdev: Selected device
|
||||
* @retval status
|
||||
*/
|
||||
|
||||
uint32_t USBH_OTG_ISR_Handler (USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
USB_OTG_GINTSTS_TypeDef gintsts;
|
||||
uint32_t retval = 0;
|
||||
|
||||
gintsts.d32 = 0;
|
||||
|
||||
/* Check if HOST Mode */
|
||||
if (USB_OTG_IsHostMode(pdev))
|
||||
{
|
||||
gintsts.d32 = USB_OTG_ReadCoreItr(pdev);
|
||||
if (!gintsts.d32)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (gintsts.b.sofintr)
|
||||
{
|
||||
retval |= USB_OTG_USBH_handle_sof_ISR (pdev);
|
||||
}
|
||||
|
||||
if (gintsts.b.rxstsqlvl)
|
||||
{
|
||||
retval |= USB_OTG_USBH_handle_rx_qlvl_ISR (pdev);
|
||||
}
|
||||
|
||||
if (gintsts.b.nptxfempty)
|
||||
{
|
||||
retval |= USB_OTG_USBH_handle_nptxfempty_ISR (pdev);
|
||||
}
|
||||
|
||||
if (gintsts.b.ptxfempty)
|
||||
{
|
||||
retval |= USB_OTG_USBH_handle_ptxfempty_ISR (pdev);
|
||||
}
|
||||
|
||||
if (gintsts.b.hcintr)
|
||||
{
|
||||
retval |= USB_OTG_USBH_handle_hc_ISR (pdev);
|
||||
}
|
||||
|
||||
if (gintsts.b.portintr)
|
||||
{
|
||||
retval |= USB_OTG_USBH_handle_port_ISR (pdev);
|
||||
}
|
||||
|
||||
if (gintsts.b.disconnect)
|
||||
{
|
||||
retval |= USB_OTG_USBH_handle_Disconnect_ISR (pdev);
|
||||
|
||||
}
|
||||
|
||||
if (gintsts.b.incomplisoout)
|
||||
{
|
||||
retval |= USB_OTG_USBH_handle_IncompletePeriodicXfer_ISR (pdev);
|
||||
}
|
||||
|
||||
|
||||
}
|
||||
return retval;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USB_OTG_USBH_handle_hc_ISR
|
||||
* This function indicates that one or more host channels has a pending
|
||||
* @param pdev: Selected device
|
||||
* @retval status
|
||||
*/
|
||||
static uint32_t USB_OTG_USBH_handle_hc_ISR (USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
USB_OTG_HAINT_TypeDef haint;
|
||||
USB_OTG_HCCHAR_TypeDef hcchar;
|
||||
uint32_t i = 0;
|
||||
uint32_t retval = 0;
|
||||
|
||||
/* Clear appropriate bits in HCINTn to clear the interrupt bit in
|
||||
* GINTSTS */
|
||||
|
||||
haint.d32 = USB_OTG_ReadHostAllChannels_intr(pdev);
|
||||
|
||||
for (i = 0; i < pdev->cfg.host_channels ; i++)
|
||||
{
|
||||
if (haint.b.chint & (1 << i))
|
||||
{
|
||||
hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[i]->HCCHAR);
|
||||
|
||||
if (hcchar.b.epdir)
|
||||
{
|
||||
retval |= USB_OTG_USBH_handle_hc_n_In_ISR (pdev, i);
|
||||
}
|
||||
else
|
||||
{
|
||||
retval |= USB_OTG_USBH_handle_hc_n_Out_ISR (pdev, i);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USB_OTG_otg_hcd_handle_sof_intr
|
||||
* Handles the start-of-frame interrupt in host mode.
|
||||
* @param pdev: Selected device
|
||||
* @retval status
|
||||
*/
|
||||
static uint32_t USB_OTG_USBH_handle_sof_ISR (USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
USB_OTG_GINTSTS_TypeDef gintsts;
|
||||
|
||||
|
||||
gintsts.d32 = 0;
|
||||
/* Clear interrupt */
|
||||
gintsts.b.sofintr = 1;
|
||||
USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USB_OTG_USBH_handle_Disconnect_ISR
|
||||
* Handles disconnect event.
|
||||
* @param pdev: Selected device
|
||||
* @retval status
|
||||
*/
|
||||
static uint32_t USB_OTG_USBH_handle_Disconnect_ISR (USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
USB_OTG_GINTSTS_TypeDef gintsts;
|
||||
|
||||
pdev->host.ConnSts = 0;
|
||||
gintsts.d32 = 0;
|
||||
|
||||
pdev->host.port_cb->Disconnect(pdev);
|
||||
|
||||
/* Clear interrupt */
|
||||
gintsts.b.disconnect = 1;
|
||||
USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USB_OTG_USBH_handle_nptxfempty_ISR
|
||||
* Handles non periodic tx fifo empty.
|
||||
* @param pdev: Selected device
|
||||
* @retval status
|
||||
*/
|
||||
static uint32_t USB_OTG_USBH_handle_nptxfempty_ISR (USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
USB_OTG_GINTMSK_TypeDef intmsk;
|
||||
USB_OTG_HNPTXSTS_TypeDef hnptxsts;
|
||||
uint16_t len_words , len;
|
||||
|
||||
hnptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->HNPTXSTS);
|
||||
|
||||
len_words = (pdev->host.hc[hnptxsts.b.chnum].xfer_len + 3) / 4;
|
||||
|
||||
while ((hnptxsts.b.nptxfspcavail > len_words)&&
|
||||
(pdev->host.hc[hnptxsts.b.chnum].xfer_len != 0))
|
||||
{
|
||||
|
||||
len = hnptxsts.b.nptxfspcavail * 4;
|
||||
|
||||
if (len > pdev->host.hc[hnptxsts.b.chnum].xfer_len)
|
||||
{
|
||||
/* Last packet */
|
||||
len = pdev->host.hc[hnptxsts.b.chnum].xfer_len;
|
||||
|
||||
intmsk.d32 = 0;
|
||||
intmsk.b.nptxfempty = 1;
|
||||
USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, intmsk.d32, 0);
|
||||
}
|
||||
|
||||
len_words = (pdev->host.hc[hnptxsts.b.chnum].xfer_len + 3) / 4;
|
||||
|
||||
USB_OTG_WritePacket (pdev , pdev->host.hc[hnptxsts.b.chnum].xfer_buff, hnptxsts.b.chnum, len);
|
||||
|
||||
pdev->host.hc[hnptxsts.b.chnum].xfer_buff += len;
|
||||
pdev->host.hc[hnptxsts.b.chnum].xfer_len -= len;
|
||||
pdev->host.hc[hnptxsts.b.chnum].xfer_count += len;
|
||||
|
||||
hnptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->HNPTXSTS);
|
||||
}
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USB_OTG_USBH_handle_ptxfempty_ISR
|
||||
* Handles periodic tx fifo empty
|
||||
* @param pdev: Selected device
|
||||
* @retval status
|
||||
*/
|
||||
static uint32_t USB_OTG_USBH_handle_ptxfempty_ISR (USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
USB_OTG_GINTMSK_TypeDef intmsk;
|
||||
USB_OTG_HPTXSTS_TypeDef hptxsts;
|
||||
uint16_t len_words , len;
|
||||
|
||||
hptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HPTXSTS);
|
||||
|
||||
len_words = (pdev->host.hc[hptxsts.b.chnum].xfer_len + 3) / 4;
|
||||
|
||||
while ((hptxsts.b.ptxfspcavail > len_words)&&
|
||||
(pdev->host.hc[hptxsts.b.chnum].xfer_len != 0))
|
||||
{
|
||||
|
||||
len = hptxsts.b.ptxfspcavail * 4;
|
||||
|
||||
if (len > pdev->host.hc[hptxsts.b.chnum].xfer_len)
|
||||
{
|
||||
len = pdev->host.hc[hptxsts.b.chnum].xfer_len;
|
||||
/* Last packet */
|
||||
intmsk.d32 = 0;
|
||||
intmsk.b.ptxfempty = 1;
|
||||
USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, intmsk.d32, 0);
|
||||
}
|
||||
|
||||
len_words = (pdev->host.hc[hptxsts.b.chnum].xfer_len + 3) / 4;
|
||||
|
||||
USB_OTG_WritePacket (pdev , pdev->host.hc[hptxsts.b.chnum].xfer_buff, hptxsts.b.chnum, len);
|
||||
|
||||
pdev->host.hc[hptxsts.b.chnum].xfer_buff += len;
|
||||
pdev->host.hc[hptxsts.b.chnum].xfer_len -= len;
|
||||
pdev->host.hc[hptxsts.b.chnum].xfer_count += len;
|
||||
|
||||
hptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HPTXSTS);
|
||||
}
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USB_OTG_USBH_handle_port_ISR
|
||||
* This function determines which interrupt conditions have occurred
|
||||
* @param pdev: Selected device
|
||||
* @retval status
|
||||
*/
|
||||
static uint32_t USB_OTG_USBH_handle_port_ISR (USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
USB_OTG_HPRT0_TypeDef hprt0;
|
||||
USB_OTG_HPRT0_TypeDef hprt0_dup;
|
||||
USB_OTG_HCFG_TypeDef hcfg;
|
||||
uint32_t do_reset = 0;
|
||||
uint32_t retval = 0;
|
||||
|
||||
hcfg.d32 = 0;
|
||||
hprt0.d32 = 0;
|
||||
hprt0_dup.d32 = 0;
|
||||
|
||||
hprt0.d32 = USB_OTG_READ_REG32(pdev->regs.HPRT0);
|
||||
hprt0_dup.d32 = USB_OTG_READ_REG32(pdev->regs.HPRT0);
|
||||
|
||||
/* Clear the interrupt bits in GINTSTS */
|
||||
|
||||
hprt0_dup.b.prtena = 0;
|
||||
hprt0_dup.b.prtconndet = 0;
|
||||
hprt0_dup.b.prtenchng = 0;
|
||||
hprt0_dup.b.prtovrcurrchng = 0;
|
||||
|
||||
/* Port Connect Detected */
|
||||
if (hprt0.b.prtconndet)
|
||||
{
|
||||
pdev->host.port_cb->Connect(pdev);
|
||||
hprt0_dup.b.prtconndet = 1;
|
||||
do_reset = 1;
|
||||
retval |= 1;
|
||||
}
|
||||
|
||||
/* Port Enable Changed */
|
||||
if (hprt0.b.prtenchng)
|
||||
{
|
||||
hprt0_dup.b.prtenchng = 1;
|
||||
if (hprt0.b.prtena == 1)
|
||||
{
|
||||
pdev->host.ConnSts = 1;
|
||||
|
||||
if ((hprt0.b.prtspd == HPRT0_PRTSPD_LOW_SPEED) ||
|
||||
(hprt0.b.prtspd == HPRT0_PRTSPD_FULL_SPEED))
|
||||
{
|
||||
|
||||
hcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HCFG);
|
||||
|
||||
if (hprt0.b.prtspd == HPRT0_PRTSPD_LOW_SPEED)
|
||||
{
|
||||
USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HFIR, 6000 );
|
||||
if (hcfg.b.fslspclksel != HCFG_6_MHZ)
|
||||
{
|
||||
if(pdev->cfg.coreID == USB_OTG_FS_CORE_ID)
|
||||
{
|
||||
USB_OTG_InitFSLSPClkSel(pdev ,HCFG_6_MHZ );
|
||||
}
|
||||
do_reset = 1;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
|
||||
USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HFIR, 48000 );
|
||||
if (hcfg.b.fslspclksel != HCFG_48_MHZ)
|
||||
{
|
||||
USB_OTG_InitFSLSPClkSel(pdev ,HCFG_48_MHZ );
|
||||
do_reset = 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
do_reset = 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
/* Overcurrent Change Interrupt */
|
||||
if (hprt0.b.prtovrcurrchng)
|
||||
{
|
||||
hprt0_dup.b.prtovrcurrchng = 1;
|
||||
retval |= 1;
|
||||
}
|
||||
if (do_reset)
|
||||
{
|
||||
USB_OTG_ResetPort(pdev);
|
||||
|
||||
}
|
||||
/* Clear Port Interrupts */
|
||||
USB_OTG_WRITE_REG32(pdev->regs.HPRT0, hprt0_dup.d32);
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USB_OTG_USBH_handle_hc_n_Out_ISR
|
||||
* Handles interrupt for a specific Host Channel
|
||||
* @param pdev: Selected device
|
||||
* @param hc_num: Channel number
|
||||
* @retval status
|
||||
*/
|
||||
uint32_t USB_OTG_USBH_handle_hc_n_Out_ISR (USB_OTG_CORE_HANDLE *pdev , uint32_t num)
|
||||
{
|
||||
|
||||
USB_OTG_HCINTn_TypeDef hcint;
|
||||
USB_OTG_HCGINTMSK_TypeDef hcintmsk;
|
||||
USB_OTG_HC_REGS *hcreg;
|
||||
USB_OTG_HCCHAR_TypeDef hcchar;
|
||||
|
||||
hcreg = pdev->regs.HC_REGS[num];
|
||||
hcint.d32 = USB_OTG_READ_REG32(&hcreg->HCINT);
|
||||
hcintmsk.d32 = USB_OTG_READ_REG32(&hcreg->HCGINTMSK);
|
||||
hcint.d32 = hcint.d32 & hcintmsk.d32;
|
||||
|
||||
hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[num]->HCCHAR);
|
||||
|
||||
if (hcint.b.ahberr)
|
||||
{
|
||||
CLEAR_HC_INT(hcreg ,ahberr);
|
||||
UNMASK_HOST_INT_CHH (num);
|
||||
}
|
||||
else if (hcint.b.ack)
|
||||
{
|
||||
CLEAR_HC_INT(hcreg , ack);
|
||||
}
|
||||
|
||||
else if (hcint.b.xfercompl)
|
||||
{
|
||||
pdev->host.ErrCnt[num] = 0;
|
||||
UNMASK_HOST_INT_CHH (num);
|
||||
USB_OTG_HC_Halt(pdev, num);
|
||||
CLEAR_HC_INT(hcreg , xfercompl);
|
||||
pdev->host.HC_Status[num] = HC_XFRC;
|
||||
}
|
||||
|
||||
else if (hcint.b.stall)
|
||||
{
|
||||
CLEAR_HC_INT(hcreg , stall);
|
||||
UNMASK_HOST_INT_CHH (num);
|
||||
USB_OTG_HC_Halt(pdev, num);
|
||||
pdev->host.HC_Status[num] = HC_STALL;
|
||||
}
|
||||
|
||||
else if (hcint.b.nak)
|
||||
{
|
||||
pdev->host.ErrCnt[num] = 0;
|
||||
UNMASK_HOST_INT_CHH (num);
|
||||
USB_OTG_HC_Halt(pdev, num);
|
||||
CLEAR_HC_INT(hcreg , nak);
|
||||
pdev->host.HC_Status[num] = HC_NAK;
|
||||
}
|
||||
|
||||
else if (hcint.b.xacterr)
|
||||
{
|
||||
UNMASK_HOST_INT_CHH (num);
|
||||
USB_OTG_HC_Halt(pdev, num);
|
||||
pdev->host.ErrCnt[num] ++;
|
||||
pdev->host.HC_Status[num] = HC_XACTERR;
|
||||
CLEAR_HC_INT(hcreg , xacterr);
|
||||
}
|
||||
else if (hcint.b.nyet)
|
||||
{
|
||||
pdev->host.ErrCnt[num] = 0;
|
||||
UNMASK_HOST_INT_CHH (num);
|
||||
USB_OTG_HC_Halt(pdev, num);
|
||||
CLEAR_HC_INT(hcreg , nyet);
|
||||
pdev->host.HC_Status[num] = HC_NYET;
|
||||
}
|
||||
else if (hcint.b.datatglerr)
|
||||
{
|
||||
|
||||
UNMASK_HOST_INT_CHH (num);
|
||||
USB_OTG_HC_Halt(pdev, num);
|
||||
CLEAR_HC_INT(hcreg , nak);
|
||||
pdev->host.HC_Status[num] = HC_DATATGLERR;
|
||||
|
||||
CLEAR_HC_INT(hcreg , datatglerr);
|
||||
}
|
||||
else if (hcint.b.chhltd)
|
||||
{
|
||||
MASK_HOST_INT_CHH (num);
|
||||
|
||||
if(pdev->host.HC_Status[num] == HC_XFRC)
|
||||
{
|
||||
pdev->host.URB_State[num] = URB_DONE;
|
||||
|
||||
if (hcchar.b.eptype == EP_TYPE_BULK)
|
||||
{
|
||||
pdev->host.hc[num].toggle_out ^= 1;
|
||||
}
|
||||
}
|
||||
else if(pdev->host.HC_Status[num] == HC_NAK)
|
||||
{
|
||||
pdev->host.URB_State[num] = URB_NOTREADY;
|
||||
}
|
||||
else if(pdev->host.HC_Status[num] == HC_NYET)
|
||||
{
|
||||
if(pdev->host.hc[num].do_ping == 1)
|
||||
{
|
||||
USB_OTG_HC_DoPing(pdev, num);
|
||||
}
|
||||
pdev->host.URB_State[num] = URB_NOTREADY;
|
||||
}
|
||||
else if(pdev->host.HC_Status[num] == HC_STALL)
|
||||
{
|
||||
pdev->host.URB_State[num] = URB_STALL;
|
||||
}
|
||||
else if(pdev->host.HC_Status[num] == HC_XACTERR)
|
||||
{
|
||||
if (pdev->host.ErrCnt[num] == 3)
|
||||
{
|
||||
pdev->host.URB_State[num] = URB_ERROR;
|
||||
pdev->host.ErrCnt[num] = 0;
|
||||
}
|
||||
}
|
||||
CLEAR_HC_INT(hcreg , chhltd);
|
||||
}
|
||||
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USB_OTG_USBH_handle_hc_n_In_ISR
|
||||
* Handles interrupt for a specific Host Channel
|
||||
* @param pdev: Selected device
|
||||
* @param hc_num: Channel number
|
||||
* @retval status
|
||||
*/
|
||||
uint32_t USB_OTG_USBH_handle_hc_n_In_ISR (USB_OTG_CORE_HANDLE *pdev , uint32_t num)
|
||||
{
|
||||
USB_OTG_HCINTn_TypeDef hcint;
|
||||
USB_OTG_HCGINTMSK_TypeDef hcintmsk;
|
||||
USB_OTG_HCCHAR_TypeDef hcchar;
|
||||
USB_OTG_HCTSIZn_TypeDef hctsiz;
|
||||
USB_OTG_HC_REGS *hcreg;
|
||||
|
||||
|
||||
hcreg = pdev->regs.HC_REGS[num];
|
||||
hcint.d32 = USB_OTG_READ_REG32(&hcreg->HCINT);
|
||||
hcintmsk.d32 = USB_OTG_READ_REG32(&hcreg->HCGINTMSK);
|
||||
hcint.d32 = hcint.d32 & hcintmsk.d32;
|
||||
hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[num]->HCCHAR);
|
||||
hcintmsk.d32 = 0;
|
||||
|
||||
|
||||
if (hcint.b.ahberr)
|
||||
{
|
||||
CLEAR_HC_INT(hcreg ,ahberr);
|
||||
UNMASK_HOST_INT_CHH (num);
|
||||
}
|
||||
else if (hcint.b.ack)
|
||||
{
|
||||
CLEAR_HC_INT(hcreg ,ack);
|
||||
}
|
||||
|
||||
else if (hcint.b.stall)
|
||||
{
|
||||
UNMASK_HOST_INT_CHH (num);
|
||||
pdev->host.HC_Status[num] = HC_STALL;
|
||||
CLEAR_HC_INT(hcreg , nak); /* Clear the NAK Condition */
|
||||
CLEAR_HC_INT(hcreg , stall); /* Clear the STALL Condition */
|
||||
hcint.b.nak = 0; /* NOTE: When there is a 'stall', reset also nak,
|
||||
else, the pdev->host.HC_Status = HC_STALL
|
||||
will be overwritten by 'nak' in code below */
|
||||
USB_OTG_HC_Halt(pdev, num);
|
||||
}
|
||||
else if (hcint.b.datatglerr)
|
||||
{
|
||||
|
||||
UNMASK_HOST_INT_CHH (num);
|
||||
USB_OTG_HC_Halt(pdev, num);
|
||||
CLEAR_HC_INT(hcreg , nak);
|
||||
pdev->host.HC_Status[num] = HC_DATATGLERR;
|
||||
CLEAR_HC_INT(hcreg , datatglerr);
|
||||
}
|
||||
|
||||
if (hcint.b.frmovrun)
|
||||
{
|
||||
UNMASK_HOST_INT_CHH (num);
|
||||
USB_OTG_HC_Halt(pdev, num);
|
||||
CLEAR_HC_INT(hcreg ,frmovrun);
|
||||
}
|
||||
|
||||
else if (hcint.b.xfercompl)
|
||||
{
|
||||
|
||||
if (pdev->cfg.dma_enable == 1)
|
||||
{
|
||||
hctsiz.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[num]->HCTSIZ);
|
||||
pdev->host.XferCnt[num] = pdev->host.hc[num].xfer_len - hctsiz.b.xfersize;
|
||||
}
|
||||
|
||||
pdev->host.HC_Status[num] = HC_XFRC;
|
||||
pdev->host.ErrCnt [num]= 0;
|
||||
CLEAR_HC_INT(hcreg , xfercompl);
|
||||
|
||||
if ((hcchar.b.eptype == EP_TYPE_CTRL)||
|
||||
(hcchar.b.eptype == EP_TYPE_BULK))
|
||||
{
|
||||
UNMASK_HOST_INT_CHH (num);
|
||||
USB_OTG_HC_Halt(pdev, num);
|
||||
CLEAR_HC_INT(hcreg , nak);
|
||||
pdev->host.hc[num].toggle_in ^= 1;
|
||||
|
||||
}
|
||||
else if(hcchar.b.eptype == EP_TYPE_INTR)
|
||||
{
|
||||
hcchar.b.oddfrm = 1;
|
||||
USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[num]->HCCHAR, hcchar.d32);
|
||||
pdev->host.URB_State[num] = URB_DONE;
|
||||
}
|
||||
|
||||
}
|
||||
else if (hcint.b.chhltd)
|
||||
{
|
||||
MASK_HOST_INT_CHH (num);
|
||||
|
||||
if(pdev->host.HC_Status[num] == HC_XFRC)
|
||||
{
|
||||
pdev->host.URB_State[num] = URB_DONE;
|
||||
}
|
||||
|
||||
else if (pdev->host.HC_Status[num] == HC_STALL)
|
||||
{
|
||||
pdev->host.URB_State[num] = URB_STALL;
|
||||
}
|
||||
|
||||
else if((pdev->host.HC_Status[num] == HC_XACTERR) ||
|
||||
(pdev->host.HC_Status[num] == HC_DATATGLERR))
|
||||
{
|
||||
pdev->host.ErrCnt[num] = 0;
|
||||
pdev->host.URB_State[num] = URB_ERROR;
|
||||
|
||||
}
|
||||
else if(hcchar.b.eptype == EP_TYPE_INTR)
|
||||
{
|
||||
pdev->host.hc[num].toggle_in ^= 1;
|
||||
}
|
||||
|
||||
CLEAR_HC_INT(hcreg , chhltd);
|
||||
|
||||
}
|
||||
else if (hcint.b.xacterr)
|
||||
{
|
||||
UNMASK_HOST_INT_CHH (num);
|
||||
pdev->host.ErrCnt[num] ++;
|
||||
pdev->host.HC_Status[num] = HC_XACTERR;
|
||||
USB_OTG_HC_Halt(pdev, num);
|
||||
CLEAR_HC_INT(hcreg , xacterr);
|
||||
|
||||
}
|
||||
else if (hcint.b.nak)
|
||||
{
|
||||
if(hcchar.b.eptype == EP_TYPE_INTR)
|
||||
{
|
||||
UNMASK_HOST_INT_CHH (num);
|
||||
USB_OTG_HC_Halt(pdev, num);
|
||||
CLEAR_HC_INT(hcreg , nak);
|
||||
}
|
||||
else if ((hcchar.b.eptype == EP_TYPE_CTRL)||
|
||||
(hcchar.b.eptype == EP_TYPE_BULK))
|
||||
{
|
||||
/* re-activate the channel */
|
||||
hcchar.b.chen = 1;
|
||||
hcchar.b.chdis = 0;
|
||||
USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[num]->HCCHAR, hcchar.d32);
|
||||
}
|
||||
pdev->host.HC_Status[num] = HC_NAK;
|
||||
}
|
||||
|
||||
|
||||
return 1;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USB_OTG_USBH_handle_rx_qlvl_ISR
|
||||
* Handles the Rx Status Queue Level Interrupt
|
||||
* @param pdev: Selected device
|
||||
* @retval status
|
||||
*/
|
||||
|
||||
static uint32_t USB_OTG_USBH_handle_rx_qlvl_ISR (USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
USB_OTG_GRXFSTS_TypeDef grxsts;
|
||||
USB_OTG_GINTMSK_TypeDef intmsk;
|
||||
USB_OTG_HCTSIZn_TypeDef hctsiz;
|
||||
USB_OTG_HCCHAR_TypeDef hcchar;
|
||||
__IO uint8_t channelnum =0;
|
||||
uint32_t count;
|
||||
|
||||
/* Disable the Rx Status Queue Level interrupt */
|
||||
intmsk.d32 = 0;
|
||||
intmsk.b.rxstsqlvl = 1;
|
||||
USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, intmsk.d32, 0);
|
||||
|
||||
grxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GRXSTSP);
|
||||
channelnum = grxsts.b.chnum;
|
||||
hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[channelnum]->HCCHAR);
|
||||
|
||||
switch (grxsts.b.pktsts)
|
||||
{
|
||||
case GRXSTS_PKTSTS_IN:
|
||||
/* Read the data into the host buffer. */
|
||||
if ((grxsts.b.bcnt > 0) && (pdev->host.hc[channelnum].xfer_buff != (void *)0))
|
||||
{
|
||||
|
||||
USB_OTG_ReadPacket(pdev, pdev->host.hc[channelnum].xfer_buff, grxsts.b.bcnt);
|
||||
/*manage multiple Xfer */
|
||||
pdev->host.hc[grxsts.b.chnum].xfer_buff += grxsts.b.bcnt;
|
||||
pdev->host.hc[grxsts.b.chnum].xfer_count += grxsts.b.bcnt;
|
||||
|
||||
|
||||
count = pdev->host.hc[channelnum].xfer_count;
|
||||
pdev->host.XferCnt[channelnum] = count;
|
||||
|
||||
hctsiz.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[channelnum]->HCTSIZ);
|
||||
if(hctsiz.b.pktcnt > 0)
|
||||
{
|
||||
/* re-activate the channel when more packets are expected */
|
||||
hcchar.b.chen = 1;
|
||||
hcchar.b.chdis = 0;
|
||||
USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[channelnum]->HCCHAR, hcchar.d32);
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
||||
case GRXSTS_PKTSTS_IN_XFER_COMP:
|
||||
|
||||
case GRXSTS_PKTSTS_DATA_TOGGLE_ERR:
|
||||
case GRXSTS_PKTSTS_CH_HALTED:
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
/* Enable the Rx Status Queue Level interrupt */
|
||||
intmsk.b.rxstsqlvl = 1;
|
||||
USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GINTMSK, 0, intmsk.d32);
|
||||
return 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USB_OTG_USBH_handle_IncompletePeriodicXfer_ISR
|
||||
* Handles the incomplete Periodic transfer Interrupt
|
||||
* @param pdev: Selected device
|
||||
* @retval status
|
||||
*/
|
||||
static uint32_t USB_OTG_USBH_handle_IncompletePeriodicXfer_ISR (USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
|
||||
USB_OTG_GINTSTS_TypeDef gintsts;
|
||||
USB_OTG_HCCHAR_TypeDef hcchar;
|
||||
|
||||
|
||||
|
||||
|
||||
hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[0]->HCCHAR);
|
||||
hcchar.b.chen = 1;
|
||||
hcchar.b.chdis = 1;
|
||||
USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[0]->HCCHAR, hcchar.d32);
|
||||
|
||||
gintsts.d32 = 0;
|
||||
/* Clear interrupt */
|
||||
gintsts.b.incomplisoout = 1;
|
||||
USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
|
||||
|
|
@ -0,0 +1,175 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file usb_otg.c
|
||||
* @author MCD Application Team
|
||||
* @version V2.0.0
|
||||
* @date 22-July-2011
|
||||
* @brief OTG Core Layer
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "usb_defines.h"
|
||||
#include "usb_regs.h"
|
||||
#include "usb_core.h"
|
||||
#include "usb_otg.h"
|
||||
|
||||
/** @addtogroup USB_OTG_DRIVER
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USB_OTG
|
||||
* @brief This file is the interface between EFSL ans Host mass-storage class
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_OTG_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_OTG_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/** @defgroup USB_OTG_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_OTG_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_OTG_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
static uint32_t USB_OTG_Read_itr(USB_OTG_CORE_HANDLE *pdev);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_OTG_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/* OTG Interrupt Handler */
|
||||
|
||||
|
||||
/**
|
||||
* @brief STM32_USBO_OTG_ISR_Handler
|
||||
*
|
||||
* @param None
|
||||
* @retval : None
|
||||
*/
|
||||
uint32_t STM32_USBO_OTG_ISR_Handler(USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
uint32_t retval = 0;
|
||||
USB_OTG_GINTSTS_TypeDef gintsts ;
|
||||
gintsts.d32 = 0;
|
||||
|
||||
gintsts.d32 = USB_OTG_Read_itr(pdev);
|
||||
if (gintsts.d32 == 0)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
if (gintsts.b.otgintr)
|
||||
{
|
||||
retval |= 1;//USB_OTG_HandleOTG_ISR(pdev);
|
||||
}
|
||||
if (gintsts.b.conidstschng)
|
||||
{
|
||||
retval |= 2;//USB_OTG_HandleConnectorIDStatusChange_ISR(pdev);
|
||||
}
|
||||
if (gintsts.b.sessreqintr)
|
||||
{
|
||||
retval |= 3;//USB_OTG_HandleSessionRequest_ISR(pdev);
|
||||
}
|
||||
return retval;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief USB_OTG_Read_itr
|
||||
* returns the Core Interrupt register
|
||||
* @param None
|
||||
* @retval : status
|
||||
*/
|
||||
static uint32_t USB_OTG_Read_itr(USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
USB_OTG_GINTSTS_TypeDef gintsts;
|
||||
USB_OTG_GINTMSK_TypeDef gintmsk;
|
||||
USB_OTG_GINTMSK_TypeDef gintmsk_common;
|
||||
|
||||
|
||||
gintsts.d32 = 0;
|
||||
gintmsk.d32 = 0;
|
||||
gintmsk_common.d32 = 0;
|
||||
|
||||
/* OTG interrupts */
|
||||
gintmsk_common.b.sessreqintr = 1;
|
||||
gintmsk_common.b.conidstschng = 1;
|
||||
gintmsk_common.b.otgintr = 1;
|
||||
|
||||
gintsts.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GINTSTS);
|
||||
gintmsk.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GINTMSK);
|
||||
return ((gintsts.d32 & gintmsk.d32 ) & gintmsk_common.d32);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief USB_OTG_GetCurrentState
|
||||
* Return current OTG State
|
||||
* @param None
|
||||
* @retval : None
|
||||
*/
|
||||
uint32_t USB_OTG_GetCurrentState (USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
return pdev->otg.OTG_State;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||
Ładowanie…
Reference in New Issue