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Merge pull request #324 from mlu/master 

Added STM32F7 Support
pull/326/head
texane 2015-08-13 22:31:14 +02:00
rodzic 6d3f105d2a 7fbd79eef3
commit c15bb3830f
3 zmienionych plików z 74 dodań i 15 usunięć
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26
gdbserver/gdb-server.c
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@ -383,6 +383,30 @@ static const char* const memory_map_template =
" <memory type=\"rom\" start=\"0x1ffff800\" length=\"0x10\"/>" // option byte area
"</memory-map>";
static const char* const memory_map_template_F7 =
"<?xml version=\"1.0\"?>"
"<!DOCTYPE memory-map PUBLIC \"+//IDN gnu.org//DTD GDB Memory Map V1.0//EN\""
" \"http://sourceware.org/gdb/gdb-memory-map.dtd\">"
"<memory-map>"
" <memory type=\"ram\" start=\"0x00000000\" length=\"0x4000\"/>" // ITCM ram 16kB
" <memory type=\"rom\" start=\"0x00200000\" length=\"0x100000\"/>" // ITCM flash
" <memory type=\"ram\" start=\"0x20000000\" length=\"0x50000\"/>" // sram
" <memory type=\"flash\" start=\"0x08000000\" length=\"0x20000\">" // Sectors 0..3
" <property name=\"blocksize\">0x8000</property>" // 32kB
" </memory>"
" <memory type=\"flash\" start=\"0x08020000\" length=\"0x20000\">" // Sector 4
" <property name=\"blocksize\">0x20000</property>" // 128kB
" </memory>"
" <memory type=\"flash\" start=\"0x08040000\" length=\"0xC0000\">" // Sectors 5..7
" <property name=\"blocksize\">0x40000</property>" // 128kB
" </memory>"
" <memory type=\"ram\" start=\"0x40000000\" length=\"0x1fffffff\"/>" // peripheral regs
" <memory type=\"ram\" start=\"0x60000000\" length=\"0x7fffffff\"/>" // AHB3 Peripherals
" <memory type=\"ram\" start=\"0xe0000000\" length=\"0x1fffffff\"/>" // cortex regs
" <memory type=\"rom\" start=\"0x00100000\" length=\"0xEDC0\"/>" // bootrom
" <memory type=\"rom\" start=\"0x1fff0000\" length=\"0x20\"/>" // option byte area
"</memory-map>";
char* make_memory_map(stlink_t *sl) {
/* This will be freed in serve() */
char* map = malloc(4096);
@ -390,6 +414,8 @@ char* make_memory_map(stlink_t *sl) {
if(sl->chip_id==STM32_CHIPID_F4 || sl->chip_id==STM32_CHIPID_F446) {
strcpy(map, memory_map_template_F4);
} else if(sl->chip_id==STM32_CHIPID_F4 || sl->chip_id==STM32_CHIPID_F7) {
strcpy(map, memory_map_template_F7);
} else if(sl->chip_id==STM32_CHIPID_F4_HD) {
strcpy(map, memory_map_template_F4_HD);
} else if(sl->chip_id==STM32_CHIPID_F2) {

51
src/stlink-common.c
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@ -180,7 +180,7 @@ static inline uint32_t read_flash_cr(stlink_t *sl) {
uint32_t res;
if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) ||(sl->chip_id == STM32_CHIPID_F4_DE) ||
(sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
(sl->chip_id == STM32_CHIPID_F446))
(sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7))
res = stlink_read_debug32(sl, FLASH_F4_CR);
else if (sl->chip_id == STM32_CHIPID_L4)
res = stlink_read_debug32(sl, STM32L4_FLASH_CR);
@ -198,7 +198,7 @@ static inline unsigned int is_flash_locked(stlink_t *sl) {
if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) ||
(sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
(sl->chip_id == STM32_CHIPID_F446))
(sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7))
return cr & (1 << FLASH_F4_CR_LOCK);
else if (sl->chip_id == STM32_CHIPID_L4)
return cr & (1lu << STM32L4_FLASH_CR_LOCK);
@ -214,7 +214,7 @@ static void unlock_flash(stlink_t *sl) {
*/
if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) ||
(sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
(sl->chip_id == STM32_CHIPID_F446)) {
(sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7)) {
stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY1);
stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY2);
} else if (sl->chip_id == STM32_CHIPID_L4) {
@ -244,7 +244,7 @@ static int unlock_flash_if(stlink_t *sl) {
static void lock_flash(stlink_t *sl) {
if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) ||
(sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
(sl->chip_id == STM32_CHIPID_F446)) {
(sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7)) {
const uint32_t n = read_flash_cr(sl) | (1 << FLASH_F4_CR_LOCK);
stlink_write_debug32(sl, FLASH_F4_CR, n);
} else if (sl->chip_id == STM32_CHIPID_L4) {
@ -261,7 +261,7 @@ static void lock_flash(stlink_t *sl) {
static void set_flash_cr_pg(stlink_t *sl) {
if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) ||
(sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
(sl->chip_id == STM32_CHIPID_F446)) {
(sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7)) {
uint32_t x = read_flash_cr(sl);
x |= (1 << FLASH_CR_PG);
stlink_write_debug32(sl, FLASH_F4_CR, x);
@ -280,7 +280,7 @@ static void __attribute__((unused)) clear_flash_cr_pg(stlink_t *sl) {
const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_PG);
if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) ||
(sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
(sl->chip_id == STM32_CHIPID_F446))
(sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7))
stlink_write_debug32(sl, FLASH_F4_CR, n);
else
stlink_write_debug32(sl, FLASH_CR, n);
@ -299,7 +299,7 @@ static void __attribute__((unused)) clear_flash_cr_per(stlink_t *sl) {
static void set_flash_cr_mer(stlink_t *sl) {
if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) ||
(sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
(sl->chip_id == STM32_CHIPID_F446))
(sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7))
stlink_write_debug32(sl, FLASH_F4_CR,
stlink_read_debug32(sl, FLASH_F4_CR) | (1 << FLASH_CR_MER));
else if (sl->chip_id == STM32_CHIPID_L4) {
@ -315,7 +315,7 @@ static void set_flash_cr_mer(stlink_t *sl) {
static void __attribute__((unused)) clear_flash_cr_mer(stlink_t *sl) {
if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) ||
(sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
(sl->chip_id == STM32_CHIPID_F446))
(sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7))
stlink_write_debug32(sl, FLASH_F4_CR,
stlink_read_debug32(sl, FLASH_F4_CR) & ~(1 << FLASH_CR_MER));
else
@ -326,7 +326,7 @@ static void __attribute__((unused)) clear_flash_cr_mer(stlink_t *sl) {
static void set_flash_cr_strt(stlink_t *sl) {
if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) ||
(sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
(sl->chip_id == STM32_CHIPID_F446)) {
(sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7)) {
uint32_t x = read_flash_cr(sl);
x |= (1 << FLASH_F4_CR_STRT);
stlink_write_debug32(sl, FLASH_F4_CR, x);
@ -348,7 +348,7 @@ static inline uint32_t read_flash_sr(stlink_t *sl) {
uint32_t res;
if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) ||
(sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
(sl->chip_id == STM32_CHIPID_F446))
(sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7))
res = stlink_read_debug32(sl, FLASH_F4_SR);
else if (sl->chip_id == STM32_CHIPID_L4)
res = stlink_read_debug32(sl, STM32L4_FLASH_SR);
@ -361,7 +361,7 @@ static inline uint32_t read_flash_sr(stlink_t *sl) {
static inline unsigned int is_flash_busy(stlink_t *sl) {
if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) ||
(sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
(sl->chip_id == STM32_CHIPID_F446))
(sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7))
return read_flash_sr(sl) & (1 << FLASH_F4_SR_BSY);
else if (sl->chip_id == STM32_CHIPID_L4)
return read_flash_sr(sl) & (1 << STM32L4_FLASH_SR_BSY);
@ -1137,7 +1137,7 @@ uint32_t calculate_L4_page(stlink_t *sl, uint32_t flashaddr) {
uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){
if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) ||
(sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
(sl->chip_id == STM32_CHIPID_F446)) {
(sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7)) {
uint32_t sector=calculate_F4_sectornum(flashaddr);
if (sector>= 12) {
sector -= 12;
@ -1159,7 +1159,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr)
{
if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) ||
(sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
(sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_L4)) {
(sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_L4)) {
/* wait for ongoing op to finish */
wait_flash_busy(sl);
@ -1535,6 +1535,23 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) {
0x00, 0x20, 0x02, 0x40 // flash_base: .word 0x40022000
};
static const uint8_t loader_code_stm32f7[] = {
0x08, 0x4b,
0x72, 0xb1,
0x04, 0x68,
0x0c, 0x60,
0xbf, 0xf3, 0x4f, 0x8f, // DSB Memory barrier for in order flash write
0xdc, 0x89,
0x14, 0xf0, 0x01, 0x0f,
0xfb, 0xd1,
0x00, 0xf1, 0x04, 0x00,
0x01, 0xf1, 0x04, 0x01,
0xa2, 0xf1, 0x01, 0x02,
0xef, 0xe7,
0x00, 0xbe, // bkpt #0x00
0x00, 0x3c, 0x02, 0x40,
};
const uint8_t* loader_code;
size_t loader_size;
@ -1561,6 +1578,9 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) {
loader_code = loader_code_stm32f4_lv;
loader_size = sizeof(loader_code_stm32f4_lv);
}
} else if (sl->chip_id == STM32_CHIPID_F7){
loader_code = loader_code_stm32f7;
loader_size = sizeof(loader_code_stm32f7);
} else if (sl->chip_id == STM32_CHIPID_F0 || sl->chip_id == STM32_CHIPID_F04 || sl->chip_id == STM32_CHIPID_F0_CAN || sl->chip_id == STM32_CHIPID_F0_SMALL || sl->chip_id == STM32_CHIPID_F09X) {
loader_code = loader_code_stm32f0;
loader_size = sizeof(loader_code_stm32f0);
@ -1746,6 +1766,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t
(sl->chip_id == STM32_CHIPID_F4_HD) ||
(sl->chip_id == STM32_CHIPID_F411RE) ||
(sl->chip_id == STM32_CHIPID_F446) ||
(sl->chip_id == STM32_CHIPID_F7) ||
(sl->chip_id == STM32_CHIPID_L4)) {
/* todo: check write operation */
@ -2005,7 +2026,7 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons
} else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4 || (sl->chip_id == STM32_CHIPID_F4_DE) ||
sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD || (sl->chip_id == STM32_CHIPID_F411RE) ||
(sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_L4)) {
(sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_L4)) {
size_t count = size / sizeof(uint32_t);
if (size % sizeof(uint32_t)) ++count;
@ -2069,7 +2090,7 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons
} else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4 || (sl->chip_id == STM32_CHIPID_F4_DE) ||
sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD || (sl->chip_id == STM32_CHIPID_F411RE) ||
(sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_L4)) {
(sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_L4)) {
stlink_read_reg(sl, 2, &rr);
if (rr.r[2] != 0) {

12
src/stlink-common.h
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@ -140,6 +140,8 @@ extern "C" {
#define STM32_CHIPID_F0_CAN 0x448
#define STM32_CHIPID_F7 0x449
/*
* 0x436 is actually assigned to some L1 chips that are called "Medium-Plus"
* and some that are called "High". 0x427 is assigned to the other "Medium-
@ -174,6 +176,16 @@ extern "C" {
// These maps are from a combination of the Programming Manuals, and
// also the Reference manuals. (flash size reg is normally in ref man)
static const chip_params_t devices[] = {
{
//RM0385 and DS10916 document was used to find these paramaters
.chip_id = STM32_CHIPID_F7,
.description = "F7 device",
.flash_size_reg = 0x1ff0f442, // section 41.2
.flash_pagesize = 0x800, // No flash pages
.sram_size = 0x50000, // "SRAM" byte size in hex from DS Fig 18
.bootrom_base = 0x00100000, // "System memory" starting address from DS Fig 18
.bootrom_size = 0xEDC0 // "System memory" byte size in hex from DS Fig 18
},
{ // table 2, PM0063
.chip_id = STM32_CHIPID_F1_MEDIUM,
.description = "F1 Medium-density device",