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General Project Update 

- Formatting fixes
- Commented CI build setting for Ubuntu 16.04
- Updated CHANGELOG.md
pull/1140/head
nightwalker-87 2021-04-24 14:16:29 +02:00
rodzic 6993491f90
commit c115ab2e0f
4 zmienionych plików z 323 dodań i 275 usunięć
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210
.github/workflows/c-cpp.yml vendored
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@ -7,98 +7,97 @@ on:
branches: [master, develop, testing]
jobs:
# Linux
# Linux
# job_linux_16_04_64_gcc:
# name: ubuntu-16.04 gcc
# runs-on: ubuntu-16.04
# steps:
# - uses: actions/checkout@v2
# - name: Install dependencies
# run: sudo apt-get install gcc-5 libusb-1.0.0-dev libgtk-3-dev rpm
# - name: make debug
# run: sudo make clean && make debug
# - name: make test
# run: sudo make clean && make test
# - name: make release
# run: sudo make clean && make release
# - name: sudo make install
# run: sudo make clean && sudo make install
# - name: sudo make package
# run: sudo make package
# - name: sudo make uninstall
# run: sudo make uninstall && sudo make clean
job_linux_16_04_64_gcc:
name: ubuntu-16.04 gcc
runs-on: ubuntu-16.04
steps:
- uses: actions/checkout@v2
- name: Install dependencies
run: sudo apt-get install gcc-5 libusb-1.0.0-dev libgtk-3-dev rpm
- name: make debug
run: sudo make clean && make debug
- name: make test
run: sudo make clean && make test
- name: make release
run: sudo make clean && make release
- name: sudo make install
run: sudo make clean && sudo make install
- name: sudo make package
run: sudo make package
- name: sudo make uninstall
run: sudo make uninstall && sudo make clean
# job_linux_16_04_32_gcc:
# name: ubuntu-16.04 gcc 32-bit
# runs-on: ubuntu-16.04
# steps:
# - uses: actions/checkout@v2
# - name: Install dependencies
# run: sudo apt-get install gcc-5 libusb-1.0.0-dev libgtk-3-dev rpm
# - name: Set compiler flags
# run: |
# CFLAGS="$CFLAGS -m32"
# CXXFLAGS="$CXXFLAGS -m32"
# LDFLAGS="$LDFLAGS -m32"
# - name: make debug
# run: sudo make clean && make debug
# - name: make test
# run: sudo make clean && make test
# - name: make release
# run: sudo make clean && make release
# - name: sudo make install
# run: sudo make clean && sudo make install
# - name: sudo make package
# run: sudo make package
# - name: sudo make uninstall
# run: sudo make uninstall && sudo make clean
job_linux_16_04_32_gcc:
name: ubuntu-16.04 gcc 32-bit
runs-on: ubuntu-16.04
steps:
- uses: actions/checkout@v2
- name: Install dependencies
run: sudo apt-get install gcc-5 libusb-1.0.0-dev libgtk-3-dev rpm
- name: Set compiler flags
run: |
CFLAGS="$CFLAGS -m32"
CXXFLAGS="$CXXFLAGS -m32"
LDFLAGS="$LDFLAGS -m32"
- name: make debug
run: sudo make clean && make debug
- name: make test
run: sudo make clean && make test
- name: make release
run: sudo make clean && make release
- name: sudo make install
run: sudo make clean && sudo make install
- name: sudo make package
run: sudo make package
- name: sudo make uninstall
run: sudo make uninstall && sudo make clean
# job_linux_16_04_64_clang:
# name: ubuntu-16.04 clang
# runs-on: ubuntu-16.04
# steps:
# - uses: actions/checkout@v2
# - name: Install dependencies
# run: sudo apt-get install clang-3.5 libusb-1.0.0-dev libgtk-3-dev rpm
# - name: make debug
# run: sudo make clean && make debug
# - name: make test
# run: sudo make clean && make test
# - name: make release
# run: sudo make clean && make release
# - name: sudo make install
# run: sudo make clean && sudo make install
# - name: sudo make package
# run: sudo make package
# - name: sudo make uninstall
# run: sudo make uninstall && sudo make clean
job_linux_16_04_64_clang:
name: ubuntu-16.04 clang
runs-on: ubuntu-16.04
steps:
- uses: actions/checkout@v2
- name: Install dependencies
run: sudo apt-get install clang-3.5 libusb-1.0.0-dev libgtk-3-dev rpm
- name: make debug
run: sudo make clean && make debug
- name: make test
run: sudo make clean && make test
- name: make release
run: sudo make clean && make release
- name: sudo make install
run: sudo make clean && sudo make install
- name: sudo make package
run: sudo make package
- name: sudo make uninstall
run: sudo make uninstall && sudo make clean
job_linux_16_04_32_clang:
name: ubuntu-16.04 clang 32-bit
runs-on: ubuntu-16.04
steps:
- uses: actions/checkout@v2
- name: Install dependencies
run: sudo apt-get install clang-3.5 libusb-1.0.0-dev libgtk-3-dev rpm
- name: Set compiler flags
run: |
CFLAGS="$CFLAGS -m32"
CXXFLAGS="$CXXFLAGS -m32"
LDFLAGS="$LDFLAGS -m32"
- name: make debug
run: sudo make clean && make debug
- name: make test
run: sudo make clean && make test
- name: make release
run: sudo make clean && make release
- name: sudo make install
run: sudo make clean && sudo make install
- name: sudo make package
run: sudo make package
- name: sudo make uninstall
run: sudo make uninstall && sudo make clean
# job_linux_16_04_32_clang:
# name: ubuntu-16.04 clang 32-bit
# runs-on: ubuntu-16.04
# steps:
# - uses: actions/checkout@v2
# - name: Install dependencies
# run: sudo apt-get install clang-3.5 libusb-1.0.0-dev libgtk-3-dev rpm
# - name: Set compiler flags
# run: |
# CFLAGS="$CFLAGS -m32"
# CXXFLAGS="$CXXFLAGS -m32"
# LDFLAGS="$LDFLAGS -m32"
# - name: make debug
# run: sudo make clean && make debug
# - name: make test
# run: sudo make clean && make test
# - name: make release
# run: sudo make clean && make release
# - name: sudo make install
# run: sudo make clean && sudo make install
# - name: sudo make package
# run: sudo make package
# - name: sudo make uninstall
# run: sudo make uninstall && sudo make clean
job_linux_18_04_64_gcc:
name: ubuntu-18.04 gcc
@ -144,7 +143,7 @@ jobs:
run: sudo make package
- name: sudo make uninstall
run: sudo make uninstall && sudo make clean
job_linux_18_04_64_clang:
name: ubuntu-18.04 clang
runs-on: ubuntu-18.04
@ -280,7 +279,7 @@ jobs:
- name: sudo make uninstall
run: sudo make uninstall && sudo make clean
# macOS
# macOS
# job_macos_10_14_64_gcc:
# name: macos-10.14 gcc
@ -411,7 +410,6 @@ jobs:
run: sudo make package
- name: sudo make uninstall
run: sudo make uninstall && sudo make clean
# job_macos_11_gcc:
# name: macos-11.0 gcc
# runs-on: macos-11.0
@ -431,7 +429,6 @@ jobs:
# run: sudo make package
# - name: sudo make uninstall
# run: sudo make uninstall && sudo make clean
# job_macos_11_clang:
# name: macos-11.0 clang
# runs-on: macos-11.0
@ -451,20 +448,19 @@ jobs:
# run: sudo make package
# - name: sudo make uninstall
# run: sudo make uninstall && sudo make clean
# Linux MinGW cross compliation
# job_linux_20_04_cross:
# name: ubuntu-20.04 mingw64
# runs-on: ubuntu-20.04
# steps:
# - uses: actions/checkout@v2
# - name: Install dependencies
# run: sudo apt-get install gcc-10 libusb-1.0.0-dev libgtk-3-dev rpm mingw-w64
# - name: Building Release for Windows (x86-64) ...
# run: sudo mkdir -p build-mingw && cd build-mingw && sudo cmake \
# -DCMAKE_SYSTEM_NAME=Windows \
# -DTOOLCHAIN_PREFIX=x86_64-w64-mingw32 \
# -DCMAKE_TOOLCHAIN_FILE=$PWD/../cmake/modules/set_toolchain.cmake \
# -DCMAKE_INSTALL_PREFIX=$PWD/install $PWD && \
# sudo make && sudo rm -rf build-mingw && cd -
# job_linux_20_04_cross:
# name: ubuntu-20.04 mingw64
# runs-on: ubuntu-20.04
# steps:
# - uses: actions/checkout@v2
# - name: Install dependencies
# run: sudo apt-get install gcc-10 libusb-1.0.0-dev libgtk-3-dev rpm mingw-w64
# - name: Building Release for Windows (x86-64) ...
# run: sudo mkdir -p build-mingw && cd build-mingw && sudo cmake \
# -DCMAKE_SYSTEM_NAME=Windows \
# -DTOOLCHAIN_PREFIX=x86_64-w64-mingw32 \
# -DCMAKE_TOOLCHAIN_FILE=$PWD/../cmake/modules/set_toolchain.cmake \
# -DCMAKE_INSTALL_PREFIX=$PWD/install $PWD && \
# sudo make && sudo rm -rf build-mingw && cd -

4
CHANGELOG.md
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@ -41,7 +41,7 @@ Updates & changes:
Fixes:
- Flash loader rework ([#356](https://github.com/stlink-org/stlink/pull/356), [#556](https://github.com/stlink-org/stlink/pull/556), [#593](https://github.com/stlink-org/stlink/pull/593), [#597](https://github.com/stlink-org/stlink/pull/597), [#607](https://github.com/stlink-org/stlink/pull/607), [#612](https://github.com/stlink-org/stlink/pull/612), [#638](https://github.com/stlink-org/stlink/pull/638), [#661](https://github.com/stlink-org/stlink/pull/661), [#690](https://github.com/stlink-org/stlink/pull/690), [#807](https://github.com/stlink-org/stlink/pull/807), [#817](https://github.com/stlink-org/stlink/pull/817), [#818](https://github.com/stlink-org/stlink/pull/818), [#854](https://github.com/stlink-org/stlink/pull/854), [#868](https://github.com/stlink-org/stlink/pull/868), [#967](https://github.com/stlink-org/stlink/pull/967), [#979](https://github.com/stlink-org/stlink/pull/979), [#1043](https://github.com/stlink-org/stlink/pull/1043), [#1054](https://github.com/stlink-org/stlink/pull/1054), [#1092](https://github.com/stlink-org/stlink/pull/1092), [#1105](https://github.com/stlink-org/stlink/pull/1105), [#1113](https://github.com/stlink-org/stlink/pull/1113))
- Fixed old DFU serial number for STLINK programmers ([#417](https://github.com/stlink-org/stlink/pull/417), [#494](https://github.com/stlink-org/stlink/pull/494), [#1106](https://github.com/stlink-org/stlink/pull/1106))
- Fixed old DFU serial number for STLINK programmers ([#417](https://github.com/stlink-org/stlink/pull/417), [#494](https://github.com/stlink-org/stlink/pull/494), [#1106](https://github.com/stlink-org/stlink/pull/1106), [#1121](https://github.com/stlink-org/stlink/pull/1121))
- Use vl flashloader for all STM32F1 series ([#769](https://github.com/stlink-org/stlink/pull/769), [#1041](https://github.com/stlink-org/stlink/pull/1041), [#1044](https://github.com/stlink-org/stlink/pull/1044))
- [regression] Changed timeout on flash write ([#787](https://github.com/stlink-org/stlink/pull/787), [#981](https://github.com/stlink-org/stlink/pull/981), [#987](https://github.com/stlink-org/stlink/pull/987))
- cmake compile failure with external `CMAKE_MODULE_PATH` set ([#962](https://github.com/stlink-org/stlink/pull/962))
@ -165,7 +165,7 @@ Fixes:
- Set static link for `libssp` (stack-smashing protection) ([#960](https://github.com/stlink-org/stlink/pull/960), [#961](https://github.com/stlink-org/stlink/pull/961))
- Fixed udev rules installing to wrong directory ([#966](https://github.com/stlink-org/stlink/pull/966))
- Fixed formatting for options display in `st-flash` & `st-info` (commits [#c783d0e](https://github.com/stlink-org/stlink/commit/c783d0e777ccc83a7a8be26a4f4d3414e0478560) and [#562cd24](https://github.com/stlink-org/stlink/commit/562cd2496e696dbd22950925866aac662d81ee5f))
- Fixed reading of chip ID on Cortex-M0+ core ([#1125](https://github.com/stlink-org/stlink/pull/1125), [#1126](https://github.com/stlink-org/stlink/pull/1126))
- Fixed reading of chip ID on Cortex-M0+ core ([#1125](https://github.com/stlink-org/stlink/pull/1125), [#1126](https://github.com/stlink-org/stlink/pull/1126), [#1133](https://github.com/stlink-org/stlink/pull/1133))
# v1.6.0

31
inc/stm32.h
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@ -8,24 +8,31 @@
#define STM32_H
/* Cortex core ids */
#define STM32VL_CORE_ID 0x1ba01477
#define STM32F7_CORE_ID 0x5ba02477
#define STM32H7_CORE_ID 0x6ba02477 // STM32H7 SWD ID Code
#define STM32VL_CORE_ID 0x1ba01477
#define STM32F7_CORE_ID 0x5ba02477
#define STM32H7_CORE_ID 0x6ba02477 // STM32H7 SWD ID Code
#define STM32H7_CORE_ID_JTAG 0x6ba00477 // STM32H7 JTAG ID Code (RM0433 pg3065)
/* Constant STM32 memory map figures */
#define STM32_FLASH_BASE ((uint32_t)0x08000000)
#define STM32_F1_FLASH_BANK2_BASE ((uint32_t)0x08080000)
#define STM32_H7_FLASH_BANK2_BASE ((uint32_t)0x08100000)
#define STM32_SRAM_BASE ((uint32_t)0x20000000)
#define STM32_G0_OPTION_BYTES_BASE ((uint32_t)0x1FFF7800)
#define STM32_G4_OPTION_BYTES_BASE ((uint32_t)0x1FFFF800)
#define STM32_L0_CATx_OPTION_BYTES_BASE ((uint32_t)0x1FF80000)
#define STM32_SRAM_BASE ((uint32_t)0x20000000)
#define STM32_FLASH_BASE ((uint32_t)0x08000000)
#define STM32_F1_FLASH_BANK2_BASE ((uint32_t)0x08080000)
#define STM32_H7_FLASH_BANK2_BASE ((uint32_t)0x08100000)
#define STM32_F2_OPTION_BYTES_BASE ((uint32_t)0x1FFFC000)
#define STM32_L4_OPTION_BYTES_BASE ((uint32_t)0x1FFF7800)
#define STM32_L1_OPTION_BYTES_BASE ((uint32_t)0x1FF80000)
#define STM32_F4_OPTION_BYTES_BASE ((uint32_t)0x40023C14)
#define STM32_F7_OPTION_BYTES_BASE ((uint32_t)0x1FFF0000)
#define STM32_H7_OPTION_BYTES_BASE ((uint32_t)0x5200201C)
#define STM32_G0_OPTION_BYTES_BASE ((uint32_t)0x1FFF7800)
#define STM32_L4_OPTION_BYTES_BASE ((uint32_t)0x1FFF7800)
#define STM32_L0_OPTION_BYTES_BASE ((uint32_t)0x1FF80000)
#define STM32_L1_OPTION_BYTES_BASE ((uint32_t)0x1FF80000)
#define STM32_F0_OPTION_BYTES_BASE ((uint32_t)0x1FFFF800)
#define STM32_F1_OPTION_BYTES_BASE ((uint32_t)0x1FFFF800)
#define STM32_F3_OPTION_BYTES_BASE ((uint32_t)0x1FFFF800)
#define STM32_G4_OPTION_BYTES_BASE ((uint32_t)0x1FFFF800)
#endif // STM32_H

353
src/stlink-lib/chipid.c
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@ -7,12 +7,15 @@ static const struct stlink_chipid_params devices[] = {
.chip_id = STLINK_CHIPID_STM32_F7XXXX,
.description = "F76xxx",
.flash_type = STLINK_FLASH_TYPE_F7,
.flash_size_reg = 0x1ff0f442, // section 45.2
.flash_pagesize = 0x800, // No flash pages
.sram_size = 0x80000, // "SRAM" byte size in hex from
.bootrom_base = 0x00200000, // ! "System memory" starting address from
.bootrom_size = 0xEDC0, // ! @todo "System memory" byte size in hex from
.option_base = STM32_F7_OPTION_BYTES_BASE, // Used for reading back the option bytes, writing uses FLASH_F7_OPTCR and FLASH_F7_OPTCR1
.flash_size_reg = 0x1ff0f442, // section 45.2
.flash_pagesize = 0x800, // No flash pages
.sram_size = 0x80000, // "SRAM" byte size in hex from
.bootrom_base = 0x00200000, // ! "System memory" starting address from
.bootrom_size = 0xEDC0, // ! @todo "System memory" byte size in hex from
.option_base =
STM32_F7_OPTION_BYTES_BASE, // Used for reading back the option
// bytes, writing uses FLASH_F7_OPTCR
// and FLASH_F7_OPTCR1
.option_size = 0x20,
.flags = CHIP_F_HAS_SWO_TRACING,
},
@ -21,11 +24,13 @@ static const struct stlink_chipid_params devices[] = {
.chip_id = STLINK_CHIPID_STM32_F7,
.description = "F7xx",
.flash_type = STLINK_FLASH_TYPE_F4,
.flash_size_reg = 0x1ff0f442, // section 41.2
.flash_pagesize = 0x800, // No flash pages
.sram_size = 0x50000, // "SRAM" byte size in hex from DS Fig 18
.bootrom_base = 0x00100000, // "System memory" starting address from DS Fig 18
.bootrom_size = 0xEDC0, // "System memory" byte size in hex from DS Fig 18
.flash_size_reg = 0x1ff0f442, // section 41.2
.flash_pagesize = 0x800, // No flash pages
.sram_size = 0x50000, // "SRAM" byte size in hex from DS Fig 18
.bootrom_base =
0x00100000, // "System memory" starting address from DS Fig 18
.bootrom_size =
0xEDC0, // "System memory" byte size in hex from DS Fig 18
.flags = CHIP_F_HAS_SWO_TRACING,
},
{
@ -33,14 +38,17 @@ static const struct stlink_chipid_params devices[] = {
.chip_id = STLINK_CHIPID_STM32_F72XXX,
.description = "F72x/F73x",
.flash_type = STLINK_FLASH_TYPE_F4,
.flash_size_reg = 0x1ff07a22, // section 35.2
.flash_pagesize = 0x800, // No flash pages
.sram_size = 0x40000, // "SRAM" byte size in hex from DS Fig 24
.bootrom_base = 0x00100000, // "System memory" starting address from DS Fig 24
.bootrom_size = 0xEDC0, // "System memory" byte size in hex from DS Fig 24
.flash_size_reg = 0x1ff07a22, // section 35.2
.flash_pagesize = 0x800, // No flash pages
.sram_size = 0x40000, // "SRAM" byte size in hex from DS Fig 24
.bootrom_base =
0x00100000, // "System memory" starting address from DS Fig 24
.bootrom_size =
0xEDC0, // "System memory" byte size in hex from DS Fig 24
.flags = CHIP_F_HAS_SWO_TRACING,
},
{ // table 2, PM0063
{
// table 2, PM0063
.chip_id = STLINK_CHIPID_STM32_F1_MEDIUM,
.description = "F1xx Medium-density",
.flash_type = STLINK_FLASH_TYPE_F0,
@ -51,11 +59,12 @@ static const struct stlink_chipid_params devices[] = {
.bootrom_size = 0x800,
.flags = CHIP_F_HAS_SWO_TRACING,
},
{ // table 1, PM0059
{
// table 1, PM0059
.chip_id = STLINK_CHIPID_STM32_F2,
.description = "F2xx",
.flash_type = STLINK_FLASH_TYPE_F4,
.flash_size_reg = 0x1fff7a22, // as in RM0033 Rev 5
.flash_size_reg = 0x1fff7a22, // as in RM0033 Rev 5
.flash_pagesize = 0x20000,
.sram_size = 0x20000,
.bootrom_base = 0x1fff0000,
@ -64,7 +73,8 @@ static const struct stlink_chipid_params devices[] = {
.option_size = 4,
.flags = CHIP_F_HAS_SWO_TRACING,
},
{ // PM0063
{
// PM0063
.chip_id = STLINK_CHIPID_STM32_F1_LOW,
.description = "F1 Low-density device",
.flash_type = STLINK_FLASH_TYPE_F0,
@ -79,7 +89,7 @@ static const struct stlink_chipid_params devices[] = {
.chip_id = STLINK_CHIPID_STM32_F4,
.description = "F4xx",
.flash_type = STLINK_FLASH_TYPE_F4,
.flash_size_reg = 0x1FFF7A22, // As in rm0090 since Rev 2
.flash_size_reg = 0x1FFF7A22, // As in rm0090 since Rev 2
.flash_pagesize = 0x4000,
.sram_size = 0x30000,
.bootrom_base = 0x1fff0000,
@ -92,7 +102,7 @@ static const struct stlink_chipid_params devices[] = {
.chip_id = STLINK_CHIPID_STM32_F4_DSI,
.description = "F46x/F47x",
.flash_type = STLINK_FLASH_TYPE_F4,
.flash_size_reg = 0x1FFF7A22, // As in rm0090 since Rev 2
.flash_size_reg = 0x1FFF7A22, // As in rm0090 since Rev 2
.flash_pagesize = 0x4000,
.sram_size = 0x40000,
.bootrom_base = 0x1fff0000,
@ -103,7 +113,7 @@ static const struct stlink_chipid_params devices[] = {
.chip_id = STLINK_CHIPID_STM32_F4_HD,
.description = "F42x/F43x",
.flash_type = STLINK_FLASH_TYPE_F4,
.flash_size_reg = 0x1FFF7A22, // As in rm0090 since Rev 2
.flash_size_reg = 0x1FFF7A22, // As in rm0090 since Rev 2
.flash_pagesize = 0x4000,
.sram_size = 0x40000,
.bootrom_base = 0x1fff0000,
@ -224,7 +234,8 @@ static const struct stlink_chipid_params devices[] = {
.bootrom_size = 0x4800,
.flags = CHIP_F_HAS_SWO_TRACING,
},
{ // Low and Medium density VL have same chipid. RM0041 25.6.1
{
// Low and Medium density VL have same chipid. RM0041 25.6.1
.chip_id = STLINK_CHIPID_STM32_F1_VL_MEDIUM_LOW,
.description = "F1xx Value Line",
.flash_type = STLINK_FLASH_TYPE_F0,
@ -315,11 +326,12 @@ static const struct stlink_chipid_params devices[] = {
.chip_id = STLINK_CHIPID_STM32_F0_CAN,
.description = "F07x",
.flash_type = STLINK_FLASH_TYPE_F0,
.flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735)
.flash_pagesize = 0x800, // Page sizes listed in Table 4
.sram_size = 0x4000, // "SRAM" byte size in hex from Table 2
.bootrom_base = 0x1fffC800, // "System memory" starting address from Table 2
.bootrom_size = 0x3000, // "System memory" byte size in hex from Table 2
.flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735)
.flash_pagesize = 0x800, // Page sizes listed in Table 4
.sram_size = 0x4000, // "SRAM" byte size in hex from Table 2
.bootrom_base =
0x1fffC800, // "System memory" starting address from Table 2
.bootrom_size = 0x3000, // "System memory" byte size in hex from Table 2
},
{
// Use this as an example for mapping future chips:
@ -327,11 +339,12 @@ static const struct stlink_chipid_params devices[] = {
.chip_id = STLINK_CHIPID_STM32_F0,
.description = "F0xx",
.flash_type = STLINK_FLASH_TYPE_F0,
.flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735)
.flash_pagesize = 0x400, // Page sizes listed in Table 4
.sram_size = 0x2000, // "SRAM" byte size in hex from Table 2
.bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2
.bootrom_size = 0xC00, // "System memory" byte size in hex from Table 2
.flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735)
.flash_pagesize = 0x400, // Page sizes listed in Table 4
.sram_size = 0x2000, // "SRAM" byte size in hex from Table 2
.bootrom_base =
0x1fffec00, // "System memory" starting address from Table 2
.bootrom_size = 0xC00, // "System memory" byte size in hex from Table 2
},
{
// RM0402 document was used to find these parameters
@ -339,11 +352,12 @@ static const struct stlink_chipid_params devices[] = {
.chip_id = STLINK_CHIPID_STM32_F412,
.description = "F412",
.flash_type = STLINK_FLASH_TYPE_F4,
.flash_size_reg = 0x1FFF7A22, // "Flash size data register" (pg1135)
.flash_pagesize = 0x4000, // Table 5. Flash module organization ?
.sram_size = 0x40000, // "SRAM" byte size in hex from Table 4
.bootrom_base = 0x1FFF0000, // "System memory" starting address from Table 4
.bootrom_size = 0x7800, // "System memory" byte size in hex from Table 4
.flash_size_reg = 0x1FFF7A22, // "Flash size data register" (pg1135)
.flash_pagesize = 0x4000, // Table 5. Flash module organization ?
.sram_size = 0x40000, // "SRAM" byte size in hex from Table 4
.bootrom_base =
0x1FFF0000, // "System memory" starting address from Table 4
.bootrom_size = 0x7800, // "System memory" byte size in hex from Table 4
.flags = CHIP_F_HAS_SWO_TRACING,
},
{
@ -352,22 +366,27 @@ static const struct stlink_chipid_params devices[] = {
.chip_id = STLINK_CHIPID_STM32_F413,
.description = "F413",
.flash_type = STLINK_FLASH_TYPE_F4,
.flash_size_reg = 0x1FFF7A22, // "Flash size data register" Section 35.2
.flash_pagesize = 0x4000, // Table 5. Flash module organization (variable sector sizes, but 0x4000 is smallest)
.sram_size = 0x50000, // "SRAM" byte size in hex from Figure 2 (Table 4 only says 0x40000)
.bootrom_base = 0x1FFF0000, // "System memory" starting address from Table 4
.bootrom_size = 0x7800, // "System memory" byte size in hex from Table 4
.flash_size_reg = 0x1FFF7A22, // "Flash size data register" Section 35.2
.flash_pagesize =
0x4000, // Table 5. Flash module organization (variable sector
// sizes, but 0x4000 is smallest)
.sram_size = 0x50000, // "SRAM" byte size in hex from Figure 2 (Table 4
// only says 0x40000)
.bootrom_base =
0x1FFF0000, // "System memory" starting address from Table 4
.bootrom_size = 0x7800, // "System memory" byte size in hex from Table 4
.flags = CHIP_F_HAS_SWO_TRACING,
},
{
.chip_id = STLINK_CHIPID_STM32_F09X,
.description = "F09X",
.flash_type = STLINK_FLASH_TYPE_F0,
.flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735)
.flash_pagesize = 0x800, // Page sizes listed in Table 4 (pg 56)
.sram_size = 0x8000, // "SRAM" byte size in hex from Table 2 (pg 50)
.bootrom_base = 0x1fffd800, // "System memory" starting address from Table 2
.bootrom_size = 0x2000, // "System memory" byte size in hex from Table 2
.flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735)
.flash_pagesize = 0x800, // Page sizes listed in Table 4 (pg 56)
.sram_size = 0x8000, // "SRAM" byte size in hex from Table 2 (pg 50)
.bootrom_base =
0x1fffd800, // "System memory" starting address from Table 2
.bootrom_size = 0x2000, // "System memory" byte size in hex from Table 2
},
{
// Use this as an example for mapping future chips:
@ -375,11 +394,12 @@ static const struct stlink_chipid_params devices[] = {
.chip_id = STLINK_CHIPID_STM32_F04,
.description = "F04x",
.flash_type = STLINK_FLASH_TYPE_F0,
.flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735)
.flash_pagesize = 0x400, // Page sizes listed in Table 4
.sram_size = 0x1800, // "SRAM" byte size in hex from Table 2
.bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2
.bootrom_size = 0xC00, // "System memory" byte size in hex from Table 2
.flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735)
.flash_pagesize = 0x400, // Page sizes listed in Table 4
.sram_size = 0x1800, // "SRAM" byte size in hex from Table 2
.bootrom_base =
0x1fffec00, // "System memory" starting address from Table 2
.bootrom_size = 0xC00, // "System memory" byte size in hex from Table 2
},
{
// Use this as an example for mapping future chips:
@ -387,11 +407,12 @@ static const struct stlink_chipid_params devices[] = {
.chip_id = STLINK_CHIPID_STM32_F0_SMALL,
.description = "F0xx small",
.flash_type = STLINK_FLASH_TYPE_F0,
.flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735)
.flash_pagesize = 0x400, // Page sizes listed in Table 4
.sram_size = 0x1000, // "SRAM" byte size in hex from Table 2
.bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2
.bootrom_size = 0xC00, // "System memory" byte size in hex from Table 2
.flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735)
.flash_pagesize = 0x400, // Page sizes listed in Table 4
.sram_size = 0x1000, // "SRAM" byte size in hex from Table 2
.bootrom_base =
0x1fffec00, // "System memory" starting address from Table 2
.bootrom_size = 0xC00, // "System memory" byte size in hex from Table 2
},
{
// STM32F30x
@ -416,7 +437,7 @@ static const struct stlink_chipid_params devices[] = {
.sram_size = 0x2000,
.bootrom_base = 0x1ff0000,
.bootrom_size = 0x1000,
.option_base = STM32_L0_CATx_OPTION_BYTES_BASE,
.option_base = STM32_L0_OPTION_BYTES_BASE,
.option_size = 20,
},
{
@ -430,7 +451,7 @@ static const struct stlink_chipid_params devices[] = {
.sram_size = 0x5000,
.bootrom_base = 0x1ff0000,
.bootrom_size = 0x2000,
.option_base = STM32_L0_CATx_OPTION_BYTES_BASE,
.option_base = STM32_L0_OPTION_BYTES_BASE,
.option_size = 20,
},
{
@ -444,7 +465,7 @@ static const struct stlink_chipid_params devices[] = {
.sram_size = 0x2000,
.bootrom_base = 0x1ff0000,
.bootrom_size = 0x1000,
.option_base = STM32_L0_CATx_OPTION_BYTES_BASE,
.option_base = STM32_L0_OPTION_BYTES_BASE,
.option_size = 20,
},
{
@ -466,10 +487,10 @@ static const struct stlink_chipid_params devices[] = {
.chip_id = STLINK_CHIPID_STM32_F303_HIGH,
.description = "F303 high density",
.flash_type = STLINK_FLASH_TYPE_F0,
.flash_size_reg = 0x1ffff7cc, // 34.2.1 Flash size data register
.flash_pagesize = 0x800, // 4.2.1 Flash memory organization
.sram_size = 0x10000, // 3.3 Embedded SRAM
.bootrom_base = 0x1fffd800, // 3.3.2 / Table 4 System Memory
.flash_size_reg = 0x1ffff7cc, // 34.2.1 Flash size data register
.flash_pagesize = 0x800, // 4.2.1 Flash memory organization
.sram_size = 0x10000, // 3.3 Embedded SRAM
.bootrom_base = 0x1fffd800, // 3.3.2 / Table 4 System Memory
.bootrom_size = 0x2000,
.flags = CHIP_F_HAS_SWO_TRACING,
},
@ -479,15 +500,18 @@ static const struct stlink_chipid_params devices[] = {
.chip_id = STLINK_CHIPID_STM32_L4,
.description = "L4xx",
.flash_type = STLINK_FLASH_TYPE_L4,
.flash_size_reg = 0x1FFF75e0, // "Flash size data register" (sec 45.2, page 1671)
.flash_pagesize = 0x800, // 2k (sec 3.2, page 78; also appears in sec 3.3.1
// and tables 4-6 on pages 79-81)
// SRAM1 is "up to" 96k in the standard Cortex-M memory map;
// SRAM2 is 32k mapped at at 0x10000000 (sec 2.3, page 73 for
// sizes; table 2, page 74 for SRAM2 location)
.flash_size_reg =
0x1FFF75e0, // "Flash size data register" (sec 45.2, page 1671)
.flash_pagesize =
0x800, // 2k (sec 3.2, page 78; also appears in sec 3.3.1
// and tables 4-6 on pages 79-81)
// SRAM1 is "up to" 96k in the standard Cortex-M memory map;
// SRAM2 is 32k mapped at at 0x10000000 (sec 2.3, page 73 for
// sizes; table 2, page 74 for SRAM2 location)
.sram_size = 0x18000,
.bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory)
.bootrom_size = 0x7000, // 28k (per bank), same source as base
.bootrom_base =
0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory)
.bootrom_size = 0x7000, // 28k (per bank), same source as base
.option_base = STM32_L4_OPTION_BYTES_BASE,
.option_size = 4,
.flags = CHIP_F_HAS_SWO_TRACING,
@ -498,11 +522,13 @@ static const struct stlink_chipid_params devices[] = {
.chip_id = STLINK_CHIPID_STM32_L4RX,
.description = "L4Rx",
.flash_type = STLINK_FLASH_TYPE_L4,
.flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 52.2, page 2049)
.flash_pagesize = 0x1000, // 4k, section 3.3, pg 97
.sram_size = 0xa0000, // 192k (SRAM1) + 64k SRAM2 + 384k SRAM3 = 640k, or 0xA0000
.bootrom_base = 0x1fff0000, // 3.3.1, pg 99
.bootrom_size = 0x7000, // 28k (per bank), same source as base (pg 99)
.flash_size_reg =
0x1fff75e0, // "Flash size data register" (sec 52.2, page 2049)
.flash_pagesize = 0x1000, // 4k, section 3.3, pg 97
.sram_size =
0xa0000, // 192k (SRAM1) + 64k SRAM2 + 384k SRAM3 = 640k, or 0xA0000
.bootrom_base = 0x1fff0000, // 3.3.1, pg 99
.bootrom_size = 0x7000, // 28k (per bank), same source as base (pg 99)
.flags = CHIP_F_HAS_SWO_TRACING,
},
{
@ -511,13 +537,16 @@ static const struct stlink_chipid_params devices[] = {
.chip_id = STLINK_CHIPID_STM32_L41X,
.description = "L41x",
.flash_type = STLINK_FLASH_TYPE_L4,
.flash_size_reg = 0x1fff75e0, // "Flash size data register" (RM0394, sec 47.2, page 1586)
.flash_pagesize = 0x800, // 2k (DS12469, sec 3.4, page 17)
// SRAM1 is 32k at 0x20000000
// SRAM2 is 8k at 0x10000000 and 0x20008000 (DS12469, sec 3.5, page 18)
.sram_size = 0xa000, // 40k (DS12469, sec 3.5, page 18)
.bootrom_base = 0x1fff0000, // System Memory (RM0394, sec 3.3.1, table 8)
.bootrom_size = 0x7000, // 28k, same source as base
.flash_size_reg = 0x1fff75e0, // "Flash size data register" (RM0394,
// sec 47.2, page 1586)
.flash_pagesize = 0x800, // 2k (DS12469, sec 3.4, page 17)
// SRAM1 is 32k at 0x20000000
// SRAM2 is 8k at 0x10000000 and 0x20008000
// (DS12469, sec 3.5, page 18)
.sram_size = 0xa000, // 40k (DS12469, sec 3.5, page 18)
.bootrom_base =
0x1fff0000, // System Memory (RM0394, sec 3.3.1, table 8)
.bootrom_size = 0x7000, // 28k, same source as base
.flags = CHIP_F_HAS_SWO_TRACING,
},
{
@ -526,15 +555,18 @@ static const struct stlink_chipid_params devices[] = {
.chip_id = STLINK_CHIPID_STM32_L43X,
.description = "L43x/L44x",
.flash_type = STLINK_FLASH_TYPE_L4,
.flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 43.2, page 1410)
.flash_pagesize = 0x800, // 2k (sec 3.2, page 74; also appears in sec 3.3.1
// and tables 7-8 on pages 75-76)
// SRAM1 is "up to" 64k in the standard Cortex-M memory map;
// SRAM2 is 16k mapped at 0x10000000 (sec 2.3, page 73 for
// sizes; table 2, page 74 for SRAM2 location)
.flash_size_reg =
0x1fff75e0, // "Flash size data register" (sec 43.2, page 1410)
.flash_pagesize =
0x800, // 2k (sec 3.2, page 74; also appears in sec 3.3.1
// and tables 7-8 on pages 75-76)
// SRAM1 is "up to" 64k in the standard Cortex-M memory map;
// SRAM2 is 16k mapped at 0x10000000 (sec 2.3, page 73 for
// sizes; table 2, page 74 for SRAM2 location)
.sram_size = 0xc000,
.bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory)
.bootrom_size = 0x7000, // 28k (per bank), same source as base
.bootrom_base =
0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory)
.bootrom_size = 0x7000, // 28k (per bank), same source as base
.option_base = STM32_L4_OPTION_BYTES_BASE,
.option_size = 4,
.flags = CHIP_F_HAS_SWO_TRACING,
@ -545,13 +577,15 @@ static const struct stlink_chipid_params devices[] = {
.chip_id = STLINK_CHIPID_STM32_L496X,
.description = "L496x/L4A6x",
.flash_type = STLINK_FLASH_TYPE_L4,
.flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 49.2, page 1809)
.flash_pagesize = 0x800, // Page erase (2 Kbyte) (sec 3.2, page 93)
// SRAM1 is 256k at 0x20000000
// SRAM2 is 64k at 0x20040000 (sec 2.2.1, fig 2, page 74)
.sram_size = 0x40000, // Embedded SRAM (sec 2.4, page 84)
.bootrom_base = 0x1fff0000, // System Memory (Bank 1) (sec 3.3.1)
.bootrom_size = 0x7000, // 28k (per bank), same source as base
.flash_size_reg =
0x1fff75e0, // "Flash size data register" (sec 49.2, page 1809)
.flash_pagesize =
0x800, // Page erase (2 Kbyte) (sec 3.2, page 93)
// SRAM1 is 256k at 0x20000000
// SRAM2 is 64k at 0x20040000 (sec 2.2.1, fig 2, page 74)
.sram_size = 0x40000, // Embedded SRAM (sec 2.4, page 84)
.bootrom_base = 0x1fff0000, // System Memory (Bank 1) (sec 3.3.1)
.bootrom_size = 0x7000, // 28k (per bank), same source as base
.option_base = STM32_L4_OPTION_BYTES_BASE,
.option_size = 4,
.flags = CHIP_F_HAS_SWO_TRACING,
@ -562,14 +596,18 @@ static const struct stlink_chipid_params devices[] = {
.chip_id = STLINK_CHIPID_STM32_L46X,
.description = "L45x/46x",
.flash_type = STLINK_FLASH_TYPE_L4,
.flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 45.2, page 1463)
.flash_pagesize = 0x800, // 2k (sec 3.2, page 73; also appears in sec 3.3.1
// and tables 7 on pages 73-74)
// SRAM1 is 128k at 0x20000000;
// SRAM2 is 32k mapped at 0x10000000 (sec 2.4.2, table 3-4, page 68, also fig 2 on page 63)
.flash_size_reg =
0x1fff75e0, // "Flash size data register" (sec 45.2, page 1463)
.flash_pagesize =
0x800, // 2k (sec 3.2, page 73; also appears in sec 3.3.1
// and tables 7 on pages 73-74)
// SRAM1 is 128k at 0x20000000;
// SRAM2 is 32k mapped at 0x10000000 (sec 2.4.2, table 3-4,
// page 68, also fig 2 on page 63)
.sram_size = 0x20000,
.bootrom_base = 0x1fff0000, // Tables 6, pages 71-72 (Bank 1 system memory, also fig 2 on page 63)
.bootrom_size = 0x7000, // 28k (per bank), same source as base
.bootrom_base = 0x1fff0000, // Tables 6, pages 71-72 (Bank 1 system
// memory, also fig 2 on page 63)
.bootrom_size = 0x7000, // 28k (per bank), same source as base
.flags = CHIP_F_HAS_SWO_TRACING,
},
{
@ -588,11 +626,11 @@ static const struct stlink_chipid_params devices[] = {
.chip_id = STLINK_CHIPID_STM32_G0_CAT1,
.description = "G030/G031/G041",
.flash_type = STLINK_FLASH_TYPE_G0,
.flash_size_reg = 0x1FFF75E0, // Section 38.2
.flash_pagesize = 0x800, // 2k (sec 3.2)
.sram_size = 0x2000, // 8k (sec 2.3)
.flash_size_reg = 0x1FFF75E0, // Section 38.2
.flash_pagesize = 0x800, // 2k (sec 3.2)
.sram_size = 0x2000, // 8k (sec 2.3)
.bootrom_base = 0x1fff0000,
.bootrom_size = 0x2000, // 8k (sec 2.2.2 table 3)
.bootrom_size = 0x2000, // 8k (sec 2.2.2 table 3)
.option_base = STM32_G0_OPTION_BYTES_BASE,
.option_size = 4,
},
@ -601,11 +639,11 @@ static const struct stlink_chipid_params devices[] = {
.chip_id = STLINK_CHIPID_STM32_G0_CAT2,
.description = "G070/G071/G081",
.flash_type = STLINK_FLASH_TYPE_G0,
.flash_size_reg = 0x1FFF75E0, // Section 38.2
.flash_pagesize = 0x800, // 2k (sec 3.2)
.sram_size = 0x9000, // 36k (sec 2.3)
.flash_size_reg = 0x1FFF75E0, // Section 38.2
.flash_pagesize = 0x800, // 2k (sec 3.2)
.sram_size = 0x9000, // 36k (sec 2.3)
.bootrom_base = 0x1fff0000,
.bootrom_size = 0x7000, // 28k (sec 2.2.2 table 2)
.bootrom_size = 0x7000, // 28k (sec 2.2.2 table 2)
.option_base = STM32_G0_OPTION_BYTES_BASE,
.option_size = 4,
},
@ -614,14 +652,15 @@ static const struct stlink_chipid_params devices[] = {
.chip_id = STLINK_CHIPID_STM32_G4_CAT2,
.description = "G4 Category-2",
.flash_type = STLINK_FLASH_TYPE_G4,
.flash_size_reg = 0x1FFF75E0, // Section 47.2
.flash_pagesize = 0x800, // 2k (sec 3.3.1)
// SRAM1 is 16k at 0x20000000
// SRAM2 is 6k at 0x20014000
// SRAM3/CCM is 10k at 0x10000000, aliased at 0x20018000
.sram_size = 0x8000, // 32k (sec 2.4)
.flash_size_reg = 0x1FFF75E0, // Section 47.2
.flash_pagesize =
0x800, // 2k (sec 3.3.1)
// SRAM1 is 16k at 0x20000000
// SRAM2 is 6k at 0x20014000
// SRAM3/CCM is 10k at 0x10000000, aliased at 0x20018000
.sram_size = 0x8000, // 32k (sec 2.4)
.bootrom_base = 0x1fff0000,
.bootrom_size = 0x7000, // 28k (table 2)
.bootrom_size = 0x7000, // 28k (table 2)
.option_base = STM32_G4_OPTION_BYTES_BASE,
.option_size = 4,
.flags = CHIP_F_HAS_SWO_TRACING,
@ -631,14 +670,15 @@ static const struct stlink_chipid_params devices[] = {
.chip_id = STLINK_CHIPID_STM32_G4_CAT3,
.description = "G4 Category-3",
.flash_type = STLINK_FLASH_TYPE_G4,
.flash_size_reg = 0x1FFF75E0, // Section 47.2
.flash_pagesize = 0x800, // 2k (sec 3.3.1)
// SRAM1 is 80k at 0x20000000
// SRAM2 is 16k at 0x20014000
// SRAM3/CCM is 32k at 0x10000000, aliased at 0x20018000
.sram_size = 0x18000, // 128k (sec 2.4)
.flash_size_reg = 0x1FFF75E0, // Section 47.2
.flash_pagesize =
0x800, // 2k (sec 3.3.1)
// SRAM1 is 80k at 0x20000000
// SRAM2 is 16k at 0x20014000
// SRAM3/CCM is 32k at 0x10000000, aliased at 0x20018000
.sram_size = 0x18000, // 128k (sec 2.4)
.bootrom_base = 0x1fff0000,
.bootrom_size = 0x7000, // 28k (table 2)
.bootrom_size = 0x7000, // 28k (table 2)
.option_base = STM32_G4_OPTION_BYTES_BASE,
.option_size = 4,
.flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING,
@ -649,7 +689,7 @@ static const struct stlink_chipid_params devices[] = {
.description = "WB55",
.flash_type = STLINK_FLASH_TYPE_WB,
.flash_size_reg = 0x1FFF75E0,
.flash_pagesize = 0x1000, // 4k
.flash_pagesize = 0x1000, // 4k
.sram_size = 0x40000,
.bootrom_base = 0x1fff0000, // see the memory map
.bootrom_size = 0x7000,
@ -660,13 +700,15 @@ static const struct stlink_chipid_params devices[] = {
.chip_id = STLINK_CHIPID_STM32_H74XXX,
.description = "H74x/H75x",
.flash_type = STLINK_FLASH_TYPE_H7,
.flash_size_reg = 0x1ff1e880, // "Flash size register" (pg3272)
.flash_pagesize = 0x20000, // 128k sector (pg147)
.sram_size = 0x20000, // 128k "DTCM" from Table 7
.bootrom_base = 0x1ff00000, // "System memory" starting address from Table 7
.bootrom_size = 0x20000, // "System memory" byte size in hex from Table 7
.flash_size_reg = 0x1ff1e880, // "Flash size register" (pg3272)
.flash_pagesize = 0x20000, // 128k sector (pg147)
.sram_size = 0x20000, // 128k "DTCM" from Table 7
.bootrom_base =
0x1ff00000, // "System memory" starting address from Table 7
.bootrom_size =
0x20000, // "System memory" byte size in hex from Table 7
.option_base = STM32_H7_OPTION_BYTES_BASE,
.option_size = 44, // FLASH_OPTSR_CUR to FLASH_BOOT_PRGR from Table 28
.option_size = 44, // FLASH_OPTSR_CUR to FLASH_BOOT_PRGR from Table 28
.flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING,
},
{
@ -674,11 +716,13 @@ static const struct stlink_chipid_params devices[] = {
.chip_id = STLINK_CHIPID_STM32_H7AX,
.description = "H7Ax/H7Bx",
.flash_type = STLINK_FLASH_TYPE_H7,
.flash_size_reg = 0x08FFF80C, // "Flash size register" (p.2949)
.flash_pagesize = 0x2000, // 8k sector (p.146)
.sram_size = 0x20000, // 128k "DTCM" (Figure 1)
.bootrom_base = 0x1FF00000, // "System memory" starting address (Table 12-14)
.bootrom_size = 0x20000, // "System memory" byte size in hex splitted to two banks (Table 12-14)
.flash_size_reg = 0x08FFF80C, // "Flash size register" (p.2949)
.flash_pagesize = 0x2000, // 8k sector (p.146)
.sram_size = 0x20000, // 128k "DTCM" (Figure 1)
.bootrom_base =
0x1FF00000, // "System memory" starting address (Table 12-14)
.bootrom_size = 0x20000, // "System memory" byte size in hex splitted to
// two banks (Table 12-14)
.option_base = STM32_H7_OPTION_BYTES_BASE,
.option_size = 44,
.flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING,
@ -688,11 +732,12 @@ static const struct stlink_chipid_params devices[] = {
.chip_id = STLINK_CHIPID_STM32_H72X,
.description = "H72x/H73x",
.flash_type = STLINK_FLASH_TYPE_H7,
.flash_size_reg = 0x1FF1E880, // "Flash size register" (p.3286)
.flash_pagesize = 0x20000, // 128k sector (p.152)
.sram_size = 0x20000, // 128k "DTCM" (Figure 1)
.bootrom_base = 0x1FF00000, // "System memory" starting address (Table 6)
.bootrom_size = 0x20000, // "System memory" byte size in hex (Table 6)
.flash_size_reg = 0x1FF1E880, // "Flash size register" (p.3286)
.flash_pagesize = 0x20000, // 128k sector (p.152)
.sram_size = 0x20000, // 128k "DTCM" (Figure 1)
.bootrom_base =
0x1FF00000, // "System memory" starting address (Table 6)
.bootrom_size = 0x20000, // "System memory" byte size in hex (Table 6)
.option_base = STM32_H7_OPTION_BYTES_BASE,
.option_size = 44,
.flags = CHIP_F_HAS_SWO_TRACING,
@ -712,13 +757,13 @@ static const struct stlink_chipid_params devices[] = {
};
const struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid) {
const struct stlink_chipid_params *params = NULL;
const struct stlink_chipid_params *params = NULL;
for (size_t n = 0; n < STLINK_ARRAY_SIZE(devices); n++)
if (devices[n].chip_id == chipid) {
params = &devices[n];
break;
}
for (size_t n = 0; n < STLINK_ARRAY_SIZE(devices); n++)
if (devices[n].chip_id == chipid) {
params = &devices[n];
break;
}
return(params);
return (params);
}