From bff61510b154efd1759bf99dd87c98c8c9cfcaa8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?L=C3=A9o=20DUBOIN?= Date: Thu, 8 Aug 2024 19:34:15 +0200 Subject: [PATCH] STM32Gx: flash: clear programming mode before erasing As described in 3.3.8, if erasing while another mode's "enable" bit is set, a programming sequence error will be raised. This change makes sure this will not happen for an erase operation. --- src/stlink-lib/common_flash.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/stlink-lib/common_flash.c b/src/stlink-lib/common_flash.c index 726f263..70d3e7d 100644 --- a/src/stlink-lib/common_flash.c +++ b/src/stlink-lib/common_flash.c @@ -1122,6 +1122,10 @@ int32_t stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { stlink_read_debug32(sl, FLASH_Gx_CR, &val); // sec 3.7.5 - PNB[9:0] is offset by 3. PER is 0x2. val &= ~(0x7FF << 3); + // sec 3.3.8 - Error PGSERR + // * In the page erase sequence: PG, FSTPG and MER1 are not cleared when PER is set + val &= ~(1 << FLASH_Gx_CR_MER1 | 1 << FLASH_Gx_CR_MER2); + val &= ~(1 << FLASH_Gx_CR_PG); // Products of the Gx series with more than 128K of flash use 2 banks. // In this case we need to specify which bank to erase (sec 3.7.5 - BKER) if (sl->flash_size > (128 * 1024) &&