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STM32F76xxx: Added flashing in dual bank mode 

(Closes #1174)
pull/1373/head
nightwalker-87 2023-11-27 22:00:27 +01:00
rodzic 4637b1497b
commit ba335a47ab
6 zmienionych plików z 145 dodań i 52 usunięć
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28
inc/stlink.h
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@ -199,23 +199,23 @@ struct _stlink {
// transport layer verboseness: 0 for no debug info, 10 for lots
int32_t verbose;
int32_t opt;
uint32_t core_id; // set by stlink_core_id(), result from STLINK_DEBUGREADCOREID
uint32_t chip_id; // set by stlink_load_device_params(), used to identify flash and sram
enum target_state core_stat; // set by stlink_status()
uint32_t core_id; // set by stlink_core_id(), result from STLINK_DEBUGREADCOREID
uint32_t chip_id; // set by stlink_load_device_params(), used to identify flash and sram
enum target_state core_stat; // set by stlink_status()
char serial[STLINK_SERIAL_BUFFER_SIZE];
int32_t freq; // set by stlink_open_usb(), values: STLINK_SWDCLK_xxx_DIVISOR
int32_t freq; // set by stlink_open_usb(), values: STLINK_SWDCLK_xxx_DIVISOR
enum stm32_flash_type flash_type;
// stlink_chipid_params.flash_type, set by stlink_load_device_params(), values: STM32_FLASH_TYPE_xx
stm32_addr_t flash_base; // STM32_FLASH_BASE, set by stlink_load_device_params()
uint32_t flash_size; // calculated by stlink_load_device_params()
uint32_t flash_pgsz; // stlink_chipid_params.flash_pagesize, set by stlink_load_device_params()
stm32_addr_t flash_base; // STM32_FLASH_BASE, set by stlink_load_device_params()
uint32_t flash_size; // calculated by stlink_load_device_params()
uint32_t flash_pgsz; // stlink_chipid_params.flash_pagesize, set by stlink_load_device_params()
/* sram settings */
stm32_addr_t sram_base; // STM32_SRAM_BASE, set by stlink_load_device_params()
uint32_t sram_size; // stlink_chipid_params.sram_size, set by stlink_load_device_params()
stm32_addr_t sram_base; // STM32_SRAM_BASE, set by stlink_load_device_params()
uint32_t sram_size; // stlink_chipid_params.sram_size, set by stlink_load_device_params()
/* option settings */
stm32_addr_t option_base;
@ -224,14 +224,16 @@ struct _stlink {
// bootloader
// sys_base and sys_size are not used by the tools, but are only there to download the bootloader code
// (see tests/sg.c)
stm32_addr_t sys_base; // stlink_chipid_params.bootrom_base, set by stlink_load_device_params()
uint32_t sys_size; // stlink_chipid_params.bootrom_size, set by stlink_load_device_params()
stm32_addr_t sys_base; // stlink_chipid_params.bootrom_base, set by stlink_load_device_params()
uint32_t sys_size; // stlink_chipid_params.bootrom_size, set by stlink_load_device_params()
struct stlink_version_ version;
uint32_t chip_flags; // stlink_chipid_params.flags, set by stlink_load_device_params(), values: CHIP_F_xxx
uint32_t chip_flags; // stlink_chipid_params.flags, set by stlink_load_device_params(), values: CHIP_F_xxx
uint32_t max_trace_freq; // set by stlink_open_usb()
uint32_t max_trace_freq; // set by stlink_open_usb()
bool dual_bank; // set for F7xxx devices by reading optcr
uint32_t otp_base;
uint32_t otp_size;

59
inc/stm32flash.h
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@ -142,6 +142,7 @@
#define FLASH_F7_OPTCR_START 1
#define FLASH_F7_OPTCR1_BOOT_ADD0 0
#define FLASH_F7_OPTCR1_BOOT_ADD1 16
#define FLASH_F7_OPTCR_DBANK (29) /* FLASH_OPTCR Dual Bank Mode */
// F7 Flash control register
#define FLASH_F7_CR_STRT 16
@ -152,12 +153,12 @@
// F7 Flash status register
#define FLASH_F7_SR_BSY 16
#define FLASH_F7_SR_ERS_ERR 7 /* Erase Sequence Error */
#define FLASH_F7_SR_PGP_ERR 6 /* Programming parallelism error */
#define FLASH_F7_SR_PGA_ERR 5 /* Programming alignment error */
#define FLASH_F7_SR_WRP_ERR 4 /* Write protection error */
#define FLASH_F7_SR_OP_ERR 1 /* Operation error */
#define FLASH_F7_SR_EOP 0 /* End of operation */
#define FLASH_F7_SR_ERS_ERR 7 /* Erase Sequence Error */
#define FLASH_F7_SR_PGP_ERR 6 /* Programming parallelism error */
#define FLASH_F7_SR_PGA_ERR 5 /* Programming alignment error */
#define FLASH_F7_SR_WRP_ERR 4 /* Write protection error */
#define FLASH_F7_SR_OP_ERR 1 /* Operation error */
#define FLASH_F7_SR_EOP 0 /* End of operation */
#define FLASH_F7_SR_ERROR_MASK \
((1 << FLASH_F7_SR_ERS_ERR) | (1 << FLASH_F7_SR_PGP_ERR) | \
(1 << FLASH_F7_SR_PGA_ERR) | (1 << FLASH_F7_SR_WRP_ERR) | \
@ -196,8 +197,8 @@
#define FLASH_Gx_SR_PROGERR (3)
#define FLASH_Gx_SR_WRPERR (4)
#define FLASH_Gx_SR_PGAERR (5)
#define FLASH_Gx_SR_BSY (16) /* FLASH_SR Busy */
#define FLASH_Gx_SR_EOP (0) /* FLASH_EOP End of Operation */
#define FLASH_Gx_SR_BSY (16) /* FLASH_SR Busy */
#define FLASH_Gx_SR_EOP (0) /* FLASH_EOP End of Operation */
// == STM32G0 == (RM0444 Table 1, sec. 3.7)
// Mostly the same as G4 chips, but the notation
@ -272,8 +273,8 @@
#define FLASH_H7_SR_WRPERR 17
#define FLASH_H7_SR_PGSERR 18
#define FLASH_H7_SR_STRBERR 19
#define FLASH_H7_SR_ERROR_MASK \
((1 << FLASH_H7_SR_PGSERR) | (1 << FLASH_H7_SR_STRBERR) | \
#define FLASH_H7_SR_ERROR_MASK \
((1 << FLASH_H7_SR_PGSERR) | (1 << FLASH_H7_SR_STRBERR) | \
(1 << FLASH_H7_SR_WRPERR))
// == STM32L0/L1/L4/L5 ==
@ -332,27 +333,27 @@
#define FLASH_L4_OPTR (FLASH_REGS_ADDR + 0x20)
// L4 Flash status register
#define FLASH_L4_SR_ERROR_MASK 0x3f8 /* SR [9:3] */
#define FLASH_L4_SR_ERROR_MASK 0x3f8 // SR [9:3]
#define FLASH_L4_SR_PROGERR 3
#define FLASH_L4_SR_WRPERR 4
#define FLASH_L4_SR_PGAERR 5
#define FLASH_L4_SR_BSY 16
// L4 Flash control register
#define FLASH_L4_CR_LOCK 31 /* Lock control register */
#define FLASH_L4_CR_OPTLOCK 30 /* Lock option bytes */
#define FLASH_L4_CR_PG 0 /* Program */
#define FLASH_L4_CR_PER 1 /* Page erase */
#define FLASH_L4_CR_MER1 2 /* Bank 1 erase */
#define FLASH_L4_CR_MER2 15 /* Bank 2 erase */
#define FLASH_L4_CR_STRT 16 /* Start command */
#define FLASH_L4_CR_OPTSTRT 17 /* Start writing option bytes */
#define FLASH_L4_CR_BKER 11 /* Bank select for page erase */
#define FLASH_L4_CR_PNB 3 /* Page number (8 bits) */
#define FLASH_L4_CR_OBL_LAUNCH 27 /* Option bytes reload */
#define FLASH_L4_CR_LOCK 31 /* Lock control register */
#define FLASH_L4_CR_OPTLOCK 30 /* Lock option bytes */
#define FLASH_L4_CR_PG 0 /* Program */
#define FLASH_L4_CR_PER 1 /* Page erase */
#define FLASH_L4_CR_MER1 2 /* Bank 1 erase */
#define FLASH_L4_CR_MER2 15 /* Bank 2 erase */
#define FLASH_L4_CR_STRT 16 /* Start command */
#define FLASH_L4_CR_OPTSTRT 17 /* Start writing option bytes */
#define FLASH_L4_CR_BKER 11 /* Bank select for page erase */
#define FLASH_L4_CR_PNB 3 /* Page number (8 bits) */
#define FLASH_L4_CR_OBL_LAUNCH 27 /* Option bytes reload */
// Bits requesting flash operations (useful when we want to clear them)
#define FLASH_L4_CR_OPBITS \
(uint32_t)((1lu << FLASH_L4_CR_PG) | (1lu << FLASH_L4_CR_PER) | \
#define FLASH_L4_CR_OPBITS \
(uint32_t)((1lu << FLASH_L4_CR_PG) | (1lu << FLASH_L4_CR_PER) | \
(1lu << FLASH_L4_CR_MER1) | (1lu << FLASH_L4_CR_MER1))
// Page is fully specified by BKER and PNB
#define FLASH_L4_CR_PAGEMASK (uint32_t)(0x1fflu << FLASH_L4_CR_PNB)
@ -428,10 +429,10 @@
#define FLASH_WB_CR_LOCK (31) /* Lock */
// WB Flash status register
#define FLASH_WB_SR_ERROR_MASK (0x3f8) /* SR [9:3] */
#define FLASH_WB_SR_PROGERR (3) /* Programming alignment error */
#define FLASH_WB_SR_WRPERR (4) /* Write protection error */
#define FLASH_WB_SR_PGAERR (5) /* Programming error */
#define FLASH_WB_SR_BSY (16) /* Busy */
#define FLASH_WB_SR_ERROR_MASK (0x3f8) // SR [9:3]
#define FLASH_WB_SR_PROGERR (3) /* Programming alignment error */
#define FLASH_WB_SR_WRPERR (4) /* Write protection error */
#define FLASH_WB_SR_PGAERR (5) /* Programming error */
#define FLASH_WB_SR_BSY (16) /* Busy */
#endif // STM32FLASH_H

8
src/stlink-lib/calculate.c
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@ -36,7 +36,7 @@ uint32_t calculate_F4_sectornum(uint32_t flashaddr) {
}
}
uint32_t calculate_F7_sectornum(uint32_t flashaddr) {
uint32_t calculate_F7_sectornum_old(uint32_t flashaddr) {
flashaddr &= ~STM32_FLASH_BASE; // Page now holding the actual flash address
if (flashaddr < 0x20000) {
@ -49,10 +49,8 @@ uint32_t calculate_F7_sectornum(uint32_t flashaddr) {
}
uint32_t calculate_H7_sectornum(stlink_t *sl, uint32_t flashaddr, uint32_t bank) {
flashaddr &=
~((bank == BANK_1)
? STM32_FLASH_BASE
: STM32_H7_FLASH_BANK2_BASE); // sector holding the flash address
// sector holding the flash address
flashaddr &= ~((bank == BANK_1) ? STM32_FLASH_BASE : STM32_H7_FLASH_BANK2_BASE);
return (flashaddr / sl->flash_pgsz);
}

94
src/stlink-lib/common.c
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@ -318,6 +318,19 @@ int32_t stlink_load_device_params(stlink_t *sl) {
}
}
// F76xxx device with dual bank
if (sl->chip_id == STM32_CHIPID_F76xxx) {
// Check the nDBANK bit in OPTCR
uint32_t optcr;
stlink_read_option_control_register32(sl, & optcr);
if (!(optcr & (1 << STM32F7_FLASH_OPTCR_DBANK)))
{
sl->dual_bank = true;
}
DLOG("*** stm32f76xx dual-bank %d ***\n", sl->dual_bank);
}
// H7 devices with small flash has one bank
if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK &&
sl->flash_type == STM32_FLASH_TYPE_H7) {
@ -830,8 +843,87 @@ int32_t write_buffer_to_sram(stlink_t *sl, flash_loader_t *fl, const uint8_t *bu
return (ret);
}
/* STM32F7 Series Flash memory dual bank mode
* See application note AN4826 pp.18
*/
struct sectors_f7 {
int sector;
uint32_t base;
uint32_t size;
};
static const struct sectors_f7 f7_single[] = {
{ 0, 0x08000000, 0x8000 },
{ 1, 0x08008000, 0x8000 },
{ 2, 0x08010000, 0x8000 },
{ 3, 0x08018000, 0x8000 },
{ 4, 0x08020000, 0x20000 },
{ 5, 0x08040000, 0x40000 },
{ 6, 0x08080000, 0x40000 },
{ 7, 0x080C0000, 0x40000 },
{ 0, 0, 0 },
};
static const struct sectors_f7 f7_dual[] = {
{ 0, 0x08000000, 0x4000 },
{ 1, 0x08004000, 0x4000 },
{ 2, 0x08008000, 0x4000 },
{ 3, 0x0800C000, 0x4000 },
{ 4, 0x08010000, 0x10000 },
{ 5, 0x08020000, 0x20000 },
{ 6, 0x08040000, 0x20000 },
{ 7, 0x08060000, 0x20000 },
{ 8, 0x08080000, 0x20000 },
{ 9, 0x080A0000, 0x20000 },
{ 10, 0x080C0000, 0x20000 },
{ 11, 0x080E0000, 0x20000 },
{ 12, 0x08100000, 0x4000 },
{ 13, 0x08104000, 0x4000 },
{ 14, 0x08108000, 0x4000 },
{ 15, 0x0810C000, 0x4000 },
{ 16, 0x08110000, 0x10000 },
{ 17, 0x08120000, 0x20000 },
{ 18, 0x08140000, 0x20000 },
{ 19, 0x08160000, 0x20000 },
{ 20, 0x08180000, 0x20000 },
{ 21, 0x081A0000, 0x20000 },
{ 22, 0x081C0000, 0x20000 },
{ 23, 0x081E0000, 0x20000 },
{ 0, 0, 0 },
};
static const struct sectors_f7 *get_f7_info(stlink_t *sl) {
return sl->dual_bank ? f7_dual : f7_single;
}
static const struct sectors_f7 *find_sector(stlink_t *sl, uint32_t flashaddr) {
for (const struct sectors_f7 *s = get_f7_info(sl); s->base; s++) {
const uint32_t end = s->base + s->size;
if ((s->base <= flashaddr) && (flashaddr < end)) {
return s;
}
}
fprintf(stderr, "Bad address %#x\n", flashaddr);
exit(0);
}
uint32_t calculate_F7_sectornum(stlink_t *sl, uint32_t flashaddr) {
if (sl->chip_id == STM32_CHIPID_F76xxx) {
const struct sectors_f7 *s = find_sector(sl, flashaddr);
return s->sector;
}
return calculate_F7_sectornum_old(flashaddr);
}
// 291
uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr) {
if (sl->chip_id == STM32_CHIPID_F76xxx) {
const struct sectors_f7 *s = find_sector(sl, flashaddr);
return s->size;
}
if ((sl->chip_id == STM32_CHIPID_F2) ||
(sl->chip_id == STM32_CHIPID_F4) ||
(sl->chip_id == STM32_CHIPID_F4_DE) ||
@ -857,7 +949,7 @@ uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr) {
}
} else if (sl->chip_id == STM32_CHIPID_F7 ||
sl->chip_id == STM32_CHIPID_F76xxx) {
uint32_t sector = calculate_F7_sectornum(flashaddr);
uint32_t sector = calculate_F7_sectornum(sl, flashaddr);
if (sector < 4) {
sl->flash_pgsz = 0x8000;

4
src/stlink-lib/common_flash.c
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@ -145,7 +145,7 @@ static inline int32_t write_flash_sr(stlink_t *sl, uint32_t bank, uint32_t val)
} else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) {
sr_reg = FLASH_F4_SR;
} else if (sl->flash_type == STM32_FLASH_TYPE_F7) {
sr_reg = FLASH_F7_SR;
sr_reg = (bank == BANK_1) ? FLASH_F7_SR1 : FLASH_F7_SR2;
} else if (sl->flash_type == STM32_FLASH_TYPE_G0 ||
sl->flash_type == STM32_FLASH_TYPE_G4) {
sr_reg = FLASH_Gx_SR;
@ -1025,7 +1025,7 @@ int32_t stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) {
} else if (sl->chip_id == STM32_CHIPID_F7 ||
sl->chip_id == STM32_CHIPID_F76xxx) {
// calculate the actual page from the address
uint32_t sector = calculate_F7_sectornum(flashaddr);
uint32_t sector = calculate_F7_sectornum(sl, flashaddr);
fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x ", sector,
stlink_calculate_pagesize(sl, flashaddr));

4
src/stlink-lib/flash_loader.c
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@ -363,7 +363,7 @@ int32_t stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t t
/* Run loader */
stlink_run(sl, RUN_FLASH_LOADER);
/*
/*
* This piece of code used to try to spin for .1 second by waiting doing 10000 rounds of 10 µs.
* But because this usually runs on Unix-like OSes, the 10 µs get rounded up to the "tick"
* (actually almost two ticks) of the system. 1 ms. Thus, the ten thousand attempts, when
@ -393,7 +393,7 @@ int32_t stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t t
// check written byte count
stlink_read_reg(sl, 2, &rr);
/*
/*
* The chunk size for loading is not rounded. The flash loader
* subtracts the size of the written block (1-8 bytes) from
* the remaining size each time. A negative value may mean that