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Restructuring of stlink-lib 

- Renamed #defines in stm32_register.h
- Updated note on ldconfig in compiling.md
- Minor formatting fixes
pull/1453/head
nightwalker-87 2025-01-12 17:32:54 +01:00
rodzic 8654988ad2
commit b9bef5c3dc
10 zmienionych plików z 247 dodań i 250 usunięć
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5
doc/compiling.md
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@ -119,13 +119,10 @@ or execute (Debian-based systems only): `apt-get install gcc build-essential cma
5. Run `make debug` to create the _Debug_ target (_optional_)<br />
The debug target is only necessary in order to modify the sources and to run under a debugger.
6. Run `make package`to build a Debian Package. The generated packages can be found in the subdirectory `./build/Release/dist`.
7. Installing system-wide (`sudo make install`) requires the dynamic library cache to be updated with `sudo ldconfig` afterwards.
As an option you may also install to an individual user-defined folder e.g `$HOME` with `make install DESTDIR=$HOME`.
### How to avoid the error message: "Can not open shared object file"
When installing system-wide (`sudo make install`) the dynamic library cache needs to be updated with the command `ldconfig`.
#### Removal:
1. Run `make uninstall` to perform a clean uninstall of the package from the system.

194
inc/stm32_register.h
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@ -7,126 +7,126 @@
#ifndef STM32_REGISTER_H
#define STM32_REGISTER_H
#define STLINK_REG_CM3_CPUID 0xE000ED00
#define STM32_REG_CM3_CPUID 0xe000ed00
#define STLINK_REG_CMx_CPUID_PARTNO_CM0 0xC20
#define STLINK_REG_CMx_CPUID_PARTNO_CM0P 0xC60
#define STLINK_REG_CMx_CPUID_PARTNO_CM3 0xC23
#define STLINK_REG_CMx_CPUID_PARTNO_CM4 0xC24
#define STLINK_REG_CMx_CPUID_PARTNO_CM7 0xC27
#define STLINK_REG_CMx_CPUID_PARTNO_CM33 0xD21
#define STLINK_REG_CMx_CPUID_IMPL_ARM 0x41
#define STM32_REG_CMx_CPUID_PARTNO_CM0 0xc20
#define STM32_REG_CMx_CPUID_PARTNO_CM0P 0xc60
#define STM32_REG_CMx_CPUID_PARTNO_CM3 0xc23
#define STM32_REG_CMx_CPUID_PARTNO_CM4 0xc24
#define STM32_REG_CMx_CPUID_PARTNO_CM7 0xc27
#define STM32_REG_CMx_CPUID_PARTNO_CM33 0xd21
#define STM32_REG_CMx_CPUID_IMPL_ARM 0x41
#define STLINK_REG_CM3_FP_CTRL 0xE0002000 // Flash Patch Control Register
#define STLINK_REG_CM3_FP_COMPn(n) (0xE0002008 + n*4)
#define STLINK_REG_CM3_FP_CTRL_KEY (1 << 1)
#define STLINK_REG_CM7_FP_LAR 0xE0000FB0
#define STLINK_REG_CM7_FP_LAR_KEY 0xC5ACCE55
#define STM32_REG_CM3_FP_CTRL 0xe0002000 // Flash Patch Control Register
#define STM32_REG_CM3_FP_COMPn(n) (0xe0002008 + n * 4)
#define STM32_REG_CM3_FP_CTRL_KEY (1 << 1)
#define STM32_REG_CM7_FP_LAR 0xe0000fb0
#define STM32_REG_CM7_FP_LAR_KEY 0xc5acce55
#define STLINK_REG_CM3_DEMCR 0xE000EDFC
#define STLINK_REG_CM3_DEMCR_TRCENA (1 << 24)
#define STLINK_REG_CM3_DEMCR_VC_HARDERR (1 << 10)
#define STLINK_REG_CM3_DEMCR_VC_BUSERR (1 << 8)
#define STLINK_REG_CM3_DEMCR_VC_CORERESET (1 << 0)
#define STLINK_REG_CM3_DWT_COMPn(n) (0xE0001020 + n*16)
#define STLINK_REG_CM3_DWT_MASKn(n) (0xE0001024 + n*16)
#define STLINK_REG_CM3_DWT_FUNn(n) (0xE0001028 + n*16)
#define STM32_REG_CM3_DEMCR 0xe000edfc
#define STM32_REG_CM3_DEMCR_TRCENA (1 << 24)
#define STM32_REG_CM3_DEMCR_VC_HARDERR (1 << 10)
#define STM32_REG_CM3_DEMCR_VC_BUSERR (1 << 8)
#define STM32_REG_CM3_DEMCR_VC_CORERESET (1 << 0)
#define STM32_REG_CM3_DWT_COMPn(n) (0xe0001020 + n * 16)
#define STM32_REG_CM3_DWT_MASKn(n) (0xe0001024 + n * 16)
#define STM32_REG_CM3_DWT_FUNn(n) (0xe0001028 + n * 16)
/* Cortex™-M3 Technical Reference Manual */
/* Configurable Fault Status Register */
#define STLINK_REG_CFSR 0xE000ED28
#define STM32_REG_CFSR 0xe000ed28
/* Hard Fault Status Register */
#define STLINK_REG_HFSR 0xE000ED2C
#define STM32_REG_HFSR 0xe000ed2c
/* Debug Halting Control and Status Register */
#define STLINK_REG_DFSR 0xE000ED30
#define STLINK_REG_DFSR_HALT (1 << 0)
#define STLINK_REG_DFSR_BKPT (1 << 1)
#define STLINK_REG_DFSR_VCATCH (1 << 3)
#define STLINK_REG_DFSR_EXTERNAL (1 << 4)
#define STLINK_REG_DFSR_CLEAR 0x0000001F
#define STLINK_REG_DHCSR 0xe000edf0
#define STLINK_REG_DHCSR_DBGKEY (0xA05F << 16)
#define STLINK_REG_DHCSR_C_DEBUGEN (1 << 0)
#define STLINK_REG_DHCSR_C_HALT (1 << 1)
#define STLINK_REG_DHCSR_C_STEP (1 << 2)
#define STLINK_REG_DHCSR_C_MASKINTS (1 << 3)
#define STLINK_REG_DHCSR_S_REGRDY (1 << 16)
#define STLINK_REG_DHCSR_S_HALT (1 << 17)
#define STLINK_REG_DHCSR_S_SLEEP (1 << 18)
#define STLINK_REG_DHCSR_S_LOCKUP (1 << 19)
#define STLINK_REG_DHCSR_S_RETIRE_ST (1 << 24)
#define STLINK_REG_DHCSR_S_RESET_ST (1 << 25)
#define STLINK_REG_DCRSR 0xe000edf4
#define STLINK_REG_DCRDR 0xe000edf8
#define STLINK_REG_DEMCR 0xe000edfc
#define STLINK_REG_DEMCR_TRCENA (1 << 24)
#define STM32_REG_DFSR 0xe000ed30
#define STM32_REG_DFSR_HALT (1 << 0)
#define STM32_REG_DFSR_BKPT (1 << 1)
#define STM32_REG_DFSR_VCATCH (1 << 3)
#define STM32_REG_DFSR_EXTERNAL (1 << 4)
#define STM32_REG_DFSR_CLEAR 0x0000001f
#define STM32_REG_DHCSR 0xe000edf0
#define STM32_REG_DHCSR_DBGKEY (0xa05f << 16)
#define STM32_REG_DHCSR_C_DEBUGEN (1 << 0)
#define STM32_REG_DHCSR_C_HALT (1 << 1)
#define STM32_REG_DHCSR_C_STEP (1 << 2)
#define STM32_REG_DHCSR_C_MASKINTS (1 << 3)
#define STM32_REG_DHCSR_S_REGRDY (1 << 16)
#define STM32_REG_DHCSR_S_HALT (1 << 17)
#define STM32_REG_DHCSR_S_SLEEP (1 << 18)
#define STM32_REG_DHCSR_S_LOCKUP (1 << 19)
#define STM32_REG_DHCSR_S_RETIRE_ST (1 << 24)
#define STM32_REG_DHCSR_S_RESET_ST (1 << 25)
#define STM32_REG_DCRSR 0xe000edf4
#define STM32_REG_DCRDR 0xe000edf8
#define STM32_REG_DEMCR 0xe000edfc
#define STM32_REG_DEMCR_TRCENA (1 << 24)
/* MCU Debug Component Registers */
#define STLINK_REG_DBGMCU_CR 0xE0042004 // Debug MCU Configuration Register
#define STLINK_REG_DBGMCU_CR_DBG_SLEEP (1 << 0)
#define STLINK_REG_DBGMCU_CR_DBG_STOP (1 << 1)
#define STLINK_REG_DBGMCU_CR_DBG_STANDBY (1 << 2)
#define STLINK_REG_DBGMCU_CR_TRACE_IOEN (1 << 5)
#define STLINK_REG_DBGMCU_CR_TRACE_MODE_ASYNC (0x00 << 6)
#define STM32_REG_DBGMCU_CR 0xe0042004 // Debug MCU Configuration Register
#define STM32_REG_DBGMCU_CR_DBG_SLEEP (1 << 0)
#define STM32_REG_DBGMCU_CR_DBG_STOP (1 << 1)
#define STM32_REG_DBGMCU_CR_DBG_STANDBY (1 << 2)
#define STM32_REG_DBGMCU_CR_TRACE_IOEN (1 << 5)
#define STM32_REG_DBGMCU_CR_TRACE_MODE_ASYNC (0x00 << 6)
/* Data Watchpoint and Trace (DWT) Registers */
#define STLINK_REG_DWT_CTRL 0xE0001000 // DWT Control Register
#define STLINK_REG_DWT_CTRL_NUM_COMP (1 << 28)
#define STLINK_REG_DWT_CTRL_CYC_TAP (1 << 9)
#define STLINK_REG_DWT_CTRL_POST_INIT (1 << 5)
#define STLINK_REG_DWT_CTRL_POST_PRESET (1 << 1)
#define STLINK_REG_DWT_CTRL_CYCCNT_ENA (1 << 0)
#define STLINK_REG_DWT_FUNCTION0 0xE0001028 // DWT Function Register 0
#define STLINK_REG_DWT_FUNCTION1 0xE0001038 // DWT Function Register 1
#define STLINK_REG_DWT_FUNCTION2 0xE0001048 // DWT Function Register 2
#define STLINK_REG_DWT_FUNCTION3 0xE0001058 // DWT Function Register 3
#define STM32_REG_DWT_CTRL 0xe0001000 // DWT Control Register
#define STM32_REG_DWT_CTRL_NUM_COMP (1 << 28)
#define STM32_REG_DWT_CTRL_CYC_TAP (1 << 9)
#define STM32_REG_DWT_CTRL_POST_INIT (1 << 5)
#define STM32_REG_DWT_CTRL_POST_PRESET (1 << 1)
#define STM32_REG_DWT_CTRL_CYCCNT_ENA (1 << 0)
#define STM32_REG_DWT_FUNCTION0 0xe0001028 // DWT Function Register 0
#define STM32_REG_DWT_FUNCTION1 0xe0001038 // DWT Function Register 1
#define STM32_REG_DWT_FUNCTION2 0xe0001048 // DWT Function Register 2
#define STM32_REG_DWT_FUNCTION3 0xe0001058 // DWT Function Register 3
/* Instrumentation Trace Macrocell (ITM) Registers */
#define STLINK_REG_ITM_TER 0xE0000E00 // ITM Trace Enable Register
#define STLINK_REG_ITM_TER_PORTS_ALL (0xFFFFFFFF)
#define STLINK_REG_ITM_TPR 0xE0000E40 // ITM Trace Privilege Register
#define STLINK_REG_ITM_TPR_PORTS_ALL (0x0F)
#define STLINK_REG_ITM_TCR 0xE0000E80 // ITM Trace Control Register
#define STLINK_REG_ITM_TCR_TRACE_BUS_ID_1 (0x01 << 16)
#define STLINK_REG_ITM_TCR_SWO_ENA (1 << 4)
#define STLINK_REG_ITM_TCR_DWT_ENA (1 << 3)
#define STLINK_REG_ITM_TCR_SYNC_ENA (1 << 2)
#define STLINK_REG_ITM_TCR_TS_ENA (1 << 1)
#define STLINK_REG_ITM_TCR_ITM_ENA (1 << 0)
#define STLINK_REG_ITM_TCC 0xE0000E90 // ITM Trace Cycle Count
#define STLINK_REG_ITM_LAR 0xE0000FB0 // ITM Lock Access Register
#define STLINK_REG_ITM_LAR_KEY 0xC5ACCE55
#define STM32_REG_ITM_TER 0xe0000e00 // ITM Trace Enable Register
#define STM32_REG_ITM_TER_PORTS_ALL (0xffffffff)
#define STM32_REG_ITM_TPR 0xe0000e40 // ITM Trace Privilege Register
#define STM32_REG_ITM_TPR_PORTS_ALL (0x0f)
#define STM32_REG_ITM_TCR 0xe0000e80 // ITM Trace Control Register
#define STM32_REG_ITM_TCR_TRACE_BUS_ID_1 (0x01 << 16)
#define STM32_REG_ITM_TCR_SWO_ENA (1 << 4)
#define STM32_REG_ITM_TCR_DWT_ENA (1 << 3)
#define STM32_REG_ITM_TCR_SYNC_ENA (1 << 2)
#define STM32_REG_ITM_TCR_TS_ENA (1 << 1)
#define STM32_REG_ITM_TCR_ITM_ENA (1 << 0)
#define STM32_REG_ITM_TCC 0xe0000e90 // ITM Trace Cycle Count
#define STM32_REG_ITM_LAR 0xe0000fb0 // ITM Lock Access Register
#define STM32_REG_ITM_LAR_KEY 0xc5acce55
/* Trace Port Interface (TPI) Registers */
#define STLINK_REG_TPI_CSPSR 0xE0040004 // TPI Current Parallel Port Size Reg
#define STLINK_REG_TPI_CSPSR_PORT_SIZE_1 (0x01 << 0)
#define STLINK_REG_TPI_ACPR 0xE0040010 // TPI Async Clock Prescaler Register
#define STLINK_REG_TPI_ACPR_MAX (0x1FFF)
#define STLINK_REG_TPI_SPPR 0xE00400F0 // TPI Selected Pin Protocol Register
#define STLINK_REG_TPI_SPPR_SWO_MANCHESTER (0x01 << 0)
#define STLINK_REG_TPI_SPPR_SWO_NRZ (0x02 << 0)
#define STLINK_REG_TPI_FFCR 0xE0040304 // TPI Formatter and Flush Control Register
#define STLINK_REG_TPI_FFCR_TRIG_IN (0x01 << 8)
#define STM32_REG_TPI_CSPSR 0xe0040004 // TPI Current Parallel Port Size Reg
#define STM32_REG_TPI_CSPSR_PORT_SIZE_1 (0x01 << 0)
#define STM32_REG_TPI_ACPR 0xe0040010 // TPI Async Clock Prescaler Register
#define STM32_REG_TPI_ACPR_MAX (0x1fff)
#define STM32_REG_TPI_SPPR 0xe00400f0 // TPI Selected Pin Protocol Register
#define STM32_REG_TPI_SPPR_SWO_MANCHESTER (0x01 << 0)
#define STM32_REG_TPI_SPPR_SWO_NRZ (0x02 << 0)
#define STM32_REG_TPI_FFCR 0xe0040304 // TPI Formatter and Flush Control Register
#define STM32_REG_TPI_FFCR_TRIG_IN (0x01 << 8)
/* Application Interrupt and Reset Control Register */
#define STLINK_REG_AIRCR 0xe000ed0c
#define STLINK_REG_AIRCR_VECTKEY 0x05fa0000
#define STLINK_REG_AIRCR_SYSRESETREQ 0x00000004
#define STLINK_REG_AIRCR_VECTRESET 0x00000001
#define STM32_REG_AIRCR 0xe000ed0c
#define STM32_REG_AIRCR_VECTKEY 0x05fa0000
#define STM32_REG_AIRCR_SYSRESETREQ 0x00000004
#define STM32_REG_AIRCR_VECTRESET 0x00000001
/* ARM Cortex-M7 Processor Technical Reference Manual */
/* Cache Control and Status Register */
#define STLINK_REG_CM7_CTR 0xE000ED7C
#define STLINK_REG_CM7_CLIDR 0xE000ED78
#define STLINK_REG_CM7_CCR 0xE000ED14
#define STLINK_REG_CM7_CCR_DC (1 << 16)
#define STLINK_REG_CM7_CCR_IC (1 << 17)
#define STLINK_REG_CM7_CSSELR 0xE000ED84
#define STLINK_REG_CM7_DCCSW 0xE000EF6C
#define STLINK_REG_CM7_ICIALLU 0xE000EF50
#define STLINK_REG_CM7_CCSIDR 0xE000ED80
#define STM32_REG_CM7_CTR 0xe000ed7c
#define STM32_REG_CM7_CLIDR 0xe000ed78
#define STM32_REG_CM7_CCR 0xe000ed14
#define STM32_REG_CM7_CCR_DC (1 << 16)
#define STM32_REG_CM7_CCR_IC (1 << 17)
#define STM32_REG_CM7_CSSELR 0xe000ed84
#define STM32_REG_CM7_DCCSW 0xe000ef6c
#define STM32_REG_CM7_ICIALLU 0xe000ef50
#define STM32_REG_CM7_CCSIDR 0xe000ed80
#endif // STM32_REGISTER_H

84
src/st-trace/trace.c
Wyświetl plik

@ -258,63 +258,63 @@ static bool enable_trace(stlink_t *stlink, const st_settings_t *settings, uint32
if (!settings->force) return false;
}
stlink_write_debug32(stlink, STLINK_REG_DHCSR,
STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_DEBUGEN |
STLINK_REG_DHCSR_C_HALT);
stlink_write_debug32(stlink, STLINK_REG_DEMCR, STLINK_REG_DEMCR_TRCENA);
stlink_write_debug32(stlink, STLINK_REG_CM3_FP_CTRL,
STLINK_REG_CM3_FP_CTRL_KEY);
stlink_write_debug32(stlink, STLINK_REG_DWT_FUNCTION0, 0);
stlink_write_debug32(stlink, STLINK_REG_DWT_FUNCTION1, 0);
stlink_write_debug32(stlink, STLINK_REG_DWT_FUNCTION2, 0);
stlink_write_debug32(stlink, STLINK_REG_DWT_FUNCTION3, 0);
stlink_write_debug32(stlink, STLINK_REG_DWT_CTRL, 0);
stlink_write_debug32(stlink, STLINK_REG_DBGMCU_CR,
STLINK_REG_DBGMCU_CR_DBG_SLEEP | STLINK_REG_DBGMCU_CR_DBG_STOP |
STLINK_REG_DBGMCU_CR_DBG_STANDBY | STLINK_REG_DBGMCU_CR_TRACE_IOEN |
STLINK_REG_DBGMCU_CR_TRACE_MODE_ASYNC);
stlink_write_debug32(stlink, STM32_REG_DHCSR,
STM32_REG_DHCSR_DBGKEY | STM32_REG_DHCSR_C_DEBUGEN |
STM32_REG_DHCSR_C_HALT);
stlink_write_debug32(stlink, STM32_REG_DEMCR, STM32_REG_DEMCR_TRCENA);
stlink_write_debug32(stlink, STM32_REG_CM3_FP_CTRL,
STM32_REG_CM3_FP_CTRL_KEY);
stlink_write_debug32(stlink, STM32_REG_DWT_FUNCTION0, 0);
stlink_write_debug32(stlink, STM32_REG_DWT_FUNCTION1, 0);
stlink_write_debug32(stlink, STM32_REG_DWT_FUNCTION2, 0);
stlink_write_debug32(stlink, STM32_REG_DWT_FUNCTION3, 0);
stlink_write_debug32(stlink, STM32_REG_DWT_CTRL, 0);
stlink_write_debug32(stlink, STM32_REG_DBGMCU_CR,
STM32_REG_DBGMCU_CR_DBG_SLEEP | STM32_REG_DBGMCU_CR_DBG_STOP |
STM32_REG_DBGMCU_CR_DBG_STANDBY | STM32_REG_DBGMCU_CR_TRACE_IOEN |
STM32_REG_DBGMCU_CR_TRACE_MODE_ASYNC);
if (stlink_trace_enable(stlink, trace_frequency)) {
ELOG("Unable to turn on tracing in stlink\n");
if (!settings->force) return false;
}
stlink_write_debug32(stlink, STLINK_REG_TPI_CSPSR, STLINK_REG_TPI_CSPSR_PORT_SIZE_1);
stlink_write_debug32(stlink, STM32_REG_TPI_CSPSR, STM32_REG_TPI_CSPSR_PORT_SIZE_1);
if (settings->core_frequency) {
uint32_t prescaler = settings->core_frequency / trace_frequency - 1;
if (prescaler > STLINK_REG_TPI_ACPR_MAX) {
if (prescaler > STM32_REG_TPI_ACPR_MAX) {
ELOG("Trace frequency prescaler %d out of range. Try setting a faster "
"trace frequency.\n", prescaler);
if (!settings->force) return false;
}
stlink_write_debug32(stlink, STLINK_REG_TPI_ACPR,
stlink_write_debug32(stlink, STM32_REG_TPI_ACPR,
prescaler); // Set TPIU_ACPR clock divisor
}
stlink_write_debug32(stlink, STLINK_REG_TPI_FFCR,
STLINK_REG_TPI_FFCR_TRIG_IN);
stlink_write_debug32(stlink, STLINK_REG_TPI_SPPR,
STLINK_REG_TPI_SPPR_SWO_NRZ);
stlink_write_debug32(stlink, STLINK_REG_ITM_LAR, STLINK_REG_ITM_LAR_KEY);
stlink_write_debug32(stlink, STLINK_REG_ITM_TCC, 0x00000400); // Set sync counter
stlink_write_debug32(stlink, STLINK_REG_ITM_TCR,
STLINK_REG_ITM_TCR_TRACE_BUS_ID_1 |
STLINK_REG_ITM_TCR_TS_ENA |
STLINK_REG_ITM_TCR_ITM_ENA);
stlink_write_debug32(stlink, STLINK_REG_ITM_TER,
STLINK_REG_ITM_TER_PORTS_ALL);
stlink_write_debug32(stlink, STLINK_REG_ITM_TPR,
STLINK_REG_ITM_TPR_PORTS_ALL);
stlink_write_debug32(stlink, STLINK_REG_DWT_CTRL,
4 * STLINK_REG_DWT_CTRL_NUM_COMP |
STLINK_REG_DWT_CTRL_CYC_TAP |
0xF * STLINK_REG_DWT_CTRL_POST_INIT |
0xF * STLINK_REG_DWT_CTRL_POST_PRESET |
STLINK_REG_DWT_CTRL_CYCCNT_ENA);
stlink_write_debug32(stlink, STLINK_REG_DEMCR, STLINK_REG_DEMCR_TRCENA);
stlink_write_debug32(stlink, STM32_REG_TPI_FFCR,
STM32_REG_TPI_FFCR_TRIG_IN);
stlink_write_debug32(stlink, STM32_REG_TPI_SPPR,
STM32_REG_TPI_SPPR_SWO_NRZ);
stlink_write_debug32(stlink, STM32_REG_ITM_LAR, STM32_REG_ITM_LAR_KEY);
stlink_write_debug32(stlink, STM32_REG_ITM_TCC, 0x00000400); // Set sync counter
stlink_write_debug32(stlink, STM32_REG_ITM_TCR,
STM32_REG_ITM_TCR_TRACE_BUS_ID_1 |
STM32_REG_ITM_TCR_TS_ENA |
STM32_REG_ITM_TCR_ITM_ENA);
stlink_write_debug32(stlink, STM32_REG_ITM_TER,
STM32_REG_ITM_TER_PORTS_ALL);
stlink_write_debug32(stlink, STM32_REG_ITM_TPR,
STM32_REG_ITM_TPR_PORTS_ALL);
stlink_write_debug32(stlink, STM32_REG_DWT_CTRL,
4 * STM32_REG_DWT_CTRL_NUM_COMP |
STM32_REG_DWT_CTRL_CYC_TAP |
0xF * STM32_REG_DWT_CTRL_POST_INIT |
0xF * STM32_REG_DWT_CTRL_POST_PRESET |
STM32_REG_DWT_CTRL_CYCCNT_ENA);
stlink_write_debug32(stlink, STM32_REG_DEMCR, STM32_REG_DEMCR_TRCENA);
uint32_t prescaler = 0;
stlink_read_debug32(stlink, STLINK_REG_TPI_ACPR, &prescaler);
stlink_read_debug32(stlink, STM32_REG_TPI_ACPR, &prescaler);
if (prescaler) {
uint32_t system_clock_speed = (prescaler + 1) * trace_frequency;
ILOG("Trace Port Interface configured to expect a %d Hz system clock.\n",
@ -470,7 +470,7 @@ static void check_for_configuration_error(stlink_t *stlink, st_trace_t *trace, u
if (error_no_data || error_low_data || error_bad_data) {
uint32_t prescaler = 0;
stlink_read_debug32(stlink, STLINK_REG_TPI_ACPR, &prescaler);
stlink_read_debug32(stlink, STM32_REG_TPI_ACPR, &prescaler);
if (prescaler) {
uint32_t system_clock_speed = (prescaler + 1) * trace_frequency;
WLOG("Verify the system clock is running at %d Hz.\n", system_clock_speed);
@ -583,7 +583,7 @@ int32_t main(int32_t argc, char **argv) {
if (settings.core_frequency != 0) {
if (max_trace_freq > settings.core_frequency / 5) max_trace_freq = settings.core_frequency / 5;
min_trace_freq = settings.core_frequency / (STLINK_REG_TPI_ACPR_MAX + 1);
min_trace_freq = settings.core_frequency / (STM32_REG_TPI_ACPR_MAX + 1);
}
if (trace_frequency > max_trace_freq || trace_frequency < min_trace_freq) {
ELOG("Invalid trace frequency %d (min %d max %d)\n", trace_frequency, min_trace_freq,

58
src/st-util/gdb-server.c
Wyświetl plik

@ -425,14 +425,14 @@ static void init_data_watchpoints(stlink_t *sl) {
DLOG("init watchpoints\n");
// set TRCENA in debug command to turn on DWT unit
stlink_read_debug32(sl, STLINK_REG_CM3_DEMCR, &data);
data |= STLINK_REG_CM3_DEMCR_TRCENA;
stlink_write_debug32(sl, STLINK_REG_CM3_DEMCR, data);
stlink_read_debug32(sl, STM32_REG_CM3_DEMCR, &data);
data |= STM32_REG_CM3_DEMCR_TRCENA;
stlink_write_debug32(sl, STM32_REG_CM3_DEMCR, data);
// make sure all watchpoints are cleared
for (int32_t i = 0; i < DATA_WATCH_NUM; i++) {
data_watches[i].fun = WATCHDISABLED;
stlink_write_debug32(sl, STLINK_REG_CM3_DWT_FUNn(i), 0);
stlink_write_debug32(sl, STM32_REG_CM3_DWT_FUNn(i), 0);
}
}
@ -463,16 +463,16 @@ static int32_t add_data_watchpoint(stlink_t *sl, enum watchfun wf, stm32_addr_t
data_watches[i].mask = mask;
// insert comparator address
stlink_write_debug32(sl, STLINK_REG_CM3_DWT_COMPn(i), addr);
stlink_write_debug32(sl, STM32_REG_CM3_DWT_COMPn(i), addr);
// insert mask
stlink_write_debug32(sl, STLINK_REG_CM3_DWT_MASKn(i), mask);
stlink_write_debug32(sl, STM32_REG_CM3_DWT_MASKn(i), mask);
// insert function
stlink_write_debug32(sl, STLINK_REG_CM3_DWT_FUNn(i), wf);
stlink_write_debug32(sl, STM32_REG_CM3_DWT_FUNn(i), wf);
// just to make sure the matched bit is clear !
stlink_read_debug32(sl, STLINK_REG_CM3_DWT_FUNn(i), &dummy);
stlink_read_debug32(sl, STM32_REG_CM3_DWT_FUNn(i), &dummy);
return (0);
}
}
@ -489,7 +489,7 @@ static int32_t delete_data_watchpoint(stlink_t *sl, stm32_addr_t addr) {
DLOG("delete watchpoint %d addr %x\n", i, addr);
data_watches[i].fun = WATCHDISABLED;
stlink_write_debug32(sl, STLINK_REG_CM3_DWT_FUNn(i), 0);
stlink_write_debug32(sl, STM32_REG_CM3_DWT_FUNn(i), 0);
return (0);
}
@ -520,24 +520,24 @@ static struct code_hw_breakpoint code_breaks[CODE_BREAK_NUM_MAX];
static void init_code_breakpoints(stlink_t *sl) {
uint32_t val;
memset(sl->q_buf, 0, 4);
stlink_write_debug32(sl, STLINK_REG_CM3_FP_CTRL, 0x03 /* KEY | ENABLE */);
stlink_read_debug32(sl, STLINK_REG_CM3_FP_CTRL, &val);
stlink_write_debug32(sl, STM32_REG_CM3_FP_CTRL, 0x03 /* KEY | ENABLE */);
stlink_read_debug32(sl, STM32_REG_CM3_FP_CTRL, &val);
code_break_num = ((val >> 4) & 0xf);
code_lit_num = ((val >> 8) & 0xf);
code_break_rev = ((val >> 28) & 0xf);
ILOG("Found %i hw breakpoint registers\n", code_break_num);
stlink_read_debug32(sl, STLINK_REG_CM3_CPUID, &val);
stlink_read_debug32(sl, STM32_REG_CM3_CPUID, &val);
if (((val>>4) & 0xFFF) == 0xC27) {
// Cortex-M7 can have locked to write FP_* registers
// IHI0029D, p. 48, Lock Access Register
stlink_write_debug32(sl, STLINK_REG_CM7_FP_LAR, STLINK_REG_CM7_FP_LAR_KEY);
stlink_write_debug32(sl, STM32_REG_CM7_FP_LAR, STM32_REG_CM7_FP_LAR_KEY);
}
for (int32_t i = 0; i < code_break_num; i++) {
code_breaks[i].type = 0;
stlink_write_debug32(sl, STLINK_REG_CM3_FP_COMPn(i), 0);
stlink_write_debug32(sl, STM32_REG_CM3_FP_COMPn(i), 0);
}
}
@ -592,11 +592,11 @@ static int32_t update_code_breakpoint(stlink_t *sl, stm32_addr_t addr, int32_t s
if (bp->type == 0) {
DLOG("clearing hw break %d\n", id);
stlink_write_debug32(sl, STLINK_REG_CM3_FP_COMPn(id), 0);
stlink_write_debug32(sl, STM32_REG_CM3_FP_COMPn(id), 0);
} else {
DLOG("setting hw break %d at %08x (%d)\n", id, bp->addr, bp->type);
DLOG("reg %08x \n", mask);
stlink_write_debug32(sl, STLINK_REG_CM3_FP_COMPn(id), mask);
stlink_write_debug32(sl, STM32_REG_CM3_FP_COMPn(id), mask);
}
return (0);
@ -771,7 +771,7 @@ static void read_cache_level_desc(stlink_t *sl, struct cache_level_desc *desc) {
uint32_t ccsidr;
uint32_t log2_nsets;
stlink_read_debug32(sl, STLINK_REG_CM7_CCSIDR, &ccsidr);
stlink_read_debug32(sl, STM32_REG_CM7_CCSIDR, &ccsidr);
desc->nsets = ((ccsidr >> 13) & 0x3fff) + 1;
desc->nways = ((ccsidr >> 3) & 0x1ff) + 1;
desc->log2_nways = ceil_log2 (desc->nways);
@ -788,7 +788,7 @@ static void init_cache (stlink_t *sl) {
int32_t i;
// Check have cache
stlink_read_debug32(sl, STLINK_REG_CM7_CTR, &ctr);
stlink_read_debug32(sl, STM32_REG_CM7_CTR, &ctr);
if ((ctr >> 29) != 0x04) {
cache_desc.used = 0;
return;
@ -797,12 +797,12 @@ static void init_cache (stlink_t *sl) {
cache_desc.dminline = 4 << ((ctr >> 16) & 0x0f);
cache_desc.iminline = 4 << (ctr & 0x0f);
stlink_read_debug32(sl, STLINK_REG_CM7_CLIDR, &clidr);
stlink_read_debug32(sl, STM32_REG_CM7_CLIDR, &clidr);
cache_desc.louu = (clidr >> 27) & 7;
stlink_read_debug32(sl, STLINK_REG_CM7_CCR, &ccr);
stlink_read_debug32(sl, STM32_REG_CM7_CCR, &ccr);
ILOG("Chip clidr: %08x, I-Cache: %s, D-Cache: %s\n",
clidr, ccr & STLINK_REG_CM7_CCR_IC ? "on" : "off", ccr & STLINK_REG_CM7_CCR_DC ? "on" : "off");
clidr, ccr & STM32_REG_CM7_CCR_IC ? "on" : "off", ccr & STM32_REG_CM7_CCR_DC ? "on" : "off");
ILOG(" cache: LoUU: %u, LoC: %u, LoUIS: %u\n",
(clidr >> 27) & 7, (clidr >> 24) & 7, (clidr >> 21) & 7);
ILOG(" cache: ctr: %08x, DminLine: %u bytes, IminLine: %u bytes\n", ctr,
@ -814,13 +814,13 @@ static void init_cache (stlink_t *sl) {
cache_desc.icache[i].width = 0;
if (ct == 2 || ct == 3 || ct == 4) { // data
stlink_write_debug32(sl, STLINK_REG_CM7_CSSELR, i << 1);
stlink_write_debug32(sl, STM32_REG_CM7_CSSELR, i << 1);
ILOG("D-Cache L%d: ", i);
read_cache_level_desc(sl, &cache_desc.dcache[i]);
}
if (ct == 1 || ct == 3) { // instruction
stlink_write_debug32(sl, STLINK_REG_CM7_CSSELR, (i << 1) | 1);
stlink_write_debug32(sl, STM32_REG_CM7_CSSELR, (i << 1) | 1);
ILOG("I-Cache L%d: ", i);
read_cache_level_desc(sl, &cache_desc.icache[i]);
}
@ -830,7 +830,7 @@ static void init_cache (stlink_t *sl) {
static void cache_flush(stlink_t *sl, uint32_t ccr) {
int32_t level;
if (ccr & STLINK_REG_CM7_CCR_DC) {
if (ccr & STM32_REG_CM7_CCR_DC) {
for (level = cache_desc.louu - 1; level >= 0; level--) {
struct cache_level_desc *desc = &cache_desc.dcache[level];
uint32_t addr;
@ -842,15 +842,15 @@ static void cache_flush(stlink_t *sl, uint32_t ccr) {
uint32_t way;
for (way = 0; way < desc->nways; way++) {
stlink_write_debug32(sl, STLINK_REG_CM7_DCCSW, addr | (way << way_sh));
stlink_write_debug32(sl, STM32_REG_CM7_DCCSW, addr | (way << way_sh));
}
}
}
}
// invalidate all I-cache to oPU
if (ccr & STLINK_REG_CM7_CCR_IC) {
stlink_write_debug32(sl, STLINK_REG_CM7_ICIALLU, 0);
if (ccr & STM32_REG_CM7_CCR_IC) {
stlink_write_debug32(sl, STM32_REG_CM7_ICIALLU, 0);
}
}
@ -871,8 +871,8 @@ static void cache_sync(stlink_t *sl) {
if (!cache_modified) { return; }
cache_modified = 0;
stlink_read_debug32(sl, STLINK_REG_CM7_CCR, &ccr);
if (ccr & (STLINK_REG_CM7_CCR_IC | STLINK_REG_CM7_CCR_DC)) { cache_flush(sl, ccr); }
stlink_read_debug32(sl, STM32_REG_CM7_CCR, &ccr);
if (ccr & (STM32_REG_CM7_CCR_IC | STM32_REG_CM7_CCR_DC)) { cache_flush(sl, ccr); }
}
static uint32_t unhexify(const char *in, char *out, uint32_t out_count) {

74
src/stlink-lib/common_legacy.c
Wyświetl plik

@ -85,7 +85,7 @@ int32_t stlink_exit_debug_mode(stlink_t *sl) {
if (sl->flash_type != STM32_FLASH_TYPE_UNKNOWN &&
sl->core_stat != TARGET_RESET) {
// stop debugging if the target has been identified
stlink_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY);
stlink_write_debug32(sl, STM32_REG_DHCSR, STM32_REG_DHCSR_DBGKEY);
}
return (sl->backend->exit_debug_mode(sl));
@ -145,7 +145,7 @@ int32_t stlink_chip_id(stlink_t *sl, uint32_t *chip_id) {
// Read the CPU ID to determine where to read the core id
if (stlink_cpu_id(sl, &cpu_id) ||
cpu_id.implementer_id != STLINK_REG_CMx_CPUID_IMPL_ARM) {
cpu_id.implementer_id != STM32_REG_CMx_CPUID_IMPL_ARM) {
ELOG("Can not connect to target. Please use \'connect under reset\' and try again\n");
return -1;
}
@ -156,16 +156,16 @@ int32_t stlink_chip_id(stlink_t *sl, uint32_t *chip_id) {
*/
if ((sl->core_id == STM32_CORE_ID_M7F_M33_SWD || sl->core_id == STM32_CORE_ID_M7F_M33_JTAG) &&
cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM7) {
cpu_id.part == STM32_REG_CMx_CPUID_PARTNO_CM7) {
// STM32H7 chipid in 0x5c001000 (RM0433 pg3189)
ret = stlink_read_debug32(sl, 0x5c001000, chip_id);
} else if (cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM0 ||
cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM0P) {
} else if (cpu_id.part == STM32_REG_CMx_CPUID_PARTNO_CM0 ||
cpu_id.part == STM32_REG_CMx_CPUID_PARTNO_CM0P) {
// STM32F0 (RM0091, pg914; RM0360, pg713)
// STM32L0 (RM0377, pg813; RM0367, pg915; RM0376, pg917)
// STM32G0 (RM0444, pg1367)
ret = stlink_read_debug32(sl, 0x40015800, chip_id);
} else if (cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM33) {
} else if (cpu_id.part == STM32_REG_CMx_CPUID_PARTNO_CM33) {
// STM32L5 (RM0438, pg2157)
ret = stlink_read_debug32(sl, 0xE0044000, chip_id);
} else /* СM3, СM4, CM7 */ {
@ -191,7 +191,7 @@ int32_t stlink_chip_id(stlink_t *sl, uint32_t *chip_id) {
// Fix chip_id for F4 rev A errata, read CPU ID, as CoreID is the same for
// F2/F4
if (*chip_id == 0x411 && cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM4) {
if (*chip_id == 0x411 && cpu_id.part == STM32_REG_CMx_CPUID_PARTNO_CM4) {
*chip_id = 0x413;
}
}
@ -208,7 +208,7 @@ int32_t stlink_chip_id(stlink_t *sl, uint32_t *chip_id) {
int32_t stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid) {
uint32_t raw;
if (stlink_read_debug32(sl, STLINK_REG_CM3_CPUID, &raw)) {
if (stlink_read_debug32(sl, STM32_REG_CM3_CPUID, &raw)) {
cpuid->implementer_id = 0;
cpuid->variant = 0;
cpuid->part = 0;
@ -344,7 +344,7 @@ int32_t stlink_reset(stlink_t *sl, enum reset_type type) {
if (type == RESET_AUTO) {
// clear S_RESET_ST in DHCSR register for reset state detection
stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr);
stlink_read_debug32(sl, STM32_REG_DHCSR, &dhcsr);
}
if (type == RESET_HARD || type == RESET_AUTO) {
@ -366,8 +366,8 @@ int32_t stlink_reset(stlink_t *sl, enum reset_type type) {
*/
dhcsr = 0;
int32_t res = stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr);
if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0 && !res) {
int32_t res = stlink_read_debug32(sl, STM32_REG_DHCSR, &dhcsr);
if ((dhcsr & STM32_REG_DHCSR_S_RESET_ST) == 0 && !res) {
// reset not done yet --> try reset through AIRCR so that NRST does not need to be connected
ILOG("NRST is not connected --> using software reset via AIRCR\n");
DLOG("NRST not connected --> Reset through SYSRESETREQ\n");
@ -377,9 +377,9 @@ int32_t stlink_reset(stlink_t *sl, enum reset_type type) {
// waiting for reset the S_RESET_ST bit within 500ms
timeout = time_ms() + 500;
while (time_ms() < timeout) {
dhcsr = STLINK_REG_DHCSR_S_RESET_ST;
stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr);
if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0) {
dhcsr = STM32_REG_DHCSR_S_RESET_ST;
stlink_read_debug32(sl, STM32_REG_DHCSR, &dhcsr);
if ((dhcsr & STM32_REG_DHCSR_S_RESET_ST) == 0) {
return (0);
}
}
@ -403,33 +403,33 @@ int32_t stlink_soft_reset(stlink_t *sl, int32_t halt_on_reset) {
// halt core and enable debugging (if not already done)
// C_DEBUGEN is required to Halt on reset (DDI0337E, p. 10-6)
stlink_write_debug32(sl, STLINK_REG_DHCSR,
STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_HALT |
STLINK_REG_DHCSR_C_DEBUGEN);
stlink_write_debug32(sl, STM32_REG_DHCSR,
STM32_REG_DHCSR_DBGKEY | STM32_REG_DHCSR_C_HALT |
STM32_REG_DHCSR_C_DEBUGEN);
// enable Halt on reset by set VC_CORERESET and TRCENA (DDI0337E, p. 10-10)
if (halt_on_reset) {
stlink_write_debug32(
sl, STLINK_REG_CM3_DEMCR,
STLINK_REG_CM3_DEMCR_TRCENA | STLINK_REG_CM3_DEMCR_VC_HARDERR |
STLINK_REG_CM3_DEMCR_VC_BUSERR | STLINK_REG_CM3_DEMCR_VC_CORERESET);
sl, STM32_REG_CM3_DEMCR,
STM32_REG_CM3_DEMCR_TRCENA | STM32_REG_CM3_DEMCR_VC_HARDERR |
STM32_REG_CM3_DEMCR_VC_BUSERR | STM32_REG_CM3_DEMCR_VC_CORERESET);
// clear VCATCH in the DFSR register
stlink_write_debug32(sl, STLINK_REG_DFSR, STLINK_REG_DFSR_VCATCH);
stlink_write_debug32(sl, STM32_REG_DFSR, STM32_REG_DFSR_VCATCH);
} else {
stlink_write_debug32(sl, STLINK_REG_CM3_DEMCR,
STLINK_REG_CM3_DEMCR_TRCENA |
STLINK_REG_CM3_DEMCR_VC_HARDERR |
STLINK_REG_CM3_DEMCR_VC_BUSERR);
stlink_write_debug32(sl, STM32_REG_CM3_DEMCR,
STM32_REG_CM3_DEMCR_TRCENA |
STM32_REG_CM3_DEMCR_VC_HARDERR |
STM32_REG_CM3_DEMCR_VC_BUSERR);
}
// clear S_RESET_ST in the DHCSR register
stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr);
stlink_read_debug32(sl, STM32_REG_DHCSR, &dhcsr);
// soft reset (core reset) by SYSRESETREQ (DDI0337E, p. 8-23)
ret = stlink_write_debug32(sl, STLINK_REG_AIRCR,
STLINK_REG_AIRCR_VECTKEY |
STLINK_REG_AIRCR_SYSRESETREQ);
ret = stlink_write_debug32(sl, STM32_REG_AIRCR,
STM32_REG_AIRCR_VECTKEY |
STM32_REG_AIRCR_SYSRESETREQ);
if (ret) {
ELOG("Soft reset failed: error write to AIRCR\n");
return (ret);
@ -440,15 +440,15 @@ int32_t stlink_soft_reset(stlink_t *sl, int32_t halt_on_reset) {
timeout = time_ms() + 500;
while (time_ms() < timeout) {
// DDI0337E, p. 10-4, Debug Halting Control and Status Register
dhcsr = STLINK_REG_DHCSR_S_RESET_ST;
stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr);
if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0) {
dhcsr = STM32_REG_DHCSR_S_RESET_ST;
stlink_read_debug32(sl, STM32_REG_DHCSR, &dhcsr);
if ((dhcsr & STM32_REG_DHCSR_S_RESET_ST) == 0) {
if (halt_on_reset) {
// waiting halt by the SYSRESETREQ exception
// DDI0403E, p. C1-699, Debug Fault Status Register
dfsr = 0;
stlink_read_debug32(sl, STLINK_REG_DFSR, &dfsr);
if ((dfsr & STLINK_REG_DFSR_VCATCH) == 0) {
stlink_read_debug32(sl, STM32_REG_DFSR, &dfsr);
if ((dfsr & STM32_REG_DFSR_VCATCH) == 0) {
continue;
}
}
@ -458,7 +458,7 @@ int32_t stlink_soft_reset(stlink_t *sl, int32_t halt_on_reset) {
}
// reset DFSR register. DFSR is power-on reset only (DDI0337H, p. 7-5)
stlink_write_debug32(sl, STLINK_REG_DFSR, STLINK_REG_DFSR_CLEAR);
stlink_write_debug32(sl, STM32_REG_DFSR, STM32_REG_DFSR_CLEAR);
if (timeout) {
ELOG("Soft reset failed: timeout\n");
@ -1051,8 +1051,8 @@ int32_t stlink_target_connect(stlink_t *sl, enum connect_type connect) {
// check NRST connection
uint32_t dhcsr = 0;
stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr);
if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0) {
stlink_read_debug32(sl, STM32_REG_DHCSR, &dhcsr);
if ((dhcsr & STM32_REG_DHCSR_S_RESET_ST) == 0) {
WLOG("NRST is not connected\n");
}

38
src/stlink-lib/flash_loader.c
Wyświetl plik

@ -167,13 +167,13 @@ int32_t stlink_flash_loader_init(stlink_t *sl, flash_loader_t *fl) {
uint32_t dfsr, cfsr, hfsr;
/* Interrupt masking according to DDI0419C, Table C1-7 firstly force halt */
stlink_write_debug32(sl, STLINK_REG_DHCSR,
STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_DEBUGEN |
STLINK_REG_DHCSR_C_HALT);
stlink_write_debug32(sl, STM32_REG_DHCSR,
STM32_REG_DHCSR_DBGKEY | STM32_REG_DHCSR_C_DEBUGEN |
STM32_REG_DHCSR_C_HALT);
/* and only then disable interrupts */
stlink_write_debug32(sl, STLINK_REG_DHCSR,
STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_DEBUGEN |
STLINK_REG_DHCSR_C_HALT | STLINK_REG_DHCSR_C_MASKINTS);
stlink_write_debug32(sl, STM32_REG_DHCSR,
STM32_REG_DHCSR_DBGKEY | STM32_REG_DHCSR_C_DEBUGEN |
STM32_REG_DHCSR_C_HALT | STM32_REG_DHCSR_C_MASKINTS);
// allocate the loader in SRAM
if (stlink_flash_loader_write_to_sram(sl, &fl->loader_addr, &size) == -1) {
@ -193,17 +193,17 @@ int32_t stlink_flash_loader_init(stlink_t *sl, flash_loader_t *fl) {
}
/* Clear Fault Status Register for handling flash loader error */
if (!stlink_read_debug32(sl, STLINK_REG_DFSR, &dfsr) && dfsr) {
if (!stlink_read_debug32(sl, STM32_REG_DFSR, &dfsr) && dfsr) {
ILOG("Clear DFSR\n");
stlink_write_debug32(sl, STLINK_REG_DFSR, dfsr);
stlink_write_debug32(sl, STM32_REG_DFSR, dfsr);
}
if (!stlink_read_debug32(sl, STLINK_REG_CFSR, &cfsr) && cfsr) {
if (!stlink_read_debug32(sl, STM32_REG_CFSR, &cfsr) && cfsr) {
ILOG("Clear CFSR\n");
stlink_write_debug32(sl, STLINK_REG_CFSR, cfsr);
stlink_write_debug32(sl, STM32_REG_CFSR, cfsr);
}
if (!stlink_read_debug32(sl, STLINK_REG_HFSR, &hfsr) && hfsr) {
if (!stlink_read_debug32(sl, STM32_REG_HFSR, &hfsr) && hfsr) {
ILOG("Clear HFSR\n");
stlink_write_debug32(sl, STLINK_REG_HFSR, hfsr);
stlink_write_debug32(sl, STM32_REG_HFSR, hfsr);
}
return (0);
@ -409,10 +409,10 @@ int32_t stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t t
error:
dhcsr = dfsr = cfsr = hfsr = 0;
stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr);
stlink_read_debug32(sl, STLINK_REG_DFSR, &dfsr);
stlink_read_debug32(sl, STLINK_REG_CFSR, &cfsr);
stlink_read_debug32(sl, STLINK_REG_HFSR, &hfsr);
stlink_read_debug32(sl, STM32_REG_DHCSR, &dhcsr);
stlink_read_debug32(sl, STM32_REG_DFSR, &dfsr);
stlink_read_debug32(sl, STM32_REG_CFSR, &cfsr);
stlink_read_debug32(sl, STM32_REG_HFSR, &hfsr);
stlink_read_all_regs(sl, &rr);
WLOG("Loader state: R2 0x%X R15 0x%X\n", rr.r[2], rr.r[15]);
@ -900,9 +900,9 @@ int32_t stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl) {
}
// enable interrupt
if (!stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr)) {
stlink_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_DEBUGEN |
(dhcsr & (~STLINK_REG_DHCSR_C_MASKINTS)));
if (!stlink_read_debug32(sl, STM32_REG_DHCSR, &dhcsr)) {
stlink_write_debug32(sl, STM32_REG_DHCSR, STM32_REG_DHCSR_DBGKEY | STM32_REG_DHCSR_C_DEBUGEN |
(dhcsr & (~STM32_REG_DHCSR_C_MASKINTS)));
}
// restore DMA state

4
src/stlink-lib/read_write.c
Wyświetl plik

@ -105,7 +105,7 @@ int32_t stlink_read_unsupported_reg(stlink_t *sl, int32_t r_idx,
DLOG("*** stlink_read_unsupported_reg\n");
DLOG(" (%d) ***\n", r_idx);
/* Convert to values used by STLINK_REG_DCRSR */
/* Convert to values used by STM32_REG_DCRSR */
if (r_idx >= 0x1C &&
r_idx <= 0x1F) { // primask, basepri, faultmask, or control
r_convert = 0x14;
@ -128,7 +128,7 @@ int32_t stlink_write_unsupported_reg(stlink_t *sl, uint32_t val, int32_t r_idx,
DLOG("*** stlink_write_unsupported_reg\n");
DLOG(" (%d) ***\n", r_idx);
/* Convert to values used by STLINK_REG_DCRSR */
/* Convert to values used by STM32_REG_DCRSR */
if (r_idx >= 0x1C &&
r_idx <= 0x1F) { /* primask, basepri, faultmask, or control */
r_convert = r_idx; // the backend function handles this

6
src/stlink-lib/sg_legacy.c
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@ -572,9 +572,9 @@ int32_t _stlink_sg_reset(stlink_t *sl) {
if (stlink_q(sl)) { return (-1); }
// Reset through AIRCR so NRST does not need to be connected
if (stlink_write_debug32(sl, STLINK_REG_AIRCR,
STLINK_REG_AIRCR_VECTKEY | \
STLINK_REG_AIRCR_SYSRESETREQ)) {
if (stlink_write_debug32(sl, STM32_REG_AIRCR,
STM32_REG_AIRCR_VECTKEY | \
STM32_REG_AIRCR_SYSRESETREQ)) {
return (-1);
}

32
src/stlink-lib/usb.c
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@ -412,15 +412,15 @@ int32_t _stlink_usb_status_v2(stlink_t *sl) {
int32_t result;
uint32_t status = 0;
result = _stlink_usb_read_debug32(sl, STLINK_REG_DHCSR, &status);
result = _stlink_usb_read_debug32(sl, STM32_REG_DHCSR, &status);
DLOG("core status: %08X\n", status);
if (result != 0) {
sl->core_stat = TARGET_UNKNOWN;
} else {
if (status & STLINK_REG_DHCSR_C_HALT) {
if (status & STM32_REG_DHCSR_C_HALT) {
sl->core_stat = TARGET_HALTED;
} else if (status & STLINK_REG_DHCSR_S_RESET_ST) {
} else if (status & STM32_REG_DHCSR_S_RESET_ST) {
sl->core_stat = TARGET_RESET;
} else {
sl->core_stat = TARGET_RUNNING;
@ -465,7 +465,7 @@ int32_t _stlink_usb_force_debug(stlink_t *sl) {
int32_t res;
if (sl->version.jtag_api != STLINK_JTAG_API_V1) {
res = _stlink_usb_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_HALT | STLINK_REG_DHCSR_C_DEBUGEN);
res = _stlink_usb_write_debug32(sl, STM32_REG_DHCSR, STM32_REG_DHCSR_DBGKEY | STM32_REG_DHCSR_C_HALT | STM32_REG_DHCSR_C_DEBUGEN);
return (res);
}
@ -557,12 +557,12 @@ int32_t _stlink_usb_step(stlink_t* sl) {
if (sl->version.jtag_api != STLINK_JTAG_API_V1) {
// emulates the JTAG v1 API by using DHCSR
_stlink_usb_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_HALT |
STLINK_REG_DHCSR_C_MASKINTS | STLINK_REG_DHCSR_C_DEBUGEN);
_stlink_usb_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_STEP |
STLINK_REG_DHCSR_C_MASKINTS | STLINK_REG_DHCSR_C_DEBUGEN);
return _stlink_usb_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_HALT |
STLINK_REG_DHCSR_C_DEBUGEN);
_stlink_usb_write_debug32(sl, STM32_REG_DHCSR, STM32_REG_DHCSR_DBGKEY | STM32_REG_DHCSR_C_HALT |
STM32_REG_DHCSR_C_MASKINTS | STM32_REG_DHCSR_C_DEBUGEN);
_stlink_usb_write_debug32(sl, STM32_REG_DHCSR, STM32_REG_DHCSR_DBGKEY | STM32_REG_DHCSR_C_STEP |
STM32_REG_DHCSR_C_MASKINTS | STM32_REG_DHCSR_C_DEBUGEN);
return _stlink_usb_write_debug32(sl, STM32_REG_DHCSR, STM32_REG_DHCSR_DBGKEY | STM32_REG_DHCSR_C_HALT |
STM32_REG_DHCSR_C_DEBUGEN);
}
unsigned char* const data = sl->q_buf;
@ -589,8 +589,8 @@ int32_t _stlink_usb_run(stlink_t* sl, enum run_type type) {
int32_t res;
if (sl->version.jtag_api != STLINK_JTAG_API_V1) {
res = _stlink_usb_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_DEBUGEN |
((type==RUN_FLASH_LOADER)?STLINK_REG_DHCSR_C_MASKINTS:0));
res = _stlink_usb_write_debug32(sl, STM32_REG_DHCSR, STM32_REG_DHCSR_DBGKEY | STM32_REG_DHCSR_C_DEBUGEN |
((type==RUN_FLASH_LOADER)?STM32_REG_DHCSR_C_MASKINTS:0));
return (res);
}
@ -843,11 +843,11 @@ int32_t _stlink_usb_read_unsupported_reg(stlink_t *sl, int32_t r_idx, struct stl
for (int32_t i = 1; i < 4; i++) sl->q_buf[i] = 0;
ret = _stlink_usb_write_mem32(sl, STLINK_REG_DCRSR, 4);
ret = _stlink_usb_write_mem32(sl, STM32_REG_DCRSR, 4);
if (ret == -1) { return (ret); }
ret = _stlink_usb_read_mem32(sl, STLINK_REG_DCRDR, 4);
ret = _stlink_usb_read_mem32(sl, STM32_REG_DCRDR, 4);
if (ret == -1) { return (ret); }
@ -936,7 +936,7 @@ int32_t _stlink_usb_write_unsupported_reg(stlink_t *sl, uint32_t val, int32_t r_
write_uint32(sl->q_buf, val);
ret = _stlink_usb_write_mem32(sl, STLINK_REG_DCRDR, 4);
ret = _stlink_usb_write_mem32(sl, STM32_REG_DCRDR, 4);
if (ret == -1) { return (ret); }
@ -945,7 +945,7 @@ int32_t _stlink_usb_write_unsupported_reg(stlink_t *sl, uint32_t val, int32_t r_
sl->q_buf[2] = 0x01;
sl->q_buf[3] = 0;
return (_stlink_usb_write_mem32(sl, STLINK_REG_DCRSR, 4));
return (_stlink_usb_write_mem32(sl, STM32_REG_DCRSR, 4));
}
int32_t _stlink_usb_write_reg(stlink_t *sl, uint32_t reg, int32_t idx) {

2
tests/usb.c
Wyświetl plik

@ -71,7 +71,7 @@ int32_t main(int32_t ac, char** av) {
stlink_read_mem32(sl, sram_base + off, 4);
printf("FP_CTRL\n");
stlink_read_mem32(sl, STLINK_REG_CM3_FP_CTRL, 4);
stlink_read_mem32(sl, STM32_REG_CM3_FP_CTRL, 4);
// no idea what reg this is...
// stlink_read_mem32(sl, 0xe000ed90, 4);