kopia lustrzana https://github.com/stlink-org/stlink
Add supprt for STM32L4 flash driver
No loader yet, but we can erase!pull/321/head
rodzic
67fd44b837
commit
ab464492f7
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@ -63,6 +63,28 @@
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#define FLASH_L1_FPRG 10
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#define FLASH_L1_PROG 3
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//32L4 register base is at FLASH_REGS_ADDR (0x40022000)
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#define STM32L4_FLASH_KEYR (FLASH_REGS_ADDR + 0x08)
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#define STM32L4_FLASH_SR (FLASH_REGS_ADDR + 0x10)
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#define STM32L4_FLASH_CR (FLASH_REGS_ADDR + 0x14)
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#define STM32L4_FLASH_OPTR (FLASH_REGS_ADDR + 0x20)
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#define STM32L4_FLASH_SR_BSY 16
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#define STM32L4_FLASH_SR_ERRMASK 0x3f8 /* SR [9:3] */
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#define STM32L4_FLASH_CR_LOCK 31 /* Lock control register */
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#define STM32L4_FLASH_CR_PG 0 /* Program */
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#define STM32L4_FLASH_CR_PER 1 /* Page erase */
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#define STM32L4_FLASH_CR_MER1 2 /* Bank 1 erase */
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#define STM32L4_FLASH_CR_MER2 15 /* Bank 2 erase */
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#define STM32L4_FLASH_CR_STRT 16 /* Start command */
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#define STM32L4_FLASH_CR_BKER 11 /* Bank select for page erase */
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#define STM32L4_FLASH_CR_PNB 3 /* Page number (8 bits) */
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// Page is fully specified by BKER and PNB
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#define STM32L4_FLASH_CR_PAGEMASK (0x1fflu << STM32L4_FLASH_CR_PNB)
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#define STM32L4_FLASH_OPTR_DUALBANK 21
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//STM32L0x flash register base and offsets
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//same as 32L1 above
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// RM0090 - DM00031020.pdf
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@ -156,6 +178,8 @@ static inline uint32_t read_flash_cr(stlink_t *sl) {
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(sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
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(sl->chip_id == STM32_CHIPID_F446))
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res = stlink_read_debug32(sl, FLASH_F4_CR);
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else if (sl->chip_id == STM32_CHIPID_L4)
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res = stlink_read_debug32(sl, STM32L4_FLASH_CR);
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else
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res = stlink_read_debug32(sl, FLASH_CR);
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#if DEBUG_FLASH
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@ -166,12 +190,16 @@ static inline uint32_t read_flash_cr(stlink_t *sl) {
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static inline unsigned int is_flash_locked(stlink_t *sl) {
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/* return non zero for true */
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uint32_t cr = read_flash_cr(sl);
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if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) ||
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(sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
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(sl->chip_id == STM32_CHIPID_F446))
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return read_flash_cr(sl) & (1 << FLASH_F4_CR_LOCK);
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return cr & (1 << FLASH_F4_CR_LOCK);
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else if (sl->chip_id == STM32_CHIPID_L4)
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return cr & (1lu << STM32L4_FLASH_CR_LOCK);
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else
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return read_flash_cr(sl) & (1 << FLASH_CR_LOCK);
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return cr & (1 << FLASH_CR_LOCK);
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}
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static void unlock_flash(stlink_t *sl) {
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@ -185,6 +213,9 @@ static void unlock_flash(stlink_t *sl) {
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(sl->chip_id == STM32_CHIPID_F446)) {
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stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY1);
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stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY2);
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} else if (sl->chip_id == STM32_CHIPID_L4) {
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stlink_write_debug32(sl, STM32L4_FLASH_KEYR, FLASH_KEY1);
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stlink_write_debug32(sl, STM32L4_FLASH_KEYR, FLASH_KEY2);
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} else {
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stlink_write_debug32(sl, FLASH_KEYR, FLASH_KEY1);
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stlink_write_debug32(sl, FLASH_KEYR, FLASH_KEY2);
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@ -212,6 +243,9 @@ static void lock_flash(stlink_t *sl) {
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(sl->chip_id == STM32_CHIPID_F446)) {
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const uint32_t n = read_flash_cr(sl) | (1 << FLASH_F4_CR_LOCK);
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stlink_write_debug32(sl, FLASH_F4_CR, n);
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} else if (sl->chip_id == STM32_CHIPID_L4) {
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const uint32_t n = read_flash_cr(sl) | (1lu << STM32L4_FLASH_CR_LOCK);
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stlink_write_debug32(sl, STM32L4_FLASH_CR, n);
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} else {
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/* write to 1 only. reset by hw at unlock sequence */
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const uint32_t n = read_flash_cr(sl) | (1 << FLASH_CR_LOCK);
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@ -227,6 +261,10 @@ static void set_flash_cr_pg(stlink_t *sl) {
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uint32_t x = read_flash_cr(sl);
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x |= (1 << FLASH_CR_PG);
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stlink_write_debug32(sl, FLASH_F4_CR, x);
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} else if (sl->chip_id == STM32_CHIPID_L4) {
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uint32_t x = read_flash_cr(sl);
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x |= (1 << STM32L4_FLASH_CR_PG);
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stlink_write_debug32(sl, STM32L4_FLASH_CR, x);
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} else {
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const uint32_t n = 1 << FLASH_CR_PG;
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stlink_write_debug32(sl, FLASH_CR, n);
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@ -244,8 +282,14 @@ static void __attribute__((unused)) clear_flash_cr_pg(stlink_t *sl) {
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}
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static void set_flash_cr_per(stlink_t *sl) {
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const uint32_t n = 1 << FLASH_CR_PER;
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stlink_write_debug32(sl, FLASH_CR, n);
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if (sl->chip_id == STM32_CHIPID_L4) {
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uint32_t n = read_flash_cr(sl);
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n |= (1lu << STM32L4_FLASH_CR_PER);
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stlink_write_debug32(sl, STM32L4_FLASH_CR, n);
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} else {
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const uint32_t n = 1 << FLASH_CR_PER;
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stlink_write_debug32(sl, FLASH_CR, n);
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}
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}
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static void __attribute__((unused)) clear_flash_cr_per(stlink_t *sl) {
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@ -259,6 +303,11 @@ static void set_flash_cr_mer(stlink_t *sl) {
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(sl->chip_id == STM32_CHIPID_F446))
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stlink_write_debug32(sl, FLASH_F4_CR,
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stlink_read_debug32(sl, FLASH_F4_CR) | (1 << FLASH_CR_MER));
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else if (sl->chip_id == STM32_CHIPID_L4)
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stlink_write_debug32(sl, STM32L4_FLASH_CR,
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stlink_read_debug32(sl, STM32L4_FLASH_CR) |
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(1lu << STM32L4_FLASH_CR_MER1) |
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(1lu << STM32L4_FLASH_CR_MER2));
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else
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stlink_write_debug32(sl, FLASH_CR,
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stlink_read_debug32(sl, FLASH_CR) | (1 << FLASH_CR_MER));
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@ -282,6 +331,10 @@ static void set_flash_cr_strt(stlink_t *sl) {
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uint32_t x = read_flash_cr(sl);
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x |= (1 << FLASH_F4_CR_STRT);
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stlink_write_debug32(sl, FLASH_F4_CR, x);
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} else if (sl->chip_id == STM32_CHIPID_L4) {
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uint32_t x = read_flash_cr(sl);
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x |= (1lu << STM32L4_FLASH_CR_STRT);
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stlink_write_debug32(sl, STM32L4_FLASH_CR, x);
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} else {
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stlink_write_debug32(sl, FLASH_CR,
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stlink_read_debug32(sl, FLASH_CR) | (1 << FLASH_CR_STRT) );
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@ -298,6 +351,8 @@ static inline uint32_t read_flash_sr(stlink_t *sl) {
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(sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
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(sl->chip_id == STM32_CHIPID_F446))
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res = stlink_read_debug32(sl, FLASH_F4_SR);
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else if (sl->chip_id == STM32_CHIPID_L4)
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res = stlink_read_debug32(sl, STM32L4_FLASH_SR);
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else
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res = stlink_read_debug32(sl, FLASH_SR);
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//fprintf(stdout, "SR:0x%x\n", *(uint32_t*) sl->q_buf);
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@ -309,6 +364,8 @@ static inline unsigned int is_flash_busy(stlink_t *sl) {
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(sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
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(sl->chip_id == STM32_CHIPID_F446))
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return read_flash_sr(sl) & (1 << FLASH_F4_SR_BSY);
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else if (sl->chip_id == STM32_CHIPID_L4)
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return read_flash_sr(sl) & (1 << STM32L4_FLASH_SR_BSY);
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else
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return read_flash_sr(sl) & (1 << FLASH_SR_BSY);
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}
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@ -375,6 +432,17 @@ static inline void write_flash_cr_snb(stlink_t *sl, uint32_t n) {
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stlink_write_debug32(sl, FLASH_F4_CR, x);
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}
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static inline void write_flash_cr_bker_pnb(stlink_t *sl, uint32_t n) {
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uint32_t x = read_flash_cr(sl);
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x &=~ STM32L4_FLASH_CR_PAGEMASK;
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x |= (n << STM32L4_FLASH_CR_PNB);
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x |= (1lu << STM32L4_FLASH_CR_PER);
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#if DEBUG_FLASH
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fprintf(stdout, "BKER:PNB:0x%x 0x%x\n", x, n);
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#endif
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stlink_write_debug32(sl, STM32L4_FLASH_CR, x);
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}
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// Delegates to the backends...
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void stlink_close(stlink_t *sl) {
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@ -1036,6 +1104,23 @@ uint32_t calculate_F4_sectornum(uint32_t flashaddr){
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}
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// Returns BKER:PNB for the given page address
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uint32_t calculate_L4_page(stlink_t *sl, uint32_t flashaddr) {
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uint32_t bker = 0;
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uint32_t flashopt = stlink_read_debug32(sl, STM32L4_FLASH_OPTR);
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flashaddr -= STM32_FLASH_BASE;
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if (flashopt & (1lu << STM32L4_FLASH_OPTR_DUALBANK)) {
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uint32_t banksize = sl->flash_size / 2;
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if (flashaddr > banksize) {
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flashaddr -= banksize;
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bker = 0x100;
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}
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}
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// For 1MB chips without the dual-bank option set, the page address will
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// overflow into the BKER bit, which gives us the correct bank:page value.
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return bker | flashaddr/sl->flash_pgsz;
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}
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uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){
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if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) ||
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(sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
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@ -1061,7 +1146,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr)
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{
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if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) ||
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(sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
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(sl->chip_id == STM32_CHIPID_F446)) {
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(sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_L4)) {
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/* wait for ongoing op to finish */
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wait_flash_busy(sl);
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@ -1069,15 +1154,22 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr)
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unlock_flash_if(sl);
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/* select the page to erase */
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// calculate the actual page from the address
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uint32_t sector=calculate_F4_sectornum(flashaddr);
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if (sl->chip_id == STM32_CHIPID_L4) {
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// calculate the actual bank+page from the address
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uint32_t page = calculate_L4_page(sl, flashaddr);
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fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x\n", sector, stlink_calculate_pagesize(sl, flashaddr));
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write_flash_cr_bker_pnb(sl, page);
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} else {
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// calculate the actual page from the address
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uint32_t sector=calculate_F4_sectornum(flashaddr);
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//the SNB values for flash sectors in the second bank do not directly follow the values for the first bank on 2mb devices...
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if (sector >= 12) sector += 4;
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fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x\n", sector, stlink_calculate_pagesize(sl, flashaddr));
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write_flash_cr_snb(sl, sector);
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//the SNB values for flash sectors in the second bank do not directly follow the values for the first bank on 2mb devices...
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if (sector >= 12) sector += 4;
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write_flash_cr_snb(sl, sector);
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}
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/* start erase operation */
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set_flash_cr_strt(sl);
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