From 0d390c912263d6388ed875ee4972e8094e2ee9c0 Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Thu, 13 Oct 2011 23:59:24 +0200 Subject: [PATCH 01/63] Fix a signedness warning Signed-off-by: Karl Palsson --- src/stlink-usb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/stlink-usb.c b/src/stlink-usb.c index 79709ac..ebd6e35 100644 --- a/src/stlink-usb.c +++ b/src/stlink-usb.c @@ -163,7 +163,7 @@ void _stlink_usb_version(stlink_t *sl) { #if 1 /* DEBUG */ { - unsigned int i; + ssize_t i; for (i = 0; i < size; ++i) printf("%02x", buf[i]); printf("\n"); } From 4aa64b2daa46f5a36d8fa10a932833fcf66ee6f6 Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Thu, 13 Oct 2011 23:25:46 +0200 Subject: [PATCH 02/63] Size all USB receive operations Signed-off-by: Karl Palsson --- src/stlink-usb.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/src/stlink-usb.c b/src/stlink-usb.c index ebd6e35..5099bfd 100644 --- a/src/stlink-usb.c +++ b/src/stlink-usb.c @@ -155,7 +155,7 @@ void _stlink_usb_version(stlink_t *sl) { buf[0] = STLINK_GET_VERSION; buf[1] = 0x80; - size = send_recv(slu, buf, STLINK_CMD_SIZE, buf, sizeof (sl->q_buf)); + size = send_recv(slu, buf, STLINK_CMD_SIZE, buf, 6); if (size == -1) { printf("[!] send_recv\n"); return; @@ -211,7 +211,7 @@ int _stlink_usb_current_mode(stlink_t * sl) { ssize_t size; memset(buf, 0, sizeof (sl->q_buf)); buf[0] = STLINK_GET_CURRENT_MODE; - size = send_recv(slu, buf, STLINK_CMD_SIZE, buf, sizeof (sl->q_buf)); + size = send_recv(slu, buf, STLINK_CMD_SIZE, buf, 2); if (size == -1) { printf("[!] send_recv\n"); return -1; @@ -228,7 +228,7 @@ void _stlink_usb_core_id(stlink_t * sl) { buf[0] = STLINK_DEBUG_COMMAND; buf[1] = STLINK_DEBUG_READCOREID; - size = send_recv(slu, buf, STLINK_CMD_SIZE, buf, sizeof (sl->q_buf)); + size = send_recv(slu, buf, STLINK_CMD_SIZE, buf, 4); if (size == -1) { printf("[!] send_recv\n"); return; @@ -247,7 +247,7 @@ void _stlink_usb_status(stlink_t * sl) { buf[0] = STLINK_DEBUG_COMMAND; buf[1] = STLINK_DEBUG_GETSTATUS; - size = send_recv(slu, buf, STLINK_CMD_SIZE, buf, sizeof (sl->q_buf)); + size = send_recv(slu, buf, STLINK_CMD_SIZE, buf, 2); if (size == -1) { printf("[!] send_recv\n"); return; @@ -271,7 +271,7 @@ void _stlink_usb_force_debug(stlink_t *sl) { buf[0] = STLINK_DEBUG_COMMAND; buf[1] = STLINK_DEBUG_FORCEDEBUG; - size = send_recv(slu, buf, STLINK_CMD_SIZE, buf, sizeof (sl->q_buf)); + size = send_recv(slu, buf, STLINK_CMD_SIZE, buf, 2); if (size == -1) { printf("[!] send_recv\n"); return; @@ -290,7 +290,7 @@ void _stlink_usb_enter_swd_mode(stlink_t * sl) { buf[1] = STLINK_SWD_ENTER; buf[2] = STLINK_DEBUG_ENTER_SWD; - size = send_recv(slu, buf, STLINK_CMD_SIZE, buf, sizeof (sl->q_buf)); + size = send_recv(slu, buf, STLINK_CMD_SIZE, buf, 2); if (size == -1) { printf("[!] send_recv\n"); return; @@ -343,7 +343,7 @@ void _stlink_usb_step(stlink_t* sl) { buf[0] = STLINK_DEBUG_COMMAND; buf[1] = STLINK_DEBUG_STEPCORE; - size = send_recv(slu, buf, STLINK_CMD_SIZE, buf, sizeof (sl->q_buf)); + size = send_recv(slu, buf, STLINK_CMD_SIZE, buf, 2); if (size == -1) { printf("[!] send_recv\n"); return; @@ -363,7 +363,7 @@ void _stlink_usb_run(stlink_t* sl) { buf[0] = STLINK_DEBUG_COMMAND; buf[1] = STLINK_DEBUG_RUNCORE; - size = send_recv(slu, buf, STLINK_CMD_SIZE, buf, sizeof (sl->q_buf)); + size = send_recv(slu, buf, STLINK_CMD_SIZE, buf, 2); if (size == -1) { printf("[!] send_recv\n"); return; @@ -404,7 +404,7 @@ void _stlink_usb_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { assert (len < 256); buf[6] = (uint8_t) len; - size = send_recv(slu, buf, STLINK_CMD_SIZE, buf, sizeof (sl->q_buf)); + size = send_recv(slu, buf, STLINK_CMD_SIZE, buf, len); if (size == -1) { printf("[!] send_recv\n"); return; From 06a737c4cc2aa1238fcb44f422e139e1c147c41f Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Fri, 14 Oct 2011 00:03:06 +0200 Subject: [PATCH 03/63] Assert size only if Q_BUF_LEN is smaller UINT16_MAX Signed-off-by: Karl Palsson --- src/stlink-usb.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/src/stlink-usb.c b/src/stlink-usb.c index 5099bfd..b417d41 100644 --- a/src/stlink-usb.c +++ b/src/stlink-usb.c @@ -182,6 +182,9 @@ void _stlink_usb_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { write_uint16(cmd_buf + 6, len); send_only(slu, cmd_buf, STLINK_CMD_SIZE); +#if Q_BUF_LEN < UINT16_MAX + assert(len < sizeof(sl->q_buf)); // makes a compiler warning? always true? +#endif assert((len & 3) == 0); stlink_print_data(sl); send_only(slu, buf, len); @@ -200,6 +203,9 @@ void _stlink_usb_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { write_uint16(cmd_buf + 6, len); send_only(slu, cmd_buf, STLINK_CMD_SIZE); +#if Q_BUF_LEN < UINT16_MAX + assert(len < sizeof(sl->q_buf)); // makes a compiler warning? always true? +#endif stlink_print_data(sl); send_only(slu, buf, len); } @@ -392,8 +398,9 @@ void _stlink_usb_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { unsigned char* const buf = sl->q_buf; ssize_t size; - /* assume len < sizeof(sl->q_buf) */ - assert(len < sizeof(sl->q_buf)); // makes a compiler warning? always true? +#if Q_BUF_LEN < UINT16_MAX + assert(len < sizeof(sl->q_buf)); +#endif memset(buf, 0, sizeof (sl->q_buf)); buf[0] = STLINK_DEBUG_COMMAND; From 7abc08eeefdd4128ca55bcece97eda9c54a9e5bb Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Fri, 14 Oct 2011 00:06:41 +0200 Subject: [PATCH 04/63] Remove some debug output Signed-off-by: Karl Palsson --- src/stlink-usb.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/stlink-usb.c b/src/stlink-usb.c index b417d41..7bcff82 100644 --- a/src/stlink-usb.c +++ b/src/stlink-usb.c @@ -186,7 +186,6 @@ void _stlink_usb_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { assert(len < sizeof(sl->q_buf)); // makes a compiler warning? always true? #endif assert((len & 3) == 0); - stlink_print_data(sl); send_only(slu, buf, len); } @@ -206,7 +205,6 @@ void _stlink_usb_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { #if Q_BUF_LEN < UINT16_MAX assert(len < sizeof(sl->q_buf)); // makes a compiler warning? always true? #endif - stlink_print_data(sl); send_only(slu, buf, len); } From a4e5aba21e022750633039fab9efa4119062e096 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Sat, 22 Oct 2011 02:06:07 +0000 Subject: [PATCH 05/63] Fix character encodings of st provided files. --- example/lcd/stm32l_discovery_lcd.c | 4 ++-- example/lcd/stm32l_discovery_lcd.h | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/example/lcd/stm32l_discovery_lcd.c b/example/lcd/stm32l_discovery_lcd.c index 64163de..982a5f2 100644 --- a/example/lcd/stm32l_discovery_lcd.c +++ b/example/lcd/stm32l_discovery_lcd.c @@ -281,7 +281,7 @@ static void LCD_Conv_Char_Seg(uint8_t* c,bool point,bool column, uint8_t* digit) ch = star; break; - case 'µ' : + case 'µ' : ch = C_UMAP; break; @@ -301,7 +301,7 @@ static void LCD_Conv_Char_Seg(uint8_t* c,bool point,bool column, uint8_t* digit) ch = C_slatch; break; - case '°' : + case '°' : ch = C_percent_1; break; case '%' : diff --git a/example/lcd/stm32l_discovery_lcd.h b/example/lcd/stm32l_discovery_lcd.h index d496b84..bb8b0d7 100644 --- a/example/lcd/stm32l_discovery_lcd.h +++ b/example/lcd/stm32l_discovery_lcd.h @@ -85,7 +85,7 @@ MSB { 1 , 1 , 0 , 0 } #define BAR3_ON t_bar[0] |= 2 #define BAR3_OFF t_bar[0] &= ~2 -/* code for 'µ' character */ +/* code for 'µ' character */ #define C_UMAP 0x6084 /* code for 'm' character */ @@ -103,7 +103,7 @@ MSB { 1 , 1 , 0 , 0 } /* constant code for '/' */ #define C_slatch 0x00c0 -/* constant code for ° */ +/* constant code for ° */ #define C_percent_1 0xec00 /* constant code for small o */ From 234e144d5d5aba4fcbe1a9fd9563023f1ca81a57 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Sat, 22 Oct 2011 02:06:35 +0000 Subject: [PATCH 06/63] Add debug flag by default, no need not to have it in the elf. --- example/blink/Makefile | 2 +- example/lcd/Makefile | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/example/blink/Makefile b/example/blink/Makefile index 1b310b1..0f4f712 100644 --- a/example/blink/Makefile +++ b/example/blink/Makefile @@ -4,7 +4,7 @@ BIN_IMAGE=blink.bin CC=arm-none-eabi-gcc OBJCOPY=arm-none-eabi-objcopy -CFLAGS=-O2 -mlittle-endian -mthumb +CFLAGS=-O2 -mlittle-endian -mthumb -g CFLAGS+=-mcpu=cortex-m3 -ffreestanding -nostdlib -nostdinc # to run from SRAM diff --git a/example/lcd/Makefile b/example/lcd/Makefile index 0febe49..0f31ae6 100644 --- a/example/lcd/Makefile +++ b/example/lcd/Makefile @@ -2,7 +2,7 @@ ELF=lcd.elf CC=arm-none-eabi-gcc -CFLAGS=-O2 -mlittle-endian -mthumb +CFLAGS=-O2 -mlittle-endian -mthumb -g CFLAGS+=-mcpu=cortex-m3 -ffreestanding -nostdlib -nostdinc CFLAGS+=-I. From 9bc72d4519e63fb1cf657a6c93008eaa8989fd01 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Sat, 22 Oct 2011 02:11:04 +0000 Subject: [PATCH 07/63] Merge upstream texane/master --- .gitignore | 1 + AUTHORS | 2 + Makefile | 41 +- TODO | 15 +- doc/tutorial/tutorial.pdf | Bin 106136 -> 110077 bytes doc/tutorial/tutorial.tex | 65 ++- example/blink/Makefile | 11 +- example/blink/main.c | 34 +- example/blink_flash/Makefile | 36 ++ example/blink_flash/main.c | 82 ++++ example/blink_flash/startup_stm32l1xx_md.s | 366 ++++++++++++++ example/blink_flash/stm32_flash.ld | 173 +++++++ example/blink_flash/system_stm32l1xx.c | 367 ++++++++++++++ flash/Makefile | 21 +- flash/main.c | 137 +++++- gdbserver/Makefile | 19 +- gdbserver/gdb-server.c | 53 ++- src/stlink-common.h | 1 + src/stlink-sg.c | 6 +- src/stlink-usb.c | 526 +++++++++++---------- src/stlink-usb.h | 6 +- src/test_sg.c | 4 +- src/test_usb.c | 2 +- 23 files changed, 1629 insertions(+), 339 deletions(-) create mode 100644 example/blink_flash/Makefile create mode 100644 example/blink_flash/main.c create mode 100644 example/blink_flash/startup_stm32l1xx_md.s create mode 100644 example/blink_flash/stm32_flash.ld create mode 100644 example/blink_flash/system_stm32l1xx.c diff --git a/.gitignore b/.gitignore index 78d3fb5..44d2e4d 100644 --- a/.gitignore +++ b/.gitignore @@ -3,3 +3,4 @@ libstlink.a test_usb test_sg +gdbserver/st-utils \ No newline at end of file diff --git a/AUTHORS b/AUTHORS index ca1df75..0abaac6 100644 --- a/AUTHORS +++ b/AUTHORS @@ -7,3 +7,5 @@ karlp@tweak.net.au h0rr0rrdrag@gmail.com mstempin@com1.fr bon@elektron.ikp.physik.tu-darmstadt.de +nelsonjm@macpod.neta +ned@bike-nomad.com \ No newline at end of file diff --git a/Makefile b/Makefile index 4c3b44b..c5bb1d9 100644 --- a/Makefile +++ b/Makefile @@ -1,21 +1,36 @@ - +# make ... for both libusb and libsg +# +# make CONFIG_USE_LIBSG=0 ... +# for just libusb +# VPATH=src -SOURCES_LIB=stlink-common.c stlink-usb.c stlink-sg.c +SOURCES_LIB=stlink-common.c stlink-usb.c OBJS_LIB=$(SOURCES_LIB:.c=.o) +TEST_PROGRAMS=test_usb +LDFLAGS=-lusb-1.0 -L. -lstlink + +ifeq ($(CONFIG_USE_LIBSG),) +CONFIG_USE_LIBSG=1 +endif + +ifneq ($(CONFIG_USE_LIBSG),0) +SOURCES_LIB+=stlink-sg.c +CFLAGS+=-DCONFIG_USE_LIBSG=1 +LDFLAGS+=-lsgutils2 +TEST_PROGRAMS+=test_sg +endif CFLAGS+=-g -CFLAGS+=-DCONFIG_USE_LIBUSB -CFLAGS+=-DCONFIG_USE_LIBSG -CFLAGS+=-DDEBUG +CFLAGS+=-DCONFIG_USE_LIBUSB=1 +CFLAGS+=-DDEBUG=1 CFLAGS+=-std=gnu99 CFLAGS+=-Wall -Wextra -LDFLAGS=-lstlink -lusb-1.0 -lsgutils2 -L. LIBRARY=libstlink.a -all: $(LIBRARY) test_usb test_sg +all: $(LIBRARY) flash gdbserver $(TEST_PROGRAMS) $(LIBRARY): $(OBJS_LIB) @echo "objs are $(OBJS_LIB)" @@ -42,5 +57,15 @@ clean: rm -rf $(LIBRARY) rm -rf test_usb* rm -rf test_sg* + +distclean: clean + $(MAKE) -C flash clean + $(MAKE) -C gdbserver clean -.PHONY: clean all +flash: + $(MAKE) -C flash CONFIG_USE_LIBSG="$(CONFIG_USE_LIBSG)" + +gdbserver: + $(MAKE) -C gdbserver + +.PHONY: clean all flash gdbserver diff --git a/TODO b/TODO index 4d1929c..e3795fc 100644 --- a/TODO +++ b/TODO @@ -1,10 +1,17 @@ -. flash writing is not working from GDB -add a standalone application, flash/ +. flash tool + . test support for reading + . writing is not working. refer to the specs, may have changed for stm32l + . then test with blink_flash example + . then update the documentation -. add a startup.S based example +. documentation + . make README points to doc/tutorial . remove libsg dependency using: https://github.com/afaerber/stlink/tree/master/libstlink . compile and test a realtime kernel, for instance: -http://www.chibios.org/dokuwiki/doku.php?id=start +http://www.chibios.org/dokuwiki/doku.php?id=chibios:articles:stm32l_discovery +svn checkout https://chibios.svn.sourceforge.net/svnroot/chibios/trunk ; +cd chibios/trunk/demos/ARMCM3-STM32L152-DISCOVERY ; +make ; diff --git a/doc/tutorial/tutorial.pdf b/doc/tutorial/tutorial.pdf index b84d061f57921ebc02df6a11261675a97c3d31fa..9202ed4dc33c1bcafdcf4db30807103a22c846c8 100644 GIT binary patch delta 65756 zcmZU(W0WRA(=FPzZQIuLv^{Oxw%z@-ZQHhO+qP}@wC=p$d%kn;TK7jrMP}^SQBkW_ zW@Tihbwhk@Le!ywfUz=h5+xdxPyuWbrfmn9kb-V`gJUy=16Fl^bjo20s>_y2N?St1 zz`~MvR8aPwGxvn@CoGJuP9CdPvTU%;BB6hlHF(lzf(<0X$>`NP48kbt2UrHF1hpq<;E|&YDbaWdNvQM85lkGS3<3G=^+cg> zfL^HYV!O_&3aQ>`Lkn`_KqNX@0d}ix+ii-$0cQ2`Lw`#M__WKNE9--% z)Ic|&Z-=zW*$^84X$c-nC{0X!?$Kva?D0{c zkbU&w^AvRUXuS@*HYqI>RAGF$AZ>v~H@HqB!2iz6ui(!cowt5cpfYuq<=a^eG#Z!Q zWXrMR359SzX>ZyjtLx2d$hP=NB2B0(Ih^i*@J z{^hzJH%i#HFL#H2A4r6w4+#fN0#ayd?VYWT|GLdFhIGGvrV3qh^u%!&Ker3M8V1>5 z+)+coT%jtjPE{*-KV&yceTk@D2B_f2e5Aj(u!doD7 z$%pc(cI+|P&QfHz))d&`ECHL#Z$Q%fM&Xtx|57w8bicD(C$PX82K)&T+geh&awuM! zTnJEEyG*N{R0NVfu<*sI4&cvjr0bPUpED$Iz~q6REVA$Y43yP>=2tv^GtdRiKZ>%4&X=uny_D`#1Z$m=e$i(lnJ$dFhE?!+3lWk+CI#7 z=0UlHZGavW$s)O48{+H-DWr)jVUh07Xwo+u{5|Qf3=3v*`~v#C)@2FDD}@zJ{%T_a zP64#gF|P#_)B*z+1XLhbJoKPD&$i8Z1Q2rgSiORrFh)uIu%)eBNK~lV!y?E|`0JOZ z$M+LvXPx-Jgw7- zFmAZa@`4mms-fYv>rYcX&ivMD^EQ0UT|Y*yqa+tS`p_DFUI3_*3Hjl{N1wLI*6U1d zDEAbBtr)Zjau*hG=S0>Ydq1J?TvRxlIhJ%GC(MB3-7~6GrQbpzc>yp#Ubg^ZRO;6I zN|CX*SCOzc`fu&SS^DoS?;NCY_(ppV!s}0sF3FV5&va)A1d6JMk^%DF{c^Xr$G=na z1W~)E=4C0$Spd8*(~f5qd!d1^d{cn5G0vk|9yDT@bjGcYN1=;JT7yB~Zir=onO!3z z?dvD30Zxe?e`}-z0YUHDg~P^x@@?ez9ozgi(9hG&dItf6!@*)r-~IOiY!23WYn$ie zq)OVb$`4bI@a$VF1Ew5Gs%_f-)RlxtQmD8ue+6O5YWO8km}i#K;s(%FfbSkGdt`5%-+Wu+jd(VD1cWz z;=KnVVBO$dG_5UQhl3(+E=k69TKOiQI5(5pIGyq3Q2d`)PQrw)ORme3mfRV?P&`Ko zc<#Y>_;wPWSdpg_0l4G&&%Jl6V^Rx6o2-Zvv-l*wX=Mx#1I2P3Ha)T4VTyFga%=CU z)JqeMY)aN^n=G|IH2^jrmF*@+hxw&bnI6gSw4aZ6D+^NU1)_iM>fFgG+>wn28}G?9#xCiQrpG&kp}foCgR z=!}yk>dr1s*~UDwiT{=l-%S~(fQhogB#XKf7vA9DLcbM7eP{gzz6vCR9oA|exTf1SWEK*Yy<{H@-n3OGsDr)jk^#5&@&p*n+(A;-TZ zL9=4G)2jPHcdGN(1a~H^2CJTJ2rG7w3VP$VpID^$cmu%BXPt$dfzPwg2Z%a=(S4$| zj^Ej0??|%Vka=^$a(u_HFee^S{DOVwju#pzPY@b%s`yD7qZ|5>w&%Dz!_(KWoLBx8*8iEMt=>ug8Suw+H&woo!U=Hpbe7#kp_E!VZi0Q5d%Yd#U8OI zv`XxFcUxYYRIol`Rj%w539W6b00wSn;=6jX9xOK? z6)(sW5X&YQ)qjaSAdlD9{Xk?{o*2`Gf45Om1prpDZhI-IB0B3VF(ry76l;BqeI!KX zIqeOtKTnpC)iw&+MVzT{PB_P&Y)0|kl1O5S<{9ilUTQ`bh~oO{uOcY)oVOfRTq^}l z*`q$#0Hx>$VTkvY2LYv35P3o09XJTIduChH8ApKE#7?3@4w$gTE~o(?k# zJ3s_I8&8+8p;bE4uMC2?<^xY1c%w^J21s-`cf9*Z&qiQtyH~#~c73^OLdc^kSBsNv zFvk$@SuQRlfgR%c@P1H(Iav6dh;+~)qM~^tZ|ig|CN(FA@n~=-c+4<1Y*EFiFw`I> zrZjz5`X}o#gQJ&mNkP5-ub&LZtm@+PC4itVyM&)*K0#!j4*8)74kONu#)8F>Da5kuH&K;gyezT_Xc7t~&U(Q2^M7 zY9Do70`!zgzY_-Zn@>Pl-Z{SK5PC^m!v%fR46H4GO(5BK9_+{7%HRao| zf@OMg**FADE$4QvRmBne08p%x2!1Ya-{0uiL3&}zF$2IOj5jqMRt59B}s)j`q$(uBTvc(o)x!Jawhgisb#7sgTf7@*bQuc!vI&+x8LW~ zVv1)@DRxZWpy8ZuT)nI1uCLs^kVDOdaME_?wj;s)G(Zp?pg&|fj8 zjJau?+KWEmI*>WAj%^4Sd4F$4q$6p1DE<_?zbUy8Rfo9khfaGVJxO_YuVZNp(qyju8zV)0hZA>}R)E7?y?=R~nrtfcH4kok zYgsFB!jD?%GoWVqY-64w%39;c+U3T~M|YtArdHxu!Ei4Oh5b=&XmJ|ML1`(ewbdzd z^M2yEp{86y~mFK#Wz*K_=);Dh>Y0tXw@$&PtuoS9gtxwU3}T)e^-B0QkeKd;1uoK!z4Cr$45Zed)nesZ{5C9bK(0NN*bGc zn){2uU#AzAwnJqbqjmHUcDknbd?^FCy^_SvwjD00B0n6UD%eZ&CZbPv-C0wk`Ib>c z#BT$wj)$^iUZQewv^Q-l4ia_GfBdj^2xDSv?Bwidl1PL34#v&K@!!4pvD%-1TS=sz zOEtPVJXOf**DrH_5NLVKv+8Qw7{sP=i6CkkOiz_+b~+1u&w zrmj?$^+=kZJoBVI8FCB^HYg*sr-kT`oC9e^4bvnRwNa6Vx{6kaWBxD`^M@6 z1}<>au;plhG=PzY@)#Li5K106+k^JJOuhEdn*Ff9~bN;z5T3 z%`xY-3K+~T;2W=Clq0b{n1NJ+ZJ4>lV*-t29ZzV!FS={MXd8FU$)ZD;JM0mo7$Y|o0av@4-E*3F=K_gq5QuS1h&lnLh z3JMk|j>7}k$~YrL(Nf%tY`qZOXp?~Nk$?l?w$SCXrufi28GqwT_{8cxmu zmNV`qJX;s#)mUR!^#6}gK7O^L7u^L4Gh%g zXN~(wf~mQt5Eb8YYMe?G7TH%n-o=d~_KjW3$*KVmhKuS6KQ$!R?Gc|44{ujdTr*)` z15ra}rboTDDEddhWai$uAt?rves+*%{Jth=e{AL!K63Jm`q;1=>IM*iI;po&59Cs!^DNnzIB)Jzd3XN4dVXpsT-z6RE`7^%13RvB^GOwc`5P5lb7J&PCH6Ak>s9 zG(RV{3WKt-PI@vZd0zja0`f0QxN09v#XEe7C}WfA^==>OhSF`j}teO1_ulZ-jjFOD+m zMHiqaQufBi(nU_>q zXDDSE4};SzR>zGGiyQCZnWxfexbj{@EF0Y6e?Bhd)tSi{^#s#( z-A7eZHP31rm^7Vt>{4*90@O}`6L_tK4|nbK?M(>%D7Z8-fL~VjO5hVDauBq~jn`0C zq)+I04QyMmVTobDv)~UF&G7=6mIA021TOS!RvmphkG0_x-x-;+I_RZzMlz>QW+aaf zc&^gWTurCP>$0?1KeXu!tCre}lShJeJdYLEt$LlbU<(75_A@Z{0C9VcNDF-WO0Srl z!}ShfEVIw9M1@@b{k652M~&Nabe-RZ_}Hb5DxztyF@w0SF_hvfyrVsG;)4T-YfG2O z`q4ewtir7qr54v{g@)pSw)g8^Ao@;VM0Fix26plug{*?$fmtNRF1Vu&UhfX7=6XHqWpmqfBS~q zs569+dNE!R5%YVXa3Mq3Hskzy=DDaq6r`gnMKIP$WT|-h4?nRNbK}sqK-@tDBoC+> z*>H^T5>o%l^d~y&)}TMyqn>YBK^y+?;Yrd+6FijqRxqQPfcmT#FoeKhw@2^tDo3MC5njuV#+m_aX|6Evq`^akVrWVoOoe(tI`e_nj8Fgr1btkZL-?=Y^S z7xZTFrEjt8LfQw)RxdGv?x*&4r?_@i>olrBa5aaz&gLtcP-*}h=&zsgigfaMOF!qH zL4Xr3+1p(=;0Q_LwqfiL-!TkaXUh|U$D)rP(Ifmjfs#{<#VFwW0`@_2Z)Sg_gs7KO zDl4D!9u0F{0oF0uMYrD@g^C(nihquwEL$P-0i}ithKK2NyU$5B4L41TCB1Qu#VoCp zcumWw2o|RboZO;^bq!Zz$S`!f+Mmrd(q>StN}#bAaG2B{(~dZ`JoP-Kb0>2@;9m=s zZ!#S8z@-J;77_~7ssr=mJD#DbPcKJM1${k2SCccS!hi#b-=9@uq@J3^FOd}`7dMkoAMj(0Wx zg%hdX4bJs~ciH4u12Wt{eEm#hSZQdDFPB3I=y`jGnZb%s55En-OWIrTa$-zl_2aJo z1fV+Q77hVqlA^jJ4(=sz?@=Ns??G_sn#&eYW^Fw&xv}>jm5iC7 zAe5s0ZD@%qn({=Zdd9>6vtCJTAS_SJLxfGlCSU~SNR%Xy10G6DC*T5TP_QP!Obd`x z)y~n%LW9Ra@ONh8YHM}Gcby^vuzJ9w1(;~*=%RwkMM!BtSH{BJQR8$G(wFB@LKYT! zC|L$~UOBUJWhps4RbAn0H_5LVqE_x*na~2H~9Y-#>Vy^+W*S`ApXBLRxZ|mxB6eY zL_%V+L`Gt$Mqy%GU~)F5|CO+8MgKSczYHw@5@qLN{y*&hMgKR_|BGV#pUD4} z|3&=2HrD@e0W&A=laMs-k|Y3wurW6}k(q*ku(2d=QhWllHm*^20|T?A<`Ds-(QtFI zz%WXi*qS+;vk?8O!m=^{Z3>xsW)61t#QFg$K=cc^ytdUMILzS<3ej3#|MoV1 zfY)8WfxR1L8#vU>&5f)*{LKw;z{hcxn&ZyxPvuQ@dB%FBmkWROECCFPD7vQsY8{QqG?eX1@*x^ zm%RfBe<0HGi)v)|OGodU>K~jM9~=VHH!wW-Mnpd914UwWu4e)sV+Ar6Xb}(xgHedf z?hFi0Z(sc2{_y~l$5sMOYj5X1|K@;%+62Om~+Q2hYu>4ETl z@85f0y}sXC{y)Y)t;+Lr2fOoMgN04i)KGn2wPZV$uel=H-@mbye{^vz`+jorfIM@} zi2N>Q-!56|S+RQo%s&9#fL@vJpXqNs-EY0opC2)@eQTSq)|?BypdZ5S{OI83k6!HC z$E&NS9^8k#SNQs`US;^bUJQUHn6b?Rz-2);x4{m!TO`&Gh0%P4MKuXFTa z$4wX#QrIo%b)}co)sOP=BOwE5`#Z-5h%}IX?0g&SE+>n#5ADeBP7NT=%>@)i0to*W z%bEfb8|M#0@1y#HtOvz1`N?zp)y^LV+gEl6=>Uqw|AXmJ4}_KcZ#b6*fQ0L(@Qmom zFL>P>mWkSD{s!6o!S>Dgw^A{R;>YjS0rUrU7q`5=! z3g8J)FF1qnQwN|-1AKw@jM{u7zWpnm@$Y%DSN#C*3b($4?sBHgzsxG!YHakl{U!YS zsx9ynY<)YD_oL7|YWn&QKF)t&>>E3DAN$ygGzb0`d$@BRbNf0?82GCBRlfM)%fgfX z3+P8-^3^}HL{C}CqMX5t^J~X-KJ%H zhYH+$lLO4z#1zl9xfQVD7Rp+)FRtVBZjPYga>T&Icgg`5(4af8rwXADUB(yPi*MC9 z`aK;MwDp%6fHqY`d)jNwSAwkzXfdr3@uQd2hYDUp*laQDlY(V@$G0dywPO^^iM^yj z)*1A^ITOQ{JYZ*Q#?V-%2YGU6p2R&@tRBPN(yl>-f6AjOxw3)F^)UX>;t)k>M?XqN z$uk1aH?d#ij*cN}Yfo?N2rd>|6X7B@H&JDj^jTpD-~vUHe=7HwcsW3JJLAYM>r|)8 znWGFO?@Lk>_y|`*mBJ=dMuy9{zCU>X2{fo~%0*8NnQaWyBHL1R_dYn)CKc1#_E2Y}?9)>^)2D?XypP{a zUSv`RP|Ht@zTuJMFTll&IT%WeH~cafcwhe`s8;n}Co9ap0`Izqmf=h3wlvNVk-;sQ^@w9oKIpQZb64@223r<{}&nA0@f(MdR`d zz}}Ii>F=U_O5^h;lx(dgL&Kl;A$$QHvo_^+Sn>~ZzGruf{rA1tQN*o~>$<;}xm2;_ zLm6%4<4c<`1VP$WJqW+pS;J7>J(653PBn|}O=*^hd{W3wk35G+yZti7XyZ|IPp+~s z(TM0LrzZOxc)mEUCjPK?W13FKtOZjM1N`X<>OaQts)R%yc!1((g%<525FeekfcO(4 z#aUaHe_ES0*TvUPh|agH1o2l{!eTd#M(&a}AR$EE7s)lUFP9}^C=><42aeDe01;TWC*pbFV2qa{vDhQ=0M<$qTQ3gL;N{=a0VX^Fr@W*r$~jBIfYQI; zbfHG!vK&%|haEEuVk@S4djE;ZbQ0r2VsZZJwA3;OehQf*q%cjK+Nw@8a^5p(EmFfyFW zVx>mHIyaAT^IgpStqcc{<66fg&Axj}1@mf561{Yht2OIHRC)+J8I4szhV!q(P$$1ZZ`W#`lcM zZ(Xs=KNa6 zBgRTbjX{Mzdk`$Ydrgvh@^J-*%pIWaEtybSaa<{E%>y_s?6?OkxDY)(8_FdxTAET; z!{(h=30;%$>hPUZ#$-vL03u_m3at`5S(=MvqJH6@U!CEA_x>KonIUp9y69%545Zt% zUqRM<+2PS9$wm~x;)styE%h%2Rd>AxtP|QBoH;mJ`42Mq^T)QL+|D=5RMR|hK%3-2 zP7o0+eYGJ+%LF{rA5k*IZ@oxne0ZDGLX z&9x?bkVj6oWbvh9?#ca&TRxAEq}hsVR&d!s7J6Dq1mj5D?6V+(n1D>Ogq0UJ zOe(V3qTZO-eLC&mvimo(WtjPJLXzN9G}mQoWMrGh#!K{i9A`|KUK4w+hW>^f1B;RV z#T*3O1U@B{)#>kiitgQRSL~EKWygV~!X#?Y!!Hu>lj4fc34oVu4#CVHRcq_^(KIE( zbK%>UhTOV8&T|LEeUq~gaUXFAS#;dU`|6NKt6QzVVFF*yTfmwbGlE_Slk3q$>A-4S zOJ!kZgQu%41*oHw=Q7RDwdIGHkjmvxPuZAs0)zHp76_BIBih!9csF(i z)-i6ZKNWymv;j*&hS;OHVtT%GCIdb9*|C)h>DSwId{s)vxZb9cG3FlQqdNCYhQX#A zf_UBeqbe%3FV?jIy{oA_vC(s|%jaN*nvtJtJ7Tgi6yBzh%588ESFZdaKIX_sX9tj` z==C(@(({0yp(DO-2i1T~bQxDt&{AOifK7GS!P6xl7{G{qhkmX0uu-(s5oOFxrunFr zb?^YS*md^ng2H!?3TfXBBYrTpa>o9gbKp^ksjkJ1Y=coTUj>WuI5thRd#xp(aao3a zU^4^{_De5pL`j9n0+WMsV$Ui6&jVLx1jQ{o?APxZkrQ3DN@eU~>4j~?=J4qt7#m?? z)6l&2M8H$vbKs3yA7*8~6oX69lGoiM?7oxl_qbOmuHWC9oLl^t+m@J38NC^)LrGtCW;5|3U5glaUWyw5yN?o5byw8dsEF|90aT4?3FVwRlPn8>XeTepLe*X@zrIpZRuP? z`j5gP=fr!j7`6+n}&GQRIFJrmV}vbWu9qS3I83cgS}vq*Q> zZ^vNWlRD(2Ynp(U2%gg^RlnTj-YNzaB`J%lZ5<9IwmKfpd#zC0s@G>~bchfEGUdwi zYb&l8X5zwyr3?~1OWYdz679=YOa``0ubKKT2 z*U%PT!N0xp!^TWW#Ed+j`?*Z6OYOXd!hVVVMJn=XWC8)nAzD&TNT%_Pm>Z%#bW~fI z`62sn&yG2AyVH8mD%uL#)Y@O2xB&|OI0`M^36$YOrr3LrHKiA|dC9&YR< zp$Pk^HwHsO{FD6hLF$P(*s3J-LM3BD20D^F8e=G@ZW}07BV)ak7Iyt@0u9G3)$Yg4 z_|>i!vj1@9jyZTJliY2r3y@`xV5Zd_!{;VLMh?`IRej&NJLvW*gZJ$)P@EVGJS;*f zA2rJ`U(VO9yh%Kr;q#I@J26q!VX(faYkXhdTNB4>z^O*X)=nJ`@9C~eo8OZ=bJCpk zjC6Q1gZZPpLmjje<^&C==757?vKI2rD){!fSK}`l0A@nyGqTW33|OB4?)7EQqRoqj zZM&~2gd;_J4=ToGHT{Dxn=+3g8mkbthR43(Bunfwru;tR_>Cgu#7&g*25Kxfw298K z$}!#+ORzoRP^A<_7RvDh3%|4#xLXwQ6%Lx=U#pol z`$u6i65>6K-IXQ)Z5l(j5E)TcSD(k;jWFts;EwzFop8a73*dkkT565U2O*u$E}PoX zP*+_@59XH1g!6^+IGBnwFJ7MtKTO+Xu%&18T>Z({khD7_I+T2ZQO&mh*1UPo6 z`4_Jk&xq&QvupBCO!N%Y3A7%Q#!c$zkiK$4myu*aH!A%QW_)ifp8dzgKA+uJ;@|7w zCX6~q2hz+yZa_QgT6c*lXoln$csh|J~1R}pKIXMuErh85eLv8?$@>kleI3tN4OL&(8)ft))kE72{~%$-|b zjcz~CChQ9nj;$}}AThtblF!$1x zxi?w=0PJX@vRJ;o0Mmc@8d9%?H+*#wN!$)+I<-f1U1+jkiPor-v4^i*+k0E+SN(75 zs%VcCdM`Tcd|))my{#-5RLmm+zIxB@-+IJg)<=Jj&|KSYw+7`dJnw{L_xpfCV3(K@ zhX9tdONMX(hmZP?Ti4hsCDs$Ibj7Fhiy8FvMq~Ch#v)~ZCkWo`H;iVMUbHfE{KTiU zl5n|HAMukHqnkiQuVkF-~%r+V~9}uvrkoON(MO<1~u-g1&%Y8REm+ z&x4hZx?<%>aLFSSN^Ce(H)%+fRklG&CyFR+y)jakSvB&@ZYjRLDp2}~e#vKuo)23P zUhq)92ehWWq)GOa6Yy2XEw;Z|+OQ59%ofn%A9SYUt#`n1?6_pe;ZPWlNo~i*MFXH} z`aGxxHN@ebog&j4jqP+>b^^t+Fx~#u3h^+vfkgHtg1D>bBqZ;FN4p^@tCW>UHFSN- zH?*3JKmFak*#@gF>xPmNY$e;z$YD-Yf0?DE_!?Gk$pN zoRIk6wUk^d_h$rIx>6r*wm&S&)dSjJrWl{{_uM)o)Jm3eWp#4adt_6d!zRlQNR(FhWYm#2pYrv@k(qL$!) z%+VE6iypR{)`sWTlNlC}PEalRwj>X0PukF{26$OOg=5LYRq^BLxckTM%>at_Nk+XI zAemediKIP_-%^C|Gt71+w+~SMM6HN4NVS#(Q_t}wHL2tV%UxOa*L?zDiAo)tgLhq* zk`5U_6fAqYIEWVugXqv^(4|k_AV$gJ_#;o6mD?JiC#h>Xt6YXg7Y^errM&HnY0MNk zub7NZDTI|kac^{W&UB$D(SQ#|rz55VVnk_bV$Z?_~!Tv1du=(xQ$}=aeuwj;w zP2RyK8WA0T8zyDHBjI0z1@Kf0i^QXhN#iQCn|ce?H8Y+n7soT(a;wjJ^ta+lNtihA zGj2e=qnamscvzVep7sk<`d+Hr&~7Uxk7sp8UV`dZG>T)!4H{)!Jb)w#*yFa3)e%sM zb@#bmkM{*>&9M1@XJec#kin^Z`12_C(CwYHFIAj*U}bCFGhZSV;IlH}l}nnO zv;k;)4DFdXka^WSQJD!~4@dO+owgeVNQ{pKEo8tkK|zEj`@OIkqOU^KL+hb=%rMZP0|xFQIA>b^~X8})fIg{j{w~RljDDX@$oM7xn;r0 zD=Y@4g@pmH>l7~crYAJOLW}pE-ss`18{r26h}*80(n=M6@Px_q_M3R+N*xVK5KDiG zi8HC+td5zxkHSv2y2ZDNtBcflwPVVCy9O~G#@mwNg+G#?%p2E8aNpV);U8K&?8faG zl$Q;gqn=kM9RXq{XFcM`uoRo8eRuOg%XGGI!xE zn>9!fTT2GINb*W~-GWV`5|fi|ALFlVWXe_))E2gt0G!(aLnH9Ye@sM-@>FY!gnlQ% ztJMOgP-ys8dyeSI3h41dW82_MB4L`l#VE!$W$w<0L;%b(Fc`f+fIA`cN&>ynIfzuM z%OlP0On7Mw(QX3+NZCU&93e=z_>_&pvt_JlJ!LmrI{5y@E8dTT?i`-2Yz7@qm4`dF z{BmL1p$P9Ag+~Ew-DH*yrlcyAM4@sX(o-TcrvxiIfyxAC5IX_$)bC=VXj-0J+g<%J zqRa?cPJp^U*&Zd%ZH#_4*yua;;s_gXd;i|Fp}X3cvu*3w&BmiO3B1~cwlYV_y#Kc6Hs(^=I;atr+MT zf+q4t`xnqS&u-_Q@X?me5(XNQ13ePAyCaU7D?pi^VvKn4BuhhK_h$JtQ)dJbwR>wz z^eq7HGYwhec57|SB`9j5!{YTi9ad*5hrysO@xd2fB~*pr+;bASWY;1G*{PwaR0BQy zbx-Y6iL`=>(e(h6xgN)?gdJ*)x2WB_*bLtnv3E5dWEc-eLxKInz0$gFs1LtElCB@L z5|CmkVr=R0HrYri31U)kL5Q<3HdHjBnT08eQ)^Sns^2*J7`RNie_H-ax=9Gt#i_yy zrh*@=)`8?v&G#L*Wjv|9{iDf#AD(-Y{m7HJ6{aCq?XWxkQvO#D)xXkJoT!?N4MBPG z_)pP6h7g4mJIbvhPyE1IprDiC8T&EU8^E0>cd;~ty=6u-V$?3JboJsgFod?_@%Y%X zbuBi{1R`_^13|mVU7X)qTqwlqZ}F{(b=vS_N2UBI7JN206Uql<7j@f-y*sQrir7tx znc8svlOt1z$PLn`1aqRXn5Wy?%Km8=4!B5;X<_?HULOQB@5=JjfV2-yjWhuPD1g(= z#m4cos*Mt>thv?{g&!ADbrFOix+uw+rmjRPj6u>;(AUZ$tVmzknj@8}Y^{q{%?m_I zp7sE^A1Aa+UYrxODM}>01U+5X+k4km56Xfrz{XWy9C5tY=-HzJVQkt=dG0I$tbmzx zF?RDU$q5_eYw_N!LjYNK;Fm!QPtD$& z0D8inzDgr^=KSlQbC^#h45zHY7(!gZ^H{WXt9r-ohS8Wn#qa`=IvY1)Ll(0bk#t0m+RZCbSTyqyoGrZv~6sY2nVK>04Hacz{>0MA>dz zQ|_Nk-*$Af&QNViZx}qLm*skxy6bE5?>nH(IsY8Yqq5~|uKW4~Pdxi7$~EC&>N41B z0+r2k)?BmsV({3LN2^>Rg(T?_{7GQ)9U0ph9f4gCpx&^73*vXHwZFsm6_(FKovpA? z+|R;PwOOpT4v4xz6OF5H!hna_`Iy~YI{shf@c5E%L&_yjoJ*c$R1y$96_g$vhUN$M zw%eD{x9D?w@Yy581ovo0))WI}#2l#t%kQ2xV@feq_~4?t<<6?~RQT{IQ3w3$wn3e* z-}YgZD8Eda#%2Y+YHYM=#HDY5lhkP(&n||mI+COQs0Q1Yt&L~}kN}9|#zj>2^1{73 z)^4_)Yvw++^9vvEBe^{1r`n=a{F!rULCj>Jt7FYzZpIw}C{guuVcptw2aGA3-%Za5 zT+hC#rQ%KJMOl~(_ZFY~QxQY6y7!8Eu@t{owtPj!0_nmgjdo^!K~ym>MZdjNtC^x+ zy?zktpA=aW_EFOC`2kd5!o_0IOvRvgnEsv4dRvQ?_&Uj#aT%dQQe~HSQoj3pYN0%@ zMqjm1N;y!c6+=ykS+8!Iq7(GYMzT3Hw`BC|7UIW~rv0vZmCfVw$3mDFV_3@W@y(+_ zYOAECb+kmMLKq450-HgSh<5DS8el_Z)=0TYls$CRS2jXV{{=`KMMar(daYU)G4^8l zHr88zZOm0X1xIqElE*EeNgwL3hkBNA?K@d zg2+i%@|{6cz{MgDCe9G}o{+xIRePO1wh_9{DD&#HD+eIHc-nrpJ*oTwj0Gp|=El8= z{MLMdhpFCFkvw&|$#j?3jzN2({UbKE2PE~C#^E;|EYa5Qxz<2Z=+~EfiSYTDnkWE} zZk|sH=mH4KRLEbpJIl_jR=Hyo{L&a1n+ z=jpM?sq#MBPDeW-9bJAdE;2KslIh!ITcLCGTfn-1Pn99jW(x_pj9PahcUr)1TOS2Hq;U;uI@RKjg00$VU?W>s(AZ3(*<)E)UY z3|KB5X^#&`tX4_s(3c(f)K4Y%aj7PE*^wi_kT+72Z|qwMd2HXbY-EsLsDMjD?q_-y z%3w2IpLF;9(<)%twqU=o%;(`xf>SAToOM3WS9f6cRbCu+m8T&pZCASP>dUq<<16{# zGyzNW>#tAec5o$i@#<|f z<~)gVOoWcTrM%-LRC8XwUCWA`#2I^sFQA6@oti=ls#$_uaLlS4%CPXn2~O8crFNM8zx^7{y46M^MMziL4-Xy zqMF+eZ`cH!UbGJvf!!c}ia&nuYSzI31YHb5|cJnF^ zZ}mKM0~^iT!m_J*M#`eUQA2LPA8^1}55KwL)kAT_8)YRswvEZL_!D$dwA>tf=75T8V8-446CP~^a$WavQ$nN19tYNtdB<5Yo5W8J+qQ{g4R_&P> zy};{Xwjr5Q>r;|S#PKO{2DK>)5T(_qY^WU4MDzm`Ly1kpCMj~vHB2SkKK-#rs6%Pq zz9JwL2F{<4T5iP8K8({l0N9q)Fk~&+jr2JiJuhkcRzS=79UU897p>|XI3|o@-8DSx zk4KwI)wn6u^jDgVC40V11jdpx(OPjjTTckAs5Jm3n*;;tJ5lQ4sNaP>I+uU-pL(IG zZ6&TSR3n|p#Bq8uDiYX?1ks_Y6Tys=bg%Yi;x#855U?H6`S53 zXuw>0-`BL>i90})g!Eapf6qcO_L@rF47?){7l@vU5s}=gSmFu$@&1TP3R(F6K=3hG zujQq^#$P{mYD|O~;-vqOtY^Hvve<~zd5Vsk%%*v|h4fv;CG&b`;G*!#J%%tp86>z2 zcuyR4ipl&xRNZ56U`^C6?AW$#+cqb*Cz{xtBs;dviH(V!iEZ1qt?zkHeQ%vQ|9W-p z|J}9v-q&J`1h;`>1m<%@3u1=a(GLPfplar7R20z2?*bkjMmS1uK}%_J*R0{BXZi^n zSMPl{;~gb7&5r~FOKT^2)~bF9FS28=*DCnZFBInniv@eoAkW#ZhR^0>T`xM$rhoy? z5gZ5|#vhYt`_)WR?&`2E|CA~pOEi&v1KFquUq-!cI^pc*0Qb|$Er<2TFyHlf1a#Y< zyA}d@o*Ut;h@-yC+W2<$OfGtLV2=s~6q84-G!H5P4-MBrng#A2gru_1F^pIBa1NI) zOvTrU!=5cS;2DL(kL8~waSf*6>%*TfgIyv2T98a)nU^PPzJvu4{gm$wa1YaR^2&o} zYl|T6O5Oye0E9uRYu%qc1i3$hQZ@$`Fy5mZF-sOK9BACTCa*?5sH$v_n>jVh#QhJJ z6<2@0iaCN=r9$8?GOQY?ryov|5W_XbGaz}l)lcrV;uOJM|9(RYv0~O5`Vo#dSa6)| zgYHJi)Js?qUkwGjmFnzY%jR0SP1F*X$&J+9YR<;V27qA&n+97;3F1k;c?Qo)exOH^ ztyE1yh#6+CSucJ5?!{e3c*s5{*En{QQ`XnJC8JGvLJ#pRhpk&{MMVDOlRS8h_w@JwJr)7HAsi;r6@v?iR5lF9@E% z*3k-W0SxlYlMhK`aSs$^>W+;Pp|Ntft8lPyfd@_j;Fz(TQ-7PeAswsiS2k*Q*Id>= zgd)#oBzF9YPYdES$8Vi#8&3kM2V@P(qpmL1s?yLK;!{LZHWBV#T{$}=ZE?u^xP%WS zGNlG#jc1f6NMXt#eSWHV+v1tw@n9O)a8h2Q0)WC5Yq}a={0$_8wF#+_$4=#eQ$2+s+E*zu!)ErKMeQ0ZN%V3NluL{l*f~lC2F6{1uxVH3n zpHAV;5orjTI>VMq2m3+*-lth@=#KW4BArxLHH6Mn5GjW-Ymsl)6`gid1aF0XEO~-I zP|&`c#v6a()@!<9&B){WW1Zg7I*j@sRWIKY0cX7gJGn&Ng+Ca zm7(4~IFhr92)paNv|e*MTQ+a$xveENo{zU261!a5Y~QKilx2$;*ghBiqr;0hyy#U@ zYqX+4rY>z|Lhv{(c$Vb2;@cClX#z3_z~Aumin`w2WtuppKX$$L01N2Hd$WR{*ID4| zI>M#IRrhm2+x*t4Cew+Mv%w`n^W^KgV0<^#?SOIzj@r5zXZM`(n6WWU*w7=$+r zY$+1F7KECZ&}*tV$Rry6w#Hb(QI0GU!mBvS{ZNL9+`xPv`#IY1x4rI3(~F4o9 z2?-Tmu%CGxIif8`J8o7a-~ouhN(^Tp_4(sr^0bA#2SDeyE%qtiNK7ttj|%b`f6%fP zzL(yS^BZ@ORt80b*IgV9m`n)(MF|?k9}b>qT8#GDs7|9gLlb^{S(V_on~}>%G-E>f zYIpl>mzqs-r!H;EFL{^TW~evkSY3waO`N>hedsAdPMC;(XNn4uk;!kkvd_PjrlGm{ z>l}qFv|@OEkp{f?kX*-$)q$O zmN=7@lmpx)x%X&C&kt~pv|*9WHQx0}CxdlF2PS{yKhp2Op`^r6uheRRp zv#C>3-~Uf91o7TbuW3J*l9?Lnvbj`ltnr*kRTe#kmTr)=AQf4wk5)bOe zBQ@8{3=w|H{H36Q%hn4j6hH!(OWEq zhXrJ_CXqWG1a5R9xgd)94ReXlc1u@Hc66#PAl{+?KfcZES%ASadW2w;wA=o5Qs}Au z0_zwoGjwu4NEf$2$9W_edWNgTM7fYz7k=V_KJf0d!IL(KzsL6OO0BgK0^LdU%TW8m zcw?{{e}0&UF;EGpbml6t)!@{{+}1cDk{923ns$~;F2nC;d2HoFin(_69Mbhc^Jkw- zo6KO}nh=Ar4^wMlwjw0#2jCdf(?@azIfxbUG?C!F?@j5lNhER_tOR*@Y)I5xwW6x7 z{yw6Fm$-ko+xyGc*@2iGeP{SJNiO*y`IF{JJvz3l`pqy(8G5IF2@K+}r&$Jw5B zOYN7ZtT0WwW^Ju9S)`U}nBl3fQVRdbB&W^t-+E#s7%4Ca=(I)+XrT6laeHt7By(GH zTgIqg_K&ungcht8@KoA~LMIp2M~A_X`hx9?izzW=><@4&lW7=~bk?v&H{tmz+P26c z?FtEY#F+&q*bI|7dS0?de+(M3|K8bW&-mdrt5GzLjr-Vvm71Psg>{YoiR^i6sDYgG zoSm{5vyz%$C?|p$$6k1`_BZZ?L*Dzh%2wBQVm_{i-=Wqon3Iv{SjGJk_Oyo2RIkfx`lKd{2W@=Wt%cJT}s3s<0xbdhAcz%&%ICJ8Qc3RQ-d}k!0 zK5zPCsNek%4T?(}*`R_+cTNuh9$M_P(b@!dLZiU=!1x+u7gy*Ruf@UJEtNsE9%3j9 zE@#s1;-sM++_-~p;BT_wEhQnX%IYjSa0g&h&F6j_dleQH&~n-1468rs&(G>B?nfzOrGov@FE z*PDPAV$M3@l;5j`laW2(^SqKRbx%@*qAAE-pt#%-?IEqThRw7=cU(&i9b>>}sDO#Y8U(Uv3qGx6>lzF(8P z9WbSVLoS_`C-~Io5JdUw8Gf}2@)Z_3r6IswJJUG<-g*o^@rL8)7`dy6koj$tLEdb$ z9Me1b`Cr910ZjU!HGRi_(-w4Zl%)#S*djl3Z329r4dc@>RQ#Q_(_(ZYcb)|SH*!>q z@)mY+;CU3>Rxih6J95!&%>Rx$vM_5H8ktdr zNE-Ulc#v18B-Fgv!Z(jZtU6zT_Pqm?2Rb(@oM+RDsE8gUmZKh&?)IxlMl#VAbG?=E z$abF@)_kfv114Odnuv3S1IJmFHi>dbLmawGlTTb;v);xj zJ6|+x)2y(6<0G8Ad_lfALH;}>7c^T*^He1a4j&JGu!y^$hcjei4T`sbzfb)TvVy6H zJ_U6ce;Klkc1#-#`SyHGtS8CVF0`=<*^204#l^`w4DNmCFYrq1r5XzUgvIIC%LjUl ztgf3-eY064>j3Mj*WAn@4%Jd+cYWF6Pz^WZ`+iHXNO}WDIjj|@U{&xaZn`yUCN961 z^UGC@TY7Vz@!jfZ#-&m~SI{KX)2mBoSmfx-OH`_uR~q@+Kfg1tp`h>Od|svX&0$_qrIx%|^&Es~0j|WU=eu zj&MdKsstlj^5lY%5NAR2djdO?YwqqoQoFG%a^0!=f_c?(%Wi+5>BYYpmhAH}ZEIG` zsnaV-0;Lnv-F2Pi3?U-YQpbjP_F$3<$}2|B{593~kN;bts7@1&=~==F$|>mZAnesL z>1z2Pf~1;B+lhJ&m>znTsO{-?c^?+u*-AJf-F+{Cx$!@>gx!vrgRKYn&geswN~=g4 ztyK-mS{Q;o!rwuS9xEhuAZNj_H3dNrunhmv^ZNjIWd?_4)gyQye|SWG9*oq)~gfdaY0c1Ah4h zp3=EX*?Q)H-?t=0wx+D70D(9&bq7?|MBR;|Hn(S6Y*Cn?90(T-u8~5YZ?(SBUKml4 zh!y8E3ySSoc=mLc`{eB2(!Qw@Rrka}Qp3Whj=24Kl=QzGdD1CdUZ3A}T(4{DQf3Q8&m>& zyQcMcH_AxK*rdOu;ZTdo*V6Uy(nT~{+Q*D!;oI-M4igv-wI9r3e4B6FBgE4q;-XN4 zB=jeb7xO|4ECVSurk{bhKq@uz=0k!goMc(57D)D|=gI~uA^aoy;~hk`O4S)?$|Rzb zn%F;}cqH@kT&!QSqiDpz?G;gBa-uq!mPli-Fb#XG(a_x_Qqg4%-U>{M4|nU%ve@iM zSnWWuG`V%&T=%Bd)qUcgQM`u#=M+o$*b5P`LfNkAq2uf*>V@J{6BFqTdQ319f`D78 z8wBIf{pY`gr4D72+4NIF4oV-&^j8MLx*HK(`=Ca?;1X+nFTOPDwO2$xdld-AbuVl- zKcTm(@!+*fGu%n8nceUYOvKawBH6s0&Jzen+{J2hBGc>OM>k$@14Sj&vO9TIa7LMc zAIz+Xc6wO;^Q@bZ-n5Itu7M!cCq$)|cu(T5vp52a@=!_!8q!zIH4U&Lei6poMbP&n z^r57gPhTNOLpk>hi1Q$&*qQLT14z6mOs@Kzhw`^jnTuK(9f{i3o)^wMyr#Lw#{kXB z*fm35?ara8^2@WtepS`K^^zI?elFPo%<=F*Xv(vvds+TaHr`O-j*aJV*6W@`rTrd@ zv+v=bP0V7Bgvl@?lH0fmN~r3mg4BN&Fkz3Ko^vQnQwjHW7IR;{(zCKP=eJnmi5%>S zm3-8U0yffr;*xSPw3dqM;vPElu8i%^5W3Zwh?T7F)x+FtUmsCs>NX{JkldGnVCWEc z{oR?l2r5w#5qj+>HSb=`)(MfATLD&72D!xY^KkY*n9;s55HB{;8J7TVmY?R?u!_>f zsk)q+r^M@HPLvv`Aunhc39}JLP8u`fv51Z7^-$+XDNj!b`J#>=ucFMGlTf2!h9xQR zz&7gE;8>Fn3KImfHc5os-~9<7s+{q&u`s%2T?yuRk8zd-5T2;rM_a_BPasi$6sB=h z8$&Gc$rmWb*ZNUGG@jV)!Wb%V0QW0b$L}D5W5$lq2JshPzmiuaS@5x<_^Cl=LGH~7 zrM4jK2w>j_23^Je@k(KpbzYZnWbAAn?H-n-*DZ?9T5qxB)ic*t2(|*ke~`EkR;mz2 z6j!0wm4vsACT&(oA;1Z?7SV#kj`X@R5xDm<%?X1)!KV8~|K|Ru56I2`&IyE-S(q+A zXY7W1ilVx2>-DWDf#-%e{&A~mGWQgII{Wu&n}p{?X)IVux<1 zCFn&s)?)|OL(=+m0TOI~fuNeu?HsQDC6Am3wh+p_QWKo*+iTJ{f`$z{c9R*7-B|ba zF-Cz+h-$a!Mo68Wl5T&97>sS#@XQQ>{@uta@f-SiEVnrwCg193AtI%4qKEs_aYA7Z+cZ!2$ z5?=)&$TfQYV;K)wsUD14*y{f7)N7J}S`DM>7uLi~e5G>gwdvCUr0OViACb2v3kTEe znpmrD>loox5JpG)6NA3Vu3)P1oQ|hOGfZV;*|Bgc7B8?YDPvg7mCot=WYV@FYvjNP zIJ1_)yR~YBf)SZ@?Y|dfeKfWz3FS9xZKG&nLfIzbNbu_ssac*ijIZ)X zm%L7D)qda-lcY9dNu1b5tMm%^OK4DDp7;Bo?-Z|Yh|MPyn)IPowgEVAFzU3XNPoOB2hKY&N4 z2$mW-JTf-7SvQO8AlGYk8vHpJzKv{7DCj~_yaLdm%>p{X(p#okyRqyGcCYM~DCh&C zN;Q-0BK`khN*F~GAr}%f@!4IJRVwqhB!$`#2TWSesiFPsjp=4?m(-TFTZ#AYSi3;y z=+cQcgYyd2ed!BVtGcIIJ7zZ zV*v8uZALhk4(3I1b)3km;88w*9Bf~ zUvi7XzvuQo0Y25?w5c{W2Pv2|DA6#MArrO^d;sRO$2W}&`(x)sWf+A7UekAEZsKu* zw2a>TzdA-DHp`3qSJKS-1=>3*i~S5iu|#4tst^JxN*h*HcO#HJ5B%;o$EyleGl0#C z^ZWXA$`HMtw!Yd1_dpPHP{-f50qjv4LN$G8I=d+2vVH1VN$u)4(h+L2L^gOFQADQY zqs_`P7c=oe1~_YkP8{ZfcCS>ar2zFqJ-lKU6(;P7IE4qlqInk%|KDY7ue&a93jL9) zbqne`55KVQ)N}Y5%nz>!d9G-_W?=Tw4O*USfo#Aolc}xE5{sBXFHjgN@Btp>>zyE-XL;2=J@y)t$$u1 z{)!ppSMl=%GB#7m_#akqB6+gp(rZo?RDa}-k zh0UOMe+XiX43$=DFSg1#Mu7876RCampVeBbfdKd>GYgeVSQAod2|zlL_b>Y+I58gX zv&s{ne?{?v>0RA34R+{!_oEVhZOcXS*YNKg8pf4?h7G}`wUPS0iM^;Fd5LA=>Ut=U zvkFY%;3`kQs>AlLLLZOLyd}*77f~!qR*1U1&U{#d@KhlRo`c`A2mm7RX3`jN(sU$U zlaglpP|nu)&c>d?f_G9M38xi*h-ppxOlfH`W%IbGg8zQr{KzInOR#qhl`YKn;9`8O zUWpHdK1-MIN*}9e>f;SMpg9pwuk_0yjCLJ$IAcX4^~z-Bc&>;-iAj9Oj%zIK5$(H2 z$Xyual8~|Yu$=jga2!*vJAYCo~ z!dsFY+hRHUbY|kxFtPSKpR( zephR54UNhxcR)DL8+51jWEu8H(dsQ|NX6_1_G(UNH~M}K!e`vL27<(>WT{t5pxh=eNt8oai&W(B zU=;x@+Q2UVGoUK6C1`2lR8uK6vY&V3lBowJ_(JiMYvqJ&cKbYbQ)d)n*VzDch80y) z$D_McX9M0~-ri{H^)M3zKFiMw{!Pb$r zFUKt$e@qsQN%$E>BG=v4S{7!eWt}%@$MzNRiOM%G8bEQ{UEzg1-t8vJV%_NgdW4U! zFkI2*n~USw?M9$|V!7x^YRY z?$vJpbr{y0F+CmaCR-^q)trb{3S#v7n>y4$f8tCeHcP*F;;G!6LpIud+AI0Ae#8tZ zNOkkB8OTK>@-5cOb(zDw3;OeM7{@VHo`L{8V<03YM)^(N&~^93tu>LD`;|;fV{c$c zitH2jq1Gn}<{Gn*LH|ZGCpSym9g3glZ_e0#wy|*PJWvX4nSf;n`UZ&D&ZOJ(4>zzcn>G&38$YBh7A(2sZ711L`2JS{@ZsC_Fj{Q2&vimt&6PM%;1zeQmjB z10)LD5UcS5LXd{VUG~V9|9m2A^KjqnjVbJ>fDcS@AboK;y+I}18qApw6~%J#C8r!b z3k!gTf(Y1SD>r-j55r*zG0rZKA`?JmRw^=PvT0~SI9!9!xl>T<+O3~{8h$m8@05dM z%4@7pp^3-8%QU@O-@8IuVeL(D$Dyn>2o4JPZJgU^tSwf2R=<LqRcZ_#1n z*g}%l6=#`spCY+&iQxNTpizs`FQQJ~t>@j=Z_Kogs}hGHEL#G2i&kd8_$eh_R|~V@fmMUZHHRJz{kZx@4@?}M7#)qx3g}&2OduwxH*$S>*gQBMfS9wp3uwu;&M0Z2ps z$N?#B`E@b-VNne+33cE*{`%d=6ygx!}r z6dvB1?mDR5#-yDBDAkeX5D2e|l{YmvwJyla&5hD|dBw;k7@YH6` z?sl4umFcvakVlrSyPYS2x=Ivj0Umu?eCZO}sx0Vf=A^-2K;8h-zYFX=v;- z?sZ#hf~1_3iMdkh{yO!$5(A^r4cv3Ct`6iReHBOtQBYve2SMVJ@_+swdcB7ID1GlP zz7x3zw1!`(3xZ=J82!(U6n(O{06eGHXEWum-*#mn-&vwdPo{rjK$C$XqpXCO*_(ar z`R`-Om-WN%?Tc^B!*92bZwJYODNRk_oc7!N=DQGDH%qVWdwtLJPfm`IyZF$PskrUe zU!Xkmwi`=#W@+r?`-~#npBSIa*wp%Q+myotgVTeZE0NoSjpKb8h?$bdI6<=Jhu-iQ@BZd&f)e)q7@H>S7uY-R?HTZ@R_t+GYG0KPh1M?mT3(P0!50Ic6 zAR-91hvX?N9TZ^?2#4$;xeZ$ZK~M!w$b%k;-$qF8!-UvIzDSusf;NDNd-9;Y|2Fd; z!n8pV#{T;zckI8i^v!7RZ3Oy5ocI;tYerhA|9j4;blUg<`Qv2yh4@7Uh#duPO^0z5 zCJesvzvYb|rN7gfsvG)+KZFq!z5|E}(?7w5by>cl{T8eqkw0h_-jLaRF|6Kg<)5PCJ2T9=l}#l zKlwgYfaHC%BjbG(~KenVe zk*F9W2F*fx28-wyq_OEBOZG6*3O5u~$~?~#*W1I?1%7v(0E4tYu3P#T6-|&7j&flZ zp3r;t=4k=J8}FuP)yEbH2dK+ris@#LBZ& zt68{T^pW<@0s~Ya-Qt86E^axH?U$LwVaDXIpEEH6gpCifD@6*oK>@n zcJ(yiVT(S?>nF}gcfq*J%>yQ=t<9{V*Ea93(K3l~Pd>iMK)w2PsGsU*9uTw*s`e?G zeX>9(kOxZlt(}4J%im5JQQ908B|R78k9@%Te^`g!3yD&XpbEEv06Nt7c$wzuL}oV^ES7w&#@^=p&l9ckyml)X5- z$X3$kR*E!_=d497tpp5(BASj_0#)5!`F-qy(~@@xrM6_-pI>%h=who&SCg(9t0lj{3oTEd~Yo4TdMdD^}+$a*(@Wr%D+9(x+@(mP$aA z&Gr(hHUNvqb63S9QXZp^vA`CP3P0N-FrV=xX5kTmr6eFJR_orcfnN@@b2!ua1TcNo zVO9Qjb2A}`u7;~l;RB0;H#bmP7VT55xCi-QRcpEzXD=Q{?8XqmUxKk1fmDglcC+$%)O@9aO?C^mI>EcL9~$VtR@d$9c&s=?uSz` zcl0m6TVGz{gE>(+-Jjxc4?+kwKKP)eVXWzJ2r(2-xCiL5htvcRL_)ewxd7be9H}zq zKe=3`GJGL*6n$;kpE|B5-l7~yF8Ru%6LEHROIAnFO6a%>BuI-9gQYE>KAFYGruZL8 zv-{cncbR!h(sjy3OGABkE%R2ACKrsJPOwV)!Ump`673HQw9p%-;%3BZd9-bg@W^%1 zD_EY++zUGLBzmhe;igQe3qZ(ReuV@K<#nMvKb}fs+L7ym%S@eKBFs76oKb3ZS=Q0e zO)KZk`RU8eWhn0zdRCF1-!dYTl?4*q>whllrr>6ZWL`5~G23CB3;T;OxI%>0EcEW$ za%Z7)JO2{ONw(eU&tRM z`NqilL<~3tB}ZC*5Y}iTh01lB84NQctL5h*ysscDiH$!oI7dAv>O;8n)z%_v{2IpK z^C(+0ab4dch3nFzJfR^MY)G-SbG-#9=za<$qE7ttw}~)o@GgLSUiG43D--+_D+scC zWClBv6(L#}*2@}9!vV7N)fzcp39VO4xv~0YEE!-}`SvRhgix}Z0j5=>V$AeVw_@^q zlWNL!nw>1GDWzS?YL+iL$!e%2Dm24WheW9iFb*Ot3D}t)g;p3YI<{Du7<%`N zC2`Y=PgOh~{r22Ls2`S64e5>B_4)z0+lot7b_L>Z01l*3wQjmI5N6C=zzJ`=d-rYkzSHFkl^Jsum!ACe9RXipk6B7wPKmlYsrhPb``b+uO$>pHr^vKFI%i-Lm5 z)hbM}h(11cYahLt&2r`qkZvaL-}tz;>DMK5BWuG9c>oCFTuRGV5|u~>RA|9#7_KHn zk?}pfq*RWEtCcL$=*4!<$`>LcqnX0!l^t#iZA61HA3SWCtM5IgDn_+u*$8=`Q&rLm zJE8vG1I;SsXUVJ>Mveqmk5x!-Bo>8j97>{JF?Ip5h`$RYhh_;_j?4iwH_axPe0)!IG$R`*XT%q^>Bf zNZ}woVVVBJqZuT*-o=fsF2&Vt==u`rpH9N^6aW)hJb9Hcma3WV^Ir>@bI-B?248<3 z)D>1;DW^N9a<@I(YNq-u`szvh9N_fAz?b6>9WoW7lNYmc5>IVY*!c%REOA#EGA{HV z5|w8!T9p{W(an>_)y9gNV@h)nHVuv|Un`k`GY=k%Zuyt=3WkXPbi)hcSBq(}c&Z%* z4Zv2!S9_F8kYhY1fK6#K6;#9=+5U!PfYYENajyTqWaT~@hrWgwAjQnY_2F7}K%5u{ z357_mBr~iw6R`i-uZZ{4hwiocsfX;yAP*tZMJAy+5#4lNlCNkS8jC%tOC&)tZ3|+z zWw(XuZDp5^yp%wX_JSsZt-^m<^?8Hv1b{_+U+?~J5KZB2YMU4)b&c4PlMB_`GiSX6 zber)`q|U)39qt#|=bm(=wBI4yhjb{b-|DM~HnqBP*4o?R+fC(YRwKZ%0dS=J9yWL7m?0x3hzyQrJ!k51JE>c%RIc}IP;f?_a4m2B>O0;vOs5_`Uw@$+)2&OD8`lAN*Yj^YQ`O~MB_@d z!b?9Y$M*pT-u9TkMJ;K!1Hs-kQ zNbsv}zhJzn#?!_%jKGe7?iGqnhDr>JRaeT#LTba3lPU`p=vd)4;6tQ14EUAahg=;& zpvz6@MMR^Vgxu8HMb)ktpDH-*X2#y>W?Wn$lX+*OHJU8z4J(9i5o{kbigu}lQPOaX z9#7>`m2xA%tqx^Izx8z`Y1@%Fr&m{?4=k`0dcT^9;LD)VnbVK`GDCqMu;U%{A|793 zF~OWCq;L56aq6`K@K1F?K_}^cH|L96GOV_m`DgK1p9oLKspLGeS#W*q$OQ2voa5gL zc7$%_<%w5o=(knVuW(BF z73UEJVLATs-qmo2`?K*NuLh7mhQnSwP}$XGTdo!PhdH)yz($KS8UE*nWtwEP7u`|g zz~aL7Z?huH@C&8+KMvR|%*A2+n22iyOdfQl)(|&2ewxRQ2lny0C2lS>mc3XPLXc%* zH!e6f6x-eBy1KB7`mN+GRSEmus49vH>l|g1QD5<k-Kn5j8MfQ(NEbY0!_Z?N-} zI=hVq4e(QF!(a8-H#m6-(~HJLnp0&{>iLEVzy7`NUTF8LO|$Z8-g?R+OQW4ml(I1;8C>;&%5lQW8E zi}Msk`7D=BwKeWJ^zexP;aI@r{@^ES;HlEM`{Tu*gz)H}>y8kS?ywTIVp!V~$hcPa zcq^0k1Ti1%E_VYgY4`4 zL1m)?ky9m_4@;a5vpIHg=na*Bj=kcCRUk2g*7#k^vh48)4D2tIh$f2ZQfJi7dQgWa*j)tH6F#zjVj2D5Y{8Tk_;g%0J= z4NoQ|ThJ=5zE@k)>l#;;26e-e&-XQOfbvtj{=+X32NgREBMR){Io05gz@50@=*PPm z0sz(4aS$5m_C>nRWjBDb5YVw~#jAgEl8q{1Q$I50J%&4MrGN+{kvm;Z8gp;%CXCG| z@3|=mIorw1g0-B~33$eqn`SRTqE0&3hb@=i?45&REpuf)Rd zzrDd;DFYh8Jb_OVAVfv?l~?myERWuLrn|eeJlA&C4Ua< z+_r1>@>b0LBw~2-vBg^#zUf@79E^Lxv9FBgs%9GNNajqa-`rXGPaG)oj;F0{yhIr1)N zd5mk=*#S4@T+r+)WT2-H`N{F5MdPwwK=OTEAkb9T%HUGYoVnw0&JWZdq~pUWx7VPr zoCj=s3(gBiB}+RW>)wII_XE2I#k=rW8r*W8m=t~HuM>ZZv@&Hdv-H|AL4HmNwpX8L zf!s7OOpiASEm@{IMtZqI{)_2As@_|qj+Ld~rDx6zc{itgK;d)PPb$ZO7WqMesP9VV4cVC3pj{@+x|TgDQg_&?kLet4s4lCp z*T^7Khp%*EjUnJA${OUqYY8K{Rog-&JLJuDM=LMVtmsifM*2l<%ChPAB)!6*N}w-a zdRmfSy@`&qDWsAgY6quVom*BUZ965s_>uBEA@b%ggl=jQ*sayX7;sbN zH^ybM#H8(qCuHLMmW<&?Zxp5FYviLZO4b%dwA$t!egH_v1#-Zt;N%GCBM|q3MG_At z+31MW_qb4pu)T?Aa7@a*W@b6pK_+w6jPCRiH|*Dbuz*Jx1$r;wRH6Tt;)A|Plx$v0 z&t_to4XM?4-O>IxI$<<-QZLM)D3osg6Gqv*H49rQckcRC@8gtC|K76NqTnf6S7jgn>u z0!831=2rYoGAyDT(+}u~<kDdq-0}c9Yn4AlPU%Wen{Q@(gT06ai0{^= zZ@cCEBS{~33p&Wu5Q8-qL}F1OkTw4hgBYi!a}R?frtR+$JXP&)*GDwHe%|mr-X~6J zQb!jp&FC$*FC}a*_fAb06=WZE)VAxNA_@Sv33;M5^D{#nysjadF_(e7Qo?fvGfXc} z5K;N28JEqlO)|AC4z-L}0pKaLob*XUv8e$LRnf}74nIIgS`Oc$qM9?j%I2Ns+V6*U z%X7tc4#7%O15$!Y!i*C;X5hHdVs$lJJWQ_8Kusiwn3M4BeaG+2oio!r>dEl5r<8z_ z6J;=Fe=3$(BY&?A8Wd-}5%&i~5UfNt6>Z`FVhz^xggj z8!3z<+v||=@h^JW_n2*qTl@Vz=hOxHU{lAD zts)b*gz9X6b~j2u(9Yp?K_~A)V9ljr)La9tP5Tzt*52}@H~ z@^Wxz>cH7*THn>Towwqqn9mnm-Dr8SiA!g}>$#(H_CsX&m)r`8TDUlT*vLCpnU2@1 z?@M;zKjo~ed3fe>$@?mjhJ#>C`YovhjVr_}{i9&DXS@eOp%MjkZG`|b@$TuLjp#2q zlrV47kDjP^WjAi+Bn(zHw~0zR-Okv7Iv#v=a>B^hy<_LgMmV~E20xMJU+cGBsu``k z9!`t_He~iDfO)U$kg5h_$7*Q1bYURraurDeM>Mme1H+*dHQ9$yB8ZnGez@j!Z-fCy zX9i7S7MpQpuHo}M0SQQ)XTCbF`|Ps}PaG`wtK+VnxaTiA`8%Ni>hC=f{R;!UaNk7U zFFHfkorp!~Qxx3uj^S0E1%tUwGqJF(@1Ctz0{JzoIn&Y7lBV2il7y@|{7Cg=x=e1Y zt1h{Vp_Ei-xg5#!y?`%Fy1qZKZDL=!%~eC(;K7zhelIP7G6`sAt`tTW&M8a~Q!n4Z z=67?*Xs1#nEox*$KOHhfhAj45+UA)6e-ksTOsJBab{f7*)ighbb3)YUj`;1>W$CTL ze=Fiw7`(wb1KoZvRMvhA)N8`-qc?Tv59`bC)lf3?=g2crW2 zje(orlvOvh^|TbT_XZ*E2>W?3f_UeWnH6==5rDT$z;$uno3A-=v9>m;)=8C+!r&xP zHlOT)!!@D3=_nc^q4G)gHAN?B{C=M%e~gz`kHS;D)Ng}<82jPW zv1>%yv>=mgM>aCE3*J(%(~7<%hPo&cBAzJzz*oIf*U0WC{h(%YH-3RHGe+{RoZD7x zl;RFf&IxezQQ5xFX7P)7=YDk6i&^8rO4p5e8~Fv+?jRBm)8^B#nK8WQkf)W#Zq< zFOgA>{rjcM_{+vtQzG7uI3om$+JB$=-{x9T7D6k1fBIlkNdZXQ4C zBxDockTCTXTidy8X$uLq?xQT5Bt>wxmFDbfugxV??Zt*929vmDoVjTQ<&q7Ce(ME-~9e4%R|2_2;^V|r* zy9+%fcUgHNCdEmaoWef@Fe@PjNm?bKZxKl9X8B4(N}5Z_5cUEJ6OA})5o8{>=lSyj zo*s$8QXII1Q-d64XEM4pAz_!%WDjK ziivfQHs6;Kf|mK;7ZU5mM{QP)B|^>EdN8N>ghUH;4p&^<|JQQr6aO>u|FLzBvAsm? z7O&l&+O}=mw%wk(J+=R}ZQHhO^VGI&-*eyOP40)A%+6$1CbQ?mMrNM;)?#Qd?I*t_ z)G6C2s=7OT$VfB~5pKpft)0eyx5Z%FabEKsB^Y10dBZ$CXM!*78K=$lF!%_k2DrmH zCgwBQ5-XbGp8UY`k8u9J9*cj~0UDaJ#S!nJ`DNEgK+jVP*H%kDij_4ID zy;0GXc8Mz~6hG_;SgME7nM6=J0P5HD(_W6C!+!(sF=lkV4sN&@c}X{lzeeJ(1=N;U z5M(HP5S06;aEj}I`b!B(OF@x3{$W6lKe^S88<1GHUPc;k2;#@Kgym!4+m!$-7$}0f z@I3qiNtAH99W$im9%O^tI8emd-FpEQ|2E9;?)8Brg9z%1V_WHu0~yTh`L|jI2-`xc z;uElc8&V-ml#Rk|Vgj+~%kH9hsAY>6-Fhi$Z|+>ktgMtyu|e^mo;A>}BA^Ariroly zB3PT){z1_2qq`AEeGehw=5(Af5~L_=JLi_6cPCX0t7BW=AN@iF5AE+Hr??YSe{?Wo zlyNv<%S`E!77=LODG|<61kfacJu^+m1`;dRPZvGSpjoe-0Ow@e9D0w&W+OGMz%k*p zoF>;r(1JRqP=q2j*8sSXoJU>SUmq`X22pbxqSfV$rhdUfb;)rOUr|};9zqi^c_p;X zrX)Qhy(l7i--y@Fix1kpm!QcHiMQIsX1F2soI$05i5eO;B$J z{cN+>?E+rVX+$|@kxssOYg~}yrz87eIHyZqI~f0$)XL8K$KM`${6di67-jWudu1+R z^IYwUx}v|(fXMni_>OVZbUZuU z?UbG6e(E_J(701_A(9-{*YWnJJjSNcGz)yDy1z|0#}9y_iL~L9t>6{#tJh5 zu`OB3!Iw4PVZS`70Hp5t@VA`u=!`ux+K>pSGL?a3HLLH`HehGgq!7L=3JKlikH;up z_UTECwnZ)sE%>N;_zS|nq12qGN{}QFuZ(b_SDjhU<_zIv{A6VpV!+Y~4DKk~mcIub1kMl96N8NqCtgGKya9$k7rJXq!#&2Y=5LGj@(GcX2HXC~W(Q5o+s` z&c*f?dS{l!9Kdd5Js(koJdK@Lq7l@-ZB_YBwB$|ADUyVku;uTDBxvpDmI>@Q6;2_!Va>*O))S-J$+S%=KWixnJ=sy zoU^sT3!plK!x&lAUuUAWA&4+=8z9omH2_(lE)ZHFAq?5D`F%rd!gkhDxNG9YM70=r zE=I1sb~zI;pEPema)$Q15RaF99syPuDpKz?Z8iB^dV$*eIr#)Q2`$a^qNaM>(TH;dog5194S+NS<<5ByQRO*xES-AXC_GU~rJ zD?59UB>w@xSl1yu5yik$cytpo{R5~PkzX*jcT<854 zY8T9L8Eq1}?xwT|D%IZ1Edl;a=UYV175cXLyEmu6zfz71F~hAvPzZLBg(wN;)$L^d z55RIV@T1kAW&`7muJ>dlM7zWKhD7)ma6`NSIh3Gkk9LbxS3)58g{Lcmh~wk65CTz|K{@k(x1Xk$xGy~-$3=sVe#B(Ir)B#ET_XV&>} zGtiZPyKvr`K9kklPlv!wlnWWj>_H0s!5!4I{Ls#4KXsnnOlDi{BKg%~HC8h{~Q z+B=%(_fpsV@1!70v6MPLzjt}ugmyTjG4j6HAr()Y4I^u+YEMCqHBlNs#<&7An!}gg zbC{*=u;&^MK;~#QI&zrlItdw_vpK1n^pWYmHP4 zy+KTNYikSb$SmYOkzEiSMYh8=lRP6#1nr1a~dwdXW3}wNr zCyri|f{Es_c-l2V@w7jVbDP@@6pa(x@l5<(l`5aZ;G(jwu*bDnpiK?=SD4{le11BQ zp2^}RF|U+1D5F<1clbANVGajN23GMTRmo*KP<*U|jz>q}K4r|N0n55r($a~H<8{eC z0eiiXqt1jOcDYj6;dot-d&bC>LaZczw8YtTo%$YD=p8> zWqq!ztBvS7n{qf8m)9CCJYE*~2EasW6M1q`Ad=sSlAf8r!i|tChJQMeFX2wWqlADF zsLAgT2y8LHtv{cw0UZ-O%v6nJoK9fx@z)@0K@egSrO{WuWxi$sHxprn{3NnReDuTXkayX&@(w)tshoKLYc7p}*K(cg+I3 z2z492tYVi9-<+FYDD&YfA|-vJZulK@TK#sU&BTf)GNVEj-IkqdKZOIpYI#w$ zQc5NwapMP9tp)kK2>L+ekt8)FPlq@0+CC@caD~VqpdiMkjh%Rgmqlv>X<<9{Hgd)} zw~cENVQ>UQ0{$d!PjroK5c6hyisj4Zkr+NEXX2|&`(T8|4%pfxLC?&?#O!LjjUW(3 z%yaegaK*)ej+&U%i7Q2p0vV;O3om<#W5`BI+T{MicR9i3lk=FTJ1Pb{?(u=Qnv0Hp zH=G}a5lEYI=P68lRT~DSxhYKvETL!f4Yv{PZ~xsV3ji!LlB_08{B6|xz_i(Tmh_0; zDz*2ay?(91EF~!D?##56Nf*qDVxGz(9KR@|-m}K~cWns+)+5Lvrmd|G zJaja#>4)tdZ2!M*2A(KORyQlolhh(|O{t2$8vqAlPN$K#fYDa+UgP}g;FIy0t|1TU zG?UCbIJ@%d>w7B#sO3L88PyE%i+S8QIWG4$zYI?`-@i%}78iLC-=V>Yxb2%iu=F1 zDF8CQ6#a$3aGvQcj`l`xQ@%WNkr-NTO95#q&C&|mb*W#AEO9N!XP?&=hy6BdpQ6~CFX3ZJ8D^`(D z+Not~x{_5ipL^B<6;PP%#=$R%9d1UU`-H5cLDAH3@697<=t&M{#mK6T6);_gQh>=e zykYw2Nb-u+%vWR!Z}h*|Y*Afh;XSvS#EM?xt7R76Z{(AJfr);uLgf*S=coAEaQ~%MCHT|cJ-q` zfjS3{ImE!RO zv%HNYplIfJ(2I4}=}EPU(fZ2s18M7?(oEcr^*N0G;B1{-v4Y0-$r4Do9xzJK>E$(k zuW}d1Dx_RM2ONIVFNx@&25Ktn({Zi_zqC*NzDKp|*4^2^{q{30R;F0U*=NuTdbL=)_uJ6Cu2W|Qr55s z*>QM=;z?o#WEiBW;Bs5bj5pEyFzkN6?JKYZ0?5@g7rav@Q+3EU zmT#U1s8F&66Maet1T@w-33@YAqMocQ7B9#sk<(wmKDIpFgOXwUkPE=#&Tr^pS{ssV z%QMU99)=#Kg$MZI>>ohQ2f(jmLCXEhW}v^3Yl7&H?1x!OTOmR zae3NzrC@3>#{DE@5~8aR3Y9LjU++Jj#q6`>GhJx*`Q-WKsX#stIVaB)x8IYS$v(*! zjkE+Ih_3gU7pbm!JYFnH<+a>E;h zA`{agQs*Zvj~Z&44622{IPbnzEm>Q=80>^>V5yRv$|b^dDtn@^+p7v7)?+-DnF^`} zyI~Ct*#5-pE0*--itIgIX+BZW*Usv$oJ+dFV>2b3TXBzLl*vD7&j*IyrD#5g`zy@Z z@#Aw5f=4H*0nA2rL=SbN9^$YI8sB;*`q9w0#D3F2I|n?#Yr$D@9UaZrMGrAG($AIX z^?mnM?CKVJ6|~m<^j8NHh#%Ih$)TEr6x|9}#t@j=ZdW!gjUA8~tW=cdylIaSI# zP&C-sk*FsH3DZ!##0qcqg9vfF5<2JmKNeGl*PN$;Y_{SQLq0U~3f)flik6*@6+`%O z5DrZafDzbgmcHLrivtq~e0=3058DMM`%3%(latfkm($8h$|bg)v9>aVg}%1zzCesb zWh(wn6ox1c%wEgaXrImA^EPa&TxRvk!x_p_O}@YV)px2sWbT!6oUH;PYtd4lah>AB zWY(jupyBzjc(!k}R`5VZa6e>bP9mn_kRw+GfYQ~A+wJ=jw0~t#wCvQbP<#TpdtPfJ zA@D0YKL$dXB7>`IO1fcNMh_ZDv8|eazjktPS9jy1njfX&S-lHe9c+Pq^as2p>oG>hClD7RPm{@2k zZz$U<)l!}Pv&xGyXGlEJJc3A*%)HxPU-TY})m)!R%%zm^3-K$8GPaj!YP56Eb>9Ag zi;MsDuTL?xe-2$8@fQ1;8WLNBg-_TYfW?njZ^RtR#RV70Fqevho1m#+bLTExYNSrX z@llp3T$P{_pSxJKd`-VMCan$qlQ04kEHmb)MGBXWVsXzdzEcsPSR^{2lxB4gCJty- z7y&!puyBpsFUhSUgQ_lt@L3%q*bo_!p87@vhQPrOuju-r&kAnd{U`;^`io2gfWg2l zBr(uhd3kI8vU?R*tcv^;lnL1PSLr6h%c2X^iHzh?FHN}b_03)opd`bUqU>hZ*ZX z)TR?t@N=^^iz-l!Q4I=&ic5~jsk;7BGh5GR8g1#YpDT);!vyRODw8JxVO!w@6-50r zPnnp${D^{3=rLQFbcd=5;LqNpN&knAOk9p5G~H|Vr3u7BC*1GL4CZm&be!W3aNQ=Zt@c+#@?O;PMbMS<}rdM^{!q;u5y-ofL`ut{gTCc3Bgcs zlkGNEqLFO~bqVG3#SIBHR)^Y4T+nuTL@s&nWvH_5VQR;VSD(u;?v%%EtQ-XCtDj<$ zx5+_>5_RlQ-3B8!WUc&ji}czao)E1F^rrsB0kIE{dW!JZ>-`LyTd+9s1I>ivfb)Cn z2|5ax`*FH@;B8D9AVKYq$f4^k7u4Q~fwwi0y|gw2D-Y<0q?=0g>0X9SgsJ+B2=DC?=2$fB~#e{(cik&M}@DE2d34wT^=9utm# zOKF?Ar^|&7upkGdUvYQWk8XF${3{X#Gs}Zj37E?ZPst#@32b9zdc0BpQKf#1Dc2)d zk~{zryh!_j%`(mLUU1I`gieL;rwpSMQ=O!~G|EBF-F0{_0t`a5@Vi3lH9fkerykrY z486c$S6M54#NPFz>1k3;bYdy57zh+rQ@%J`8`?J>u+2q&REO`fjO|(HK=vEf|MU0! z`6m=dNx`TmJ1ghnLxVqSORb0t8g8}a%$p*vgx3^p`!LRW{DqF5O+4}mjFde^GdTfRf%8o@uqepcMU0%e)z^i4r-xAAvt+)Bm7=~f{HNM>&RIkt0D zg>O8>Sq-9$rT=}+#!+{AK2p)kP&aFRambp=%))wn_031-b>9(uAlCaMVo_)~r*Sq~ zU5>4K`R;Z(1Sd)@?%1R8@0NpFTr%~4U!TB<0PU-!G}Gsnyjx#+A7{~?G$<@A%8e7> z)2U!b4n1OV32<&$txJcDd0!tbcK?`!ZU~&waAZw08$+Q#6OkPu=?#0HcSOx=vIi5{Vg=fVboqlcL^H0f7O8p z0ORFb_-Wi{V%t*7|EM$Uj?|YjBr-OT`cM8Ew7OM$jMLR}pWx>?Lr_5G)&j)w$~~$0 za!(eh2(mn80=`PZZb`;MR6XH~=hgPyDcO~v&@WrXDHkR=qjD?I=nP zB98C??%kxZ@Py65=>z#&Xv`zm^>G9n+DquWJw*^y^DnL{5>w1gi3kQlE?*Z)In zbNq+ame!I~l-Ec^DlS7)XE0(gW-wteWiVqfXE3*P{dclS?6bs%a4>VUv^Py$vm_*9 z@SuWW5VyB;7Pqu9Bm57vtqk*jC~nTwJVId9M$QsV9AK`0J4tb~CeZGBf`N?T&f|biVEznRDU)40wJsc301f-LOrlXPsg*}F~ z3=M~2#t$z@nQS@m)aGWE^G_RS(ABhFmE1p+_I|`p{rI^rs$|3!NKHb;+KJ=l2U=+O z_tEk3(BRnV+1a?E&CSH_sWFwH9OP}2Ya;-pEUh!6(>*N{*p~xNk+Fs2N8>kK-60Sg zjr9s(Tn&$IlQ&v#3RuuTyScnQkY;XhtAA<}97q;HF*ya4@?ZS;=cMMf0fe(3zzNjQ z-0<7J4dC^IV0v{M+gM*-Uf7*jAK2O)NY*#7K7*S_Ni@29d?XIZ=*swEYhiP84h4AR zcxG&AVPOZx{#0pa5){_NGK90a-MMPd=+NY8Z)a}P-uSYMzjMPRoZLq+FNk@5K1Q&s zsq4K!X>?`c0AIMCeyvSxc5!%gzWw5;t8-;+eBBC4??fr=2yAZbY;RiamGdKB6=0Te z;sD}7K|!J5py}JhGQ2jk8h+*J$^f(`z6nSl?-(0Ge)q`7$OFL|q8xuOqaXJXXc}mk z{BrWkjO=Xhz1fNQ5v!Y;0%EaN;qVJ@FK!0C%smyXZy)YuyuH<{>IUkN?OQW}VEp?2 ze32sH)HjboaNPz>{cstG<5|k#k!h_1Ts{r5!@>$N`ciYEp#^6LX21-;`2eO_eULvt z@DBzc-;19D%48-N0E`z6QAwYFVy^KO=(o1??-tjm|CJ8@Nh_cK zq~`yXu6_W-c6r5j1Yk|9|DKmp@*{RBm|b3ocf0#TVr23`SKs<`@Z&{{IsFZ*xGHHGd&p|JwMUWAK)1tKXMaPa1}XQ~(&z?V%_;b^2pKG(sH%hr(ztt{>Cp zzjr+5`wr-v;Qh(K&TCyUK*ZesP+$|(AaF_r41ecdO#a;hA4}g5V8GnndM5as&4qGu zVsKJfO%{_-*=EdquZsz-9dOTigiQQ&0vtkSVEujUp`p*dRtQrp|J%$(q(kpEP)^c4 zcHy&p-lPR#;&RX4eq7N|m2I4Q_IixaEKtH@t<6c_AOo>d&H5xWRWpGm>M3K-Yx zBlmYMr0^>d>b@7w=+YhZ%XS4j8qvmUq}RBWjrcQ#x;Alo-=H!S`{6#~7Pu>w^7v z;oxI)w~L9HTM|GJzx~X(z}vBMP^(4GNf>5-HZDtISB%rxGmd_h$E)@z}@XHzZC!o9U=0xJ>e1s;r=E@_948WtH`Zf2W zh!E_Scyp$qLB^?GwJ*+vq#C@o&o>{O37s_2^>iHlke?i-v9Xi}XNL}HDIVli2 zCcRcf_JNRMC2ssE++~a39*ITITCubtP>(@_a+5o}pn%H(@hdVY(D6*vtQhu zSCvWUThW%r5t)`E=c2F|qW0Nw`6l#G-MDx6i?~QJyGr&HB=NVhUjocTmR!5C_T$U& zA#bK$u5SK63l8*eY>n=BxksIzTWa5KJ6pvDI;MWgCj!RBPzK!cw?_Sh;0Xi~HFqs0 z&X48h!$>NRAsLoBM*uCMrb~y17G>|VG-!GF0qsDuaGqSOl5xJ!^D8>#eCP$rf^S70 zReb~oa_IcS-+aXan_f9sk_o~kX2Gh*mBfBJO%-EFb9%T00 z%!;ouU~TTREvu2s*rizuu|>@X8Ek9y^~t(r7b+%x7ykD;6?xX4J8+Pl)e3xSDl!4i z14uu7@5bLi)G=yg5C#cz>&V{7DxL@E3#XJ0N~jxYBG<4TW z8KQ|P70J6MYWgwjf;DGR^4QpAjzUgP(;S6~?S-pJE?_28A!>*pZcq4NEQUd;E>5Q; z?eDwj_GHw7=|VdX#2CQnZ1j1}Sz&@UEbAn1+^X~~ig7Mdk?mpT%csFxrmk0$9egnf z+so$MSK?-Zd8ax6~<%IwVHAVLEO3pn3=%4Nd1+HmJERlc$uIzxd8 z{cmHgM!;GIAMfa*pN~2GNShIoZ+?e?!pV@V6yJJq41cWYN$lc_h|uBJ(#~&jMqW2| zH_b;pnvWJBwvgI@1$7h2>(OB1XAI;xP2T9Ku(?S~^EtG^ZQK{4t;$Rw5a^(LMjI|j z*ClI(2$=W9_S$BT1pZ$~n*w!jp;U>_MF4{;)EsPdpBFSG;4rMIT}S*9*k??{ z<>=f_st~EeS>M$cST<{VQB{*v)s5QBIF@Qt!8u+mvuxof403xi7VXXFqji@An(#){ zdqgWJmCA@QCj5IfWBs~9wTNSA4EwE<^}FTQ7?(k%_!c^AAx=p_@_50~08_u9KW`PZ zJOJ|i$Hz(|r7IjOegAZ*Uhs)`u8Bdc0=k)E>jInZJqlN1_nS$AUMDa$w7*!++c=#^ zNJ6kw%(>{y#{rU`q|%ngPvoT2n=E1psRkJ-xN{y`bKtE%_uI!TXcS0L(1BJOZ<=BY zG$e{9-$q&@q(UlSJ3o?v?~9=>OM7hAxPXp<$=&G&88p=?^r?jz*YH=O+X?w%-H-$M z_FpVQ`o9SHO>oZTtt>_J4dJ&wmFdgG6jeNXpP=a6gV+d)WgI7J3!j@++Fy6Oy-+b>9^W(tLA!%y;D4Wu`u50uR4^G!PSB#w7~&7h4QsxXaeM1A)G#LTq5Ju_w%7 z(%YBs+m;A9{E9*=9I{zB@g!=9K6*FSRn;|xjjz3uym9FcXNYbz8P*ck#FM8scEo04 zO4DEz6i98ea|XMZ&g`Jrk5mJ6;{iad(HOgi5XK+QH>bEXEJ4N_`ReGw&-qTER70(| zYb+f}Ey9O7)M0!?#??MvbX2uNnGl>xcjt~WpG+=|DgXm( z66+~S3TZd9j;4gm#&1DD%cfW(8(>i*PY|T+jKKsx39{|L*nnAWRHb3QWdxADckmK3 zY7cq$2`ZMxxYrUg>c*;Zf$h?EuSo9_aw{F=PX zImlU-F@>zJg7GkVrUNv|@iFu&&H#V2F`|}~u8ZuWoC|dM$V?G?fghwB5H>W`dF1a1 zfq`^w!3-CQZaZ(KbX@A&D$PQ)@Zm@wXQ>lB_NKX3n+NXHHM}KooCvrIAj>Hu+)Ft? zwKL`qytlha%INkv^Wle-s}T2HD>w_=!}-)r>)`N14^fA{UjItZtW{zL7E;}$)IBH~ zv+8sz%EcAo@=z}Lt5n_yaDyOYjjOs>p%{mwu^#P4enEaom+zu+Bc&{!*JmRdNS~}Y zCW#f6K3l81*t}AdW&y+_7Ku@M#{l~ui*tg*W>Q!MXaCwHTH}p8Ce!Xd5r5rHCvF}0 zx&sd1Kk;swho0ughF1N8ADI>3PX06D!l*<-H#*8uRtS8-Q5YlW9IXBasJ^jUVo&vbrlQFqTZ6-<1@$HwF z_N$1*$lmH2)|(y=ab+Ns8dh57fbl!0gq0(fsnK=_sZKq0jo1AR1 zsolw3H_g6w=>m8~^7F7G)zGQ>)ord@pbxdqz59V2d|vNG)!Mx6syUSM8Oaq$i#R>3 z|N1q+hSu$Nd%Q068#ar)F}ru)_wUp51QX7d=orVm7ZO5-rfL%9GR7ooh7gNl>Dgt% zZ5;F@u-(QG)#id4)nHVVulP-kt0RA=aLnx42jpLLQXT-Sd+)N}B}B~uMM(U26S;Qe zI1#~(W2|BU-k>K^ZpQrBXP5zP0R98sT%4hR9k*R7@kf(jbYytD1G@C3(c&_3JsqD$ zSiWIC0p~AL!=~UawI@*Dkdr_&b%AxR2-+NPsSqOR$tOZ{PhPv2cu8pgomJ0{GQ=I` zC@1L*MNOaPiwhUnjX#TUbn0wDRDtL>Qoc>qVv3J_KB5y`A^z^4_eOpap?p zd5*y(Z;ro3gM@7#JVk(IJt@fkR~0Jqhdp+&ZdQbn#Xcmw#x(=Ab#sD{v~4mTQFNzN zs;XNb7y<)hmBqmispjfp5`^2_Itbqavpl0j|?`X`>*6bRVsQTY$X$chEm0}L9b z7jVRkSikZH*}i)9@uKnCn2_RirLQb&(m-+>76K)H!zMRn!_*_NC2zLayTWT7oo&{b zc|QkEZQJA$&fW4 z{BvBshM|jReM^hO1besnQcZ3uaWx<%>BfTX;-dMD!YVS|2RhfL@HpSRzkttD1(8UN zDuT7gEi9%e^4Bpw0->%&e>*bKtEU&XOL7$`$H>ya(DpW-7q7sH#r%V8cw~1C;exPi z$>9!qp&KUMr&jAigTg5Pud8@T^`d-L0wwLS&KbdJ6idsB-uK>3HuhGF7Y@J(P9OL* zL;Qv;9FmNS-UzjHw@9q4Hz~8XO~esjOjT|dg6w9p_T#jK;9)6kRn(~C#{pG)SRnB^*F;lU~2|t}EW1(4frTRhIJ2Y5G5Rydrno5wf46#JhT6 z-P?wx@&dXxCA$Z)=bXhs6mPcF&KK_VNtg8zxeA`D;NEg40y?i)H=w(VkZ<8@lx>k0 ztO9O5Hj7jp;HP}H*uO49smAU<*lN-F?Z&sz{z2j^nGdX_C4Cq#2Uh@JPpO=;?A$N@ ze2={~Wp2+y=<^f&$t}Vls6~D+h}8`f;=AobAsDMpI=QOPRW|L?jR3soQ)a1OX^&1- zMlWE?UNXwU7r6m+CBg=_I;xoRjrIn7lz}0aSc+5>sxO|y>!TW%T?S!wT!~DPyUq3( zV!dj=R&!agS(l_c8gT&9<|2HoHH-jXaYvJ=%uuh57=oSdfGzXL8j~8=FlKLblv}re zBEF`wro$Fu5_f6>pe2lsBmk>6dzx)>Qul#bZ2;{ZF1PJZ9mCbWHzNLRo!keDD!w zU2K>+s`-)Uzb(Tmhdi=hd4DS39uO|Zd8I9}Vy>A(0xkO~oz5*AIy)78^lK9O;43zF z6NePWocZm2t|_OBLz}u+Hjr=L*$-Z4ySowEs{ZuF*O(@CB7<^5zhj2^G~G3Y#jR>~ zTv4DG+7HmnASa!1jLKPvPuo78onI$ z*V?pPOB%T!k%e`;^-{j_Te~TFR(t=qndR6ZoPcXsXX%Heh3T>?7gDE2GqiR7T`Up3 z?J^=1rMX5>tl6$*B|>3OYl}!>O~L&?M*&p)xIX~*zm@wHmW85;HAX9A#l4MkDSEij z=7F+G+u2($d=S!x>6VfcbPMzNMjgi9@!m9R?1nbw4tA#>jE<02XdHfzM|Vo0w~-2I zn!%ZfycgYER_d;Qvn8^I+^GRKeFj% zGE)G?<-GN}+gqkA@MjuL@juED2?7kFaO1k6ms_}JrUlwUECoYfiQ7om7v25d%$&gV zoVfPnvaLJ6(EQT$0Z;)+AH1WT_k9=65N0*Z7j@9J7?zU~#LGCuOMh~taZr*T*zVCe z(nTr7{pW>;Um|fqFrue-^>G=#YOCY$K>h+cQ{VWa--TS;V|OoO^u{_Qf)|my#++eL zkCH5w(U?44U?%t$R+Jx5dP~APz?a--f>X%o>tj&2_wrPmJ=xRFUwaf=b!@Hag(2J; zw3?*D*mTIMm}mhipoQ#;!D;yvaBjDcfa1W&1tkll(KK}MFEy`UrSKTFAV%A#i#z~; z+weM5CFDlarR(=|N%x>#k{=n8VcOLa3IR+_&IyK0dGcRQR4j6;prW3zDI)k%i6ku7 zCSQu%0hR)zS2%X!y4&{Bd(YXcJW_Dldwwk;Mm zd(H!9{BGw4QQthq75F`sa_r1p{-ZwgE>oINw$mE>`|=lyyIla3mL3XgaW~0MO(2(s zg#m_=*-4B$)YTgVwn4hYLhEYo!}Pu8RgsCwPG6C*6A-pzbVW`G9O4P|+tFScHVHYs z2g4?ip8slbhr&i_QY~u$$RvO)TVqvL8+A5}iF%bFWg7x$Vy}?H+%1~*8#|F?GDL<2 ziB=}Iu_<4x!ZQz*M~Ot2N(yT|cCGh2=*ia8RrfQ&%tKo`yb-c8)J}+KGDJwkpZA_Rz8Qt2#j!9 zVObyyH@{skf#Rtlt3C=&;vB`j-!E^%Dh2Lb{j2(chOfG(2ZTK)cufPa)nR;rTOZ>hV$g9O@ z674hN2xY=PR`|m}&6AJr?ya<3);8N<@x+Gt(S&8uE5v2-D|PyaAsqd~u_g-0NPLu{ z;rKn7HC=Q)Jy!at*-fJ9>Sv*nz2S;0=(VP#Ih-}BQL2At4io@CRQ&re>lvU$%PFXk zlSAjGT2>*j{_WnxeCi}?nD2E79<4rCx+al^;?#B2PKi_adwEW)WwOwImVlbi#3Co7 zFdN#iB$X59C@n6%yn=^UE=JV^O9};JM2zQWyZUdqi<-ZhAH0P^RAWY9Sn8Y=9+n#Z z=pWERqpc0WIb;AIQ%Ag83n3%xONfZJ-?p*Bazlhr<2eSs;GNil3Z|(wjzibCB>85U zCO>m;e!NzYlR%`lf0#ryptUnGeKGfx`c|gh>QQr8rJ7p(2DhncCgPR_6#G>UlW+Xj zT6(fug)@5{_?yV;le>fbCo6!wcPWoZdEit7LxF5-d0de4XPcB+w?6Ix1j zoYH@uf&HP89X~77*c(7@%7C^P677u*Y*H_=MO8Tlg!#qx0}epp2u|Q?)-Fr5FjDhO zKO`DVtEoSZ>hws9HuX#NJ|@H*{G;TGTkDPsxWz&BL3&JKPK+U z@*84og}2raBUZ$vu>@X0;5N1}2OCyz2WUQo$G<)_Lp@wuvt52t;z4B%N;6}8)aYE1z@F zH}?BO^WR-RCW0E;W9)vM4X-?ZqS6x@+2$dNzLv`#XLh)c}@ zNlc2qR8WO@eqj&dEc>&}BjCOv)bj00?n_OLc}f{gc5jw$-4Q3~x@$B7$N38uBGtCf z;V&2o%7ibOadi1fqFwA#Snhwia^WoRb1U{h%gml30FXTuxUk>hd&GA7jblkbCzY7in1l7 zelZak_TQ?&&*(U`Yd?urvk!;!IlIz)f+ouoFMVcKM<52~iWO3-QMgttNg!+h;WQ)7 zuhtUp4z!x%8iZmZF_pdFF@Fe7{~pfj+Xuf$)FHBQBZ9dMHWaaFlg8BjfyjYSZkrBF z9{c-S^VH~ZR4t=`aAwAJA^o1zlz~U!aygZJ6B(LcMADad+@r!+7*#9DikWX-&4kLc zJTta81o0JsFd8AM%OuG&gw2)*kdjmPm0-x8+@h(Z)+BgCh)tfG`&7SCgSDIAww)ICE# znn2;^y!YeOszFtE^DHU|F*SUfPnf+457@3Ok$z^RYc=eg^w^;Lq2*M@ECjo`w>Zh~ zYK!Q?#IR+PRupwQ+$PTeglMgB86B*x8{Eup3h$B-7A28W71X(?vZ0x{zs_y_60&{U zgU4VA)I`iMVN0m1O#AP`kWpw5j}QPWHuq0P@9F9BC7n{J!g3mjV{}Whf0$dZ$5hfV zmTmv-3Tk7&0iRkesb!Krb8w+V?Dz=+OYBj<>lBjdS;ujrivt?~g>!#MN8L$ndEaup zbk`WiX84;(hw;~T{rJeFOH9OAxgoNNKj^FFJJGZ9$`&1SA9wLoSX(#Gd9SUvs%H+F zDCwj0dEBuiEK2VSLjNW&zf>eIX?aXexBH)OWSB0e+@Ogi>pKG*vy?wg#c%m8ZC4Tu z1wCd)G#J3$;zIQUR7^VvJ;H1dl6#Xt4!^w z9&^B&7}<8+@f zSkH{4j1TTDId(wdB#85YLT#`?gO!g^7cb2>mVc)1Tq2MLkx742^eBm-#^B>LG-UmZ z8SEPXbkXjwxEpziWO0ahw3v8#B5(&_vGk=6at)Fd%m1SPdzP1c!clfEtZSzjEhlle zsng<4Ultu8Xmf1%V#0{zGWWjM@35r=oE_%ih|fl}dekY-$uDgvcTx zP+39{f)EQPWhDGBJ7c?SBe;>!3KBr(GC#_u%ff zxVt+9_uvpLxG(N*i@QT`cMa|y+$BJ8ha8^Yd(L^^ljp1Y=AXN!w|l1h>aM-3c4w~6 zCs89ijIi{&TM(K{=nu)`ipFUErt)p0_eX{jZ)bU2Q>rh*@aa!C4X?2lj){SIxNI$^ zL3qqAP7Ww+jwq~d+Y<+BssqXhIO0%MSjyPT!9>?rB`2+Jr&-zE6k5frY^~Hf^>4u_ zdWTHcRbx*jS0n{JmiDGV*DMBVQGY1OAfbb9SSiH>l$4SUDD;@Km;x4+&B^A`?kkA76NDi2``wJEkyDINgIRT{WepOjUH2 z7U9M#NOAg&wk0W=J#$utZXZTDr2D@7Ikoge+v>fb(S(qNTi{;+3I*@z8&o`eFy1#R zEP&WN!!P#?*Nr8{v=uOXI9YTj5e^7l>t*6e0e8R0=%4i24CzU5bhul@oIl%7vT#QK zq?7YP2(`9UXk8=Lp1gW}_ClI+aS-Q$i?nF!wxtpypc$DwOe;e-Y15P#lVTUo6fHz- zy}*=QTB=jD@!#165+DV+@nLlq_40>wFZDk(exk8Bcvw5|rzR&r&vu2)AchC-c0 zUU1qw&l$>d_Op^*@@GO_IpNSDx(sp!E6tOkE<|ep4yF(ju*UH$rS50@5M-O~A8*Kb z0q#Bk=4k`Dinnf(G4zwekT@UaI;RKrxjaWBo{lDn&rOMQielg>L~sp+5#Nv$KU=;) zZi`XwO&a5kcVnO1v*LeRJxF5Fi4KKOqxtTq0i?^+42=%4h4We0}WK&AiOpd^=0h6QN6Ovc#W3n zrZ4z~e}gAN9pujQJ0V6 z_75Bl&u9@}&0Xn6{Q))1adKL}YjG-I(L{KAUz&!!HJ_8MwcR7GlBzLveqlPTWpnPeBl6M@(^Cm$TjV@DnzQG zbJz=EO_f?4cv>{iCQ;gzsLQ5zvMSGx zK5FpsB~}&daz7RKhaxHuj4m8KcVlU}fjgefcI^i<9+SdudR9jL3ZWLebQxhj7Y*Xy{uqzN9CJrRS1~Q{5FXEOFseKcB zw|rw~gJk2TDl|>`Q0R1?HwtpkT(`VciB1*N75O7{)*Y)1-BO`yf)j&71v(>mG(U1r{T%%bZQAV7N3L!ry)MRNmXNr36|vt&&){O zB*H^JE8zm8gxJv%1=(T8RU*@&mTbUP(vC`L=kc=6I@?EES{l{`Du{llDqui`P1Inj zvbNMgL0!z|?~QhQ$3#bH3or-QA+nWFUl&g%)KV}00pc_M27__PwJO`DJichKIK=Wf zy^B2tp-oiXqoIbO4jaO|#NW~;uBk=1bk^JM-J)DYxT31x!Knt{ch*yzU>rVP1zsBa zG{d*l(A@@xuq&HD-8ekMbD$|CG72CRtA+0N;MaHU;r8OK)o(Krc{e}w!nC5r>KAtT zjxN3o0&xrTNB5xJwKiQJ;fADN&)HcDf9t+2tB1I;+HP7=ciiL3Gl#d~U76q4>k{j% z5*`qj+BZB=dAvtlCHsnji%;*sFiMWbIQLI{Ie!+}S-Q6&-HB4m#(pWZ!) zywBDt*9##=Ea+EA{qS@zW=WHDL-p8YBgZFM);TwYfms0uSGkr^HL8O^Tln z)9xeaN`HqiLgNV2Hv(BXh6;=oq0A458AEl`vBY2es`y@1=%dI}He|QhiqJjHJu^1*uN5z zl>3%aGmUmoxfiw?aIwMe@lasDABY%9ZB#kQ^_fJu&=2L5>1!wcD$2&CVXvurcVi%%rg z#E$+z9uF*{msJ}v;CCRRnFc}&BIctj6gY`eDm8rpJL(-rTlOw-3s{kwRKytW1Nw}v z9YyBYRv^m8^)geB5AD7D41zCpKn|)M?722YhYVYfCECndilDEye&Z<|4*k>VL}2zp zNeoH0Um%7J&Od}Wa|=mfLw>DVT1N8N(^i6#NetXFYo3hr5OD4g%{t6ZZ0+Yo9}W6i=VpCf>M+M}d^#k6m0KG(+<-nX zLJ&eaWwm^&pPBjl0Zs3WxI>qtIg2eH>?{a@T!u0;oQuw%a>+!`L3DwNKaQJ z=MCg|l0Y`1>Q4mfBHFRjd#qYIYp7!r_4$Z~TiLg4=-4P8q28e9M69t+O~=eYzkeLN zslVZr8gD+pq)5xTjlO=S2J&kcr1fjb}7iPXT4upgtwbOQ^gIQIATm{$`2=fZ78D#S%Cf zgZnJbnpKePufrM_zQOdDyP#3TRqq?zebVBkJ|XbXqcMo0=@1&^;q8}!L=KHNYVz6r z#@(LUvF4jy=DT5{6^4^YOcf%=q*D_=3o9I=f%L`LX4Xse>JyKIsZ-U8Snkj*3VaZtv+Xl(9ne=z)rVnK4HVB!5e9FUk(GLA|l;6ePnom zHhfv!NI9azHawA^D9ZPya) z%3QmTQ{;YTUsI_zYGx{vX`>j5)uM^ayZk8F__IX#%$rofzN!eo?3E z_p|WZ?2#DbISc*+$5zz(_6M~HcpmvTdZ!w@5V6P*;xbzWMhot(bo+->1JHm zMr25j+|H0vJ_}!mM0RZV`_jPcp-{H3alYp*_;Gz}K1FRXyMaQLFAW@vR!``5g@*4C zEhUb}W(HNg+LBz17RpYmw6|lbHNH{t8xf+9gwkQZx%t#ReCx-AOi4}{heOfX1pDeu zxP4GnGVIP+G!r6d-d4SVgTXq|>w{3<24*&?X!19eW4)sjlVOllz@a(GonL}#uW)YW zG|=9H1#A?JKPg%eqk>lBnBm_fGZHAN4lc|JMibswI$zV9vF~3>8UublikiRptCgg} zBk$r3k3Gp)Z<;rubdneyuv}PNlFKJ-FX(MezEKb0UmSA%NzJ|kuA&?n60&nVyZnAO zQ8$EMt~41s%q$MliXuMYpcZd8_-Yv|1Piic1KqVYBTPWRoU3B>b10<4qHE`N>amll zy8l$v0;Z;_V^q7N&1)=frd~WLHPfP6>dUFXF5(|7Cx&!(X#?k%Q63%mcmuQ07P9Q5 z;H$SZ+PLdSq!z@0EI*j9O@fXE-&z$eTMvsRon$RCCZ=FN%bi;}?4)QcUEHv#T86_E zdRnJ@qr;=n+VLT&Z<~yRy-PD!HHc3^dDM^MU(iSoID{}Ny z?8q}zbT@XI*7z9Dj9R9rZ=m9(KX%X7X~{vkdx%b)p2i{o-CqqKxu8sJwaX!vAQO_E zx@Uk%YroV#Zn4Ji38GgOF_y=ZiXl)H5TZFoLhx>46BOKob5?-69lYFmv}oOLT0S!r zgil+&z%7==6ghksZ*Y4+u8i|p*bZg>rBseTGEz}KJHV7s%~1DyRKiM}f42TRiRA9O z>b8C9*lhg-aB>HRF?^sKs*2c!de~uhbLsW+C;-MZlf8#kR{QGrPt-V|B&pU&<$K=) zP61)Jq%N##C>{w_+yufBljG6-0qeSDjb>V@UiAb<8$&JkBPAg3_zolU55FLsIDy$I zz^ai+X6f+TEs8?%j@@}?=3()c3dzONMOd35LsaArurHORHbB=QL=Xa^&2M=>R5+(brZJshun!uRk|ld?zR1@ju8Ux7a|3rjWF;~>9^1kbgO&LC8i zu$vnD1LY>%f1X7vHfofHtt?ETjDr6y1P3X4Ld4!FDZ zomb^l3)5HuO&=#KtgBNxkglXF6miQ?~`j<7r)1GbuJqLI<)Q zpG%LqdvxJogrSBT8MYsLJ3e_ch|AR0CLU{ckU*WAKjFWO+y!vpr|!NwtqFyiYbe1E z2*i`~keRn5p|Ef69njzr6tKJ~p?^~ps|LV~-?w0UP)?dWh`*swXi^BbBP4T&#C0g| z{nm}TTw$=LaZ&;(dVR^Yv6xyr(R;H~E^K~z>2+~;XY2L7)HTt9u@;m$@{-6jkd|!X z-T|5)BC`G_MmN-7S$-+TTX{;My-wfR6w24}OZlS>hPm`f#dJJ?+{Yt2)F=yu7=xa| zS=#5!qS!tuDbU@UR~D5R7J|%=_9imZ>#^+9kMGJJklyK4>$LAFX}ccJq@`MT`0>+X zXxfZtf!sUOCD&lp^xd<%GQtaDh#LErp&zZ~YF7!ev^|p}O+>6@?Nk=6XOh`YEiV`2 z`;EUINGc#>fq#;JB5+R+6x_Pio5T(K&1qGb94Js&7ZH<*D;7E#L8oU>AA4h2+FG2|*D#3qM$aN3<&WOT30s74Y2O>@Fjc$S$n=Wztl?F}KiajM z(rBOBZhis$w%3k{45wFk)J>0`do$O8PqenIa#%qA_Ypf>Pbw68!;V;4w&VflsMeUw>ySPa`pQG|gU>Zkl2EYK zILh`MpDMlZ)cr)Ep$ej?3=ur|t_n4%d0`Bt%^_)xa0b7L8Rn}vO-b4?EW=v@bAPP& zxQ09ST#~w_YmXl*yEpfv2E;?&8uPqV=4jXu^(dOv*kS3M_Wozq?n_8e|vN)Pmf6`WK>~H(PhEJUeyzgAUSHvG`cwX3AV6fa?n3;TU!i zQAZ!GG}G=s{{J6mthKYVBE}FA=BeqH4b`i zU0e4ql#qO8GamEMN_2W$KcMq8ATsBZ7ToXm}8RvYK85jJ;3PP}1@)M0?&N>jm`oew`8mKU310@{_XIyYxvr*HaD~RrB zSV)zZwyTgS5xx|MuU(-V=s?k>CbQnm8NRFayM2cRbf#HQZVRes|2CVbY!6R7t_g+F ze<2{)iO4xsTaasP$0vQNTL;}cIx*=?Hn>umbA7Ks5w1|16ef|bZ< z=vdwn_jnwp@?8hMOa6K}K9(#+MUpNI`+YQnbC6Vy%;dmcL7{pMzW+GxU0AoYTc~e_ zd)o~smC-1ceiT9RXLiaqn%uy(f?BW@d~9-`Ms18I>Z^*yT|iXTTk~ysnc(~K>-?&# z9C?R96|m$bNJ0iZqyXtu6u(js73y6QTN#I8+%*eazz@+-=}CDo`Z8;r_3SdUq0>7AkNw(h5~^xMhehUfloI|4WkB7hcHrqR#ukOC`>KWNF;i3WolC?c>d&1^ z-}xJE=$tu;B7^&Cjm^4hyveOSezuFFAGsUjgpxP^q{j-%UA6QJjFyZy-92fE<#l-3 zM_#13HMy0Mz6g7gSLDgw5X5g;zs+Pi>_&i2dT4owcK#HRRXyTEo|`goiMo&=6t5Du z77MIP{FUGZ;_1VpLHJBn1QVKFkv9K@gycHTaD&~fA;U}4dF&TY*<7`)-x$N4Vj=lg zy9GgobbsqQ?#30rd+Q|GaAj+zu8y5_Tfb#-s)6kVq>^6uIrE96F#0;2QOqBC%pao+AcHTLh| zDT5GAu&#H>a5)@gZRGlHQ*Pde^@^O2ho2ASM-LOvFnedaFcFUZ`=Mz>3P}%bA6G5N=;_-17qa*=9u?^HawqhwVUOd! z_to=xyB|w7{_=h$^zE>3UGjr@w|x~+TNHD z@a|7xN2qiS1h16@iq>++8h>Nbd!z^6Z*Eh6p!}nNxI()l)J#S>m?? z-3(PHuBoF!@W%zVOcqHMkaV^5*Af!G5UGoaDHgjIH!shGbtdf9ooiC{F?Iu!t}IiG zW)JMog{0_!W&WUqSaxb5quAuNFy;wJWj*L5LbJ3tcqV*7Rq9G-gK~M*rD5XDv3-)J z>pxHm1P%NCegWSx>}mp8gcA@nF4)y_dU?9n$Iu_7ShZks!Px$|>&59F98BNyhi(q} zguI{{C1)N@In_`PpFX$%MEHRxo0*sU(A>Fi**yuoE~HRr3IRXb2MCq}=!=*pLdxD` z2#RNn2!>j|hy9|O`&I;B0QnN=Sx2_JhE`VuRv6!&7z0;~NAR&n9Hs`NJw^*yL$me6x;K%# z@w!s@;_ye)hSHX6lk^#?y-q++7-_=61Tn7E?(`e=YkC=P2r`zX+#Jf6@HWw>TjYIE z_|6fs-^Ws`8NS5uNc)`(i|_g>j8q^Fj}t912mbG8Rdn@E@kVZ4bi-fAkE89+A= zz6QeQj)J)axs}V&?QU7%&##DcwLpN8EESDa;;(fW1K@}D z?(=odzS`Rdy1lM~;YBXUDT!KhF3>;+n5j&_;Q@GNn1{>vnEqVI1<-1_3DLmf*nD31 zcJ#n4M#I(0&&E5%p-W4~0e?R-drJbZ24GDD)zzQg)@Kn_`v;l;52BZ`fhKkxr*M_V zApz*8$OG~>Evpa=BHvt`kK=})FjA8^FWGHeGDu^qYlr6E*J17u!N_pN@Swt-8XMRx zOnNz!@9qrot~y6|i!EWpw;%ib`7DBhsz5Us6yC+Izzy*FOWJ4-`kSUDg;QMv42q60 z${l3c4XpcO#E;_{zpdfn-Gml#C3SHQbv!vU8q&6jnP2svpq>$$p;aY2qaI`6?E2%j zDI(8gkE(K>v}=l%@(2RO19D(h=cevT4s^7%$%+zhCN&%VL;7&pZujlf>HO4HT?ZSW zesy^AA%4^HCd4F1&95xWKqJe7j(yCC;F4mDCu6_*ZH*HM#8_WAS>v(9b&%+Z<#zav z6^}C7d<%(#O%E6Z4fvZ?)habPpciiMHs1mcqg&oa?Xpu!@LiTociSJSt!X1W9hZc1 zO!|TsQwd1mAU2(^Fw1P{GBDuq9uP%(_xgB|#`<_Im!8&pVLh^c6r*IuVx9Rr^HLda zX%GfvoN&1T0nKal(aYZ%ks+!}Qszh$NlYrd!&Yc;|fU4s(Au zjYtRfiAGzDBFiZQijtj$+dnxdsm0D-gT+wkD?Hd46E#iy9SRR$ot4b zqFv<2awK!z4CpT~n4s*HFYLfkPZs;dmRjms+nby{tGrVKw%2z;*)r}f9eE{}28 z70#3F6q>e95@tfXAlMO={95L2tCZt+?iSN-&8IY&cB7X~O*UStlhCsQqt#Ajs)+o6 zyTx#KmCHv&6k88E(hPKxwFx8}BV^jsjx0NMB4<_oV{64i2dyif{AV_{jT}z1czwNX z+U6`4Xp}M^yK%NfMU*}A(D-)@FayumJS@ZIy2 z5M2_;PQ*)2ycGOk1w)6^3rnAB3h;SOmR$&^PJ9?1{teA#mEUWMw6CjCs<`KH;iTtxeA?akJY zis94dc1sJGZs}Py!4nzH^)N%+75X~?kn~p{QSi2vBZa&xyH*_DXaiJ29_pRJVk>PY z(!8w&Br5jcQCy66qR3}fYXO^G77miS0~o^y?Cn(x2M_Gqa&&IZb!&zDovfSZJ#6kp z1@BOU7h1El@Gr{*gr9`zG+y(?>dL#87FIf*4lnF zdQlWQAjnD*d#F^P>HZo8J;_IZs+z!{It;J!NInZJ6KsAL#U0INPyIv7hQdtR60=@7 znbBZnJiBId*VwrCT`ifgdY(R|Ks6jmL_GwO7a=al5Pe&bpf0cQqbI_8EYK5@SOsl@ znrR=q^4E8wBWIZL$Em2BANg2-8_ungPn9DcpD3_ZR3BfuR)whz|ol9|M=^KDrm>2SeUrd`JEbUvlY3gAzIcw-md zdwG7s#x{8_8pn-v{hLzb4J%aB$bcOJk-9GN%a9C@7^xEIvs|3;j14gVX0$gjc+lLzW-~Iin`9IJ4uhBslBi8V;2*R<{T}8sL$W+#*x?^b7OC zJg=#`K{f#Za{uT%tyn5%P7LMj$JH1!bvM35g#bNqoy^({FD+mJYt{&pg44ZkpzCrF z&gbBD34I#{yc&Jx{JH@gGC_#55pjxFTn83>UFy_72K9K=jAa*N2+H;DrGgHpz3B>e z=WxuvTz#4;#rUCX@C7*Yb`sP&jIZkIu-n;cA}Klc9Rtgz3?hcojHx}p(8{V@4(8Lp zz&nRjanR%1Lo@?}^^50IzGBi}^>TL@e%s!{Ph4?-+TP&|x3qff>0{j0c?DhBCeHS? zMC&c5)S=W$-00x3JXY;{s-)L}gnF(!CeS?=A*ZkPqj9LP#exB3s9;Ukb*H@u2&;vQ z`iFOp&gSYMud2Q3!S7~s0X6VW1#j^>?}8_Gn3u|qibIsx=)1w&+ z-njW;{CYW;Hz`?dYD9lRjLSBs6>gX?Kb)jil*+1G^Wtj%*~FKSGjS#!dSie^tma+r zSv?Mz>~3mKm&>Wi6i*EP6h_Trz5k|39&Ex4p~zbaM_ zdzxV0^}Jd?5-|Mp8MZN9E*K|ZDL+?}DU7;~rPwL_)g7@F$o6vRc+Wu)!aQ#@FcS(^1E&5Q-93YU(hxN zOc3qD+kMa`Ok*yo`9GQ%?uuSlG~Po^t=3-YQxZ&ZRK?-v`@Pz949(z2jRM(V`(ug8 z>JLYO@fVhIiXCs%mt@rz#kyyI^7Yo3ML<@+e=<5lyos5QZ^+vFjE zd(BW&+SuKx?@EHt>>lmO3sPu`=}C<|Up#ZCJ{3wiblBkeb*H00Mxei3pd}G}KBKNP z_&O+odpsT+PGupl?&|0P6A3Bp*jIrTFIL#NcJ|UMg6X7o@S7T)It9Bbv_?MSSixhS zKA^>%M_)(Ic(=?Plg0dxZk|-$t0%9LY+w_$l zoS&VUrV;WlLW|z>viF?dlGuf8&hJV5Kl3#dW^lgzxxR^%JVDTsd|xiAMhE#zCP8_x z3#@rmFAAsOG|ur^6U2KNUoHPp?;fpOM1rX`*nq78W+f<>AjE&x)x?jQi?>?BYG@EI zQr6gWI@oL5)u|>tRz7Xpj~h~~0J2NT5LCDL5;L;#5%*Gcn7y%)YGp)$%BR216F~2b zdJ(X4rFddokLvu2zv-BnKyDS^0PmOj`h=JuIat){e;k&{ysaFgu1k7DOQ_DU z4f8yZC(TG~J26%IV$D@tGaYM3I@pqhJoOWt2C0J5a*fsuy6-5&>%N<_0l0N<&JMjE zM{%)|qi&r_p{amff&uW?DfkRqS8(mJLoY!GgKSWd;o3zqUX!<-;Ze*Qr$FKjvtQ&z z?=G(?{o1f&c=n?!{OKO^65F?ba!2bd+%V6|ODI0qa6?>i3S|Ony<;(vg7r3xC;(l4 z3raowQ~lE1xQIy}Ch_s7F(76MzB-HXVC9Wcc&&57AV&NaTlHe<0i?UP@f=QEEksJT zhDXa<$=Fx+!pc%x(`4DI;Sib^&3O-SMahgN{8k32O4}j7_T#=%$EM$KUeTcncFzlu z*8L4<<%^qda7N78md4__K@#MY``o=bLr!xV`_{!;@~_b94d=o!9KheLHDfEF6G1dd z<9f@QkT3K8FZS2#R5CoW8y12Z)ASr*(SA)f1b5ON>?D5QoKhQjwk$702mYi+OYUgT znoG>3K6<~+v)<>A1b2dm?CDyP#;Gbrp|GeUsu!hYU9F1G7Zm7Y#bF?%XK88{-BAU> z1@v9GZq|aWs+}%@tpnTTiIRy+lZXb%0whQEIH6pa0KLuGUTAqDBrMbrHdEi>2H(*n z6hI1PU&iP{lJaUsd@DK!e0$s;-gL$(y->QD;Z}|2@S}0uGRuxgMD()Y^=orLK~$mc z_gPD4C2gwx@csk=VS+M;e}4id7S8=(d0CxrQ1oS#gbz-aaU z0+YYa2B8Wd@p#)?`ML#(XFv%kL(&XIdlN-{2dN8KYnxjWIZZT32QUESv{MLq-kVsJ5J^6~$| zHYmj5prh;e)v$qCotQj=|Dn2w8FuMp*9%Ea%jzax=RO~Qax|9F#^HmnxMm{V7fiEb z=J(l=)z*WV91SrkK36kBqXroeq>Et6&LQPrCeRANz>Q1CC7)Jg$Xwxtbo9%(AkX0!i zeB3`vt*gj7W)l@%@>A2(UzJ=sY|;sILqxwbp)D|rx6WHmkLZm{`7IMOqEL~R?o!6K zgi0u&skrmR?42cDw7Vje^!@7>Nv>)=(c2+RGMV(`b`7r|;0{2LI2^~ghAoN1bq!-& z#}aQX#6F+;SB5=|J=Q&AXuj=FoNfhRXStX_nu?-uvJ9X&dn~0h98vx7EIZCy6F6A@ zAS$sM+478Nh_KCSKN#3Rp}HYFDr|C+1RM-ziasB(8w{^Gr0`UXgjJnmUkvO@ln|yW zP^q#grKM#gZFR|GUoE=*A@{+rRmo~}#uv<_>v_OzSWd=x*v7sUj64oTfz^G})!Y?` zy=96E4tJs!#=bENmpxAVTn9efjKkcoi>Ie_#((GAGCo?M(!g}R7zp8jUHp$@R9wJND zQO$PmQJQ&j9J>0^V^Y%6kC6pEa>z1RfR>+%|Z$_zYL;vZS69)@_Xyv;35Hn0}IOMx=i8i1do07{d+u}{d;O^;f zf~~SVNGs}SKQ8^06ga^ra_D(Er>U`N0%Bv42$=^vtruaya`2$!^$ZoKts%NNf?PWe zi5*-^P7fcHj-gvqDG$nX#>t z=A*jub)d59$89Dko5c@KA^Z}2gTs_fT0hfyLDTjj0HG(bgu{(2;umQk(&~0R)FGeX z^j_vNL*SceNfO7q(tu2vfyT$xVPTj3&-mu)%uP;t<|f(OjCg9 zuuM@%)`gRmO)7oiaZgeDP;-xiSp*8G?TcR#-F}c~c_=nH?nT6` z)9o<$ULR9eYZmdU<4C#m%dWv~nP||0eJwFgJfKZF5dt{ttrwR9$$w7KCimSqi61l6 z`ewWM!=d!LQ1(CY4|(KUMjLkZ;q21P>S)KDllGmf>vm1 zO$vqpIk8Dhpr$uks=jv^!vB8o^anR(`WLQGZ#924DdEfPc>`FJli`ofK)C#;{VkCM z<_N|#+FVLI=GxX@TG}vp`cjgK#ZCy2!K9);)Mdwm2W_b>ar_iZ9q>VGsUa^3+0lwdqSIP9EBlK28;j%|}D! z$5Xl^mB4vF>vy`@_hj)nc8-%tq5&!hwA9t_y4bGN&0y?@goS<+ia@z^E|gJ@xO)gjo^dNVJ~J6(us8QcBB^68dHti_ z5a2hJ%?*?gMI!-+>4UpRnChqtrx+jAOGIpe)sPGyn+T{GChNh68AM(KPhpyeWA{xQ zB>C2cuamz@N1T9%xmB)iC%+kO!tXemIa!Ot@Dq5EReEqRDQV6u=YB7P(?<-#)Q{4I z`0S3Bzk8@JCOupk7mOfhN?b<^&v1LBgMo&PttaCYS^FuwuJt`kHCf{0edDj@@mr4_?sHdYIg&!}KWnt#(r>NGm*s&p|K%t;C#FmRgA{_XUl~jkI+zxwF z?s?#`f&r&y(ffC9z8VKO&V`gxl-Gvq-y$yF(U^x7sN{f!NeBEVeF(hRNcJ^|($|Dd z%)SS?C$S9L#$hLUAUMw4;<+;xGwp4g7KX&g#a+WWG7Hti(Wt@qknkZEgkb^6obyH5 zNRv3o$k%VOu8Py=3SRr!sb@W+yiUc^w7Gh(wKfkb50jO#S&94J0^65+jv>F*UO*1{ zNKmqP4^J%y^x{99YUEMxf=TtT(4fs{OjPKkuAwILdX5kYb5FaTx~3#{tmgmCM9&HM zhlw6RS5`|`MV>)iQ7sAG8V^K80zMCJ3%Vx(2O)5>{$CDxV^?sjmP%6aZfbD$f6PEB z(%`L_oNWI`!Q9@=!NdlElcU901{{tFbO!>*NIJ8^2PM0LPh)WWt;Y2qy84y~H}FRS zkaZe3Qc_kQDd>A5cm+5YNIMB!3`Sf*Q$A<-`@5$hzB>x>h zfc3v9_9e`nO`WVAT^yW9IRPNU6mU8S4ge@31>6Xn9dz=aDH{kY^<&Bja!CcJ|B&XU zf`9o~5F7+f3kpvGM+5PKKIA+gGZ45D(g)wZ$`>bddlynp9?&!h{1Y}Q`+q_*_#X`Z zA0P37z==Pc!%hPy`*?7FJTU$*iU0q`mx~o-lLjsi#|B{KVEbU`2X&=^6a4pVI}JP? zf(rohP6yYr;^yJ_*yW!=YEO#r&lAAP&CSa7FBvD-2WbC{|JLIHuzhp`_@A8$10rcynn9(;9&d9(+@oW>%Tl;<7E9Pxc}Fyk46O_ zAh7~Jr2ohL4`VL2kJA00iXWl#@_dxx|CF(QVE9iW{*nRM{uL%0C+}Z+AM0_j{SVmw z+5cm3aq;{Q;s2I#a{nt54t9>e9Ay1)ko{kJ+&qAPqWc*C9UK=o?_VeYSb2bKZ2y9l zm;2uv^KxI9?vE|JZ)S|9?IFs7=nl;QBD;;Qre| z04wLeQUU+~{*LaW6nNPFP91=a zgOi*4UotMhzic_#0l;1saC7ngTgJ=&cba&4Ik^4{ zX`}y!pO=^WZ)X6kT)cq4Ap9sAcEDfJ{UhV~3z-iY2Rl3HIUAe+$OS-P`5=w?_#*p= zj8qMQMb_TJf%G5u|1*&w)f3?0mJ$``731a>mtd1%Wn}}1ii`5Hvh#3?a!RmqaRG!# l|Nm7CNQHzDoL#;+xp+94TOfRRz{SgpKt%;5sVs%?zX0zN^7sG% delta 62059 zcmV)GK)%2I+Xk4u2Cx(Y12Q)`lc6Rle{GS=PQx$|Mfd#*FUO0x9((-Awun{*R3r#1 z#3E|k5-B(+P0R0-U>+^X>dMkR*GINwdnVaxCckr0%;rnw7?RLr6)ScO(Fw0SbCLvV z%ZiFU!&Mu(M(9I|1Ai%Q2GBEw;c+B~Im-wvsuZMNg?YgtF0p+nR_7pr+%)zhnw#oc;y zJNTd`0yE`9iCi4(ruwsqRr2YMFQ)ixv*__6)_f%7Gr7xPa*XN6@MStFd$KQDVuToh48G@A_|Ss}=qP$y-U0=hZ4+c$6fH76?e4)d_RJXZ*jYc4&A%@x z%JWF4i)~Y&7gMB2ijPl}MY2gma&sXfy;@vcUaK^bhHK+gvREflrrax^q{48iU9u>W z_e{^`QYy=Cn|{dax@tDFxlS#+Tl{kS>(8@~i+^{Q*U~0Z@JwVfxCzT-uE4WZrx6(n7ua9cePH*E7EuDZPG>wGAq-#_lICWE&xJL2yu(kh?ltY z40_hajICo^ux)#EHPFs)Z;4jqs3q>*V&*mb0Yx_?S<%s011km8AT$a$Fl9;v-AqzI zLs`(8+WRdrPuq$t&V?MT;mlRrtjC_v1b-~7Lgz6+Odzfa1u3GyM-*U9^WbFaGV0~K zxN2a9O*ER_4%1P)GM;)=0-%b>Bg)FIuiBN(v$Js z+q+wmJ>-2qY`gJXkP`$kXRQ%QH72VK6q!Wi5m#MKwG0g0A!-6T-47toy)@+cs$93B z;-I|3`wHlxl8*qwcpl*i7VEaI!++FxB7{N!MTr#(S6{LQdQp_ks-j>_>?TH4ej2N; zEZ$%w`(X}ogP8R zJ>!{Ej^4nG8{rb;98a~U3;_ZX?skPF!#nD|57Sy@tOlY5Yl$=@gk-$QU;+Xs&;Z;9 z0^9>}kf*YOy+J$4F3B8-GJhhR2NM|26J!V6mbj5Pd~8y|VCqO0UJi#LSO$X!-T-um zZvvXQ09j$#XX0`q4GD3N43zYtKQ2rm=_oZvX#;79+|TBjPERyFX=Z=b)KCkKM4Z$x zK4*W^MvL7r|D=uL+`r8WNW(Blb($Cj-mQ6o+?yY-B5cdQE5(M=pa^(VPvj-3X0R%BOIWd!<8YqA5SW9!0LZh; zjAw6-c%moEqvx-s%Yog zm(7|w-PnILx3fg9yY{jxcg63^e?NaMOeQ!BJP7;?o-L$g&Uh030yY?#_x0|2TZp`( z;o0dc?1=ngTQ^rE9j2=fC9qYrRQEIq|5Zqz-_+}BomLuJ88(S^Z=cN9byuy1w)+nOWtTQ%O;)Vqskl zH}uNnaCKpQJ`mXwsgZ=dq0to_SO&bHk~{|m3PUU=?vp&^&tW7T>fE{fLu|{~?qYi# z+iibrD`LeR-sBfRl#c%kq$Yy@3rBGn2NEi3#i*ziuA(}CfI5F9aD7uOg2r1p-0EtasE)19>=voBS zJG57*-uND#lLkLyWs)<_{g+r7zsva#JyS?DHg32DajhL`Pa?EXgY$0@ZU3vI#bpm~dp zDzt;+LGKrA&H!4xM{E&FP43*&XhnacmdFiFRy68}fNH&uj*kvp6B*(g3BWOZ=>E@A zP!M}Z*UVYCSzQ0u95nW>rkI65l{nyJU>Rd<*Rh4uc@eQrXo2o1HDM&zbP$lI_v9JL z#I3yFIOli#De8OX8PPL&1Y96Bku8ETkM1v``fRj)Xm4mL0)wQJh={>JBw2s2=kQtv zf}vvQe$!(C`+1=RJeHF1SkP10NF2gDIY5^Gztb1L(`P*o!YtfLJrR;ZRt1?(iX6*L z)g)*kG=(Qwl?~0@0%t^_n8_fPw8V$F>2GlpRuXQ)+6;MsZTDb|*7!JIAu|y+(}2(1 z`bQXwWKx8Q;~7TMD=CJH?cJ$haNT%1k^U-Z*q3Na3ho-60pUYi;y{a($Rzs3H$6 z=@J(-s_zmF_yBq7L!!YLC!R|Tj*pU4eW0O?-SiC%wW+TXRi*%Oba zFx@oODg}7*J9X<@l=e7Ed;UTlpqym_l9I3CZOUq9rhM#gd7EYcv=hfb=vxx$h+u5e zJX(Urpa6j_;0S6XC=5a@8A1f85N$8ScsI{rSz=5q2#k$E2*`>^NhGap_E=oRei&gr z;w#LdhbDXqtbN_vqRnHBV(c5~Pb16i*(QzyzlNKQX?M>1?aHFZ73 z2|yFbcIm(C0qlM3Dq7xEJFJN#$F96S##|&&q{6AICRW++dm4X2@SzGk3Y<=ea#AGQ zw$0_l+a46vDN{fH`NdmC&a}jHCXd^;<$8*1>3ab5XT>5*onj_RIHvXZ`QYOmJ@0W$ zzyapm*Kte<5RPH&G5J!MBLF&xh5W!(=Ea80Tp_t{o$ z*AZUB;HE(7+p$7>uzb%wKJOiq84a8GB`IcOeT8)=l%;#g+Cd#SCv4r=d{XWm*yuy? zL2?5{n*1te2oKF%Fpr84T+JE7ig33jf<^`@`#_`mb`pQcNNd&SuPMA^Tt1PF31gTR zZqBap<)%!!EjvJuHBFtI{r8l5@uQ{IGJo^)>FEzNx2@Ja_4-XaZWF_tkVl#GS4dp? zjT=5}+P?a9KYm6yG&jX2Yip{q`@~=XsL~XDOGT@y$R7|#$6;uj9{x;3h@Ul*3CJyM zw!klqDkTdw_J9MP;(wj$`wX+2836$VF*7hUlb{+Xf8AGEZ`(!?e%G%c&_1jHYqKYp z%tHaYIhvww(O5+bq^)!FK{GNAdnR`#W zRI)Hme+D0yOC2}7Xr^MC>TYheIB%Q&a=x&^i{*E}oSyKo96)PP)oeCB>(?(%_#W*O ztz@opP3UNtEOaiF(tO*=&3xgMha)bEO}jn<%UH3#s-wG^YcT;H!AML7Na9>MbY0O` zY~alQ+1Eyift4-PsZf*p@GeN~SDBHF8Z=QdI(x`fs3rTK`_Gx4JSUL0r!Ahvu8cwrlq97FTp>}YW39H1s7SzH0}){v$R zs*Exntb*0F=d4+E>^x_y-OYuN2?dr7;?sPQ1z|{nE2D`xzALwW{dnYj7Nkl)CvfVq zDs@|Lc87Z}mCv?i$HcPJHs{m2v!?w!ETgQ{&eBff!y#NwDtqs9?xQd&NFDB>e}II9 zl!KCXjiMfJ9;#!DkV)tCej%eefyHmESCq5E)U1c`W?LD{c2g1Og6HyvgR|wSH9z1u zjaS3QYZUc%Cq!c`w#GDU#xm|Lu__K!**+xe-NG5_k-0`;KrDh1P~@yqL^I13N|95i0fU@kkUjDa zUJNHdhX1FYssWVS5GWULLm`nx>sp8>uYdKZk#QxDtoc!mT zrj4%61nvAl{yG~Z9+rGdla1NM-|^ zu3}t|duCMqspwYQA9X}8_H*}x!EI{;qvRi=Q~*sT;*!rGD8g6S7vU%TJ0-ob|2uwW znlqCd!)=1Xt4-?vAk+LrhKAfeB|i`3smYyma7(UldqE&D+f4xKFGvt~sFQde_LH6_ zJpnkA+$K1GnUxl$LNiba$}9AW6G8!`!Ow2z2G^EuB=7mdABJy1BM>YT87z#1sYD|x z1J=lhcoUFb4w==^5{A;!z9-UR@B16hPp1@26oMM~l8t|e3{g$H+HD7>rYgT}s#Nxye7c*&oXe2j4u zoCu76<5 zZe(v_Y6>$olkq5M2{s@wAa7!73R{zaDHM~CDFl;{DFl;{DFl;{DFm}hDsBM`GdCbG zAa7!73R^QVlb|djldvojv#>0H0Rl5PvobDb0s=ERlbSI62{0fqAa7!73R{!0F&?wM zF_!@WF_Ur76B98xH82VDC4e zM;+VgsAAi;?R2b)Z71EaZKu;68y(wr$F^;JnK^T2=Dh#E*7vPitLnM-zBcc@@2AL! z6jkViOzez+;&!&qbWHS&+yD_dVNE7R03#y{JtHGCEE$=qg|jvAzj9bIb)ch@g`F+; zzZfEpKttybnW&-j2T{&{&K4l;Vhvzo0Wh(1GjVV;G6I+x8M*#Tv~%PJh#Ik$R{nOac*x1g--q6;=!qyC6YGDloD2U6_JG(p6 z0t{_U{vaA!JK24I*c-YUT38zzeGvXk-4Gxyqy#YhsPM1)oQxeU?46zHoh+>XsFC3h zHy>>lvo#U1v#|l%Iy=Gsk)NoABhdJx?;Z?)9j=wFotv%Kf03z$t%>O$Wth0wGpN~G zIJf|%ME~M^h+zMbnE{;vY>bSI9PFF`paTHtZfwr*M*vlS4}0LBN~S-=A2s-R+1uFz zOh3v1`dF9(KYn1noD5xo0B1)RppVzT75|H1nV0}37RJs1BcPduE$lzuKg2-O|KN}F zceHQ^Xfu9{9}|G_kI&yvx*ro}VrOgZ@elpaBW6%j(U6lDqxq}kzm>wmcJ2T#IyQCy z9WxsvfQgBJofW|G@!<2ne*W&jf2;pfs%U8OS9bsMC}nGE2jKco5g*^>Sc8~ev+zlNa4Lx8#j{XC&0lb(#med63{^x8180c;7oIgweAI13qOzj+D z|2R>9c6I=R@E@W-5eE~1LE<080$`B(2eAPdWd1=PcC!B$PIwVjLOzYIPoX8(d8iJJd^3w~s3@h|vMzV*N0N3J&iz>gJWu>BYO z$kpy|$oj$kcy0Vk{gI0Ozu-sUf2GCr5!mUUwEsXrSKvS1**@q_ANR>W1|Plnrwe&&AIUkp+5OAlqwOyLf*+;1{tJGj>-H!7pD8qUadiB+q5r%mK1TGv_|MmW z0TAd8G=^QAw=?Dmw5$nieW((`b)(xI=bIth)kvkH^ICLlb9q99N}{UF{I>3RCzLeQ zjl8lgMtLi^MEL4;+*Ah@(wv~w^6dShAE!LE+XA~ViP=96HzfA?ZK^A!o9YCuVi^Ncz#!DuaaE`?xkd!E=ny@=WF3CS)NhW z95ykeGaWuOHR^>s((LWs3~J8AJE3$O4Xn>e6w41Utqtbr$2rf{GF4`$P8?DkEo^-7 zTh!4haxdY7WNED5UPV76*ZF>DbA-hVE(P|+&&jCc5c?`(I|dfh@n!hScA$}ecILPl zXE<7`8&Ajs$SDYGp}m60iX==EDoBQk^t13R{2pIP@Kxe9K}~4dx(GT?&eS@nz2jrB zxtXH&$88Ai_|Uf6vwYcK9w8Y@4W}ezKP8!htdT6qD_~BKspR>HDGxbC)fISY_r2%Q z|GcNO1h)+F{^@L^v&P*E=gx_Lr8xddakI(40K4&BBHPYq0CQt8P=^MnX*s!srM<~6JRv_xQ8 z=?wLR^%STaAsGdyI}=WyX78szIff^Y`E`f$ESuZzko%X~XO{xe1TAfUn>0O!LBsl) zl|8?C))eS^>l@a=_&Lm7XIWlfazc&tpfWdELoPE^Md&UE^GzlH^zmHGPD|H{DXO4z zU8iaXW#ZS#%7Gw~mssFgC;qRb$Jb9hV%S^Fg1F9=Qx#q4d`% z$dANDe{o5WsJHxh6m+!;A98M_7sK=REbY+Bx5(hhmam3akRfE?e8M5VfSy7wmK0jz zXrCA0CoawYo`vOnl04+bLp`+{YRv}M0VghwAgrCwp%IK=dDp=7;>$BgF>9C;+*!iDtIRoNuc=86bj5n zYNx#egz3qzswP~s!iF0K5y;G5i zmc11pn1zqbR_ffYjjTGwtFqzXzRH&snp*Nin+TA^S`*W-pOoTvn}O}ccs<^tP(QAn zou=SS!J*NrDD5CJ|7^*BE+eNXvMtBaF{sg1iUD*B=Gg_QlXHqBQxv2c?9#z?t5g%e7Ii5hy*mrdEqtrBdVTk1{02TvA?!k^@m zN$fuZFPKwSAj3PzKG9Gn-K1Oj8`NNnuD>zV41y(DQKAmTN5@#DBHLFYIvd>S9SZk6 zg2f~J30JQ82`h5`MIW=z(J6Fb(E`T#2s7{@Xr97h?;c4*Zj)Bi^dW@g&jc$XePK*=tivn#8z&li~KZjuFtire7+Qd3$DZz9pDTTrvwIUXMlsBJyp>qj7wi1WpFSob z^mIUJxc%CJTanl#D8HY4gvB!3nDwFvmbR5r#2)CHA-M1>q7B{;f%z0kmo7>P=2ro}EcAyF$hYek}+R1T*mY{k+E3 z#r@|K4FsMlB9gyMz^i4Wir68tl1H8UItg{aR&*yda|f->X2FNstm1XQP|ZU)F5Z6P zq&RQpU*F)6%*kyr0PT&2YW1V&ZJgB>%i*rGHu1@$=((@v@CA*CJQ!%%X&*ul{Jyg#2OKm@pWLd)mgmpFJ=#qHt&3lRdr!*fiozEB z*E^HPKh95VT zc@Ja#eQ)y>31G`fg)f?Qv~Hw3u$T>h_0D@frbcPDd%N(sMpz?>4%^jd(u>}kaE ziE$flJU6*}h6ep#_#?IsUqZcSkm_F!vzZwo)Ha8LZ$4k%D_rH6Juo zO}Is0wL2dAdLI}~SplzM;-n_^z;~|uG?Rub=RNZ&JLFY?}GGeKOhd$|hc zbe#^@{W~TdikHXFgtk&|hW*E`X%?+wr~P=5_eF(Ot1@RZNBs=}zXe=>C}e0uH4vcJ z5m=jD@!(OqlTB+dVp3Z4D@fMCaog0wR7KOkpUpz zc3-QLwrl5WcSXJirJAbo;IO_$MAc;DC_!2_UB^EK*2aZHnze)wnx(AUt*sysk>RU- zM(=Dj5BpKvvO+nV1z^5^J!tx!Q`=D;kY7j(*sR+~Yg541o(zp2*Vhq<)^Hx-9SmaN zX^MicC*D)WE4NwguE@!ts<CpfW5hPE1F?p) zunte2P|?FD-Iwow-#-!5+~S&I54m}GcuS(^c^w6-`C{@~cZ?do$z9@qN`(h$_eVK% zTK?U%uz{pM)!O?!KF2RU9?_c;?i#NYGGvLA^M>*nEdHq?iyeb3+t?qRq+r0eJ{B$| zd_-aI69PC8Y&tA1gu-x9g(>}N0vH0=>lTM|L2%NuAjUp_JPPutbBm=-tPk*o5xMvg z@4KbkA8*h~i~DLx96+-;SSDi?g`mWS6_z7gZR_7-7 z-m<6w_UGbZKs*#>#?@z(F8bsXe6}b}Wq1RI<)^kHFDNd93eF7-q?m}U-X(EVQF7UD zqu%;+Z}dZDx$&-sM;j`;DLfo%WTRF*;M=nB!omiBXUoNk z;%P^xn#ffl-YXsx=PtgxN+{-~RvoUa>QFNUxu6(_s4^PO<5`@SMTvghENIc7&nRVC|;bHfU=n$@d#X6z6iM?MxlvOUCus4@#{EmVPMpNR1 zK{&1Dg(q{jCjW|C2s?jMj(p}TY`(>}AzqiiPRy*+q)WTwH&ZR>2&61Rv=-l|?hF6I z@v<1Tv|vyGS8cB%K-OsCJreQg>!Kc_Rw;5Wd~Ld3wxS&r-d= z64wBhFK%V>&?dG6I#<hd3LzTjN*?E|;zO~{_$_Za!# zfAXxOb;SJoMY?mTHx8D|Px~d49$)-?PP2cFyO-SQ9@ISckG~3Cy=Qf0+eAQtw4kjqN#j- zvT~5-vIU^WTgE4-a`%!#S=Zp75LcK;K)dalOOu;^VPQxSY8q!L-Y@uu{bB-qKZG{C z`nIF@qmT6!V~8DpCXvb#U*YGHAqJq=5JAt*<26bzw{)7E3vE3m>=t@|f1s2szk`?8 zZL5gSN+59@eEH2%uuRb#&*~1-kM+Cw+exsK54GlN&w|WP%fhs4V|!gc-!x9%PQmTi zu2hzW@0Lxw%vmAd$dW+0IONAKNIiXH^}4&l!T4=tdt~Lex$Zr}j%&Mcf={490EWM* zASVdbUZ_Or1;*w<=DAvbvnowlmG78K&ZDO^o0>)upxsCako1*3aiO(FU8o#3H@pB( zXm^OW&@ATLDktk1`-&JFD5ArC@$QgRoX|5Tz0e6{^C{iCu}ZqUvv$3srjrrA^QIYm z4w-Gg(4~7z%S4H^mfPoKL~)0vjl1rTD0g}DHL(X`vFWo82qz_f51SBJBr!t=K!S>; zV{W^_6*(T_lSoDgVw7nbjny_w@l{nfK`FDT2pe9+Wb{my$?7_ZuijK5=w%_o z975dYBwleAGM=(YH`K$XooH*$_3ct?IzB8HYN1m*8Fo{ z=4~z#@b9WyPUNkLC}$S4lFyZ&XGP~)vvui0K<{@HuT80cC{A2oSi>huyTqi`{l>Mq zI&6OMfQ6no#v(d`5k&z{#!h(Z-1Vl<0#@V$Qb*Gc%i=6KG=3hDWYkW_L(V`Y{vNI! z8fX?)m!S09u-L)U-jOQQ5aJbVJlM|Qt75+ss6;z713`%-MNl1(0l@QGple$WCK~s?YPib$fWaADE_c^|)a)k#ld=oqh=7akyjww;+k`8U zHs0bMqER8}2xx(%1f(3;8y2oZ5T6V>>5`{ZE^p~(T3w%ZtJKM!dz`H4zga$vq$>Yz z;62|4T#Yu(K|3=1D(%9`FoWt^@xb3+lle}I5!-Et&ZZ)XKq8Zagr!Xm|GNx(@5ZTei*NB8&U)n=lI* zqNs8wmx#%DlZe_yK1XbkYE6M_>(+pzQFT8J6OYwpHff~T+NlGpm1D-^sRuZf<`#36 zRhg!pD5^$`PyPh{zn@Azhb7fpHyUj^UEo%Ky?KEib4z*E8IS{1?BC{Q;cGziQ{yVW zteF*p^K%v7PmTeQR~*Moi2}I4|Hg3Jutg+X;z4Rk0vrkoJ;}hN3z$WBL&(QD1Rte9 zu!7WZB2)FosQws(=`#lDL|rXPRaR-5kQpB1KDJ{0evQ7O0-fx$$iu>$ynHlV&wG@A z0#H%Y0~?Qsv9rHHu6s8nW)l>OfXUyxG;%;c0@cO4YuA{kR#%82kSljynx|E{Fw=+D z*R9WG3<|F}qLUcboO|%BJ)n{Bj)%@O)sJ`76_bctUN>}D&WtvTEwq7|)2)}Y{r;W; z?MhiCTEkFxvm|R&isE+|@!MqUd{Mc7oM%}gLqNb#x<_3VY4goP?_jz7{g>Hy8{ds| zgBmU7$b-$vQ16IOlU_SQ(#9!D$`1wb4z?zgYe>tP9%)y`MPeXUt|db} zl?_*J24?UTUus^z|4u~yeH1qA-k&KV*zy*cAZI_$s~r=?I3ZB<3LM}8(^5Tux{09) zDpuCcw|X$^n<$KWN5=@5!b&v!6x2an;((}EZ8U#T)xN$s2t&R7;)nBg;&^|ucGorL+-fJ#4GgnY;b+|R3EDgFC&0FZXGc)o$dy0fY-A}sv1Sa$!}eT>OTzqkyCQipkXTWhC(U5kEZ1y(}f zesv4?>k;sCR%D$^Lj&g_0usxHeew$@il_r^LVr8?!zz+CiyZvTrW0hZ^E?CEL`hep zDm>5rS^RSYk_Zn*qOPcDwF~1a7}R(8xdNpZZ9Y%`x8Wa(dDJo@Y7X&Mxgd!F+awd{ z0{d1?Rd5JYaxj;t&k}fl$^=yd8d3;^#L8bdE($f?T2`h(W{&3jtB%9Y)3zCD1jlRV zR9EFy2Lx`gA`6z!z8bbjm%4lSHgVz%y4cs}dm}Upu$@=oypw8EIlao8@Me)jS59sm zs+G#kQgTir5TqH2btoN6qV7T>JJWZYvhROBna}G{LmypZDZ$}?GyJaC?B|P&EwZiq zdc9NRPslutMQjTVDpItqAG$3r%{lej^Ex`j>~+)eQ`;CBg()BsV*th!RC6e-2_y+M zf77d@{6K0c2vt0P5N5cDQ6ej|Gj#Jn;d`|_9CxG9TytPRy*LibO7_oeeM-)3Zf*m2 z4|Oe4+?=>)NQl*ca5M4QhW(X{Z_Ae5{&mxxFhJj>U+ z{7MkZV&8%^4tO9AZ~JH%2(nGfv%PtFlkZ;fsV#zRwxLE2NYl}Kyj1&S=d;SGb%+9x znGop4Y<$Z&4S`=XaRyZFpN(~XQQ(J}ZKLMTmEVODwwX?Uau79V;`(Efg%$IRo2`t= zJ3UecCpcPFZ_H%%oGD#{QsgkjId1#2;*|`f%G`*S>6JdU?U#rbCW35v2zrX);s@L1 zrR1s|m{dGNbA1tZ6lhdY1LIt2VrT)$s|(ik-9jwPLn#oElHWM6Pu)nLHi+CkBcgie z)OsoTb>?1wlj#&&;D;|!j}!5wlJp>8BXs=+lDL)7|tugj4SuO0?QUaPcM{#H8dFCM{tv|JDK z=pJy4s}wz9uqenvO4l+jktHPc1d1;fI(BrURo+R&rKo~AmT%!KLJ;9eXCuk8Q^!4D zY;|vcxRh%ulxu5$))hl3oF0?5`eDrL2Fp=hOyld7ihaD)n*?brIP4%Bq>WlwF>v;2kds`ef2&&E;Qc)XxmJH0tBBZNL&k)qv~Jd~G() z_OOQuIVWlR2s&Pl2~r^_5w2XPF5{3?Hh#v^3_bFapPe=BwXrXuLiiiTNgj?_KeM0&V~k&N@s`{))LMoWX5rj_ z{+KvI7c_|A?L3BZDnZ|FUNG*?GIO5>Uk(a0cg>;Am5p0I99cUujGQcvEjhRXnVSTz z8BJyX2D`1gXKSANtPUiz`IsuXD!ZL+m}rc&1Ty?jM@0ZhZNPR4>Li6H7QJ2Qw1t<} z?0bZwqH@4u-aT?+0`Pr>AL0x-PiSzBY~Xt0fB1!<)gWg2es zTftp{i~${)G7P#A4J5vngaXp`7ad(+hTWpXA%+*cSfPc{QX4o*{ie`cU)ueD7Acy@ zlvE1i^Y7AFpCzutH^X?TCexiZ6$-mmf00wyb&F&1M6MG25YjW>#(xQZTLsNQWWM5z zSF4gjR$LnEhl21PMYd4(3x*@zi%Xp-mD}NjmL)BXy8% zR;^QkH%~XVReW3K?Mb8fJd53b2y)urn2HofL$Zo34Jk6=lybr__1(;pUOzW*6k4Ww zJ|lV3kIv9{p*{8h!+4-g@TiQIo^&1?r!@#8DOWzcA>4t}o2nY}!R9><40{tmHqU|>v8qgZMJrW{FWd2l5&`W%n|#RkRDMqv@_y0R;O`FWapb+E4F@QQeM zA%bB*H1BmkD!o8!V-|yY>bZZ_RyQ?7$r##>!wJ&aWJDav`T1Pr^MA z!toGY>Yg{yr5&;i!)AK2Aw}(|cjv3^yqia4ZT}(z{B39HeLeoNk>X|Ea$eWk>*U0a zjd(Qkh*r0MlSLzHq;My9q@nCo?f{VI+~FXTCGW z(oBM|0zAOy9=lHbxlq9*s#J)~d@gu8g+9b0Ikx`Vp+t)XQ}XcGxuaSUABmh^)q4uXgb8+c7|br;U>$jd zqHQz((`+uz^)fe3Z4{-!bR@tF{VeD4m|7CA&SQn%@MDE?e%QWSaF`1T( zx6~`LR>sZVwpBpu`F3sz zqKiqmzchx6aoS|E9(djt>Sh~u?lY1o(_$IAZXS!lm-<_Ij?#^1A0MRaq$VzVjhS-I ziCC;EIaI|GY$dnrSxRzI;h-9uZ7=>Yc}@Nbl;#_mwmu#%IA!qCdYvSmp{fVoC+avJ?n7W zb1p=Jgvh?|g@C(_T%+%PHQR!%`1lw4ki%oHfqC~+e0qYV@bTRde6Hil9m{Bcx*dXD zj`rEeH{G+k^O7yNH%Fpa|49x1?7MqQ8uze%QqedOdi6K=y-L08f`!Q#T)QZVM|GWt zj0H&10U$lv_-}^Wo;cRnNGpZbtxe=>6HMY(9x|K;>;q^pI-a!_KHQQ(e=5bTv{_%t zk?uzd3L=-IC1-X0xSqJEYT&qkqBin4LdSkwAahhS!PbKv*!}IQEcW|GPp(m;DvH!*6GQoyOY;9&7AT z&(FS~ZJ<#WCC;WTsoV~)Yq2-hhbEj#rAIWBdvyXti{t`DMtve2EHuvc{T%$% z>}22`Rtar>#u8*}CiZB5ct@TwIOB7*WkPDqkJhxbeC|A^ART>2^TIK{gC}NV(V~NE z*M-ON$7F%zWU{<1WyU{!ZKyAN^fNJThHLm4YfF1IMvBJH)?^wLQ#2fD3Jv&nn|WnL zY`Saj7+BUSDBnn!+9s`2X6S8rA@67{wVAbOQJ)(xSXhJ>-hw87#w!uE=txBUDj3K; zzj?r6zpn~Y{;~mLCUyukZwgUoL{cHRIo&4lBVw%zpMTrc)y5%9wrt?~#BAy6>QFXo zkaW$Wx$@<`$kL&}gkKI0D>nY=XUbAs`)Aq$U9U@lLXId=q?2a1P!LIoLmr{^y__VrP zP%F}8nO)@=A_u8V zMg(X#Z&;I^mGjP;!$nKnZ99d1X#_Lv6x!usUDs>j3|jpjawBV$DV<(zE74CCL<)yl z6C=nV|CwzNa=3vIvo@QF;9K1h_!bg0#Td^fCV=88RNGRp60@qk?%Uc!I4=!tfh_j) z0wiW4M6Kq3DU)1H8Y6HXOysZu&5H*E>URv|qMV1&s8@`q`>*Zsx&H8X%KeiHl&O=i z+zwe>8<@$(HTvAX=?{hoZhl_%V3zW;iIfBvpC_%zVe^Oj#7(-2oAHnz-hlJBGywoq z{({}sWI4RuUQ49c9Diyc`nT7!>Je%8AKHzPh9UNU(bcAR=*iDHjUFS?wfheP2GXTc zLf@V>jHB=2!|Q4JR3?vnD==a;ZPL}v3xn6UAR_cgMVK@Ae&bYIeS^9p=NwkJS4EqM3o-Q$yji}gd#%dO|(CfC@!f-(v`7E}p# zIKPvLDwHMrDa&$~I_$>slhGsziZJs52~~%G-kt1gSIP@bHbBO}dRu+Ekk4r0gf0qw z-t(q#%FrZ+ozu>RT2?NG(oKKK%WX7n{L}kA^xA`D-XVfpZy^OX-&Jb= z;;frM{k__hOX?l|;fV1?dU94;5`frJ4VTy0ekt=4L~{_>=dNC6)r<_`rJW?4?B}e1 z29*in@=41$O!o%*QfzPJ%9#*14Www4oHykv+7dIh%4Y;=~R3}_wB}i&)IglV8(^KE({pCbmm=|RWf2yhZ_wY~_gz>B;+5 z>(D=}^69*GyPAS<{~3eeH8|A-Pn_&M&(0(X9e^C#9>R1srW^NKc8T$1Z?F9;xZxLv%H&Ch+IT3*Md%AyUEI(`+$xH zZkqG&m*zCJpJ{lfwVum5uK@MvoXL63y^;+z3}Ejc2tsmeBN|KD4vr)5F_S%ms@1qiGwiI?Ef?TMs!}M~|ALoxiQ% zegobZbS3N2uH5&=m#4`#AEB;NBF16)YDzkMTUk#tS~6$(Sw{rAETCi+V$(|?bix52 zG3lVWXJgdiU?&CtmNsV}B##J8eeod_NKy3^Gpg=bfZCa3hw;JybncAd4>G;(g zDoIEDBPiI9hHprw*50=BXMM{F=`{b9JHmW)u?yX+sA~)>G8*bCG(u>9kFF;n3*~c< z97)<8w@PQH;$=Z2`w9Vx3hYbcoy|56Rnuwj4bBEkTkMF)i;>s~Egp9Oe`*7+X~U^7 zv#4o|z#?DHYTk6jy&q1pgZsvT7gr*A$Iw3G8=ZVqi0-CT^Zc?T^ zy*S!y=%mEf>lZJBf6{3^Q>>i)LXb~Uph2>(`3dv;OY3d{cN{`l@Zbb1eh};PBbElF zK)|QV-$SD^S)#P%t>Po5?`!sT%>xz$cBBbye#SphqKw(_vZU8n8cBw@Bb`Tgx+B(X zn$9t6lRxY6&vh(s8uZOq<~+|*NELB*;?XgQr7ng$v0zXyf6Q3oJ%UHn-B7+!m#Jf72?M(;-x2Cha7O92-dMWOv2?31|H@G#|Fzi$!{#cD8M$ zMDLIfM;OU{U-aWrbWNlJuAWMnW;W+R zo=*vpwfpRwe;xMfsAAoGw0SburY{NPt8^zObXlY?-a>8jMd$`uup-_Bs$5dP9=^LA zexZFAlT)jNiNH%c#Q}-0M%lrd#dxL;ePvokjun`=-Cch5m{VPJh?Ef+QK-T<&9739 zoM<$^-q1koTGWSbn)j1vMzN^G6k@O6chJ>mAcJFje_S5JNNZKr3QspW8{*Kd4~3As zbZ;?f8p-3QtuichtJ(O>;1_A0;?kg8#hAvuM%=HnG`aWXB!GUa!xF}Wpzm7R$3tI& zjA0f{pjhX%k8nQw+Vy{i#XV`B;fESYDhG8Xa)hS{5VP-s6WRjV3+l#^a==^tp4!KL zQaLwieQcPmYAg!+{PRGa6wII{ z4)m(DSllH7-n?J?r4t1lbBq(skI1bpCNR#^YgcJ9ebqeXT@5_C0@@&Qj-+l?NR%Ru z8Ex||Bb&tK_x>qaP~Mkfnj2oB&MWSoMvHd>fA1;!yAp?ipDSRp=Mr5dX{3-bS+8EC z0yYAYSTK6!uP=2m?rUo7ne`g8*mum{S%d|6I33~$7ZEPXUF_8or`zF=%A>>0urld7I6hdqD7X4aPZD?Ia|&pxKAtMeCqBzN zsxP0)EQzB+qZ-dH@_C&AOtkABY`&>Vw_2|GsM!@wOmhh6HW{)f7H9kSCble6tc#xQ zZ8>3E%Kq41mtPwZv?B-(JQh)O3yVEmf9`{xXM0pM+N+2cwa_los8$9iaeiSkGB9zc z8W`mB&Kjm)xjG@6^&1{>%>&?_UMvR`m9?D|v57T(!~^`Nvq31sQ#rn-IB6(WqL`)2 zIa~WS`sO{NLn-8HV>_<&d(&e~ueuU>501N0V6;@EfFU=+#IM)=m>_8l6=N$Jw6` zew4|v#ceqJ;w9Z@3E8vU_ZczyG?km}L%$_Cd{DUe zo~@>~^VZY@MU|45Z?;_*zrH$qe972A7ZO!7L30M0Crr*W5~1>QEqX@Sy`=JtCZ;Z~am(a)FvaV~ z!6kvXs1~u&!ji0Z!N{DLR>^NIF!mAKie@B((4-aLzI(+)u z=4n(%wrP+IeK9Ef>qR%99PAD=N#9V_%5mxz=A%TU3--&Fbued!@uNrTVsP$K+}?aB zlgD**e!w*)%6TBYOQ+cgw2B+Dddp6@GFZh`9X<|&p5UOG^V~s?HZ0&Y%-oVm3%hPD z+IShz9Ra|CFk;4Ff3u_oqJYm5T70!kszDxQO<_W|mc>tXRbPm7W9q+l(NLhX*jsOg z)D}U~+ruN;v;pAmy#Z~552Or&B#NI{aSEgb#AI=_^iomVy*fr$j*bCZI1{)HzGtoT z@BAHBs_}Ad5D;5L3}^QdRfss>#TTAa2?urvNJCl*zblVOe-ey_M7)thW}F1dbZCQv z3xm59dmKLFtrba`5-ADOZ&6lOA^A@ibZ*V5!0%!h% zSUHMaTMbPvbjw1&H!aC}VnsX)+Od8tmK^xvA_@-P{-qrmbYUZma_vlcwi}Wsr_uq> z>O2HBhidoGe*=z*-ivVE3O=#-5zzKS3qx1J&49s)Zq!OP_tq7gxd5+=lg^8fWCXL0 z-I8Nr6a&Xc+_UFYuq)3ki!*HQyADvz*CD?XFMs|@SYap^vUWH0UblO^ViIdcluk`S z-IB1Q5au9K~Pn~-pFA9g1qGNX4Fe>bvXrMZjN1CaUC@79`?wxSz+ zZKhBA*&vmbEU9mw3NGxfS&&KIS1zl5ICFeyZcD#Trb<((ZtKT&e4QphP;WnOCyJa> za&4S;66N2}54}QdIFXCR6#<1hYMd;eS%CH#)Qv8U#WVM0g-k~lm*u7j!^ zf9LoMT*2We`a9H2M^{T$w>DcW_#bpnZk7T%ps+LEC##-`oM%_Ke5QbG)l2*>@WMdeFc=w{=(o-ASm;a6W8{<&1ylhw-*8Ip<3rt(}>W z)@>3-gsdicZI!1D>IVK$J+BtTDJI?Qr|7`PUz?fS;3?18{q3UrLkeDtj0#vonYewcrE_EDs?qfWx9z>pCM@Ofi-SyR14L$+T^%9PTg?enw( zBTxPfhq6!J3cGD5J*6>|Hmzbvf1{g8)AKvpK0=aNrB+BtUqz*fOwL?fKgaEZ$m&N?-G|Ky_f{#qNCIxB0I>1*EXp ztC?e}W2-(V%e{q__wWsokmTj{u2|5T{oMbG)w1#g4hi-}i+_(vh3lJ%pM7=e#IRwe zUOzXjQ)D#mAwQe}z)g-_nH%iBj~(OGGxC$w7tuB^qUt<|4g+N!e{4h zd--*rLMbT$Ga@!avXy`U0-Je*?f?N`oj~!v~hIHvyqW=%!+)H;AzJvZuti6^#$?VzzgQHSQ%DCjnS9=}{8bB)K8tjt)N&r} z7S(#~faCBRjGq^nG^F_Y*?FfCohYGGZT^`Se{eKefHe{Xf7TYz>gTCZEi?R?$xd+P z@C|F%?*?;G?DS^4j{p7bQugef4}jzj~Hf{H2&?lYAUiw%Zjo! z@C3;c7+`#U=^%PU8-%$d>&KcfG$;Y5`4|J08oud|(v=_2y8PAmae{WWn``sJ<0fp6 zej^rUB)AhST=qVaeg5~V?k%cdzSZ8Vdks`%sv1mUW?&PLG}zvS ziH(_+A0VM5{(+4hz{<+O%*x7+NJXV-<*06Ta( zSy@=Ryv6y?M*yuU9e|CGkB9MZbAXr~$jQnSXb(^Vx>$nj-XfX;Z2=l!Q!9{*=l{5% z6|{75ao}fRad&rT2HH6@gPkmd=@*0CkWv$jJ?42KcLFfHKey^zYJ`5vc&0 zmR8RH5@>+UUEG0AAi&#!t(7Ur-ucbM)!q!`1bB-M(2!FEs5pS^|D~+>F9k-xzncSK zV`lrWyMJ5%<;cqZZ)2dTDcH^dXzyudZvim3vIPNDq!pQ6JX{z7Kzp;l6oIzR;5UDJ zpc~N27HIOO@OSD!fV7wz0Qgqnzw2{0b+U4Bab|Y5vi++@mcQJ*wOPvEOag3Y2eNl@ zM*J&3Nh>Fi>094DS^j;wHuhk5d++~{xs|<{`Cnz2xjL|D*;_ffg5)Ist@Cz-_~*<5 zVID`i=MWwx|#;Vzf1nFP+T1B0q|zx;s7wQbFl%~*f@Xq06bi* z0N?-h^WP5qr~1E7Re@Ij&W`nuM>%_QFo5r0MZ9(IKZUscdopPMy*6}!|Bavwew$|y zfcDS$8?bV*n!f#F`~SQIf1CXOoBhAM{J)O>|IJ9+)z046q8*8d}W+c{I4w@1bK?XLb7f!504xfB=q-ZcA9{Xp1{t|;-o&I6)reg6Ad`r^uANZD~)j#kpG24IOTV{5DknJrq z`+wkDX5jxK=bP@^SIs}fZ>c!^5x+Iu;cc_P|0s>^Eth{}%J!Cv^PfuIgwAh|&>!)e z2bVwMx8N?8PN093{+6AKJNO?4Z#{SY2fo$j_78l^*ZmK&zxjXj{2Tvgl1*KmoZepf zzu%g-G5-(${gna&d4Nn2mlwdM0wLD5A??4a#R%P*_9ld8srGcz=$O2hojP0}QQ?#6 zsIR74 z5ix0s?)$tr`e=U#+CaBJcF9xaIJ)wps^($-a_^V%s2eC<9Sd97Q`@iNRzP|#onea6 ziZ%!=nxo1!`7)134(Gx|j6jcZ;ej@HdpC=bJ^4y1pTL0VdlJJ@=&iTK9{VuwwO+2t z?%a(}iLZx841J3+HcjmYF*S(L#Tda0eRDk+X)ZYgw>#baHzX z@27E~L@C`pw4oI0MOnHM(Wd_-rp&Vv^muc(T-ET>?RK^vD- zRrc`ozR$KKA-A+5aGi(YhbfEPOZa(%1AKlnH1(ff{Y4X&*iCX>^n1L49w?`sP&~gb zeJ3Yn>=A#y>fdPUo(gMDK@bg707uv?$+89DKAwKn`94^Q@oFOsNmvpy4W(c`R2Q<6y1NT67x^gPnXPmLi%Y|C2scFXIidw z>MT^&$o-QNT4mWJh(c2Gob5{)hfZRCcLej;)OD9UGY(RhBU3;?p3dsyNJ*Al<`0MrgjXrb(EPU3Td@x z49=cDujltN9l5NKblv_=y5)(H{EJms!=`zVIN~TJxjb^(^MNn03wt>_ zuPvGChA0hLeEqO`dYQy_KBl^zF z!?71A6i*voKYipK0i0a}Qz!lAZufr{=Qk|M1*Z1m5ynXUnNMxj=Q(Nb+`T+@Ay0gmcX z{2^YO0VK;4W7tzT+cxY2F?)pgO<=}eLr~M5a`zC*To?aEZjpXE<#@Ik|CE1~DfU9T z^^3%l68n#jV_Z&^igDNc`FKC-3cf#XRdkN~ZT&XQ!B|xK_^x;>0+Y;~&sbRXsLB^X zx}fB)LKt>wKMgavF%5nXfitn4nAZygrG>yCk9P|DfN%32A6ZbCQP!{0sO&qWmT;Bd zdyEY~Iv76O6q#%$EaMP{$+>@UxK#FE?eTUQR{IYVU)Ug=YLZJ%ZU%()%Ff0%L?&a$ zd3RLxAngw0;VA4tlBze;8O5KtTL}}A9{9ew30X>Y8-Ji3^o$Qv{*?w#%STXjfNRFJ zAeguDfwL60jSG`3?gIIPL?&Fd6p8#@Y*}X$y1~+%;fGu-yw((w`pSRI=Ve>^=D9IK zeqEvlCSf9nVV=9>X2sU0`k^JguR{`kbwjqd54Yu!7;R?hYz5=|EP;;z3o=HmA;gX~ z-qoZ$M|VT8!<&u}oz{;|>ZB1epLS6r`sk!}fmJCCZF^eX_sUF)ZA> zeYbmS7N@ECm8@VrVpV^1I?ihI1qKy|55}Kd`~X}j`f=)dl!BHy5*zMm9i*2}oT_4& zN$!>=UH-BU99B}kAwdoLXoYqsUiZoB*uN-=XP=?p-*G9$l z3wtP^mgH?X?8Z4mfBVuRqZqKPQfMiBojnVVxtTrADgHvx4Y49Ga3RlNV23zCN+gf} z#Em!7YlDv&yI_A8$VU#Rj12fFIn$%xaRE5AFoeU z4*%MWl$n2Z=e{qJxNTdr>aP)rg}s_6jR9k(HSlHZCkeq+fzO_j21@nsHTYzgF4SV$ z=f60a-^dghJsWUwg(p+&F1umthw4t&(_tUrDE!bUG$N|^vu{bSP$Ky7#K=pX&jUmm zG^6~Tx}J<=`~w=6Uc5vn8EZYJCYCIB6+=w&)A zClgqOFoDoSRX;1fn#B2(-%&Wgl5=+{#GopYs(u*V^fE#HmaP|NI&<&)8hA=ag{!!v zV6MWBwq6;yvjw14o~zf2uVShPy>>YHXGdSTBCD6Rct&g5*y0Gc(rnerp3Wj~@J$CX zCDDI9bUnG&Aa=VlVAmPf9z2Vuf4%DdvBKNoKQ;6in8;L~i_aR@o#aMs#T6SZp zOY>D{Yc3#r$J6Ffr(IBPhQ|BzkKR~z5!}Dt#wop8cOSqPXCp5Wo>0Y0L*Z(Nysmtb z+4=6)6a**oQG@fn? z>{jRYLNMW4Oe8W5>Hzh7Qdlab>qa>&vS=F6Ts)4WQc9K%L zEo4P7@1^+l6S?&V*tQSO&@W0(1WQL!RrM!d<`tjG56MpG&G8sA$so1FA`&J?ppY3w zI54_*J$OGOQ2=CB?+r=} zKALRr&Qsnw33bwqi^Q{hBe>^_70d)hR34WK~}5x-^)X=Be<5c&76fb6XWBGZ^_Yu=$bd%H5( z3ttgLYxxIrZOb1AoPqnihs&KZtuxw@=506f@7r_NI*$v-iJaXU3NT$C zE<(O9|7XIk%rzH$CFM1=H)-y4QZAo->x6N2PX)4+KV?3#b<=P}FSduIlWi9G+v z$3f!;=ghBz8nw7z4v86oF2$Z!kTsXnV@|(YsOqnzIq;t?&4@!zt6z+eAY46|X2+w5)JC%(F(r&j}CpyGPT>-Xdh*Tc1`WE$b=%=C9+LQnUs@E^vSJMg>KbL==R zSs}HO%L@&p{FW^-s+mde5nMW8_*8n3LU%)Il?@5$!l{3knW7CbXK1$<5vV;2k+7oj zlo%LLdD~8B0b%vK1@VfC2})jTFh}3KTJr=eH&HmYwpiR@+=E0O$@HS zndCy7Ru_L|@isqJleqLPGaKnf_`Z1Ox3ue2_miv&nzQXCdpiEME!tc)AKY{r(4{oX zU_`^1hI+&ZelKMWdBt^4B5R|s{YigApNShF;|GaI=w>vh{H7H2pvABs zRas%*w!rEL=FNtx$AfWW$zMjj>&#sHz?n{^jPQZsBjV&cVI1dnykO>6|}@ay5ve< zd0v0**X`Y2QlEQYyQ}Fl=tatZ&U0)=WN6tIMLOTLvuE72RvuF`_3 zsMkfU;_c1&r5uV|od5bo0X>qR(6GNioUC*JS6L)L9y{{TTu0TZ>q>1 zC5uVkE|sZzePGzOeLEQpeemv8MlK%~7H@wf>6$W{tFh*nqYSo2WK!xgdRS0_vJrKW ztDMj6LkPp`0&7VFITAk-WV{)!2K+@uSub~`miw&=xzys5Kk?MX)v=ItT%X_|X%5=7 zK6$7ID;C82-4~?vTRm^@pqRd!4N~S1Jmgc}(IJ{fy?6CJ4OtsJkgE6BUNs1fBaVR?6qa)2q&nbo@kC|lvi=YxuE)7|{AZde8uTk)J}KP+gk z(0iu+9HdTV*eo4vOdZoUr?@H1pP>=B(IWo6+KgrakOq_j-^yKxG}XJQu#|XvBv1UC zrxdfDb-g1b>nS*qeg#W<14|671)6^-?F-S(MzU$f#}%ZIQ)nC#_mF|JBzJ4Z67O*# z*%r)DQJ+Vifl^YaYn;K-mRi#f0&G~=3;7T+X&8lrZI6la^&A~Vt3TpI;9*HbRiA$`qH^P} z_*`k>AJ*!#50!ZTY98C$_r5W%BZ_<*Zrd;I`rWj*X=_sDyP@$})b$Ev%&aay>BIenY+wztB8N7GGXl1&+sS>3f%sVt{W=al(ywWq=?(pP4h^~G0Ok3 zP>e?+&hG<*@qSvTI)%&+G3|aA!$`>uGnCGHvUdxt0Xy`8uA8u{UNR;cTeE8M#m3 ztp`W-d1q2fRYddW*$96D&?0^kUS<%97uPh&`4lE2X8X;rWLB9glvvq#6awPTyn5^! zngK|&9FNO&es-rei0b)Fh5k*uPHnO^$IdA$5i8GnMSJC?%rJ((dkk^&1j!n)E$PMp zeLk7y`m)%iwrgP=tAQi>o8exAr~@njxT5o5-It=a6vjid>2QC8>n?6^OxkJH+*0>p z3xQNGFNDmzKKcwMs(F2pr)U7r2mKsm^e9O9pJo_3G~8|SV#QA~xAH9KNR)mO#Ia=c zJH9z6y8$pt3Ux?gO?v!yIryDDC!9{wR%ToWv$oOAUCOiTxF~mX{2z ze5*Q0-ZH$E^Ll@7L!=wrW$^j`?n6;ENy z4Vv$gAQTCe`RZi+gcyJm9l%_c$HlNV+IqxS#4hNO*;gmNQp@Ja@B73%`Su+%R7eVb zf@`B5X*;f-KxK+cHB(&PDfra&*Sq&|A=`28o(IM%JH+09D zhFDJ#&L}BSTxl?nXmpAuwt*Q+M*6nc%>m<|L;HX~a5`Z~;qv=^S@u^y;KC2PKiKZF zkc&rD`obd7CN*lfx$Gxj4H#*Q*_9pw_oyn*4Xaw1m<*Lezhf<&H^!sr@HtrY8QLl4 zP``ha*PlWZP6r%)%s0yB(W3bx5#bOn6XozES7ZDzbcfn`7=2=N#D;cku6)0b9LH?J4x6XI;|l91GqC2w&`~<|lHpbt zg1r9s-_`5-hXJBPUDOoPyjHvKjQBDe1rwtoL)@p~K@7P}MYc^H;<;v7nQoZp!ask+ zOW@<#9kxmI$#HS6@vIktgH>s@E0Z8+o8aG^tZpFHJ)K9PDoPi}bhFRPZT=;7=tOX=deK3HJE zi9N$bZ@Huz63ri=z!2*SyPaQ<3$=fge}iuq2+2|u^M9zqW4$!%fHx0XZx6&Xx35h` zCH#d!#DXtIr9E?&qq|a|a5-bV*yz<=IIM~yWD2m>W&SMF;|tU3)FL4By>(yXjEPq$ zv7XAFl6?|=PnaF&OU*iK<<21okWMGv?dvJbA%x~~l&tD@NEk|LX#pon_A!4Vd||n2 zVTlmiN6+f_X9#}XIpPO(1NN0Ph;fH5)h28Ws7jHCTSk8JW39x zU(w+2eLkTEROb6Aw#^zwIw32$G#ejTaUFwkO@k9lTH{92P*oqSS33&Tukg%dmqN;z zjKAcp*i4_UX0g6|44_->LEnE@aH``TLV=XU{1|ivh4#5`l^Y99WFI`&4(<+r;D5D+ zK<;i*4{nwpH^pc~k8eSa8rX8i+YC2Pd{n7M*EZR~45!IW7ElGl&A-Dy+Dg9%)^%rt-TLkxxysuCsD zNKsA2M6Jl*gp)?ZD#?-3Q!BvMV`Z(*{s*w1j0{Y9}MNW~rN_GALyf$NjqIi%y9OoWzOYCBYn`ug)?r z#Q-Ub(uEhE^GbOQvZ#MahyB{6vaeXlX7ZfiKPuQ~^uzB~p9+d*qjO3mjd)!NUy1{@ zsy~}0W5w6wirCL%KGmS#H4X{P(7F<6-y)o4<>Po|l?n=W(?AVhWokI2Rje@@N^RA` zWB@ZPItB$kn2yPPeKJ21hCDKj{F)BIatxs@N@6)u#S9=T^?FItXnfn7dk&SILK%Hc#g9) z3;{EL?KZO+NCo{&ZUuY5d)cETTx=sS$~6pNH7jdXH9{;WK*#`V<$2{g*Ms1x5^6sU zJKA)vjO)95Q`D z%$%8RnZ?FgK6l;bk+){2(3qQuq%Lo6ueMek*vf^ki2 zUfgQ13jJd#?yriEky5Huto;#6+g#?n{j;bko%KYAoF#mtF&u|!y_=e{=!f?FC^m8F z&a7z1KpU!a;(XSwlb)68PDh8KUfP}8B@XJ0i~N7W3$XjaA+7PHBP_e(M^>c-7D>Tz zpM9ydC4<6aoeu&^jnQ3B36Z^bEz_Gk z@1-?!zm4#QkQGXAI@lY)s^{AYiMW*A1mH$L{h}SRBK-wZEy<>L3DpD_x)4s}? z7o=74+$%n3wlP*9Yg{WSoR;MK)>D75-uj>=qy{CREfRv6A8ct~*^BTFo`#Yl@e}su z6?#^^hdg_FLYgV(phjxuOdy~tNCt)`oP^|+R*XW>KaI*K7I&BMs5Ofw^uqfKjdDg0 z(dSD4*lmAgo8vg#3SVF%=n>!4fFw{Nadn+~(AlV}&eT`z<-^Y)O0wu>m^pu1sqPvg zE1Zjp#5u|zV?QRB7Y(zOEofR`t`@SleG3GFWo;bStD?Hwy4DLI4ABD#I|s#j ze&f&1ljN-@^@Ro-NG%Ajo2A}-g!t^~3pNBxRW%>#!|<%gsBPp1f{)2J#3*xb?~~Mt zYs{Esygk`}9yQ5*m86ryI_B8-yjtPGZZ{- z@s*e=*|k!VHDqDHK^Gn&zj=BWGibEreJK8c9As1Vd z?4Ihk4N;SL$#XaS1A2NSG$ADx5r<1r&8Mm{8xqP9Zxq+UW|yyt&*GdQ$p&ia5{%{;WWz^o;vW*MvKTdAO*z+;c1^l**4_Au(96Jk z==~tjLplm;I8(DoJdfl(z)Q4OyW4fk8#pbe+e_By30I!v_-ck>rSgrcMqK!k`Y{lQ zoS!k!VUXTS$FzS>8)!YWT~yHt`&)18sngec7PIl%VKs`xcn1oaS@@87@cX_PgLC9b zNJlZi-yKdyQ3Ky(zv&WgSS=|4D(R~5CRwAyrL`X~kgtO~FS@Q6JD@7wKxuBlZV|E) zkHE94t}GlrgKJp@+TQY=bS5RYniC#Wp5OxZeW_y#QQ?1>u=XYySarN+t{0gQYBXwW zv9E~*YAgwJNh8FYeSFAeX09i==cl8@DfUIlw!ZEFatjqdDh49L?w!c@&buBSvKG^sfN@Ns_ zrC+A>h;V;65H2wfB}uTmjHnuZ+urFfH5sf@xZT-rk~(;(qFoiQolZp%Wz74Xk@uuh z6j4)S`d$h^U!ARDh4<)%YEmbwwRto)LlWN_S7aZdSh|DN!P7);y`TgovVD zFK{YNG@FzIyUbbcu=Z9tpmb3ZhMO_>dLaI6rdV1Hq0v2lz009a+Tvo-O1Y>TrnJEJ zURQrA?xv7WrDgjr6ce^%#tmVc8T&_$75_PzhzFuIHT2wxK__|k?+IRYZ>66JA!z-g z0bHWGisqq}Abu%;U*#i4!P?WCw+zN`NAh&i97 z3{qwNLn$PAwq}VgA)3B4d_Qf)dxdSBVU1q(+oDeUXM*gl5e+)IvU9ZubbzP{PbB=Lfc7g#cVn5P! z2v{arAGt{p-!Z4^|GX-_9p0|;(KvyLT%93`hTODvp&}sbelI0y)Y5a69 z10m9x`}yj0*~Y}y*s7!^-e}X{1n(G4r%(2^CdeZ@*lEK-OE2rK#aVAfJ`(hrg8-4PI z{BziPUGtK=-j^Iko-cdQA6cc*NZ~^9n)a>)Bg8PqFdu(=Wbo>mI)}%fa|etZoAFWj zTu2Z`t;lSZu)|3YFZ6$Nl}_AZ`Y*TZWl1NBf(6=*rJB3Hn9wu1L}e?+JMWg#nFga? zVE_Kfs_j`5#K4i1*%T;|+TDF3@Nh?r+_e`qh5c*b*v86vQH1Z^RImbWeQSKP{9Yac zEmko1`}lJ=ON3{y`0dqNw|roEtZVxLQ1M~4U1;#mP4Zc@uQ7jXUUgU|6+c?~OZY-E zyIA)K#=@ro+L2qroEz#BR0w;PRtX9p6Ra}a6cDL2<|9_Y_HKk9PZn4@=kupdr_iy> z`Rn!9u>;y2!;b?A&^#Ve%zP|kQpL5>feV;j2WBoq*I$)@7a9kjv$ETF6Qm?QI!J$n zb{Ujrk>sZ~I~IST=c`xz>4|@kygU7FN4o|p@BKTR!Y}2^I88|0L*B#(4B0lHoZ)_~ z6{NwgGYCN2%hWlRUSaox?B z`}<~4L48Zox_=)=#;YQgecN14dJdghWUh6(Ii<#GmuP>F0=pk*7niUJ4`B@lv8jd@ zqbAv4R_>(hbxO(o{>ctblfK5WJm9qi#?6(mbUB$X$zpR;g-$`RR0V4K_Lza-|Qnd-v5dp0>q4OhcB zS$GE#8FckbtT;hXwP7wL#P92h4HPid)G1dMPEnXy(X!d)ZUPTzTC@*l-yfn{zrk2{)>lz{bp+jqU*uyVC}qyy&f`d7<(S z(_=qi4s@P=HxK|@@{8uLKGQR&64xWikmAxWS3u$ZU8-;J@$K1u`9$0loAHU?9?_en zsE#f0Jggyk`HfHWIol;5K~1$Sl|LnG04BFnHZTn+&_mFDyiTlSQcMcS4%iBg z<(I3!h6JIgS?Zv0^Ca?Vt_-nR;^~2qChxlRtFA?a9*T0*1+T1g3owZUtf)l(M8*0_ z)#SkQVY$m!BJS6QEJV+xlT#j`*i`53{Y~yK zqRr6d=$D{WmGQT^VFR2VUG*)(_rY%~;yd-w2G??|x0W6{w5=KWh&MELvL`csnc7rv z-|P*-fv;7=tJ<9PxZ%q9S3W|1H^iH;VZ@rpUpjH|$TLV+cm@^oJZfpUp!}z*2oG0)MSg!AcOKwWzOj>2*npH*feY!Axb(=8?7;&D}#X? zi)i5wOY@LX|Bf4vc+1ON*xM$~{J178sL$##!;y?)sBd$rYsFJt+`Gjsy$pQcc`T3A z(pD$6(oW>&i<5v zIH&%kV5@fF@m-0Zw2T5{xhk7O(#H(A8PX7GXu)v%%IN;lZmrjG^w*vDkG+?A)!-mL z$8%21BK?ap*G5Q-lYVsZc5};Hf?oW_be2D`m>GQ1Y;}!PL=)W#skEo5QB0`b3av9c zm9M^rnvR=Z$8Q>d5GK=Eab6pur@YpoP<;$AoS&`!XUN_#x0w5DiZe9`V9+V&Wx6>E zvN!UX@A@>p%cl0SXuH6B3R`$U@*0-fviCsf1IR~^H7TfO z2Gq*N{^AY!1=lOEzyPDUQ2Oy=m5+X)$2bDF5O=qfM)B4jWnWN{CQNS{Ok9VQe{1P% z3AGIhs*p6lbxc9NdIx+OdHRY-NrvgZv>aJK;%iHc0l!b>$G78oXWas(Ty9(~$2f&) zep5do=+4_-(rc8`9v(!W6 zTQVJ(U*uf<-wh4t7pkM1-X%0}-s@a%9%s9+=wL42fj-3K)zD;tM6MJ5btIwZcTTmL zON@-8IG-1RKiTFqTeAy+qYl2lm%hLIQ0;PpHR|!1NsY=X_tv#Zvyzm)CiybwcvFI; zx{6f*T*0l2S!A!=l12u_z|dOKfWX*F@MPG=FKj&l3+m(egpwfRj$N;1%s_O`;)dxV zMw~VxQ{oC?&$XQnJG|zY1me73?z`MNc5@eg#a~J9OCk9Fz9=}RV4QFL?Cor9(XI-O zu>-f6jawoRutDQ`S<_1EDOHE_XlUC7$Y=ckSr2|SGGE$ZHTTUg(gb%&kc}KcAF2%VL!)Mt=rU?J8BecM=m#56yGzIcJ4{8LE$9V}VEV z=D&GxL70BfOZEC3Xh@4`I_IV3(oim(do6{$>fNTCFi6C>lz!tDFcK_eQzPfrL41abU>N`#(rM!^ITg(A1K5Q%TM(seeYBZN&#>T9$nG7`ZOTtb5_oo>TNMxyJ~q93oeqgWJjMBA=>A zh&{ZK8(Rf*YK#>CYKUdaJ{W4Ji$X~5SUt|6q2t)PU}dgoXQRv`j96vQWQ{fYI=zG+ z^u61t=+h>eW%#;;Z4C3VF!B?h22DfT$>dWr4GHgzo>~JGtBK%wZX2$|6Q656V8hUA z_O1W3{ijrTRYO%f6nll7F+!JEUS|YRfl_Q5v-fV{;6VY9NEy8GS+tn?P{~{7s6rE> zBrLn8S~?+j`K}$YWAw`>9RlL{Pf45pD9$E~b|PKQS)il*Lt##|t)BKDw0I$`Za7R= zO%XI4sv)>KNxnkt#q|x`S0SNPg|q<_WxitNi0GOYym>gw$_MDxsdMOkG&8nrL~fc} z7NlMt);tP8r>*>>Xl>ldo-nuRf%*La+N{T+o@e<6LQnBH{@?A^`PE2qOL;<$3^7;*w?R{o`zDz$;_ZV@^YJOhc_Z@ zG0Ny~I7717J5skC4z3Ke%+2C6L2c_)L^MobaG5zk6+u-76oA^tjXPLe$3`rz+zP+#?e5F#4Ku zm3Uuq=lG6cn-E;J2K4Haxk!!@v4Sl(hp<_3x$7piQnS_O$Cb>$?|F*AE}Nr0N6AaZ zgVq_^%~}KNEffO1j;r5t*U^MGU>}Kedq)v~;#FZ*s-RMV!ZQz#YsFV4+Q+7{MjOho zY?|Zhg5B?_tauQzR=51JvegScSGva1AU_uvuXo&+y z1B3i*SMor`BF8t1zf*-|#t50Q7Bl31>&TXpXIxOUZDa5PhyPd!wfqq@NR*nqA4?7#}T8?fy_&zn^a35gh z{>LWa^-mdNkyZ0l5@FI>o||e4;@Vv0f#tl`$Y{>h4{+lQy3+rLmu30CyezDinx>MX z@^4{TA&u02HDJs{qQ*!>LwY0nKlH}*CiJHCrWURyiT#b_iC2vz$jtv6qhsm;yK7he!y|Z1cZF#l-_^09?BQp|b(OQqaR<&@(gpC8wvK@Q1|Ebpbh`AXqv1 zfshC+&jFuC2oN2g9$p#QSR6q}J>;+kKF$-$MuGX0>YcK!>Pu0369BuB$3ekpv(FIsVA1lMpuW&6Q`CoFP$PK zJB9+fDfSE)PEDdpT`uoS0F5)&0Cpg`iadh_K(iDU+i^tt_-cOx14CN`ueA)riKS0fVe>Y^i0)cdIu}LxPgBZ0S%w%fz-DzE{@J1 z8h#N#@7mfxf&fHsU0EJKAa)G5yxyCgh#yfX8X6!cD`xh8LB#oW;5~WgI85_9dN}N! z$Yu=qViAS&yQl} zs`iG*&jwJ_#Ik`QKMG~6d@$&WakNR)Gfhh_H5ujOvVyFHQ{N_H+ykV zV0z)(&ETJ-U9f+%?P=~LeqsnhxIp^ov%wjl-QSuvKq!TQg*ap2K-4n?279Lgw_XKV zxIpCbI|Tp$ksMIsDZvo90rE#+8?eki01?4Ya=$k$6048&4YD36t>~Lj4Jh%EU z;Vp0#Sf&Ah7#6un0Jcy31L@yJ`6)<97xAAo4?toMi@YZQo2Yq*^lzyA63n|i2Ov^* zj{GOR{gbTzlh*%}{sNE?#^w(ZKmeK<--3kFjX%Wjaet@g;8|XOBv#h|(wA31uRq&R zVEay-$Cy^9J7!K+eO5380wjUSYr0w0@w+ zo^d=sllNM;=f3P92vH_`3CmzA`C0utERU{?!JS_xK}Z|FVFNfeKEVa?ngCz00qc+K zZVCujKl||KGr429gzAv9Yo8XFl!<|z-Dfv16ZiBGy;iQDgGi_gcl7irJG}Pqg%C&f zAU-Z!tH8A1kIC6bJ4&fP7VO+*m=v>($L8Pa914M1KLL3VUrT)Gh~g{!WPWXJAXn8t zZp<9M8$i6@mc)>hVZTqk4gkF#g2kQd>1|qHXqX~L2#m7}lZU29AfHwVc^#WPct4In z!}dS00bDnC7+{PKpH{L0+j;;&1@{|%Yk?X*fmFcockau?)E4+6b1R@nQ6P2=aLfP0 z3goXRz#Mc0F3#M8z~(}*eq$wa%ZueJ2Q{Vixj2z$c&qFBFYPGe50EV`{|mon-;O4U zcP6U65uewCq(|g?$7^fj7yX)2HUE70V*RM-@@|GRFpv7YYkXHP@dZT0102|Ko3j(y zm}^=`Yy8_il}5Cuk()ijk?6SFtT##hOW^HX<8?qjx!Y2XbLiwAD}*Cj<7;=u2^GAA z^P#PX!4@vaz6ldU4^ZaB-r9)ik!Uy6KyZfmDZjrex6k*=j0o`X(Y8fK6OY2QK>>=)KVFhy*6G5Y~qFVJ2ZpMct???)_rt5<; zFhSWZB%@oRRWC~~vm=q}K!q)HM89*TNh3HizOzv~|JcPo}9_WJSF$_E`Ak+|;BI6t{=K2lHnXqs3il+Fz&^mG|y zqD#0?|4!n_H-ruP;N{mF+52mbNoQKRW-3kxf_Kzz6v@twdKbXtAlT^S827y(n<7N; zRGYGNKhr|}9WX4)n1hxXcFCmV!;euZR`4X;WrOb?fjPtSn{^$TGeSkeRo)151OYoRR8)BI-NSYop~bG( z7mam@%X!het?V%h6)${8>EvAjaj6_TY2~USiHZyv6rkwY%De+c8 zzPlAh(sYq=zUtroy_>QpTBlmix!A4W>rR_Gd77d zl3Osh2EYbZ_NP#vw%}iboqGgJ72=}l^e+&0xscI3k#Pg=)wCUGxhx6Lh+YMgpE&w_ zua}m%EUU(=M3PU5tXX1(qYC|(gRNhHRdwJmTRi*wUk>>a(Il_s-DZCmyRhiXLC`|; zYhQB3f%kqx1wjm_&m5sfr+9wXCQgD_sYq*g2*ga<3=^iq{5QNH=_H~XgF2a zReZSn3VP!6zfp&rO;Sc278FyIlZs0PoX|H*IQE{m8i=EPhku1Tiws#D_>q6(5~Cl} z`vUCK?LKWnpHF^GBS^3Di&fG29s*X&c;Eu8tgFh$k+J)k(L45~xJSfTuqQ*8rLVg7 zpOucy%+e{kknJV! zQiGC4Nt)V+$mV#=p2>VCHw2|h-Sffwr@j2dRBYNo(buAwb_CCCMY!~7g%$vf26p{V3l-9}UJN8r6E+Wc@+q{nvK1gzU48B+j}ZGI=;E9Rv;N zC1`8ydBPuLPx)Rh_@|oqWdL|k`IuE+R&F6k0n+h+bqD(U$nXA9c;g%0;6V1jd9`oN zA$V@&w(Udq15z}j|Neyr3B6&;8LM64V@z&S3TUY4r9}|V`pf^I?BClxZ!#lN5CeUG zR+IU?$*z*osz8KjEh5Ox!;xQatma9Ds>^@XY8}jBWI_JCde=nwZvg^y=jX_=*ugZn z^RousXNeG4@eW-OR3og4*z>Eg!ef}7U8)oGqpNB@T@R2le*A!Ni{%|Xbv+2qksv3+&L>3^Si} z3*Bd^KtVkXk;x7icmsH^Opfjb{#ISBLttTjOMzJ*B{5TsW2{KROm<|iKHF$-@1;Ww z&Up+D)jWnig|&uBl(OZUkle1sNaHi{zFdThX)SDNtU4dpWXvv)(x$NBq|BAi{Hf`E zx;Gf883<5jMhAMGXuPV@oWJ*|0*gDeH22avwZzXo^4ou?hXla4G?@3Mx%mt5tw7EY z;(rxvf-`m$)$uF}D|Ru92}VSQ>WFQ>Co^dpk0S#n`(qYxc!bdT1eMC~67=D}PwMa8 z>y^5~psvfr-5q!TA=E+>Un5@GxsktACQ%Huek=0}Q+2|o2Oa^{x@+X7Rqa)$nr-gM zI_%-dAQ%(pu!)2Jx>oLk{>oYt{X48Q; zdr)(!Kz0takiue@s!8DEOcM~nFMW>+4;<&|pC1PXXV+4M7<5kJ%CPmhB}N7a$C$OO zWD_mBHaa-q3doTK8>~jM`2H~J9k`lxIhJy7Xp;MMAp;IO^AH}fEYeB@?5!)e$6f+( zP5;{e64b{W8JsnWf6U;?%uTqLSs^6*J)JeOniNdj-P-8Tr6RUyX0i@KHeVEg&(P`Yr zV?#JlsR8b&J5aOioGOPtn+smfP0@%D^`=HQL(??V*W86Ys-KS~jlQli5TMmksY(%On``$2H+-+&hpxB&*`_v*_br1g zkOy&LSnu#^iuFnNW_PJL@EU^D#x%1pwNr5=6Lz%9tz@8wpc?~mPhw~&?2os@)GlT- zh)bs2-|*)&2V6vU+3W!t-DKveajcRjyGn}V2Fjzi?2bGJErlzF_|Jdt7`6>}#bKZMub*g-lG6ea!gtcJ6WGE3K95{9K7Y z#Vfroa$JrTy3Z@$o=EsR)jIQZQnm0m%AuxnBH7au20aa$Cn~#OcZJRMoiWvle~N*g zk*Xs;=wG*__}J%dRhH#w_c?r$P`2(?EfdE3uZn_@po#)=SKU#)C$YCkE&ykj3ocA< zWj@>UU$vcV@j;`JR@DNweaIAE#x>MX8+aOwxYr*BIZkf$(nVq@Y`Ps?g*jWY(D?1w zu2`;Pa%G)0cmfWdnYJq7TWR-k;EPIW?2Ngm@IftmdR)iS`G=UyFk+TKo(5qpnGVFJ zIRtCr!aCJSH_2$=_SHaWZ-B#y2&;0biDLm0KOKkvmn^T<&=P?*BA7D#Wrs=@Ur6td z7AA-E0^WAg!>oqmIO-^5Wr%pN@v7%w=LH0rwiSu@v{kE?E0!8ENUqCT;FK1AH2{1mg%>YsX!LENwyfuav zPdlI^k~H5z!u&`OEvpW~to2P6P}Rivi`Er?GHgggN!}rF72n2IK%$-t z&$M;l4UuWH)!NH9xU{FQ@k{r1SZ8~8+;kxx& zb8v_KHN!<*CZXq)QviOa_i0hUzH!)alX!lYmd`jHXcK8UQf*zT?eK#$aX_r8>UJpb zegO?Ji>Yr^e8l)=93Y@&^a~tZ2CIyQ1Gs{c7dQ)xH%Qlw{4m7FkHKuQVbU8Ss0CMT zM(qZ{?$yOamyFLaH8Qj+>KHQXCF<3yPY;SEs)=_uwcZu&U;y%Y4VfFMcVjGe1XftI z>#;O{=t@cDlDl5PR*GyvU|!t5HpW0FQemh^Hx{eOHHaD+YEg-X#et=C>-w>=K;D?F zInSw+(~=b!#L0gkSvN5TS{80td3%Ere>*ts@~5k?fH8JWqC&Go!t*ydErQr7eEYmWM?mk(2IjtkOOJSh4rnqRj^_kZS{D{0zxja7|TYMTs?<3MpCZ2a>E_k z6Y62(oo&&F&VNH*BH;YWtSH{(j4Em{xWP%)lmg@`Y^52UAnLOpjI_`rvaJb5nrP$5jZCW7 z3=6V8&C~8w2YafydDeB6$<3WIIBm`7vO^9$UwW7cZqC;n7H{aOGJ&ceFf=u|>u zvptjw2U&STG=kDb&`ULE$6aIOR;Dc~Mq&1+_*^R+Q9!&|OzagE0-q-|&yw4~$Nov5-Qx|HRM3kT#I#*t0^Ya~YB@B$x0+#*kUebFS zcp7lo*P`W}?c%0#{~q29F8V&|*-_P|1-KX4gkrXI`TW6{H)TDQHKtGeX3%FKh;Rh&Uf%c^K({DNMac#a|Z}9Yj`J9UB#ur-c?sA1w}s2s`Kb1=Y}s`i5eQ5 zzV|;r)ePNeKTwc<4*`@#9 zYPVkYy^uSsQxNI^u@ovAf&f6Iwbv(PibzmO`g+SNlr-BovNang=c_njFO=BkJ-_J% zv@>T(hmd+BgpZ{{?_9YR!62^OAPAjsfUSfD;DmQDp6U z4WtqfqV?h%qF@%@rJH=K3#4MFiXS&$pHLlIEW6 zmr9mFWb7e3MJtQk8&wCW50tvOz@qc9A6Y;Z(*jF>V0n#-YK$VmmXk1FU7qj?;El4V zS?cCW-L9Vls(r)=@&Oj(SC3DsW|4y&z~W4Ol#`Vdbf`)sEA$~!+~p3G`+-Re6(bH8CHh9Wt6WC$?y`+&}EV^teBh z!-nh=I3|TG$l>vuWkfUBWNWcGEUFkOX>&XEStsu7(>7yLT7b%xI^t@B>`+AMh7Dc3 zcr2~pM8reF;x=SgiQiu;CB%f!69fPdXL=uyiIb}h{+Ecl zYzi8kGNOM}|E`bDY$dy$o|JFO^s;{CD0u~G+YlSKX8$iwUxBBGFgG{_>WDPg> z*wLy>yt+>j>;UqMIca+FOGtRY8X{YI#TyADBM#94r}U9<;PyI#Z#2G*9!ObSvMLdC zhjzrY)~oVx3#%e4e9rC1Y>ww`+r7?wPw@Ap=OpOU;PaEN@B+OSs69jFqD#}EpN4!| z#0MyL)#>VCHp8G>1Swsz4;LTVC)r*S2i=)B@iCLpD_}$>zW*Bvjt$6Oj^OLYHMQ&y z{oI=4<&DK?;1T96`bx9ZqA&GmlzMoQv|{k{pO;$R{YCldD9NlwI$6ozPEWfkDB0(i zmeCB0k}(Dnl-@cluPij!&Dr8Hz^1p6$pQMsE_U1o2=f#6k>)4%mqp}t=3&+*V=G;Y z<4*6OM1ZuX!Y8D965Lqn`?iqUz!^7y9BbfjV3WdZ<;&eNF&BZ(h>k?5@Pdl%lT&W8 z(R~bBvcHaE5B=2>F9W0>k!O&^Avcxw&qs)r%R?D&l$*;V=mYC%c`u8nT1}pDPg)GH zKx3m4EhzH^#wCqYP(#2<2w}+HcSj&!Cv_kY6inr?+Q9Et02Qj* zask3Xm?<+Z<^wpDH=+C|e{n9Jidmmy@+s_uIC_gl6rGZ&bZ)UKpq z?*=`Hb4n&B=6CtSsIJKI-Hq!pOAS(C{WJXO8j0kr`?hu|x>BHaS~lEzupHgJFMokw zQBf}GHGxb5bFOXv!lp`AGeZ`?NTXH7nQ~23Q7QZa_iiY(Zr2f;LQ>pZKX%zkXUCPP z_2MvfVDXAIb61@}97*|W=&n9h!$FD*F@=0+CZ|R1SE7?#I8cCHLLlXyz@%cX?*oXV zTHli*g<2}ZFwFz_fV2>Ndz-nu9uVEi;m%6k#WVk_iP^#%7walB$aH5D>q0}Pl{{)| zKPG(bL`y8lH4ajGqVw?g5JYGfw{KdTc+<*x&Jt4VeEg8$5Xds?fZUc8CanLc{T7&* zf1j0}sr~oLF@vw*}_QvLALoJ+#Nra(Ku&Cx6DW_bnoBdm% zzdM%1bnuy{aVcwgilF!h_13T^_b_scNIO9j5BVJ&Y&idj!~gZc9x4k-34BZeVQqNV z$E|lV#aChsR4ST9HDFhS>f>ThW zW^hl^UacMmf|sh5cpJ7pwNWNVl{pIvo?{4{@HO~n?}l*)osrroMftx*U#;2c%?+?i4;?)P$2_f=j3S;N z#dTG#y;-?U!*GVE7Y>LVCIKqe@tm(;{=DoaZ|-u2l9fuE5iQ)&`2-^- z^KJE%kWNl`Q^~$h%_@!4MnSRBC+ho4uAiq=K9lsrS+DSLEhHlGM~=@GudO^4vv6daAPp}L z`LZv}xK3RkHL?E*bQl{ansMULmt*zXjrSA|UuI?9EX03km}z<<(St8onoU-8@PzaK z+dk6Phb*3ibpU9W?Aq!C0X=^!zhPw_0Z&xQRawE>Nbv%D?9A|QPLZjk1%pA&QfmJ` zHk-~;=H0g|Bi3yUjX7g_if2TGQg2)RVDUbr-zE8C6Q%t$4Hyv1`JOHS-u03|nPRQq zW0~e~cxm5G9v2t$YL&wvkm8FBk$_Q2I4L`SKnwDl)Ca7$@C94aaZ=Aj@-L3FwL&5| z@ru%Zzw$Iym51YsUlKi25&Iz<5{^KFc+UB1xC1!tQ`gy>QH0lE82K-{XdU>zy}9cA zPxB<^#!R0=iFCZa?l0Z3rh`LUM{HFc!?DqAqn8vI%kH;;Vl#~LCVV*GKgQNbA1Qk>IJ`wG)59#Tu$($LtVKmcTPr1ZM2Q z=!t}uJCRyV=RZ;fI*n?&3aphYARbE;vjjZus{l$#xTe7QK_80I9vJZdu?VqFm3Lgm z(cE035~N+2PP`fiOEaA1De25V_+R4Xl-Bs-lV-?ujX8%XDk z-n17e}*k5S3wM{2oih4mF{F}*?D73LV1v$BIk=bXosHT%AsVY_bA z%l;b|p0Tm${pZbno?uFs&PCCCGb%Yr0RS!G8dJW)GW~cKYk&Hb_islSQY&#*i?&Zz zs_44-Oq2yl-H&qy@-wZYi2QZy-dLzw#i<7cm{sx{bSoE$`NWLiD_AhK$Z z^>p#iA-3c(&iHMd(W-`;$fj~;9zbVE+Zep^^?7!=%x1mH*90kiqe-$iQXyl{7-(+U z*0ZG>T}HW@NWiedf^I#UT&PCscpYmxI}6^S10RXlBdsf#+R zL!OJ-M>+#Sd=)J`TU5N-a7)IT$EQYBqE21#GIR9S4ugST5!c+fP;NLXiSKrOotqk0 z_pdAqIE}&V__Tw|g&^YbG9bZ0eHq1GqX2G~79m#YvRDMWc*Ox7o1|-oV%%jn>Wq@S zvAy1$B~BY!*Wsc7Q1(v#x>P@G>MV!g)ds(hizT~tv4uOQ{f5kKFrq`PD~NEc9(W3h zfPGZ(?JLMuzPgd=EbR!%|f- zTUs6X#W>9{N)lzDc6qJiFjuZ&2#?~H;HH$ilI$A&UOcSo1%|%Dn&Vz40>XKRR{px7 z+n%uVVjSdMQ!Jm`joz&Xi9Qt#Ja{aDA*2PQ(uTWpMFc+bA_I*zCYBAB@(c%8uMKTi zhe#Ez0qwm~Wudi^0@%Hq@IKiP+pV}qaJ|FpQWog*va4rMJQ3ZB{jBMij=&-|NA@Yu zeLJxmtc1E{Pj0+ByYFD}sYx0dl)mY{*PM{^xGD55ojK$?f63EUOCY;={sR-hdh8xS zf~wE3PRL=l%+?Y@{d_76ZVB!RUJjkorc)x8@VaRrNo zOwiq5_cV6<;_v>?Mt9P_u;i#7dvmr??dSIW+TPV|=@Fqqos$pSBTzBk9wye7VB=tu zHw|c}BgOIB;$_flr$3o)Rx9k&i7Ua3L_Mnqhxd{7*-|6 zY1;4z=~aoZNR9^^^PenVSYWhUvA*qev&1Gcr1DhV(jc@>P3^8mx?!H{k&vbB0kmE{ ztm4z5JIWEKwz6W-OQ=+LjOVl;a>+v*A^`z3@qZ650FO$TDI)y8ANUwAUwzM$Ycnv9 zaPDgmCKDNZy%M@!op1173>xukG1tag6a{xAOst5o@tS9?-x;xYUOi4N9a{f|KX-Rs zu{U``D0rFsnq!mM$?u*PMrTyGVEFS$PYAl2N?-7H-nCsAt&6RDkiI6Y|4ROR_c@!C z2;3Ib0RrsLjp!>@@NzSvN#?=)G;XC&_^S55*GI4(IvAANJb^C^eG|Tg4iZg*|FAJ- zrt3t=HcuU^_Tej2SNUA*4feNXCA|TCZ@0bTSddp4rOm#r=d(~pjG!Ma<0jBLHD8oX zjxqWWp0x0<;&%QhOLsSU?sm&S)3cB4pS$=Z0%i`+)lrwyBb{?m+v$>XNW?psv|H_U z!`BS`Tr1Sg4+=IjPuuHQ4pUNJSK=qUHd%M^WQGY-%m z0xV6voqHK)AQC9NG=C1r!xMZ@1VWuGzol;H-NH0NO9cT-e~u9ZjM-#rYg zt{XU6?=SkgG!P{5d%_KwAS=;E*}YZGiR;+pKg8=G^juFzC+Z!tHFgt5djVV{{)4(Bj2KobaY6(eQ;<}q1CmoJrXQC+tc zKhYxXBkkzrv|(_>S{5VbBRk&Cz28cM9 zNXfJ9FZ%y}!rt`c4|am8dPa$(gvLL++XZ!2)Dpguo0J-(LKrS&h)}D8tM+77A$d)~ zj+FDD)^PB@40D#vtZ^Y`iM8dL0Ojp$LsI_WDu#Do9E6MSf<0%NYwa4w5rSQ!pp0^% zcs?ellz*rXKE&mHYD^t7k9Sjd2WYYjve6K1|1mX<*!#>&j&+NPoAY*P~4WsZ`8 zL>tU1ii^wcC52F)uN~F&H7lFIVYfW1|H;G8(LMDKwem_6Eg(%Tit>yZ=a2n^O0x`t zrx}N|L$4XM8kxc$)wAoB!Rz**p%R2bVE#jUi-}(|In$Fiuh+~Si9w-r3t)4)7%V4x zff4TC0D@2Vo(%h4YOh)>(Ef$=3tkx)4EbdIT!5_ za8@R|#lA7J^PCGctfE(>fP*fxV93IlgocQEkhVtJ@*9N2@YodjI$yDrP%>@AP1@?)V-~ z_NLsAbnA7JzgQw0>b%MhYFS4@Jd$wqKC#d)I9i!#_IcE`3+BM4GBxxwSvWHEK73 z5O8pH8{K7<-7xVK9H%mLHATPx`ijitCsu4j{9bxG{Iho2cn^})o#B|pPy7&YA z>tE^l!ErCXP6kG4s>yMdgt&nB@G}-(t@d24XDXvmz?eT5yc2C4%$b1NdWaw2zFE#b z?lmdQ#%7!Z+RGv>c*s)M=4)QNw6fgx(+rGiVta@Am@OJ($It18W*ir8m{q9&subL=nmhNos3 z3YaEli^a?RyL)%7krGVJc;TX>zdfC{;H4(53oOmjK3^)qU&4W?7*0r|+UZYT$ zJqUpr^>ER=r*%*n;X2yb7cp0E-)NE_O!W`RrbR1 zD>-DWtEPaK?DR#qdKph6JWd1kJ9l(&hU4Wmk+D+@AQNq0eRg%*{70mw=kdH4MF7S& z(j`uNBY|g30n%be@k%wgTccx@u~hx3^$g}`*;mT*@F)RfY_F%|z?_by!(Y>VywlKV zVl^&AWp=9%@q}T2@X->H#eSp<^I05ZZ2aWqoXMMN!9ZSQM(ZaSDv5t+VqM2L&ZOQv zvLpgF!m3m&7Xp#+uc_Cg_mj22hX8~tdnO>RP9L4DIccU6Qr#~-^~|2ijH}A0^$?Hq zYzcklRUY2L@)ML`g0WQTK|zf1Mo_i46~<8#?prx+Raup+$h#(;NoptWqH@=$YBH^{ zm}xb*rSup}klg!ZxY-*q^^W{}|S4k082mkH;*YvK>)fa;}XGyA!*M@~hdt*7F zTg8iOq4nMI+q6Z9j$sWNo(Z;rW=_qocPOa6e_T`&8q1~p1c*AWUPRUNlHs2B&6A-% z$rzI{C_yrZ8tfJGFS5~C;<1NEd0k+2TDl4|J(4&fVc~D9xN6LD53|xWV%AKqSm)Xh z4YhV0n%R#n zh=b<(P=glp3a|io%#$_1>Q%${Y+wa59cUNE;@)AsZGSian`Js{9l!H2Mj=YJf{Ju` zq}7jm4`D^-*$7v6#Mj;Y9Th%NQrqLmMp?H1M4x_L6(M0O%Jxv@M}FcW^D)?i4||nI z7y0xW)siHzaY`jcHI&KKA*13g(OZI^(%qM`lO<#ws=!b=oF|>Oaz4MvY)vtP{M`>K z&XO@m`Wte0?hp4yDzt_&gf^jU!4_J`c1C4bf$CVX3#VLV@(0@q24I_&S*V&pw{eN_ zD4l(dB!eXMy@}(CR-2H)D*Q(9$xNZRBgn>2{#jPIKl#YMF_cj1?WBVA| z5**%;4Wu~2N)Ycj7~$7~AW9=$73cfH`dnFWQyRgV&rzOqAW792tQ^u#YUtK&IaJWe~Bh9vz9L(DH<~E?S7T zB{|R%%-}X>WpK7d{ELUP)XG6PDeH^%5!#Y<(e>xh3;_`WrgwUW*FAZPZX!$Su^k<5 zZk`%ja)sHduxew!#JadOiyXuHXY(Q=_{SrE-yI;OTy43L zjs5NB_=<3$m~j(6vsa7vgf=(Vvda{2(OU@E5X?O>pQ#i4DUKl@Tg*7xb+DRZHFfPt zC-LEh`^z^0JRD7in(Jo%snfVV$St?wdm1tn+a4lHdBbzs_9UJk9SO3`f@Vl()ssgv z&unbjMF&JX(tHVZc_;6&?i|6iHIhdY8QVEu5apuSc;)jyvHW!W)?=%GdT=DnE>-Xa zAT@XFXVoQS`Ch`_VM*%9U$}BDX8CLQR@hfT$3M^iTI5#$4o4zr?xPqN?Z_^efO=HX zoz>$JKgw`0Ytn~_<^-oxpRmJ$$sj;0R_z?-9wKet-Cpg)+2|mjU;4dR?z7orhrqBy zXrS;(u3nc`ZGO*3)A2Db45Nz9(>?yLfX4W4kT5m8@sG%?S+bRL{-m6kmQ_3DQ8}JY zOsqlIjFqy}$8*04cR{gh#*&VL=S3^N=kCqX4~3p*lSyIUdC&F5h1K@-Q>F|z7tL7M zF*O(KaxfFB4)kP`UaIx?f59Vo%Y{Z%2}^X1HAp(q=#MJ1rU&v9c_l(;SdHvu34G#I zo~Rh}%Pf1BlVd?DKqHd9N4IK%?ZUNVdYO(DHO+h2K`kI!V!2DKtVMy~^B%qD?ib<> z?j7wGx(q4S>6XB&jOyuHVl+(n61oMq4$tD-tzjDG-ZD|uN_o=_x02VnTv0;gZ#d|! z(kH)SFMGN^W8=kl5VxcXs@Hu4{{*D+`~n0F=LxXCoCr$ndsQ{6jP*-ZaC=nl1?nit zFoudQK^_z}qX~`|{n**x2s0-rH%#WPRyBU^AgnHRVH7pX*ie_|E$%AjX!N;sEQZaY zFrQlFG3@cvp_xr7g~XN(HILP*4QU|sUv+mXs!;PUGY}cT_v$QI%QUr6fPk-fihR_* zXypQ%YtePfr^?^M)hXmXn7{c<7owG!+d*X2p6EtiUy9M5C%@asqq^T&dSCxLW&T9) zR9wW>JF1kC=14Xd4|cG?J?>PNYWLf;WaJ4~fS*ibOc8|b{p7)x0eeF*(g-W;b{_;e zYG9x=V7GRL2^`U)J8!Z}WehmGcR1t(_cnyY)bKFqmZGp$bI9DUAS@Rj=+ORfaf`F**MxvtD|`T!o@)Zds_NdK%+kB zHwL>URVXE@a+B&wmkE-|Gwbzo2gbp|`wh5~{KXW1{FY1sPbCA?Hw-|5?&IK1-I8sG zVF?>srw14OR9F9Ii&NunMZp3#ib(vSJE~H-1?Thtj+6;B~VrI_jb@uT{yJ!oenm_hy#@ zhOV4(qG7-7WZLSEq_u}aiBeS*9Vu!OC@({@MWQsu;IOuTzQ(LLZsOj)Tj?!LmC`noA( z%E`G!Ua+0R51GlUYOBo0z$_Id zyH}F>8`Y<){jz1|0jW?e>r3X^JjAmj_f6-PH%9&kQlFLZ7xufRK9a_9(Gn_HxESEY z=$%f9z0dx&S*!=F8E&%`gk!Xu;umi4_xz;3O!GlBPaYD}m}lkBSUP{DqR?X;mt6Ea z>I|7uk?yNmEpe54fj*vT!3rvE9JlRHt%EBU*3NxGDb)JIn-P6yAt&Yf-A2W+k)Fxd z$l?ym8`Q;gS4#00vYLbl<3DpM#=?cM)(@!5G%(_(;tfmz_gX(`d9Z0cQP)AgwG8PBbVQ2bzXbcP-fkJQlU2S70^T6#aM1orcv)Pt z(D^`F{s;yD)mQ_P(Xfx;dQ$(*!na*A)x!D9FQ1AMK1#YC`HyLag1#bcX)#C@Ar7G` z!c*jFu40=CXb8mA%hEV^ehYq{jS5ek8*FEgB9$=CcaZE+T&Mn2Dv@?GADOME>Y%9A z2k}02pwJE6DzjwX#)t_2_(j{^`(1_IaieW5e5LbCz_quHe08^7wM*&Pm;Un!YTI`L zb)7Hq9SfwD4%xTZtwk1bg#)i|&h3&SF|l7YxDe$;qu3^l4KCepB^;_p^pfuUlwRec zHd~<^p!d9EEvrjPUo1O7X?D7ss&W}p$#9u?VV)C(cbXEoB~#I=byYAa%hwY4R+bNK zFwE|QD^T%b{1#2ReXNYg)Cf$4u~6qrDA#qH)@q+e{qyMi+oZO$GqZ>Sq*7wx>}cCg z$t`*^j1-SkCesS6QoQ~okaZb)tb*9H zXZnQ(x|2hg@Z#om62P2x^v-UmMW_mzi+Z78$vhQ~LahNk_nrW(a z0C1znW?hN1&z3xH`VtN8V#l=eTPA7cwxFkkx?5=Q?Kd9=R}b*=W|mi|kj65R7Di6) z_?w6i!NoWsKj!tT>ju63-i&xy?NDL5wy6-WBi_Cw3JHxNF!lJgG{=!W7CBd_1$%*h z4ub%F$eZ(7$p)<{B8cb6`cd*oHI~Tsn-iebPlx$#mI;X~({+Y5?&=_YS>O{__z#S? zNESlx7MhUNuPdpVYb2{XY?K)021jKd5-275`6P~FVh1HcBO(bnL-csh8cblBAsa@N z$m$MnU_00=e|WN>wGmD=hns%Z&MXlO7BOMiIPg*mpf|FHa0v7Jvw8yE# z&ed?H0zI2Lpq9%pkd9g{_)PPk%szgKWA-c#a7EG-Am{(^Bfw>n-y zRm(FrA^ytbPqM~yKJBNy#|9m~N(Wck8IvRRpDV1UE)uK}E==%8)>3oOQ$mfhVV#9% zJ|5%O<>%U9a*iD)FdB8}!65+7FAeN85MOcju96+NbQY%Ek5q$mr?V&@WUJR9yrDIh z$KGKz7-R$48mkY{fl;i5rfXh_hAM|!hTHA9YLje6vm~wV-7Tpl)@)hMp?5iCg8oj; z_|7M_33SkA#%jEDWe!@IdC!s&b_Yn!cU-NWgvAB7uUntL*-~ibScCw!@xD}OKts4U zoySYtZ<%@~u`ZOM!3xYxmW-6W2=C8xm7=>igc1vN@dM%8-wTB0CbQ6JvawLspYzCJ zdV5Um!Q8){`fbf)yOxPa`XieCR;b2Tsf=>WVNG&+Y>2d%!y=gzCBU<)C!?nz#{+J- zSZNAkx@%hdVi95#xHuzQ)`D#PnH8xNS ze$HpBsZ{EY(_B^RaDk?P&a`nMs0(fzwixc)bvyXw_!?~D!~H(?E3Anr_YIjG*t9fE z&-XW$+1Vwr>&cUQO4|j9oX5ZQS}yN}g1@JDH7Md)yKP)sx|MEf?u#H%D@tWF4yk(ox{mQJD zql(b^WN-0!jJ_HK($;&u+Mz)A+AZ4my7z>#!mra?vC_PsQA}~-u4PQFd)6pDjr}hD zjZ48<3&I?a^o=JNn7C5dwdEdoTWx0VKPmPxDMZ~@R+L8USAG@ly!~Z>yje$VDyQz| zRo^px%EkELP2t@$3ODJ{_K>HO;EGtpDX%-h#pT0N~JK!xmwGSxJ_o$}HORnkC_ z`~Jc1BI>&jKXmDLX_sgNhcMkDX-#pN^9227(^zzbxPI_pIj99bANM<`Zc^70#aGOk zOeRkBoFwP>0{9#_NqsL)ZT+<8a!7xCwIIEN{0hgqVtpdGv85v47Kke78W*R-xGYkQ zRKcuLuv`VKfki-PNTYe10~!6(+A6F$?D}a*kv$w?d<(XE_FNtD)S)fUq2XhDb)2Pg zIF9+|p|ZecsPOwWhKTjqLAo~+dIbsQN4Qd&CH@+B_eCqx&4F?E{Xr(Y3Szv9vmbjObRXU>d)=_y!aN*U>XzFI<~5o-wKT0a-s0?mfnd_uU@`Y*pJ4#ET#{ zd*FqL2PVFR#`KhlR}3&6VV_f8lvCI7r)Tr{zEyLH`_$r8oCnNJlK9pXEW*@B>eOn< z_!8__3{!s^ziSE2MfmYN+U4}M|3l69hXlD$tUmF}z9G5Ub~>VlGV3JUBZRfaP%}F% zKC$7;AV73F^CfykDb+P%fn1Yb?6IG|k0An)TUvkdb|^_f_`7So>t%^y^VvuL@h6GP znzy1|%i$Itp~NH!?N*CxtuVD!EU?;TO6i+)TkkW<_mwQDjZx_7WJEL8{ml-job|Br zp|_5@shmH)Ho?4~(O&O&Pm(QFBp3jGdIY1edoy!G^LbY_z?v=)xcODdW?n^4w6 zf+dKnP(qF|)Q`+%giIq#=J)eBt+$e{_sGdYC*nJeell)eE~cIH_cLO=HQ@ zs#_sRONi}N!M}shKcB{;6`r+Cp%Sk)%y%tsWv60JXJwxKnLdC_ZSkcz#Wr_Nh-ki! z4nIIGUQ*|5HWgEJ_2MJn_vMx5%&h%2`nv4b1O?MPbliA)CfuN|`Kj&WXUg>85OV5M@zkn>X{8 z#Md5)(Dw)di?q_M8KA56jo%Win77)R+uq9HI9=cVYTI|*Es{!WwKSt&&jah0HMjvZ zLGq8XPU$Ubbmmzsfl;0R2a3x+GJmuL@oy0Sz^zv={e?p=?8dUvdD}BKUI=M(ITfqL z@wC4?$TRhpM3VVr7bI>4@6SZ%E8fYhK!lK$yEvPDEs3_gEPdsBnC`ye!;(S_q#A6a zQWpG{h&&K(uB+rel^uMr2fqG*R9`zT;w6&YHlxgHa;4d-$h6tQ(c1-Z15cNR*Fnfl z2p?Gd8-mLhBX*|Uqf$rx^+KgxfPAsu&_4u118gpyQ}X*L;d=1Mq`V)Uc< zX|A@0_LVB}E}^uf-2N2YCT#rZ=S(VEb(X>o^XwarUV(s$RE}3HxO0G}x{K;>H-hb` zF(VRPubIe2niZXPw~U+fwZyM~%`+}1bSSkP4pQ!{Af_!G!9IOl4X0)RSU6B0`ez$r zU6|c%vf}?TxpsW%_~_jrR%mYq7cx5MF+uat>hz+r+Rs?6^TuNn(!e3hlx zcLxu#eEs_Bbwn~{BDMl+Yz=58Su_Tt3iDj&D?bdH-b{PKI#tO+22k}0u2=sJbC!HV zPV&l9aWdRhLgorNb8&V^10{>#-4MYxtmX9x-qw>tG>#RJFm!c`nD`_9b<4wZdzHy& zZT2k)=VI>~7+}(XJJH-9MYpS-l$emq^EG2MQbwSk*)>$({k3OPjHe{NLrrlMPcJ^D zQrLZEGB3}&n0uT*1Xxyxvpr}NI|!dxX+-LM@=Z7{J3=G>_IZTr@fos|Mw;Ln(d0?( zsZzpBGm^;@%oo4M?MEo-8KjeJg|i)T&(X$aviDAkPLi9V52Z25@66p6Ybk7Oq3Wa~xwO`_b6&mx9ME~jL!9fNspQRUY&M26qW-9Qb|&tM3N8kUWwC5zLL zlnm(Oz)J44as=}pF)bmzu^Ev>%ECZ8Wh9mSmBIt=?VF#NPIIs|{fc=!-J*`S zbvvV{c0T0~KMFlLLS70ltY(w+G3F`<hR%jV}W5M>%|{phse(z2bx)yP5ASCgqH z$h*3$KyeqWT!RHysXFg!0gi^NEU$G|hCs~!*xfD2ulGa_&Qo_ka&LCVy; zwLD@vWOL7A8e^&titzRyQ9q{*$V61G+t(8(PNT*r^(oZ zlDTk!?{I+4NA~p`n2W3o9lurv#vlpO#@)S#`TF8GmgczZW@1K1(SxS9=$0SM$J@~2 zSB*sMnPn(>j=c?xS)_b5G7#kv8du%3U|%U@u9pnNO+*jXwmRG_jG#GFdR1dyYOk@M zw5DqK7x}q0>%OUod0$o`M3sku9y?oJYbAeS{1FbwK<{{B(HBT%Ac(2`H6$V_j6~>*p$eNDYLY+{=I+R-Qn8BC@`6+Iiv@mfuYo&~4M z)^(SFc$VX@ovG(JMad<>N0?(^kq82YFhV?~!AiDzs+WVBn)@en7Pw`leiW zr?pRRwNmxWYsP-(4|AJfLLoH>$Vf`NM1v#AIBTRI2rlJ$Ee;T+$_SA~JH8<@!O$UV_;0+; zu*uAG;Y-hlwDIi2XBmso<*k3C0!;~DPFe|CKE#7k-|HX^+`jUYH_J}xhJX^dsmAqz zr$Bp?chMOabDVG|{54{+i{F;$F&Os1*JE>VCK;R}XDx(|7EB%3U2<&Itu15Ir4jyj z1(B%gmZb5vEDQIEakt6ku7QJDgDcSP5_F?2VxE-lxlf*-7sA<({65F~;e8J#7LFZI z=GU+6w9tv9LGsX9HQ8R=kUS)07aI%$sikYb**0~i>JYZH1obqmGmbW~(Th<;cSnv&tCFS|>GHgDMde~7ECt~c5 zX?_sAzDUm-7epq5Yu=`Ymk46wZskXbt()s367~^Rxl_Rlrl#RhVOaNs@7A;&p`g;H z7o{&SnQBL{A#UKjVX)Kogss)0-NGc*&adR%D}(DlQbs(*p7KcV$=g>0ay-n+KmA5O z%2XY{02g!xScy3TAsg+38G2oxxAbMLWCm<2Oxw!rc4QH)E1T5nGATRcCMo$0Zu$mI zUnTxRBIbT}ODjzCxxv4zB$&#fIu4{|cRSo$w()&kyuBBFKd~h<>oeK=kuvygS`~xvOxhf@i zru1w2m$2EA;3L=bCq6Xa?%A(Fwc%KE-*5|iP}lGJHFj&9u2`lzRFPCx8w)<*801B) zs)12p%%=B!(JnaN!Q`Uyoji#WuH}@?y!UGK1!?AyDM9i-$`eIKcaim1;fwf!Zq9Ga zPxkB*nmWzmZ{Me;0r3)HD2Lk`LcBH`+1AN^edg*foX=h+N)cNTEB3C%9t2z7p-FDm z%2~b1qcD2%+WzWM$EhDoq(1GvdUGK^WRzz8dLEX6?1lzGWyftcSu?k6V5wEzb9Bg0 z_H9HU3bU_osq9>J-GBvwPr8^;t0n0b{F+fv7%x{M{?_SyG{Bg1Nq913JcTs01W%qy zLho#HmZ#E1ohw<><6wulM%clZ&wfR9L;_nD!dtQu{Nw5N#R`hnOsb-6u2Td1gGO%4 zJxvAh{g|%<3+wwg?V)V}hg>y{X@qUD*41yW@#zod6Ls$8Xj|w2z@yp+!QXBH^$f53vwcltWI)1RP^@}U~eCgQGd8*Jq?mI|w+t>L}*gB3t5NkU-E*@8t|p zB*Vu9V8XMEM3cgL;yz@5VmB^B>JR%g=G0L4Om1KHrOH1JZaLZ8plv>;$}bno@n#;e z#=}8ra4i(`{zL94iXdlSj-$?d9BRoP+_yQJ$^$>g$rhu0$1Uc|U5`MdW6XVTVOqD> z=-av6>&XEp-VA}UFnHywZ0hNl1o!nX&RuZVIAkAxJ&GUrqs~^Li@9|=_tv>amxo5#&OMJQDi4Ae}%@w9HaMgR)4Kj z8}&I6(?i80(jwDs%!BtK6f_b5qmhgFYTEqLHh{kike^*bOR0Q!VgCDFmTyt|Mtx0@ z_PaPW@L}=UaJe@*I*lgBNH1bnI1aa-JX)wM3m6{`DKH}1f~_ClIeqg|8^4HPzBT2y zw_Y0{Y!LxC+^*ZZvM@H1e!<#uTFTYa>V;hH)lxI${z@Mhbn5T{3 zTj_td^I5Bm4*Uu+OVWFD!26qdDmJ!?nX%%z42{0QII7XY^Xk+bN^)}P`&Y@;J-ZS6 zk}zJR=#OtI9XqsrKB^3owL~B+$t>0*U{PIfG%@ddlFMqP@-hEZaIa6E{JXdYp_#D= zXl^hNju|yv82Q&vptYfA`R3?Lq0*@RSYAOnE3Zb{e5Aaoa3=D!o@gQeU^FAL^0|Ae z&u^5UuX633cRbG7W^{tIK4m!wkX@1L=9-gzxmI9?X=+eWMn}|bTzY90-6LLlvkx>n z)vyT50|=v%)f8t3Dq5*O?}D_;H+X=v0kw@U#jJHEsLD0=V-E~+_Fr{j(^72b){Ui* z!$5uaTeB^e+c;E~#Yqp@3(4N|@~?<3cdCe;aPciD=e-fhtwrv272Z_o$_^Ne@!L~F z8xO)xJcfQVFQ&Nw-mSjQP1uAyct0pTWD5-(mO44;>jL`^=DI)5Q1IsX8dU-`bi0w%n$=z< ziSTCRDUDx9LGjV*ak%zNUiYaYX|(knO*c4?pU)0bdIy}BZVGp>4e782QBBRTv+=R| z7<%Y_9NR&pvyKTgOjju-FCsDooja|M+55i;7?f^Wa+;Cl2~#$*Rm-C5H%__nox+z+ zZ-ixG=EJ8nXiqO>X1)P12hf}Y-9E5;;-<};b@sS5 zvm6FtB&qET$`M~Fw$veLI-qY}OE5;7et0tab%4qwUhK?{vEe>&SzupY!5rr(20VI8 za=#dFt@|l3Ik2vtdFVx2DD53AY?Ayu5}3g{L^ihaV|bN4)-VKU-TZ;Oto2duc-=@+xqNr)KIy#CG8a~#1{axa-pPtfo0Jo*!yCJ=ay0Ico_Zxnvcai{Hf3Zf72A6oMP9FC=`V z>)yw3b@yj?9l0+8Imd{+i+11IP~(Bxsoz1A7Xew)Im1CevM#S zH&J2xl_(uApH}-BlMwN*DN_la>cvO9eBbdkn0^toMD(_j`|I~KCbTLfVw4%vsSgjx zl8a}Kg9(&<{FdB5-I!rXA9R!Hg+t5m9AU;N{bD{i?g*-N1rM@Ft z(WyCwQ8{o|TZ}BQUQ${XxuVJCRj))*vQDj+yh3@AdSZOmXD)>eGrDQDeR_R-r2 zNopbp9H%!f=w9H6T~?X<24UW}FDc9W)j4#Ka+9q1wzF?w)LoqJPQISw zU|X<*mS*+X`TcPfwP>|`sWR4jiG*NT{1c0{T0Rh@8=X$onS=HTNX>W>;Uc=P(N;2P=$RtlfYp4a-vGI3+MCSKb=mcK%7vr7D=RM3Qh z`q-?}8r%JsgPvk$pF)(BxXy3dU_lMm4ZTL2!cUX}bOY{3ztnmIzT*MzS>g@mBf${^Gunh&?)HNh|JtX1V*Bw_b#c0(<&ji^$Ma4Vjtvi_^_#3ZiGYcp48)e zyqjB>f?P<%O&rGG3{#(IrwaDiMOdBT==}sJ#aH`>zI5b|qLpR=-zs$ChV8ww;MpAB z!)3O4!_rWroua-cgQM}(=+RQf4C!uD1*Z64u&-Aqxsf5RePfN9RIiS2eUZwRWV2 zKoZV!K_r+TP=$r5O|4CAj6R`4F{(TeB{Y<99*72-j{)@Xmp(m&Hz6huq`<<-!^z3P z3FctqfV|}3c*%syu4H2(Y3OK5%_#Yri-Yr@Z~x0A0VN;w9Tviukev_G2Dtfoq2>5z zP+L=@{&VEy;O66olKap24~&N&s-pkDF)-IZHUCcx`k9~a4?8Hv_h$?!2I2fCM#7f@ z5C*^v{?`c<{f~fLe^26saQ=}jG+pQl{!D_CgBL2~|Ihfp{x~?ez`W31@CU}t!vV#B z|7FMt;s0y(U?_ioPUhz4`O6_UALK7PE(p&b2|^i$K>mZJf8s+24+rEghY)`7Uk zJb%&7%LC#2GeKSm_&nA5FE}`Oc_Dw5gpd30 zr1`l2W{VH}?}b3u|37u&ExP&w`C4MnZ t4oPk>k2qME`u}h8fm&D?)xpuw-qF?G)C?7x0UswH>WdffQYzA@{|9ZYR;~a5 diff --git a/doc/tutorial/tutorial.tex b/doc/tutorial/tutorial.tex index cef3632..d1ba4fd 100644 --- a/doc/tutorial/tutorial.tex +++ b/doc/tutorial/tutorial.tex @@ -56,30 +56,37 @@ point of view, those versions differ only in the transport layer used to communi (v1 uses SCSI passthru commands, while v2 uses raw USB). \paragraph{} -Before continuing, the following dependencies are required: +Before continuing, the following dependencies must be met: \begin{itemize} \item libusb-1.0 -\item libsg2 +\item libsgutils2 (optionnal) \end{itemize} +\paragraph{} +STLINK should run on any system meeting the above constraints. + \paragraph{} The STLINK software source code is retrieved using:\\ \begin{small} \begin{lstlisting}[frame=tb] -git clone https://github.com/texane/stlink stlink.git +$> git clone https://github.com/texane/stlink stlink.git \end{lstlisting} \end{small} \paragraph{} -The GDB server is called st-util and is built using:\\ +Everything can be built from the top directory:\\ \begin{small} \begin{lstlisting}[frame=tb] -$> cd stlink.git; -$> make ; -$> cd gdbserver ; -$> make ; +$> cd stlink.git +$> make CONFIG_USE_LIBSG=0 \end{lstlisting} \end{small} +It includes: +\begin{itemize} +\item a communication library (stlink.git/libstlink.a), +\item a GDB server (stlink.git/gdbserver/st-util), +\item a flash manipulation tool (stlink.git/flash/flash). +\end{itemize} \newpage @@ -88,8 +95,9 @@ $> make ; A simple LED blinking example is provided in the example directory. It is built using:\\ \begin{small} \begin{lstlisting}[frame=tb] +# update the make option accordingly to your architecture cd stlink.git/example/blink ; -PATH=$TOOLCHAIN_PATH/bin:$PATH make ; +PATH=$TOOLCHAIN_PATH/bin:$PATH make CONFIG_STM32L_DISCOVERY=1; \end{lstlisting} \end{small} @@ -102,7 +110,8 @@ are using, you must run one of the 2 commands:\\ $> sudo ./st-util /dev/sg2 # STM32L discovery kit -$> sudo ./st-util +# 2 dummy command line arguments needed, will be fixed soon +$> sudo ./st-util fu bar \end{lstlisting} \end{small} @@ -144,6 +153,31 @@ $> continue The board BLUE and GREEN leds should be blinking (those leds are near the user and reset buttons). +\newpage +\section{Reading and writing to flash} +\paragraph{} +Flash memory reading and writing is done by a separate tool. A binary running in flash is assumed to +be linked against address 0x8000000. The flash tool is then used as shown below:\\ +\begin{small} +\begin{lstlisting}[frame=tb] +# change to the flash tool directory +$> cd stlink.git/flash ; + +# stlinkv1 command to read 4096 from flash into out.bin +$> ./flash read /dev/sg2 out.bin 0x8000000 4096 + +# stlinkv2 command +$> ./flash read out.bin 0x8000000 4096 + +# stlinkv1 command to write the file in.bin into flash +$> ./flash write /dev/sg2 in.bin 0x8000000 + +# stlinkv2 command +$> ./flash write in.bin 0x8000000 +\end{lstlisting} +\end{small} + + \newpage \section{Notes} @@ -187,6 +221,17 @@ $> make \end{lstlisting} \end{small} +\subsection{STM32VL support} +\paragraph{} +It seems support for STM32VL is quite broken. If it does not work, try build STLINK using libsg: +\begin{small} +\begin{lstlisting}[frame=tb] +$> cd stlink.git +$> make CONFIG_USE_LIBSG=1 +\end{lstlisting} +\end{small} + + \newpage \section{References} \begin{itemize} diff --git a/example/blink/Makefile b/example/blink/Makefile index 0f4f712..e5f7045 100644 --- a/example/blink/Makefile +++ b/example/blink/Makefile @@ -4,8 +4,15 @@ BIN_IMAGE=blink.bin CC=arm-none-eabi-gcc OBJCOPY=arm-none-eabi-objcopy -CFLAGS=-O2 -mlittle-endian -mthumb -g -CFLAGS+=-mcpu=cortex-m3 -ffreestanding -nostdlib -nostdinc +CFLAGS=-g -O2 -mlittle-endian -mthumb +ifeq ($(CONFIG_STM32L_DISCOVERY), 1) + CFLAGS+=-mcpu=cortex-m3 -DCONFIG_STM32L_DISCOVERY +else ifeq ($(CONFIG_STM32VL_DISCOVERY), 1) + CFLAGS+=-mcpu=cortex-m3 -DCONFIG_STM32VL_DISCOVERY=1 +else ifeq ($(CONFIG_STM32F4_DISCOVERY), 1) + CFLAGS+=-mcpu=cortex-m4 -DCONFIG_STM32F4_DISCOVERY=1 +endif + CFLAGS+=-ffreestanding -nostdlib -nostdinc # to run from SRAM CFLAGS+=-Wl,-Ttext,0x20000000 -Wl,-e,0x20000000 diff --git a/example/blink/main.c b/example/blink/main.c index 929e3b9..0889b81 100644 --- a/example/blink/main.c +++ b/example/blink/main.c @@ -5,10 +5,6 @@ typedef unsigned int uint32_t; /* hardware configuration */ -#define CONFIG_STM32L_DISCOVERY 1 -#define CONFIG_STM32VL_DISCOVERY 0 - - #if CONFIG_STM32VL_DISCOVERY # define GPIOC 0x40011000 /* port C */ @@ -58,6 +54,36 @@ static inline void switch_leds_off(void) *(volatile uint32_t*)GPIOB_ODR = 0; } +#elif CONFIG_STM32F4_DISCOVERY + +#define GPIOD 0x40020C00 /* port D */ +# define GPIOD_MODER (GPIOD + 0x00) /* port mode register */ +# define GPIOD_ODR (GPIOD + 0x14) /* port output data register */ + +# define LED_GREEN (1 << 12) /* port B, pin 12 */ +# define LED_ORANGE (1 << 13) /* port B, pin 13 */ +# define LED_RED (1 << 14) /* port B, pin 14 */ +# define LED_BLUE (1 << 15) /* port B, pin 15 */ + +static inline void setup_leds(void) +{ + *(volatile uint32_t*)GPIOD_MODER |= (1 << (12 * 2)) | (1 << (13 * 2)) | + (1 << (13 * 2)) | (1 << (14 * 2)) | (1 << (15 * 2)); +} + + +static inline void switch_leds_on(void) +{ + *(volatile uint32_t*)GPIOD_ODR = LED_GREEN | LED_ORANGE | LED_RED | LED_BLUE; +} + +static inline void switch_leds_off(void) +{ + *(volatile uint32_t*)GPIOD_ODR = 0; +} + +#else +#error "Architecture must be defined!" #endif /* otherwise, error */ diff --git a/example/blink_flash/Makefile b/example/blink_flash/Makefile new file mode 100644 index 0000000..7776471 --- /dev/null +++ b/example/blink_flash/Makefile @@ -0,0 +1,36 @@ +EXECUTABLE=blink.elf +BIN_IMAGE=blink.bin + +CC=arm-none-eabi-gcc +OBJCOPY=arm-none-eabi-objcopy + +CFLAGS=-O2 -mlittle-endian -mthumb + +CFLAGS=-g -O2 -mlittle-endian -mthumb +ifeq ($(CONFIG_STM32L_DISCOVERY), 1) + CFLAGS+=-mcpu=cortex-m3 -DCONFIG_STM32L_DISCOVERY +else ifeq ($(CONFIG_STM32VL_DISCOVERY), 1) + CFLAGS+=-mcpu=cortex-m3 -DCONFIG_STM32VL_DISCOVERY=1 +else ifeq ($(CONFIG_STM32F4_DISCOVERY), 1) + CFLAGS+=-mcpu=cortex-m4 -DCONFIG_STM32F4_DISCOVERY=1 +else +$(error "must specify CONFIG_ for board!") +endif + CFLAGS+=-ffreestanding -nostdlib -nostdinc + +# to run from FLASH +CFLAGS+=-Wl,-T,stm32_flash.ld + +all: $(BIN_IMAGE) + +$(BIN_IMAGE): $(EXECUTABLE) + $(OBJCOPY) -O binary $^ $@ + +$(EXECUTABLE): main.c startup_stm32l1xx_md.s + $(CC) $(CFLAGS) $^ -o $@ + +clean: + rm -rf $(EXECUTABLE) + rm -rf $(BIN_IMAGE) + +.PHONY: all clean diff --git a/example/blink_flash/main.c b/example/blink_flash/main.c new file mode 100644 index 0000000..e93fd72 --- /dev/null +++ b/example/blink_flash/main.c @@ -0,0 +1,82 @@ +/* missing type */ + +typedef unsigned int uint32_t; + + +/* hardware configuration */ + +#define CONFIG_STM32L_DISCOVERY 1 +#define CONFIG_STM32VL_DISCOVERY 0 + + +#if CONFIG_STM32VL_DISCOVERY + +# define GPIOC 0x40011000 /* port C */ +# define GPIOC_CRH (GPIOC + 0x04) /* port configuration register high */ +# define GPIOC_ODR (GPIOC + 0x0c) /* port output data register */ + +# define LED_BLUE (1 << 8) /* port C, pin 8 */ +# define LED_GREEN (1 << 9) /* port C, pin 9 */ + +static inline void setup_leds(void) +{ + *(volatile uint32_t*)GPIOC_CRH = 0x44444411; +} + +static inline void switch_leds_on(void) +{ + *(volatile uint32_t*)GPIOC_ODR = LED_BLUE | LED_GREEN; +} + +static inline void switch_leds_off(void) +{ + *(volatile uint32_t*)GPIOC_ODR = 0; +} + +#elif CONFIG_STM32L_DISCOVERY + +# define GPIOB 0x40020400 /* port B */ +# define GPIOB_MODER (GPIOB + 0x00) /* port mode register */ +# define GPIOB_ODR (GPIOB + 0x14) /* port output data register */ + +# define LED_BLUE (1 << 6) /* port B, pin 6 */ +# define LED_GREEN (1 << 7) /* port B, pin 7 */ + +static inline void setup_leds(void) +{ + /* configure port 6 and 7 as output */ + *(volatile uint32_t*)GPIOB_MODER |= (1 << (7 * 2)) | (1 << (6 * 2)); +} + +static inline void switch_leds_on(void) +{ + *(volatile uint32_t*)GPIOB_ODR = LED_BLUE | LED_GREEN; +} + +static inline void switch_leds_off(void) +{ + *(volatile uint32_t*)GPIOB_ODR = 0; +} + +#endif /* otherwise, error */ + + +#define delay() \ +do { \ + register unsigned int i; \ + for (i = 0; i < 1000000; ++i) \ + __asm__ __volatile__ ("nop\n\t":::"memory"); \ +} while (0) + +void main(void) +{ + setup_leds(); + + while (1) + { + switch_leds_on(); + delay(); + switch_leds_off(); + delay(); + } +} diff --git a/example/blink_flash/startup_stm32l1xx_md.s b/example/blink_flash/startup_stm32l1xx_md.s new file mode 100644 index 0000000..4ec8203 --- /dev/null +++ b/example/blink_flash/startup_stm32l1xx_md.s @@ -0,0 +1,366 @@ +/** + ****************************************************************************** + * @file startup_stm32l1xx_md.s + * @author MCD Application Team + * @version V1.0.0 + * @date 31-December-2010 + * @brief STM32L1xx Ultra Low Power Medium-density Devices vector table for + * RIDE7 toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ******************************************************************************* + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ ******************************************************************************* + */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF108F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss +/* Call the clock system intitialization function.*/ +/* let main do the system initialization */ +/* bl SystemInit */ +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/******************************************************************************* +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_STAMP_IRQHandler + .word RTC_WKUP_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_IRQHandler + .word USB_HP_IRQHandler + .word USB_LP_IRQHandler + .word DAC_IRQHandler + .word COMP_IRQHandler + .word EXTI9_5_IRQHandler + .word LCD_IRQHandler + .word TIM9_IRQHandler + .word TIM10_IRQHandler + .word TIM11_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTC_Alarm_IRQHandler + .word USB_FS_WKUP_IRQHandler + .word TIM6_IRQHandler + .word TIM7_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x108. This is for boot in RAM mode for + STM32L15x ULtra Low Power Medium-density devices. */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_STAMP_IRQHandler + .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak USB_HP_IRQHandler + .thumb_set USB_HP_IRQHandler,Default_Handler + + .weak USB_LP_IRQHandler + .thumb_set USB_LP_IRQHandler,Default_Handler + + .weak DAC_IRQHandler + .thumb_set DAC_IRQHandler,Default_Handler + + .weak COMP_IRQHandler + .thumb_set COMP_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak LCD_IRQHandler + .thumb_set LCD_IRQHandler,Default_Handler + + .weak TIM9_IRQHandler + .thumb_set TIM9_IRQHandler,Default_Handler + + .weak TIM10_IRQHandler + .thumb_set TIM10_IRQHandler,Default_Handler + + .weak TIM11_IRQHandler + .thumb_set TIM11_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak USB_FS_WKUP_IRQHandler + .thumb_set USB_FS_WKUP_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + +/******************** (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE***/ + diff --git a/example/blink_flash/stm32_flash.ld b/example/blink_flash/stm32_flash.ld new file mode 100644 index 0000000..146b16e --- /dev/null +++ b/example/blink_flash/stm32_flash.ld @@ -0,0 +1,173 @@ +/* +***************************************************************************** +** +** File : stm32_flash.ld +** +** Abstract : Linker script for STM32L152RB Device with +** 128KByte FLASH, 16KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +** Environment : Atollic TrueSTUDIO(R) +** +** Distribution: The file is distributed “as is,” without any warranty +** of any kind. +** +** (c)Copyright Atollic AB. +** You may use this file as-is or modify it according to the needs of your +** project. Distribution of this file (unmodified or modified) is not +** permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the +** rights to distribute the assembled, compiled & linked contents of this +** file as part of an application binary file, provided that it is built +** using the Atollic TrueSTUDIO(R) toolchain. +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20004000; /* end of 16K RAM */ + +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0; /* required amount of heap */ +_Min_Stack_Size = 0x80; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 128K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 16K + MEMORY_B1 (rx) : ORIGIN = 0x60000000, LENGTH = 0K + RW_EEPROM (rw) : ORIGIN = 0x08080000, LENGTH = 32 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(.fini_array*)) + KEEP (*(SORT(.fini_array.*))) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = .; + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : AT ( _sidata ) + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(4); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(4); + } >RAM + + /* MEMORY_bank1 section, code must be located here explicitly */ + /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */ + .memory_b1_text : + { + *(.mb1text) /* .mb1text sections (code) */ + *(.mb1text*) /* .mb1text* sections (code) */ + *(.mb1rodata) /* read-only data (constants) */ + *(.mb1rodata*) + } >MEMORY_B1 + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } + + .DataFlash (NOLOAD): {*(.DataFlash)} >RW_EEPROM +} diff --git a/example/blink_flash/system_stm32l1xx.c b/example/blink_flash/system_stm32l1xx.c new file mode 100644 index 0000000..6deab32 --- /dev/null +++ b/example/blink_flash/system_stm32l1xx.c @@ -0,0 +1,367 @@ +/** + ****************************************************************************** + * @file system_stm32l1xx.c + * @author MCD Application Team + * @version V1.0.0 + * @date 2-June-2011 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32L1xx Ultra + * Low Medium-density devices, and is generated by the clock configuration + * tool "STM32L1xx_Clock_Configuration_V1.0.0.xls". + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32l1xx_md.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the MSI (2.1 MHz Range) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32l1xx_md.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and MSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define + * in "stm32l1xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + * System Clock Configuration + *============================================================================= + * System clock source | HSI + *----------------------------------------------------------------------------- + * SYSCLK | 16000000 Hz + *----------------------------------------------------------------------------- + * HCLK | 16000000 Hz + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 1 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 1 + *----------------------------------------------------------------------------- + * HSE Frequency | 8000000 Hz + *----------------------------------------------------------------------------- + * PLL DIV | Not Used + *----------------------------------------------------------------------------- + * PLL MUL | Not Used + *----------------------------------------------------------------------------- + * VDD | 3.3 V + *----------------------------------------------------------------------------- + * Vcore | 1.8 V (Range 1) + *----------------------------------------------------------------------------- + * Flash Latency | 0 WS + *----------------------------------------------------------------------------- + * Require 48MHz for USB clock | Disabled + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32l1xx_system + * @{ + */ + +/** @addtogroup STM32L1xx_System_Private_Includes + * @{ + */ + +#include "stm32l1xx.h" + +/** + * @} + */ + +/** @addtogroup STM32L1xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32L1xx_System_Private_Defines + * @{ + */ +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +/** + * @} + */ + +/** @addtogroup STM32L1xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32L1xx_System_Private_Variables + * @{ + */ +uint32_t SystemCoreClock = 16000000; +__I uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48}; +__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32L1xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); + +/** + * @} + */ + +/** @addtogroup STM32L1xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemCoreClock variable. + * @param None + * @retval None + */ +void SystemInit (void) +{ + /*!< Set MSION bit */ + RCC->CR |= (uint32_t)0x00000100; + + /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */ + RCC->CFGR &= (uint32_t)0x88FFC00C; + + /*!< Reset HSION, HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xEEFEFFFE; + + /*!< Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */ + RCC->CFGR &= (uint32_t)0xFF02FFFF; + + /*!< Disable all interrupts */ + RCC->CIR = 0x00000000; + + /* Configure the System clock frequency, AHB/APBx prescalers and Flash settings */ + SetSysClock(); + +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ +#endif +} + +/** + * @brief Update SystemCoreClock according to Clock Register Values + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI + * value as defined by the MSI range. + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value + * 8 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* MSI used as system clock */ + msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13; + SystemCoreClock = (32768 * (1 << (msirange + 1))); + break; + case 0x04: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + case 0x08: /* HSE used as system clock */ + SystemCoreClock = HSE_VALUE; + break; + case 0x0C: /* PLL used as system clock */ + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmul = RCC->CFGR & RCC_CFGR_PLLMUL; + plldiv = RCC->CFGR & RCC_CFGR_PLLDIV; + pllmul = PLLMulTable[(pllmul >> 18)]; + plldiv = (plldiv >> 22) + 1; + + pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + + if (pllsource == 0x00) + { + /* HSI oscillator clock selected as PLL clock entry */ + SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv); + } + else + { + /* HSE selected as PLL clock entry */ + SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv); + } + break; + default: /* MSI used as system clock */ + msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13; + SystemCoreClock = (32768 * (1 << (msirange + 1))); + break; + } + /* Compute HCLK clock frequency --------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock frequency, AHB/APBx prescalers and Flash + * settings. + * @note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ + __IO uint32_t StartUpCounter = 0, HSIStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSI */ + RCC->CR |= ((uint32_t)RCC_CR_HSION); + + /* Wait till HSI is ready and if Time out is reached exit */ + do + { + HSIStatus = RCC->CR & RCC_CR_HSIRDY; + } while((HSIStatus == 0) && (StartUpCounter != HSI_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSIRDY) != RESET) + { + HSIStatus = (uint32_t)0x01; + } + else + { + HSIStatus = (uint32_t)0x00; + } + + if (HSIStatus == (uint32_t)0x01) + { + /* Flash 0 wait state */ + FLASH->ACR &= ~FLASH_ACR_LATENCY; + + /* Disable Prefetch Buffer */ + FLASH->ACR &= ~FLASH_ACR_PRFTEN; + + /* Disable 64-bit access */ + FLASH->ACR &= ~FLASH_ACR_ACC64; + + + /* Power enable */ + RCC->APB1ENR |= RCC_APB1ENR_PWREN; + + /* Select the Voltage Range 1 (1.8 V) */ + PWR->CR = PWR_CR_VOS_0; + + + /* Wait Until the Voltage Regulator is ready */ + while((PWR->CSR & PWR_CSR_VOSF) != RESET) + { + } + + /* HCLK = SYSCLK /1*/ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + /* PCLK2 = HCLK /1*/ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK /1*/ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + + /* Select HSI as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSI; + + /* Wait till HSI is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_HSI) + { + } + } + else + { + /* If HSI fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/flash/Makefile b/flash/Makefile index fe0dff7..8a30b41 100644 --- a/flash/Makefile +++ b/flash/Makefile @@ -1,12 +1,27 @@ +# make ... for both libusb and libsg +# +# make CONFIG_USE_LIBSG=0 ... +# for just libusb +# +CC=gcc + CFLAGS+=-g -CFLAGS+=-DCONFIG_USE_LIBUSB -CFLAGS+=-DCONFIG_USE_LIBSG +CFLAGS+=-DCONFIG_USE_LIBUSB=1 CFLAGS+=-DDEBUG CFLAGS+=-std=gnu99 CFLAGS+=-Wall -Wextra CFLAGS+=-I../src -LDFLAGS=-L.. -lstlink -lusb-1.0 -lsgutils2 +LDFLAGS=-lusb-1.0 -L.. -lstlink + +ifeq ($(CONFIG_USE_LIBSG),) +CONFIG_USE_LIBSG=1 +endif + +ifneq ($(CONFIG_USE_LIBSG),0) +CFLAGS+=-DCONFIG_USE_LIBSG=1 +LDFLAGS+=-lsgutils2 +endif SRCS=main.c OBJS=$(SRCS:.c=.o) diff --git a/flash/main.c b/flash/main.c index c8b15e0..e474174 100644 --- a/flash/main.c +++ b/flash/main.c @@ -3,46 +3,133 @@ #include #include +#include +#include #include "stlink-common.h" +struct opts +{ + unsigned int do_read; + const char* devname; + const char* filename; + stm32_addr_t addr; + size_t size; +}; + +static void usage(void) +{ + puts("stlinkv1 command line: ./flash {read|write} /dev/sgX path addr "); + puts("stlinkv2 command line: ./flash {read|write} path addr "); +} + +static int get_opts(struct opts* o, int ac, char** av) +{ + /* stlinkv1 command line: ./flash {read|write} /dev/sgX path addr */ + /* stlinkv2 command line: ./flash {read|write} path addr */ + + unsigned int i = 0; + + if (ac < 3) return -1; + + /* stlinkv2 */ + o->devname = NULL; + + if (strcmp(av[0], "read") == 0) + { + o->do_read = 1; + + /* stlinkv1 mode */ + if (ac == 5) + { + o->devname = av[1]; + i = 1; + } + + o->size = strtoul(av[i + 3], NULL, 10); + } + else if (strcmp(av[0], "write") == 0) + { + o->do_read = 0; + + /* stlinkv1 mode */ + if (ac == 4) + { + o->devname = av[1]; + i = 1; + } + } + else + { + return -1; + } + + o->filename = av[i + 1]; + o->addr = strtoul(av[i + 2], NULL, 16); + + return 0; +} + + int main(int ac, char** av) { - /* stlinkv1 command line: ./flash /dev/sgX path addr */ - /* stlinkv2 command line: ./flash path addr */ - stlink_t* sl = NULL; - stm32_addr_t addr; - const char* path; - int err; + struct opts o; + int err = -1; - if (ac == 4) /* stlinkv1 */ - { - static const int scsi_verbose = 2; - sl = stlink_quirk_open(av[1], scsi_verbose); - path = av[2]; - addr = strtoul(av[3], NULL, 16); - } - else if (ac == 3) /* stlinkv2 */ - { - sl = stlink_open_usb(NULL, 10); - path = av[1]; - addr = strtoul(av[2], NULL, 16); - } - else /* invalid */ + if (get_opts(&o, ac - 1, av + 1) == -1) { printf("invalid command line\n"); + usage(); goto on_error; } - if (sl == NULL) goto on_error; - - err = stlink_fwrite_flash(sl, path, addr); - if (err == -1) + if (o.devname != NULL) /* stlinkv1 */ { - printf("stlink_fwrite_flash() == -1\n"); +#if CONFIG_USE_LIBSG + static const int scsi_verbose = 2; + sl = stlink_quirk_open(o.devname, scsi_verbose); + if (sl == NULL) goto on_error; +#else + printf("not compiled for use with STLink/V1"); goto on_error; +#endif } + else /* stlinkv2 */ + { + sl = stlink_open_usb(10); + if (sl == NULL) goto on_error; + } + + if (stlink_current_mode(sl) == STLINK_DEV_DFU_MODE) + stlink_exit_dfu_mode(sl); + + if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) + stlink_enter_swd_mode(sl); + + stlink_reset(sl); + + if (o.do_read == 0) /* write */ + { + err = stlink_fwrite_flash(sl, o.filename, o.addr); + if (err == -1) + { + printf("stlink_fwrite_flash() == -1\n"); + goto on_error; + } + } + else /* read */ + { + err = stlink_fread(sl, o.filename, o.addr, o.size); + if (err == -1) + { + printf("stlink_fread() == -1\n"); + goto on_error; + } + } + + /* success */ + err = 0; on_error: if (sl != NULL) stlink_close(sl); diff --git a/gdbserver/Makefile b/gdbserver/Makefile index e9d2774..a8d1b90 100644 --- a/gdbserver/Makefile +++ b/gdbserver/Makefile @@ -1,13 +1,24 @@ +# make ... for both libusb and libsg +# +# make CONFIG_USE_LIBSG=0 ... +# for just libusb +# PRG := st-util OBJS = gdb-remote.o gdb-server.o CFLAGS+=-g -Wall -Werror -std=gnu99 -I../src -CFLAGS+=-DCONFIG_USE_LIBUSB -CFLAGS+=-DCONFIG_USE_LIBSG -LIBS := -lstlink -lusb-1.0 -lsgutils2 -LDFLAGS+=$(LIBS) -L.. +CFLAGS+=-DCONFIG_USE_LIBUSB=1 +LDFLAGS=-lusb-1.0 -L.. -lstlink +ifeq ($(CONFIG_USE_LIBSG),) +CONFIG_USE_LIBSG=1 +endif + +ifneq ($(CONFIG_USE_LIBSG),0) +CFLAGS+=-DCONFIG_USE_LIBSG=1 +LDFLAGS+=-lsgutils2 +endif all: $(PRG) diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index 72f433f..67f0be0 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -14,6 +14,7 @@ #include #include #include +#include #include @@ -24,6 +25,12 @@ #define FLASH_PAGE_MASK (~((1 << 10) - 1)) #define FLASH_SIZE (FLASH_PAGE * 128) +volatile int do_exit = 0; +void ctrl_c(int sig) +{ + do_exit = 1; +} + static const char hex[] = "0123456789abcdef"; static const char* current_memory_map = NULL; @@ -32,6 +39,11 @@ static const char* current_memory_map = NULL; * Chip IDs are explained in the appropriate programming manual for the * DBGMCU_IDCODE register (0xE0042000) */ + +#define CORE_M3_R1 0x1BA00477 +#define CORE_M3_R2 0x4BA00477 +#define CORE_M4_R0 0x2BA01477 + struct chip_params { uint32_t chip_id; char* description; @@ -43,11 +55,11 @@ struct chip_params { { 0x410, "F1 Medium-density device", 0x1ffff7e0, 0x20000, 0x400, 0x5000, 0x1ffff000, 0x800 }, // table 2, pm0063 { 0x411, "F2 device", 0, /* No flash size register found in the docs*/ - 0x100000, 0x20000, 0x20000, 0x1ff00000, 0x7800 }, // table 1, pm0059 + 0x100000, 0x20000, 0x20000, 0x1fff0000, 0x7800 }, // table 1, pm0059 { 0x412, "F1 Low-density device", 0x1ffff7e0, 0x8000, 0x400, 0x2800, 0x1ffff000, 0x800 }, // table 1, pm0063 { 0x413, "F4 device", 0x1FFF7A10, - 0x100000, 0x20000, 0x20000, 0x1ff00000, 0x7800 }, // table 1, pm0081 + 0x100000, 0x20000, 0x30000, 0x1fff0000, 0x7800 }, // table 1, pm0081 { 0x414, "F1 High-density device", 0x1ffff7e0, 0x80000, 0x800, 0x10000, 0x1ffff000, 0x800 }, // table 3 pm0063 // This ignores the EEPROM! (and uses the page erase size, @@ -79,15 +91,10 @@ int main(int argc, char** argv) { switch(argc) { - default: { - fprintf(stderr, HelpStr, NULL); - return 1; - } - case 3 : { //sl = stlink_quirk_open(argv[2], 0); - // FIXME - hardcoded to usb.... - sl = stlink_open_usb(argv[2], 10); + // FIXME - hardcoded to usb.... + sl = stlink_open_usb(10); if(sl == NULL) return 1; break; } @@ -99,6 +106,7 @@ int main(int argc, char** argv) { } } +#if CONFIG_USE_LIBSG case 1 : { // Search ST-LINK (from /dev/sg0 to /dev/sg99) const int DevNumMax = 99; int ExistDevCount = 0; @@ -136,18 +144,32 @@ int main(int argc, char** argv) { } break; } +#endif + + default: { + fprintf(stderr, HelpStr, NULL); + return 1; + } } - if (stlink_current_mode(sl) == STLINK_DEV_DFU_MODE) { - stlink_exit_dfu_mode(sl); - } + if (stlink_current_mode(sl) == STLINK_DEV_DFU_MODE) { + stlink_exit_dfu_mode(sl); + } if(stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) { stlink_enter_swd_mode(sl); } uint32_t chip_id = stlink_chip_id(sl); - printf("Chip ID is %08x.\n", chip_id); + uint32_t core_id = stlink_core_id(sl); + + /* Fix chip_id for F4 */ + if (((chip_id & 0xFFF) == 0x411) && (core_id == CORE_M4_R0)) { + printf("Fixing wrong chip_id for STM32F4 Rev A errata\n"); + chip_id = 0x413; + } + + printf("Chip ID is %08x, Core ID is %08x.\n", chip_id, core_id); const struct chip_params* params = NULL; @@ -182,6 +204,9 @@ int main(int argc, char** argv) { while(serve(sl, port) == 0); + /* Switch back to mass storage mode before closing. */ + stlink_run(sl); + stlink_exit_debug_mode(sl); stlink_close(sl); return 0; @@ -578,7 +603,9 @@ int serve(stlink_t *sl, int port) { printf("Listening at *:%d...\n", port); + (void) signal (SIGINT, ctrl_c); int client = accept(sock, NULL, NULL); + signal (SIGINT, SIG_DFL); if(client < 0) { perror("accept"); return 1; diff --git a/src/stlink-common.h b/src/stlink-common.h index cb6c6cc..9481609 100644 --- a/src/stlink-common.h +++ b/src/stlink-common.h @@ -175,6 +175,7 @@ extern "C" { /* sram settings */ #define STM32_SRAM_BASE 0x20000000 #define STM32_SRAM_SIZE (8 * 1024) +#define STM32L_SRAM_SIZE (16 * 1024) stm32_addr_t sram_base; size_t sram_size; diff --git a/src/stlink-sg.c b/src/stlink-sg.c index f8865e1..b8220de 100644 --- a/src/stlink-sg.c +++ b/src/stlink-sg.c @@ -80,12 +80,14 @@ #include #include +#include "stlink-common.h" + +#if CONFIG_USE_LIBSG // sgutils2 (apt-get install libsgutils2-dev) #include #include - -#include "stlink-common.h" #include "stlink-sg.h" +#endif // Suspends execution of the calling process for diff --git a/src/stlink-usb.c b/src/stlink-usb.c index 2433d6c..ff9ef71 100644 --- a/src/stlink-usb.c +++ b/src/stlink-usb.c @@ -1,4 +1,3 @@ -#include #include #include #include @@ -9,6 +8,8 @@ #include "stlink-common.h" #include "stlink-usb.h" +enum SCSI_Generic_Direction {SG_DXFER_TO_DEV=0, SG_DXFER_FROM_DEV=0x80}; + void _stlink_usb_close(stlink_t* sl) { struct stlink_libusb * const handle = sl->backend_data; // maybe we couldn't even get the usb device? @@ -19,8 +20,9 @@ void _stlink_usb_close(stlink_t* sl) { if (handle->rep_trans != NULL) libusb_free_transfer(handle->rep_trans); - if (handle->usb_handle != NULL) + if (handle->usb_handle != NULL) { libusb_close(handle->usb_handle); + } libusb_exit(handle->libusb_ctx); free(handle); @@ -88,10 +90,11 @@ int submit_wait(struct stlink_libusb *slu, struct libusb_transfer * trans) { return 0; } -ssize_t send_recv(struct stlink_libusb* handle, +ssize_t send_recv(struct stlink_libusb* handle, int terminate, unsigned char* txbuf, size_t txsize, unsigned char* rxbuf, size_t rxsize) { /* note: txbuf and rxbuf can point to the same area */ + int res = 0; libusb_fill_bulk_transfer(handle->req_trans, handle->usb_handle, handle->ep_req, @@ -100,122 +103,146 @@ ssize_t send_recv(struct stlink_libusb* handle, 0 ); - printf("submit_wait(req)\n"); - if (submit_wait(handle, handle->req_trans)) return -1; /* send_only */ - if (rxsize == 0) return 0; + if (rxsize != 0) { - /* read the response */ - - libusb_fill_bulk_transfer(handle->rep_trans, handle->usb_handle, - handle->ep_rep, rxbuf, rxsize, NULL, NULL, 0); - - printf("submit_wait(rep)\n"); - - if (submit_wait(handle, handle->rep_trans)) return -1; + /* read the response */ + + libusb_fill_bulk_transfer(handle->rep_trans, handle->usb_handle, + handle->ep_rep, rxbuf, rxsize, NULL, NULL, 0); + + if (submit_wait(handle, handle->rep_trans)) return -1; + res = handle->rep_trans->actual_length; + } + if ((handle->protocoll == 1) && terminate) { + /* Read the SG reply */ + unsigned char sg_buf[13]; + libusb_fill_bulk_transfer + (handle->rep_trans, handle->usb_handle, + handle->ep_rep, sg_buf, 13, NULL, NULL, 0); + res = submit_wait(handle, handle->rep_trans); + /* The STLink doesn't seem to evaluate the sequence number */ + handle->sg_transfer_idx++; + if (res ) return -1; + } return handle->rep_trans->actual_length; } static inline int send_only -(struct stlink_libusb* handle, unsigned char* txbuf, size_t txsize) { - return send_recv(handle, txbuf, txsize, NULL, 0); +(struct stlink_libusb* handle, int terminate, + unsigned char* txbuf, size_t txsize) { + return send_recv(handle, terminate, txbuf, txsize, NULL, 0); } -// KARL - fixme, common code! (or, one per backend) -// candidate for common code... - - -static int is_stlink_device(libusb_device * dev) { +/* Search for a STLINK device, either any or teh one with the given PID + * Return the protocoll version + */ +static int is_stlink_device(libusb_device * dev, uint16_t pid) { struct libusb_device_descriptor desc; + int version; if (libusb_get_device_descriptor(dev, &desc)) return 0; - printf("device: 0x%04x, 0x%04x\n", desc.idVendor, desc.idProduct); - if (desc.idVendor != USB_ST_VID) return 0; - if (desc.idProduct != USB_STLINK_32L_PID) + if ((desc.idProduct != USB_STLINK_32L_PID) && + (desc.idProduct != USB_STLINK_PID )) return 0; - return 1; + if(pid && (pid != desc.idProduct)) + return 0; + if (desc.idProduct == USB_STLINK_PID ) + version = 1; + else + version = 2; + + return version; +} + +static int fill_command +(stlink_t * sl, enum SCSI_Generic_Direction dir, uint32_t len) { + struct stlink_libusb * const slu = sl->backend_data; + unsigned char* const cmd = sl->c_buf; + int i = 0; + memset(cmd, 0, sizeof (sl->c_buf)); + if(slu->protocoll == 1) { + cmd[i++] = 'U'; + cmd[i++] = 'S'; + cmd[i++] = 'B'; + cmd[i++] = 'C'; + write_uint32(&cmd[i], slu->sg_transfer_idx); + write_uint32(&cmd[i + 4], len); + i += 8; + cmd[i++] = (dir == SG_DXFER_FROM_DEV)?0x80:0; + cmd[i++] = 0; /* Logical unit */ + cmd[i++] = 0xa; /* Command length */ + } + return i; } void _stlink_usb_version(stlink_t *sl) { struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const buf = sl->q_buf; + unsigned char* const data = sl->q_buf; + unsigned char* const cmd = sl->c_buf; ssize_t size; + uint32_t rep_len = 6; + int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); - memset(buf, 0, sizeof (sl->q_buf)); - buf[0] = STLINK_GET_VERSION; - buf[1] = 0x80; + cmd[i++] = STLINK_GET_VERSION; - size = send_recv(slu, buf, STLINK_CMD_SIZE, buf, 6); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { printf("[!] send_recv\n"); return; } - -#if 1 /* DEBUG */ - { - ssize_t i; - for (i = 0; i < size; ++i) printf("%02x", buf[i]); - printf("\n"); - } -#endif /* DEBUG */ } void _stlink_usb_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const buf = sl->q_buf; - unsigned char *cmd_buf = sl->c_buf; + unsigned char* const data = sl->q_buf; + unsigned char* const cmd = sl->c_buf; - memset(cmd_buf, 0, STLINK_CMD_SIZE); - cmd_buf[0] = STLINK_DEBUG_COMMAND; - cmd_buf[1] = STLINK_DEBUG_WRITEMEM_32BIT; - write_uint32(cmd_buf + 2, addr); - write_uint16(cmd_buf + 6, len); - send_only(slu, cmd_buf, STLINK_CMD_SIZE); - -#if Q_BUF_LEN < UINT16_MAX - assert(len < sizeof(sl->q_buf)); // makes a compiler warning? always true? -#endif - assert((len & 3) == 0); - send_only(slu, buf, len); + int i = fill_command(sl, SG_DXFER_TO_DEV, len); + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_DEBUG_WRITEMEM_32BIT; + write_uint32(&cmd[i], addr); + write_uint16(&cmd[i + 4], len); + send_only(slu, 0, cmd, slu->cmd_len); + send_only(slu, 1, data, len); } void _stlink_usb_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const buf = sl->q_buf; - unsigned char *cmd_buf = sl->c_buf; + unsigned char* const data = sl->q_buf; + unsigned char* const cmd = sl->c_buf; - memset(cmd_buf, 0, STLINK_CMD_SIZE); - cmd_buf[0] = STLINK_DEBUG_COMMAND; - cmd_buf[1] = STLINK_DEBUG_WRITEMEM_8BIT; - write_uint32(cmd_buf + 2, addr); - write_uint16(cmd_buf + 6, len); - send_only(slu, cmd_buf, STLINK_CMD_SIZE); - -#if Q_BUF_LEN < UINT16_MAX - assert(len < sizeof(sl->q_buf)); // makes a compiler warning? always true? -#endif - send_only(slu, buf, len); + int i = fill_command(sl, SG_DXFER_TO_DEV, 0); + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_DEBUG_WRITEMEM_8BIT; + write_uint32(&cmd[i], addr); + write_uint16(&cmd[i + 4], len); + send_only(slu, 0, cmd, slu->cmd_len); + send_only(slu, 1, data, len); } int _stlink_usb_current_mode(stlink_t * sl) { struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const buf = sl->q_buf; + unsigned char* const cmd = sl->c_buf; + unsigned char* const data = sl->q_buf; ssize_t size; - memset(buf, 0, sizeof (sl->q_buf)); - buf[0] = STLINK_GET_CURRENT_MODE; - size = send_recv(slu, buf, STLINK_CMD_SIZE, buf, 2); + int rep_len = 2; + int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + + cmd[i++] = STLINK_GET_CURRENT_MODE; + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { printf("[!] send_recv\n"); return -1; @@ -225,76 +252,71 @@ int _stlink_usb_current_mode(stlink_t * sl) { void _stlink_usb_core_id(stlink_t * sl) { struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const buf = sl->q_buf; + unsigned char* const cmd = sl->c_buf; + unsigned char* const data = sl->q_buf; ssize_t size; + int rep_len = 4; + int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); - memset(buf, 0, sizeof (sl->q_buf)); - buf[0] = STLINK_DEBUG_COMMAND; - buf[1] = STLINK_DEBUG_READCOREID; + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_DEBUG_READCOREID; - size = send_recv(slu, buf, STLINK_CMD_SIZE, buf, 4); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { printf("[!] send_recv\n"); return; } - sl->core_id = read_uint32(buf, 0); + sl->core_id = read_uint32(data, 0); } void _stlink_usb_status(stlink_t * sl) { struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const buf = sl->q_buf; + unsigned char* const data = sl->q_buf; + unsigned char* const cmd = sl->c_buf; ssize_t size; + int rep_len = 2; + int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); - memset(buf, 0, sizeof (sl->q_buf)); + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_DEBUG_GETSTATUS; - buf[0] = STLINK_DEBUG_COMMAND; - buf[1] = STLINK_DEBUG_GETSTATUS; - - size = send_recv(slu, buf, STLINK_CMD_SIZE, buf, 2); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { printf("[!] send_recv\n"); return; } - - /* todo: stlink_core_stat */ - - // FIXME - decode into sl->core_stat -#if 1 /* DEBUG */ - printf("status == 0x%x\n", buf[0]); -#endif /* DEBUG */ - } void _stlink_usb_force_debug(stlink_t *sl) { struct stlink_libusb *slu = sl->backend_data; - unsigned char* const buf = sl->q_buf; + unsigned char* const data = sl->q_buf; + unsigned char* const cmd = sl->c_buf; ssize_t size; + int rep_len = 2; + int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); - memset(buf, 0, sizeof (sl->q_buf)); - - buf[0] = STLINK_DEBUG_COMMAND; - buf[1] = STLINK_DEBUG_FORCEDEBUG; - size = send_recv(slu, buf, STLINK_CMD_SIZE, buf, 2); + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_DEBUG_FORCEDEBUG; + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { printf("[!] send_recv\n"); return; } } - void _stlink_usb_enter_swd_mode(stlink_t * sl) { struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const buf = sl->q_buf; + unsigned char* const cmd = sl->c_buf; ssize_t size; + const int rep_len = 0; + int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); - memset(buf, 0, sizeof (sl->q_buf)); + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_DEBUG_ENTER; + cmd[i++] = STLINK_DEBUG_ENTER_SWD; - buf[0] = STLINK_DEBUG_COMMAND; - buf[1] = STLINK_SWD_ENTER; - buf[2] = STLINK_DEBUG_ENTER_SWD; - - size = send_recv(slu, buf, STLINK_CMD_SIZE, buf, 2); + size = send_only(slu, 1, cmd, slu->cmd_len); if (size == -1) { printf("[!] send_recv\n"); return; @@ -303,14 +325,14 @@ void _stlink_usb_enter_swd_mode(stlink_t * sl) { void _stlink_usb_exit_dfu_mode(stlink_t* sl) { struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const buf = sl->q_buf; + unsigned char* const cmd = sl->c_buf; ssize_t size; + int i = fill_command(sl, SG_DXFER_FROM_DEV, 0); - memset(buf, 0, sizeof (sl->q_buf)); - buf[0] = STLINK_DFU_COMMAND; - buf[1] = STLINK_DFU_EXIT; + cmd[i++] = STLINK_DFU_COMMAND; + cmd[i++] = STLINK_DFU_EXIT; - size = send_only(slu, buf, 16); + size = send_only(slu, 1, cmd, slu->cmd_len); if (size == -1) { printf("[!] send_recv\n"); return; @@ -323,14 +345,16 @@ void _stlink_usb_exit_dfu_mode(stlink_t* sl) { */ void _stlink_usb_reset(stlink_t * sl) { struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const buf = sl->q_buf; + unsigned char* const data = sl->q_buf; + unsigned char* const cmd = sl->c_buf; ssize_t size; + int rep_len = 2; + int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); - memset(buf, 0, sizeof (sl->q_buf)); - buf[0] = STLINK_DEBUG_COMMAND; - buf[1] = STLINK_DEBUG_RESETSYS; + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_DEBUG_RESETSYS; - size = send_recv(slu, buf, STLINK_CMD_SIZE, buf, sizeof (sl->q_buf)); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { printf("[!] send_recv\n"); return; @@ -340,14 +364,16 @@ void _stlink_usb_reset(stlink_t * sl) { void _stlink_usb_step(stlink_t* sl) { struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const buf = sl->q_buf; + unsigned char* const data = sl->q_buf; + unsigned char* const cmd = sl->c_buf; ssize_t size; + int rep_len = 2; + int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); - memset(buf, 0, sizeof (sl->q_buf)); - buf[0] = STLINK_DEBUG_COMMAND; - buf[1] = STLINK_DEBUG_STEPCORE; + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_DEBUG_STEPCORE; - size = send_recv(slu, buf, STLINK_CMD_SIZE, buf, 2); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { printf("[!] send_recv\n"); return; @@ -360,31 +386,32 @@ void _stlink_usb_step(stlink_t* sl) { */ void _stlink_usb_run(stlink_t* sl) { struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const buf = sl->q_buf; + unsigned char* const data = sl->q_buf; + unsigned char* const cmd = sl->c_buf; ssize_t size; + int rep_len = 2; + int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); - memset(buf, 0, sizeof (sl->q_buf)); - buf[0] = STLINK_DEBUG_COMMAND; - buf[1] = STLINK_DEBUG_RUNCORE; + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_DEBUG_RUNCORE; - size = send_recv(slu, buf, STLINK_CMD_SIZE, buf, 2); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { printf("[!] send_recv\n"); return; } - } void _stlink_usb_exit_debug_mode(stlink_t *sl) { struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const buf = sl->q_buf; + unsigned char* const cmd = sl->c_buf; ssize_t size; + int i = fill_command(sl, SG_DXFER_FROM_DEV, 0); - memset(buf, 0, sizeof (sl->q_buf)); - buf[0] = STLINK_DEBUG_COMMAND; - buf[1] = STLINK_DEBUG_EXIT; + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_DEBUG_EXIT; - size = send_only(slu, buf, 16); + size = send_only(slu, 1, cmd, slu->cmd_len); if (size == -1) { printf("[!] send_only\n"); return; @@ -393,21 +420,17 @@ void _stlink_usb_exit_debug_mode(stlink_t *sl) { void _stlink_usb_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const buf = sl->q_buf; + unsigned char* const data = sl->q_buf; + unsigned char* const cmd = sl->c_buf; ssize_t size; + int i = fill_command(sl, SG_DXFER_FROM_DEV, len); - /* assume len < sizeof(sl->q_buf) */ + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_DEBUG_READMEM_32BIT; + write_uint32(&cmd[i], addr); + write_uint16(&cmd[i + 4], len); - memset(buf, 0, sizeof (sl->q_buf)); - buf[0] = STLINK_DEBUG_COMMAND; - buf[1] = STLINK_DEBUG_READMEM_32BIT; - write_uint32(buf + 2, addr); - /* windows usb logs show only one byte is used for length ... */ - // Presumably, this is because usb transfers can't be 16 bits worth of bytes long... - assert (len < 256); - buf[6] = (uint8_t) len; - - size = send_recv(slu, buf, STLINK_CMD_SIZE, buf, len); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, len); if (size == -1) { printf("[!] send_recv\n"); return; @@ -418,20 +441,17 @@ void _stlink_usb_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { stlink_print_data(sl); } - -#if 1 /* stlinkv1 */ - void _stlink_usb_read_all_regs(stlink_t *sl, reg *regp) { struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const buf = sl->q_buf; - unsigned char* const cmd_buf = sl->c_buf; + unsigned char* const cmd = sl->c_buf; + unsigned char* const data = sl->q_buf; ssize_t size; - int i; + uint32_t rep_len = 84; + int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); - memset(cmd_buf, 0, STLINK_CMD_SIZE); - cmd_buf[0] = STLINK_DEBUG_COMMAND; - cmd_buf[1] = STLINK_DEBUG_READALLREGS; - size = send_recv(slu, cmd_buf, STLINK_CMD_SIZE, buf, 84); + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_DEBUG_READALLREGS; + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { printf("[!] send_recv\n"); return; @@ -455,53 +475,19 @@ void _stlink_usb_read_all_regs(stlink_t *sl, reg *regp) { DD(sl, "rw2 = 0x%08x\n", read_uint32(sl->q_buf, 80)); } -#else /* stlinkv2 */ - -static void _stlink_usb_read_all_regs(stlink_t *sl, reg *regp) { - struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const buf = sl->q_buf; - unsigned char* const cmd_buf = sl->c_buf; - ssize_t size; - int i; - -#define STLINK_JTAG_COMMAND 0xf2 -#define STLINK_JTAG_READALLREGS2 0x3a - memset(cmd_buf, 0, STLINK_CMD_SIZE); - cmd_buf[0] = STLINK_JTAG_COMMAND; - cmd_buf[1] = STLINK_JTAG_READALLREGS2; - size = send_recv(slu, cmd_buf, STLINK_CMD_SIZE, buf, 84); - - if (size == -1) { - printf("[!] send_recv\n"); - return; - } - - sl->q_len = (size_t) size; - - for(i=0; i<16; i++) - regp->r[i]= read_uint32(sl->q_buf, i*4); - - regp->xpsr = read_uint32(sl->q_buf, 64); - regp->main_sp = read_uint32(sl->q_buf, 68); - regp->process_sp = read_uint32(sl->q_buf, 72); - regp->rw = read_uint32(sl->q_buf, 76); - regp->rw2 = read_uint32(sl->q_buf, 80); -} - -#endif /* stlinkv1 */ - void _stlink_usb_read_reg(stlink_t *sl, int r_idx, reg *regp) { struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const buf = sl->q_buf; - unsigned char* const cmd_buf = sl->c_buf; + unsigned char* const data = sl->q_buf; + unsigned char* const cmd = sl->c_buf; ssize_t size; uint32_t r; + uint32_t rep_len = 4; + int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); - memset(cmd_buf, 0, STLINK_CMD_SIZE); - cmd_buf[0] = STLINK_DEBUG_COMMAND; - cmd_buf[1] = STLINK_DEBUG_READREG; - cmd_buf[2] = (uint8_t) r_idx; - size = send_recv(slu, cmd_buf, STLINK_CMD_SIZE, buf, 4); + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_DEBUG_READREG; + cmd[i++] = (uint8_t) r_idx; + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { printf("[!] send_recv\n"); return; @@ -522,31 +508,29 @@ void _stlink_usb_read_reg(stlink_t *sl, int r_idx, reg *regp) { regp->process_sp = r; break; case 19: - regp->rw = r; //XXX ?(primask, basemask etc.) + regp->rw = r; /* XXX ?(primask, basemask etc.) */ break; case 20: - regp->rw2 = r; //XXX ?(primask, basemask etc.) + regp->rw2 = r; /* XXX ?(primask, basemask etc.) */ break; default: regp->r[r_idx] = r; } } - -#if 1 /* stlinkv1 */ - void _stlink_usb_write_reg(stlink_t *sl, uint32_t reg, int idx) { struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const buf = sl->q_buf; - unsigned char *cmd_buf = sl->c_buf; + unsigned char* const data = sl->q_buf; + unsigned char* const cmd = sl->c_buf; ssize_t size; + uint32_t rep_len = 2; + int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); - memset(cmd_buf, 0, STLINK_CMD_SIZE); - cmd_buf[0] = STLINK_DEBUG_COMMAND; - cmd_buf[1] = STLINK_DEBUG_WRITEREG; - cmd_buf[2] = idx; - write_uint32(cmd_buf + 3, reg); - size = send_recv(slu, cmd_buf, STLINK_CMD_SIZE, buf, 2); + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_DEBUG_WRITEREG; + cmd[i++] = idx; + write_uint32(&cmd[i], reg); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { printf("[!] send_recv\n"); return; @@ -555,32 +539,6 @@ void _stlink_usb_write_reg(stlink_t *sl, uint32_t reg, int idx) { stlink_print_data(sl); } -#else /* stlinkv2 */ - -void _stlink_usb_write_reg(stlink_t *sl, uint32_t reg, int idx) { - struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const buf = sl->q_buf; - unsigned char *cmd_buf = sl->c_buf; - ssize_t size; - -#define STLINK_JTAG_WRITEREG2 0x34 - memset(cmd_buf, 0, STLINK_CMD_SIZE); - cmd_buf[0] = STLINK_JTAG_COMMAND; - cmd_buf[1] = STLINK_JTAG_WRITEREG2; - cmd_buf[2] = idx; - write_uint32(cmd_buf + 3, reg); - size = send_recv(slu, cmd_buf, STLINK_CMD_SIZE, buf, 2); - if (size == -1) { - printf("[!] send_recv\n"); - return; - } - sl->q_len = (size_t) size; - stlink_print_data(sl); -} - -#endif /* stlinkv1 */ - - stlink_backend_t _stlink_usb_backend = { _stlink_usb_close, _stlink_usb_exit_debug_mode, @@ -604,38 +562,48 @@ stlink_backend_t _stlink_usb_backend = { }; -stlink_t* stlink_open_usb(const char *dev_name, const int verbose) { +stlink_t* stlink_open_usb(const int verbose) { stlink_t* sl = NULL; struct stlink_libusb* slu = NULL; - - /* unused */ - dev_name = dev_name; - - sl = malloc(sizeof (stlink_t)); - slu = malloc(sizeof (struct stlink_libusb)); - if (sl == NULL) goto on_error; - if (slu == NULL) goto on_error; - - sl->verbose = verbose; - - if (slu->libusb_ctx != NULL) { - fprintf(stderr, "reopening with an existing context? undefined behaviour!\n"); - goto on_error; - } else { - if (libusb_init(&(slu->libusb_ctx))) { - fprintf(stderr, "failed to init libusb context, wrong version of libraries?\n"); - goto on_error; - } - } - int error = -1; - libusb_device** devs = NULL; libusb_device* dev; ssize_t i; ssize_t count; int config; + char *iSerial = NULL; + sl = malloc(sizeof (stlink_t)); + slu = malloc(sizeof (struct stlink_libusb)); + if (sl == NULL) goto on_error; + if (slu == NULL) goto on_error; + memset(sl, 0, sizeof (stlink_t)); + memset(slu, 0, sizeof (struct stlink_libusb)); + + sl->verbose = verbose; + sl->backend = &_stlink_usb_backend; + sl->backend_data = slu; + + sl->core_stat = STLINK_CORE_STAT_UNKNOWN; + + /* flash memory settings */ + sl->flash_base = STM32_FLASH_BASE; + sl->flash_size = STM32_FLASH_SIZE; + sl->flash_pgsz = STM32_FLASH_PGSZ; + + /* system memory */ + sl->sys_base = STM32_SYSTEM_BASE; + sl->sys_size = STM32_SYSTEM_SIZE; + + /* sram memory settings */ + sl->sram_base = STM32_SRAM_BASE; + sl->sram_size = STM32L_SRAM_SIZE; + + if (libusb_init(&(slu->libusb_ctx))) { + fprintf(stderr, "failed to init libusb context, wrong version of libraries?\n"); + goto on_error; + } + count = libusb_get_device_list(slu->libusb_ctx, &devs); if (count < 0) { printf("libusb_get_device_list\n"); @@ -644,14 +612,47 @@ stlink_t* stlink_open_usb(const char *dev_name, const int verbose) { for (i = 0; i < count; ++i) { dev = devs[i]; - if (is_stlink_device(dev)) break; + slu->protocoll = is_stlink_device(dev, 0); + if (slu->protocoll > 0) break; } - if (i == count) return NULL; + if (i == count) goto on_libusb_error; if (libusb_open(dev, &(slu->usb_handle))) { printf("libusb_open()\n"); goto on_libusb_error; } + + if (iSerial) { + unsigned char serial[256]; + struct libusb_device_descriptor desc; + int r; + + r = libusb_get_device_descriptor(dev, &desc); + if (r<0) { + printf("Can't get descriptor to match Iserial\n"); + goto on_libusb_error; + } + r = libusb_get_string_descriptor_ascii + (slu->usb_handle, desc.iSerialNumber, serial, 256); + if (r<0) { + printf("Can't get Serialnumber to match Iserial\n"); + goto on_libusb_error; + } + if (strcmp((char*)serial, iSerial)) { + printf("Mismatch in serial numbers, dev %s vs given %s\n", + serial, iSerial); + goto on_libusb_error; + } + } + + if (libusb_kernel_driver_active(slu->usb_handle, 0) == 1) { + int r; + + r = libusb_detach_kernel_driver(slu->usb_handle, 0); + if (r<0) + printf("libusb_detach_kernel_driver(() error %s\n", strerror(-r)); + goto on_libusb_error; + } if (libusb_get_configuration(slu->usb_handle, &config)) { /* this may fail for a previous configured device */ @@ -688,15 +689,20 @@ stlink_t* stlink_open_usb(const char *dev_name, const int verbose) { slu->ep_rep = 1 /* ep rep */ | LIBUSB_ENDPOINT_IN; slu->ep_req = 2 /* ep req */ | LIBUSB_ENDPOINT_OUT; - /* libusb_reset_device(slu->usb_handle); */ + slu->sg_transfer_idx = 0; + slu->cmd_len = (slu->protocoll == 1)? STLINK_SG_SIZE: STLINK_CMD_SIZE; /* success */ + if (stlink_current_mode(sl) == STLINK_DEV_DFU_MODE) { + printf("-- exit_dfu_mode\n"); + stlink_exit_dfu_mode(sl); + } + stlink_version(sl); error = 0; on_libusb_error: if (devs != NULL) { libusb_free_device_list(devs, 1); - fprintf(stderr, "freed libusb device list\n"); } if (error == -1) { @@ -704,8 +710,6 @@ on_libusb_error: return NULL; } - sl->backend = &_stlink_usb_backend; - sl->backend_data = slu; /* success */ return sl; diff --git a/src/stlink-usb.h b/src/stlink-usb.h index 4ed655b..c632a8c 100644 --- a/src/stlink-usb.h +++ b/src/stlink-usb.h @@ -15,6 +15,7 @@ extern "C" { #include #include "stlink-common.h" +#define STLINK_SG_SIZE 31 #define STLINK_CMD_SIZE 16 #if defined(CONFIG_USE_LIBUSB) @@ -25,6 +26,9 @@ extern "C" { struct libusb_transfer* rep_trans; unsigned int ep_req; unsigned int ep_rep; + int protocoll; + unsigned int sg_transfer_idx; + unsigned int cmd_len; }; #else #error "it's all bad!" @@ -32,7 +36,7 @@ extern "C" { #endif - stlink_t* stlink_open_usb(const char *dev_name, const int verbose); + stlink_t* stlink_open_usb(const int verbose); #ifdef __cplusplus diff --git a/src/test_sg.c b/src/test_sg.c index 137eca4..34fbe54 100644 --- a/src/test_sg.c +++ b/src/test_sg.c @@ -6,8 +6,10 @@ #include #include +#if CONFIG_USE_LIBSG #include #include +#endif #include "stlink-common.h" int main(int argc, char *argv[]) { @@ -210,4 +212,4 @@ int main(int argc, char *argv[]) { //fflush(stderr); fflush(stdout); return EXIT_SUCCESS; -} \ No newline at end of file +} diff --git a/src/test_usb.c b/src/test_usb.c index bd81ec1..343e355 100644 --- a/src/test_usb.c +++ b/src/test_usb.c @@ -10,7 +10,7 @@ int main(int ac, char** av) { ac = ac; av = av; - sl = stlink_open_usb(NULL, 10); + sl = stlink_open_usb(10); if (sl != NULL) { printf("-- version\n"); stlink_version(sl); From 2f7b70f1a8ef8d1204b1d16b58c4d3a160f8156a Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Sat, 22 Oct 2011 15:13:22 +0000 Subject: [PATCH 08/63] Add option parsing and help Supports setting the gdb listen port Supports setting which version of stlink to use Supports setting the device to use (in case autoprobing doesn't work) --- doc/tutorial/tutorial.pdf | Bin 110077 -> 110986 bytes doc/tutorial/tutorial.tex | 12 +-- gdbserver/gdb-server.c | 184 ++++++++++++++++++++++++++++---------- 3 files changed, 146 insertions(+), 50 deletions(-) diff --git a/doc/tutorial/tutorial.pdf b/doc/tutorial/tutorial.pdf index 9202ed4dc33c1bcafdcf4db30807103a22c846c8..4ffcc3e563b3df294e331eb3fae97f9843f31817 100644 GIT binary patch delta 47877 zcmV)IK)k>G+Xjl`2Cx$-n( z+bEVsLOuw=V)YizedAR?Q?Cc^F0Wh^qehfKH&h#_a-8~_JuO#{z7I+wNXPn6NY3_E zUHr9iMd;J+oxANQ;k#|NZT{u^5D5cnjG6}OOPP;Ak8RaoZcl@H{ot79-Of{$v;<~s zN)@Q9rY}1`ls49a9eZA%pWl>i>DDACHyNP;`Cz~Ni|HKG>)oPOiDEGkCc>uYglkxXXC!T^g* z9%zZSiAbb}qMZ2ew~i(yO=NijJHYPhp{lF9x>;RaSGPoVk%{c}iAea_?BvNS`9a{EUNlbk1of}CJj(yrO>pg^r6nvYh3_Gg*J(mW+% z{sbuHNy$F{La-#beyx2)n=QQ~d4> z!8-&RfkOG-el3duwHf;mq8OU_n*`ex~ULmnr_e_CJ zDY6J+?aMCp_bp$Ne zecxMo5y&fxdOdIPV@cW@?*3G#ymNzN?S_f6t9G){f8zrjJKKcV(QP2JHr#HTG`Brx zoJ25SaYWDC)e3U^`bd(q#(@<*OpdeK7DnhX#~Cs`#PyhETT2K~XH5gK%gse^<; ziAE3Man016sg}_-cUDYwj4;sz3Zxhiw;3c@pZ_kbz#u_MEeJ|`0<9#-)Ke1d2!aF- z4F7bZe=yW?sbh8{oQQ>q29!XX`&|ez7DQXF0HI}IS?;7YMIj#oA4sZLHpzyhKy@%@ z&yXIamF2F37v2pk|Kq@y!T%kEki-ER^i*B|ToA+^OUiN5NDRZuaBhUG-5=PmRfXKH zck6bY9eFT0gCcuIHKXMrRf4hju(z}{>b7rSe?W6?XJgXxN338K^S7*E6$>^7LG}Vj zVnyQe4~Mqs3OJd&PgD;qXd_-x4wGcFj^Yi#Ywmi&XH9CAR7ePguBagWeN2HP!0sXD zO_eS%^bMW@(;!Go%p3|chs4YwF>_#2pL$4>{|io{3oGxo8tvnqULr`*u$kW`(xDO| ze@yJU4P;KC{=fYu1D!)$waHkv*5aguB8SS%4Ws3V0*HwfwPZ5@gk#dsHN%Efx5xFl6_8r;2eQUW9PX$>0w9JQ6&R(m`AmTMozd>C_< zUk3PQpRW#>xz~kucg0m-7;Oh0Sl-f`hYhJ+9daK9H!ySOx*?7yRI!_vyoocW>cdVS zqq=ixy)7^<@Zy1q2jJNeJ-jOu@fkyQxn=_2iOGHzOs_X{ z9KK|#zbyNqMN5Gfmg}@=xma}7I;~SDEWRkgzvA}m`_|OWkS8FT!2O)RUH4$`o37&F zRkgxLXX03uSC6rRkDRHnf9q32&)A>WOhWSECvIABkPz2NnQYlM7Xxp5=+*l4*Qf6a zcBUE1nLKXUmWv^;r3ZItkBUW>I^|4U;W3ZX`~1zAJ&!o1(vDOumpc$2%1z&{ z%D$eLOFAu!FJL`4(!U`#|K&O3uDYn#Jq28w-n@3%=55z;yawWWf~zk#721OnJMMA2 zcMN9KU(#PSRE@1Gd?|w}d#702d$}45wr>49p`M(@fG5c~?O<%5`^G#1Rr+$%o_ zJyr~Jj=Sjs)$q+JD&3>%Z6~13aI3m~n>rTvDz1;1nu<{E!8an@M1~sMkto9?5a~ZY zB~pcxn;El{x)3{)i5e3FGBGlfp(ZJRU64U$}fKcPOxi5VYDN_7*-^Xh%9fYh?*@a?AC*86LUx*Q}?{&JjJwL zQ(}w#eF-RAiyF9bjc`U&y!|uM`r-}>%uuV7cpjXS(g7}$S|1d%oEp&s3zIXuP2ki& z{kGeslc**3lWrd_f9r4CHW2^rze2$Ffd*oh50R7#Y(Uf3(j_g{xZ8lP9~4VTwAhj> z*=h6N?;f;cr-`vHDK<07JM{ONyy&l_qW1Rg=XOOlK|HsNXgY3c-Ri z?k$_L>bMKW*^9y+je@N?)6H+N1dm#xB%iD742 zpY)5FHPbKEGRjJwT3Tsb*riu0mA&yhx3w@Te@Go}XaNohE(am)5}T^Kx-E{4LMGEx zZwE4p6BzuuYEC}e_VuFeu2zw8GF_I0x!^dwVdr>!WX&P=eLNZ#USdDI@0(rBlFL2N(sbGT%#u`$q$f|J`K9)AXjrXzu?m~<>`wuB2@$9njbgxY}(i4;r_$~q-r zYYNBfv6S`%4ugevvy52mf9m~f1~!vhWz>6o{?r=`qbPz$lNG4On)YW1y^yf zyS3~p2Qh!tJv;x&vYtlKvWIlO!+%p7B>3=yjGEcL6 z>A;kC1J5~Ou4it+WX3|voPS~NmSAs+WFk)a3V@>e zDti!o!gESGWB+&f%rtu@Cx&YWgM(|asJ08RA2R?V(z4CFR;9- z8u;0&Nf%`)- z`oqxpT@P0S@dRE~_lYMv@}9|4nZhZ#zOF5EQf9RXl==%66>Qg&^(U#5uMi89P8tc5 z&k!XSGdUnIAa7!7AUr$@FHB`_XLM*FGcYidp(Z(hmV^%xVVSZTQ5mpCM#P(dMPd~@%c*gZ zQuw-S2~|qr!5s?ks`;R??_$#LT?}6GCnX$rldl;d6f-#>Fd$M2FH&W5Z*_8GWpf}iH@Y*W@6j6Z95a&Mq}HJ zZ6^&H+h}ZCjs0cs2i?#6|7(5Unzd%`)<6eyBLf?NjDeFG(E8&LOLXdNtIXT&J z($TrPy3!h0JJQ-ZnDSCk16<9W%zpriKu4g13(y$wSIPic18d;FQ=^3;0Vtc9JN`?d zWNYH&YTy6_dXpa%TAH~wYD>`aW}Uy1(=vy0ReKN(zH%)PSgMc8{@wW4Xhk(KY#oUTnx;u z3=BUE{-$mK5EW1W7<^>-@BAE%9L(*U9BCcRt^Uf9?yoQ(Wfrk97P7Ur2HH3|!u-Wg z*xUhV^ig+rx_>v<(#F=+#`8bO#N5W%}3>;RxW0O)39M)%hN%75;5z`vCYe~CYG@bye0zfU?J z6J~5{W99zG{O=aiX(*|SN^4U6JLUf>1qE&00G>1~tNTf;yzYP9=^aj@ER__0{_?TyBr;pu` zvHjQ(oBwO72K?7T3xC>L8UJ6MgpfAoJ@ z+d4b^!~es;^nV}lgSXi~;0JN@f54AwSp5TjP`CaAKQ@-m=Fd?dS=xMb`XBm_Tx|af znLnIu|4047&F&xYgULU5GJG&`{1f~y1atxZ4BE$RZ>A8G_}Txs?ucxFlV)KV#EJeM4PIzJ&mCQ(#>|F+?9Cy+GU zgS5IMLVnA?jQ{F+($WAK(wd;q_U!ed7pFMA*9NmVg)uN$a3WCOj|YuQqs+hW^=j{> z>Tmg}1%I?tk|f98nH@ns5B0&dPt2{pzieeJcz#b|znWDF_N8owCQ2nz+rRi1Nv>h$ z92Oyj6Ac~|CCa56;;-AgS(NO_cYMh>Dj4t6D5gSB%}vJW$2pI+3S~yeE^K0KO)R`m zwWi z84gyeMw7AtQZoE{D9<305;2p6Dx%>My-Zwl-^W)XJf(PbP-Ci}-Cw&-&s91pz2alA zI2oc2Cak~S@t|&ZWcskaJVMZw8%&EygD07QtP?HE%3;imE9H8NC=NSDH57Pi^}pxR z7JuE-SbVYw@hWn%)?VlAgLPxal%IGuly5jpxHx+)?2I)V)@rOlyG0L}LelHt2;G@- zVtivtXkxnxq?TaB6ht^H&txBxOx>WLL$h|oRRL3*Qg|{}KPAAO?&m|8ea-ARE8|;H zI7c~UJ_9O7h)2Qd%!bpZ+4<^CjpOot_kZ7IKhNT{J>qOu`Qlt4oS>;?ou*4SWY9Rf zy6-#BoC4Kob;CRqKZmjBB+czZim#R)RN*RZz+s9a57ljNwx!^gK9PgbW#LjaO%ZgV z<5+92NccKcJs3pv5(_-n})KOZP zdMqm3%ppdk+E)0;?_wD~?DT_H1lP->yi+sJJcBDswiZrK3ZIVs37hZ|Y8t6jTws~4 zW1f$fuskb26VvH5dDxYUa(XY+ihl*R6IN6dUQliKi6KboE5TboSOFtt<0%fruW@~x zNOn&3*jE4FRx0IRAb$i(6);-oGz zdHRbqrUf$5D1o)>I%6AAo6V@h7O_{v`?NC3nKWc#g3gp@xq7kw`xA3Ntyq#PYE#AT zikJKYqu{aWYJ=;wp=Fn7O%^PyzidUZi3L}*F&|N^6(JStX*phxDcF9D=i@Ch<>UJK zSqk6U)_by&h1Z*+A-U`dwbD8up5F_x)Fc7N3fPWpGcM}oai zAz0gUwc6tTKF1oUdUvIx@eOb2P|v7FBwdI;H$^RD|-o1Qy4 ztidQ%6OI!J$TERx&<~^vG`)7;4#>ht!_#C)>)0BQTac5TG&i0*vhmF{l16d~L8*ohkL4AuH2gpGJOK#_MQM%zt)Rx&>z^ zyJ+Rz*klvW&VOms2knc7Z1*MWYob7QfN9-snu)H@78{(Xp`Jmye)znS3&UTFZ812Ha6~7Wz!>MPt-`HY~D(XbYuRYwm^4f zzDF6rC#AnUoR!;$wDgMe?tNs+HPIPYhggxoU+^=McYj{I+OMMf-8-_ZAOIeWb+!y02EKVTvZ5jNW~E<2$b%o1hHq{OG`0*tCp9=Um^-Muq@M|`4-L%$*juEonXgObyR7niY-I}_CeWf$Ur&a z7H!S;WZ3^cFq*syPR-a+MdE?yLg#5V4N1mp7Cb%9Sn@$zqf8N@T+H1Mv6w8DJXYF=N4!p0x{mr92 zFj7PC_?FWv*py|+?l;vktqwn*CR1ATvmvq)WwCf0#T>>idNVbGV$k8D6fVbSca7mX z9kyp7CLNNS%h#B?T6dPUaL*)@TE5F}qJPBevdXeuk-e3z@#ZV9Icz9IXj3f^pxYT( z|22R`7I)0w6 zP@5}PpyUBu=OsTM{A=AUjtSPVtGm0GI9jgfaj=RH2Deq`n8BOO6&`ph97u;B^10*6 zLd)VNqTY0S-}A&AujoWXUrM-3yh6yZ1!DFa@)xl9r>aa=bdoG1zfVL3gFcP1uqolA za{J)$pMYR9VR0d321`l|>3_c`fgynX9#L3lct>4xLad|XAom8>Sn9;a03T?f%ffh{ zZN-6j{dQ`cR|~=bs->X{Da$B$1s2S(?;{ccWfr3^BEeUN$`t2_)rdKSQNi`Rjjl&) zF3RQlVP zm)_hP?Qlg-yoh#6~~uP;o{0fpJ37 zwBs{%q?!<~RrkpYXP-Ro_&@a&&`&nLr#KP}hKBKHTyzK7V81H9s*|0M5@FFJzI% zdEL0y5r$!keL}w*(dCFAPL@-BjUFQrv_5L0VVi=($WlsYym$?!yy_Q89JICn%GDV< z*EUJFj~v~~daP9fCyg|Jj%53z8>d+r?)NHGX|8BkVjV9}JJQu6`(;x&acow$@m>Te z5k3C2?L(rIvwv2@tit%%vxv$d0WMbms5bt3tRt$c$ous}MfK7tYiqgMLKJK;sscMS z{8>FW9EqD1sXtCJ%=}Fy(z%bI**4FnXhYrxA)|JS4)w0@Y%RY7kh}!JO7wuTKU{eY7a5A0bVdi*uO{U)RJ)LFnvc1A0ghlkk?fD%+hB_TfQOI6)(^ z><*9Nj?o@_yj^9|(UIvuJfRCGEBx~5X$?zLb}R@qccS^ZBMSE6zumogxX)YtqIiEL ztOKlE-hWEvqE7Avbgija+s>q&LoG2DfEa#xyq*?_TLnfaUN~Yka506MbGyEC5Z0 z>+a;MSYJm?zF)yWzb27DLp)Y)Y5m0v63||xg%=U5Q&GAM`rDhI)FMBz*OIVWWm?4S z4S$`yY(0eTR1y;OeDv_w1)C$s-w4!Wm+gC-y774%2cWM@FGWHfpKN zY{a=NKB$SdiAjo_{iIOlb+{*lRR$u^9^2OP+B zySjz_%&+Lfta!7D6c%`LMau^0fIb6wU4L8m*C^eb@)=SN)Qyy|Td0GcNo6R`J!*9!H(XP>aV?vQbiWUY1c+}I=((>?A%@aJF(rV zOilR~EqjcaA>T-nKsnfCCoYLSd}4Kby2HVEt)+XVWp_C4-NR1myRm~$p+Eoz3x5<4 zllUqx6vDK8AN?6)>O0Z*uR z2)9s7W;;r!8yN@k=$pvGBmMDi5ESfCv!{Jf2_*9=J$tbVI^4f(`^HSBB7EjeGI;F2 z|7=E+>?^MjCeU2zn3EF58J;ofzJEU^-{a0x#~O^qqRl+SpAtW6foBrO2pt3oDwT}6 z?fE3n_7I;$H2O70k?Mz$%2qj^vho%vc@_nJ(~F3duJH;C(#ss6HTQZF|9 z5Z5`eSM0@%r!3-4)v#&V+>XUJE9)6ndq!=EVBgJ@$ktVm@y^o%!ccw#CVz@Pm>gJ8 zS++w-wtD=}zqT0IO84fa8ayaPxUe=JN5-*`^=(NUzoHH+@{y8YV7hl>hL)+TrO2o* z)p!e)jz8j$k7k;79+sMrQV(e_&R<+_a%+0>CT)7tjY$Yj-?${#96SZ6&(|0)X&62%t9tEjMNVg zwhF3>k^63%?_z50N))RJaP$8-+{xgnVZGz4Mm;hGL5?JbR~`{7J%2&T^{1D0lxDeI z0+~39lg7Vx4yTC*Wt}(Gb9n-Tk>0m06si6(kmn;o(I7>@q<%Hw`V$2fL|Wl~55@Do zJJo3dm`ICrXEdNq163@LEs)wx2ErtRIE?DGR=2YTEGV_RsdYq0)n%7rNPTvvG^I8D!InrG zZF3G&DShn>XoDaJq#W8A6mNVcJRNe>Ax)`X+1B}Pd41NS)F6G~e!8yrX7MnZs<_a^ zeX#@hJ=QV@Tel~0Wx+hdEyq9hJaB!88Sh^a*iw@`t#e`C}S zmxB%dn~OWcxCI~Sb8p?o_JF_=*%1{kJHNZTg3^ie2=YbZq`Jpjmi5sRliR{gn7I@| zRHdVH#8kX-MEw$v1C~&&I^VTbdqC2ds;`={``QYNBw}p+^r7YI3H{0R1FTYOo0-y@ zRLgD@#Se6FzkjcO3r}TV!jc-Tei&{!UgFfed4isBN_aNtlLD0N-sXP6)q&=v##L#o zn-+iKazO+>`l+T9>EyqgfR@C!sh=j~q^+M^wV>fqjWsLfNV%Ef$@sdQSNr&hW&)q~R0 zY0RMy3a>h*5gSpTd+?|~q!ROrhsrh4i+9iw5sO>dFtA_w9&H+1Yz;l9(@emJ1 zgVmeCSv>idy4U=LM5Kk|uo1U`??U`-Z;=Tyc7GGxS}{@dlYAwwz(FoBP37a87^uPRQ? zW+YW`*;qljZWRxN;ZE}fHB})&LH|B@s>Fti2*xAlYeM@ z2bL{0u<#Tz&{t>AVz`Q5YX;RM;PD9+HP|kT)!y1xXFz6;=Lc#|!YgSZ# zWR(Z`ZZIPYR?htm+9b=}+rgJgRu-1?hv8gnU_hfNHq&ZWQI;M#dw&)ur@ouJ zswOc`cHA?>=e2NC(O*pms~O*}48;|+D$%A&zg`j4+4`+zz!HLxGh1IFAfj`vT<`HJ zd|nax7NmB__4(+wpNj5lmPuun7dLnE-76lYd64xE!j1 zJk7YZPX)UH(EmI3pt9Ywk$-kG8D5y_4oco!vzfi;3fG`y*$i8wt6*~s$MP_{1JS(WPRC&K}h2JF&PFWiW@zZGY^g&jh%VS%|W%lyT3O z+dZ4kmFjYpT3TOpM39ST#w9HajksN5*lJ6ud^}UJPL}(UAdL7&?4^U`&l&IfGS+`W zsrI=%KOs#g<-W3uOydk^RVK=L#fyVJ8FyQ8_!S!tFv2d6c{}guGsRFe;n=rcn@+Gi z>|;R8iQ7DaPJdKlfK>4dMUNC^Me*IzI-1-1SdUEoW+hQ_Ml1QIaHi^>P5YCoqs*$H z0&6+Kz_)K&-_Kr0%VTgKO;M8EG};wkzZPCERkoYD7Ky*Mq_Nu?nDrq}n*|kyUA@aK zOJ)$S%YQ50e2Eq@YBLH8bfkwHiG{Ez;~I_lI%K8;Z9YhiTA>@6GKc9=ACl;S=9t3t z2%4fS?*(68mp9Ov-ztivQtQYf&byjrqZIH{G+?!Ta@}>S^&39J3Yqe+loeq|gXM|K z2qcbb`0rThNBoH7;cioQ_6wHGD=oIVNjR)W<9}#5t~Hw7N@CCfc$= zjDMyU<{zq)hhQPFR$#G=UxlI5Rhk&)Dd>SNQe%E24Z^$%awkqkoU{OuB1YGUMzh1V zJ(qm8ujn{F zA+KPeb`=K}$Z;C2usrds?cz_f_Fe?7w2$?!Y&uYVyXJ+1M&Z5)Uw@4; zU|zpu-`%UXF_0m8w0n7w`n1Q{PUh_ner4 z79@9+?}SqMEWHd-KNPO2{FH-TuBV?&DtyHs+t)!|0rqxvwcDxkWZT9Ry7tcbK06@I zeu_~ygMcGJfxXsICBb(#>wk&YU!oJ+xUIS8YfQ{Zx8?-jb!k2Qz*h*xPeLG5Vx6nc z0V!k-mpP5FjJjU#?vUD6`r6mUv;~PDM=F}@1{$ThJ}ZJmt^7s^g}U_HIYzoW4EdKR}?2c%bpa& z3{S3^c7m51pXnvA4L<^Eymq1UXay@}7NuCLe$a4|AjJFtaYcO%i)@(=zXa!RmO?h0 zUE^a2wn&s?4a`Run194qSet393nvYmF%Vs7-E|gZwP6XLxY(IGXtbBuon%n@y=*)f z^P=ff8r&3Xu^VXf#9zGfp<{7P%i9ecn=|3{6wGbQvx5PUd6Tb=jM(`3+7$kv^WE|* z?n!G`mN4_i@EbjssZZ8p{1yp}U`0fc-s|bcM{VV(hxD{xEPwj(=X?8$Zk#FM#L|3AU@@|Hy<{M%c)J{oXI^V-Yv}oP(M&!SVkE8Gs7rZKnD$MWSLdS&; z>z8mnF`uTJrjE#G5cw|>t%;scVoNSbvddnCuLE-Ds*mf$xuOWH0L+MI|sK?q5%ar#y}Sc8WmOR$DZJ9Oj_O zQsCK5)W=TcXz))h%IF($aO*8o!7TTdAP`za%MvFqEN6kfB9Q4^G z(jfGb?l)tMx2iDFQ5D3+K9$D1N(1-_!k9z=nbp>KHGk5i&CkB<&VAQN6KS$OYg@h&@l3Qd!}_>5)*|CxN%YOXg-a_yDPXSh)n;)+JzdZE^DY&l<3(8NBltL*P zQvi8a1HtG7)(JZM{osS8@ycYExP$0V&Y^? zXm`3!8-^yKGF(!O!UMaquUfpZEGNt!UrE4_jox}S{pT6id zkjJ(xCDQ&XgTm1<%2$TZegofxiNv91c#QoV3=Yjc8*HhK`t%ib?9*D1D@wSx>kijf zijL&@RQ+Iv0NY&oA0cqU-=ZkOW%7%A)IAQ#xx7 z+kbi|y*uoAgu08Q7001?z&djwar7oM3A=8TzE(y18ludi9;2=Y7MbWpYINrbRxh`e zQRRHzZysE75nfm^1T@Kxs+Q@N_B56qEK`D1XCqw7PRqB6NJ6322_?sy`qbl{eY7WzatL zaBf%YB(R#e5lK4bDW^!pU@Ba@HngQ}U+;jc8D&{O4CI2(U98+-lasoc`;m<|niso1 zYCj-`w=LHh>4_plyc4cb;O^Rr=L#1f{yNmGM1OCi+_UIm;x#hFn4Amprid+Fz<+$j z>@Ps~`&p#vLU%ftS4LxwcDNFiuS7DQ_>BSHeov#57PQd#5fv_nG{M&t8IOrLym;4o z2IIANaO892;Rj z;_6x$35KkXY~9Iy7_5h1*3fNuX@6unt=z%#8bf~Fvg#rq>RRMQxD*qtny+9hv!`+W zVlxi-;mZqJ+~ML-PeX2ZPWl<-@VbDxPz82r-NNo0BUa*ihUwU4B{+38lhACFYcfYX zQrosPt>FdMf{_B<$LoHdrD0+Ed$~2eZ&VV0T&ySkh5C%oyzm`jjyWrb=6`SigTQIi zX%Zc%+A2t&p%s3-Fn7vA#~j1u%PrG)dIAY2c&Ud7M=6NhHiJ)7A|S<0xf$J2FuTQd z1`kj3Vw*!pxpMp7`GcLOEG>7E?%P_eW1F!4{8`5O$f7V#Mv#&Fk2;N|34SaQ_$Z8n zTlcB0tq$CWSZXshtmo}>7KG|SKgPsH%KPrf2A4Th6unD zQWfA}NaTN#Z#JkRZL(>Qn2Xs`&}-euur&!S1@pUA>P%rNPwIf>ihpP2=<{pC8hj4X zE4!Ffggm9;L!p0q7d4#)q}?Nl?4;F!#I7{;OoD?M)%sOd`4vhr6^Y0J5oHqjKo3AO zRxf00)WdQ6Cuv;l%w=Q<)927tG_kdv@`TXrmxw zciazz3clCz17o+V@-%L}g_sSjWcw$X)+Jsq=&ob#zW?1MxDJD)Po}kKRA5Shf z^$Q^(HBX^5pJfzL4>JH=wmdV1&p?wEu+|D{y8Wd3#PB=kYoX7d0;39%N7BbX0Z4B8=OPvmO1|!wp#B5F;ey{N)d{ zRapQO{*~))5&kW;(=O)u8cBh7X zL$%(P%(8|y(+DhPKibY<@?);|T;`#Ftv|AKjR|{fSAX_F03~HNa)2mK#J%)x^3c(> zBzjS9C5_#cSL#b~?q{FoI!KTRV-&&h`5G}W>EedOYDQTTGNd9p7O>p!^z9U>o#cgB zw)7S*K`I&OVwwvA>B(`%Ds@Hj&7!0^?v$SzOM;<`jCxPjbtO85PYQUQf4^YhOMubq z(^frAF@N4fj>nFYUx-Lqs6=_CtVKb9Ekh$5G&mcx@DOMF@1(MfzFMsw$$XoQO z4uny|7YA&dx$SBuVu=XL7N)4@p)r-L1fXh0k{#R7w##{Azek0h+luY zwOQF^6kIOII<0Q72pq75P zA@iXPSVL@e2&bhMhv}WUQ9VU)qURrlp(!*aMyL6(%>Db63wlo^GWKi%EuS^iO;}E( zp;2^r=jqI0Dt5fwu;j<2x-!}qoQ{3Hb30)6?x02tspQ5mFaw|UQj^2(_e0rDekG!y z6@L$PLTATxsXU-^hIICWkfKz5Qg5i&27bCh1JTS6prk@>GtB|py={SInm?F4Vz-$| z_R%?G3ljEWpXcowjo?MAKEqN`WWF=Kpm}7yV~lQHw5?mVja9a7+qP}n_0}rewr$(C zZGL52XYJ%B`{tbav!$o~92s-;)}Q_fQu)>4pjB7zlKdW!3{6xG#fl98*pXCGSBWWT z3&xA>9a`s+luIGLr~wX!o0-4sUjP~BGTm4kCIRKo3H>p~IG0ag*f{jU{@FKa1rx+b zD4LBIYCtPMEjJc@$*6<9Sb;souR%+$RHaw7cz+J6N;inQd=lp>=gKyualj71Z7*8QW1Rw^*pYF@IZE8Z-DRZ z!&*{_5e14M@xH7_rE$cXm|=a+K0^Fr21V3VA}G|+MXG^EJa+l!OM*+p+bP#tQ``P# z_12-3%d4tQJV|*Oj<7$&t^r(u?Ojkhukt>$7ham2U)f>Y&Pr?+-^<9gl?Z8*! z6=yCX-+7+UHuM!|)NfN|22nM&-9#M6Nzx(B@cZUp;K<*av*n`4brgIKkm=j4X3diR zd+;~!v&RJxICB8i&X64do|F8A*XpN2ECI~MVC*aFVOm6o{|e5d%$0#b9j85Y%b z6hKC^BE3wuXweL7P1ZX%G#u4wD*~mFGpl)L`iY&4x7etzbd8O;ja_f*_lEKIbbO|S zIqr5U2NsT1=#RndI^FM)1$veae1gap%F!6PUlnyp&)6i!njFV(M#exp=|AQo^~DBJ zoUZuobW|GQVPa1Ru>_neH_it87YtE1+&2*z@L-9*lJv?#xyWn#wv6+hbGOZ;v7W40 z94y2SpL=u=`qZ_-DeKO^QPF-^r|%X<3Q_Cef;o>g5`|d1t+O{$94%;q`F2-M|HWl( z%H;D$wr~!vjh_0{3h2)W``&3&?Q9%^l~o8^g(B8B*e;A$ngsl3Y7a40pfCfRW#1s8 zU_)gl^p$jv(1Tn*)uj#KVy%1-w2Eir|?Te$Y zUUDMoD|&&Of~@|AMk`YN*$b21I3OmwQFW_>>%O@q-QQC(vjILq41_9GZLW`syRGCO z3>06W4b?g=^#Guw@D?s@8;|G7(h(W4f`SbS^sDd;ExEY1?Tp0Pl8>^M=oxlI_Le;Mk1OBaJZJ{-+@heZ{hRNq4Q zpnh0fmCr{Nj8n1ETL4L;#!4+^5Ej)-!R?_aylCIZ4g-1^+#7qgP75d`h^@}V+a>0F;Ya1k9@L`icXJ z6hugEOv>zUrNf+5^wMcuUF08DMV+D_TyxqZLNN=GAo_z7R*soIz0hqh#}=vfU`!HF zQfn=SL;&HI=u&+K&Qw+VdR1P^UA2MIG-dwiJ#3%`k_nM?M&MicQ(~z`GYC^T#J+~%MjsW*Ulq%U-ZrTN z87Y>RiKMkyMVXrx7=#+U-HEU6BzlgRP#La6D1i6@j^^Yf?`U^PzAjeqJIuMe?NV>! zcwP~*jeI*iIvX!_#8hU^L~xp#LhUlgP`JU?IlUK4^AbMhM?QFqYs=Az%>DtFPlYKP z5Nhyk_txxywo0;L|7A?Ple}@L?hfaLO?mO~%O$45_XD;b>hx8&G1497JfT%uckp}A z2>^aAfQS9BY`cPihM$1Lbe#5osGz|68n8nq${B;pDc6NXJ+Nt^LZog~ z+X>J)&Q7Z!ugJ^Br59)C*LEif$_2$5uz=hg-hzyho8?%>k?l#vCa3`5|A1{d|H3fGe4<=l)Fwv^l`3|IycAjrMlRA&ll1s zp7PjAmbT#AmmYH*EY418^b4)4u#R0bFm?OBUE7A$(PP}xqM1alR^M0RV?C-$GMk?41Q?s0?&-(_lqwHbqwC%ZWO_bRY1o`{)Z5bfJuf?t;*D(2~3;lGg=zNIq@Ll0oR3l zPQ|PjAqm8j9xgHq4v62{GB@@r6my_HbEs+V8u#eWp$X3&IK)}ATPmhAYX!=3NI!5a zt>ADiuDT(vsX#fT&LF-Aoj^<8bF;Voq`I&n9#XN=keHSB=!}pAW4&AsG=N2aOYsT! zLPL7Vc_zhj;P#%fJc=O*9%WtxV_nfEk=RM&uKlqWPb1c}KAI_3H6&qc3(oM$VvRnL z)O)fc+Q+(`6?|E!*j9>f5^0>wwn^K3D|9u2<`#5mF@Kw(M3rM3M6d5(pC!Ey@SIuN zL(@b+s|}vii*!jZLlPQ30q}h$J#9Kg9SdHq@%6I`chb=?`ra*nfxV1fph4{e!t7E( z`(Yl`YRF2limkB{v~L3Gw@Qy`XxIcZt_0fcOsZ)OFZ_D$j{e@r?Ujn$!ax;(If^eU zxuGx{)@6#z*EhTT^rh>=E%6I8)ME+)H|s8kwTzvwh$Y|J+>n1O0vxVO(nPCvvbS=S zB0SXSFD9+;3}^qTY-|f#oUC}AtbKs>3;{P%wOo#SoZ_{Y00Mmu<%v?L9IPpo!IxH7 zgB|+Ao9Pz%RPp{k(9-~)1ooIHF*bKqZzm=|J4f?NaHoxIfVh(u?-nVulXDxC3wWlk za9c*Aw<^>xRjNji0~m3b%r7zhd*{DAbNXeL{JlO5H{~{ToMu7{aPe)xO4e9*P97sx zeZ_#k%bEZoLR2t&RB%#FsuO3IOLJ;`ct1$`42PgfD+)O{zRd0>8|y|Fb;nodi9I0= z(Eqw-f1;PA&B;%ke|^1!ZX4X;tVK%?q;^LYf_}ri9(%g`08l^N;%taXu`4XJrpiF@ zbK!hyPirOq42w2Pp|!{i(?pP}QB;ojE@GZwqs3=?cZ#0}s8HQJ6)QN%JsjjeD#Sfi zALoDsAEA{U-G0^9h=)Cyw}WLC|n`t2WWE1H8hJ`JG zF5xHSZok84gUFkmcqrY$AmF0i1+1hC0g--U7=08*Ae`2sYKlg;_lRNf?aB`j z{my~S0N$c{LV+FN>j^%IMOWE)c_aHuF&XQ|vh3QP%ASc00kfi$rC;W*stQH_jGs~|*mQ6^e^4C^_3&G02L*R`N2x{AyD z4=~?|IMY#Q5RQ%Zuzh9^Spu5thJNGAav2vy0C>Sz^pL6agBWn$2&>lxc5=`*jrJgz zEr3=!567An%GDU>yQ^Y+KK-h?Rro@N(DHg8sTu%cc-sRc5QZOq{uXgOkkJ53`Yu}B zz~-i+#LdeyrXHsNl)0Y7DaU_y{dn7*lRA0NEFb{bCC}&Siz^rEpT*Skl^-G4{+9l; zsGeQNN&VwSOL`cCMtsDoSgCTkL@}T+3n;mfm}|czLm>x)32fdvUSSLOX93sSa*=lQ z`S0WLQ^2>?aRJ<*d`+tFU*5A)Apx%zf2_7HgdDTWyl^Kg*^HlwBpdQtn=dsI(V7z$ z@UdL5@E5GJ9b3HDzxJ&PGLWWg6MyZ27>q2-_;wsG_3tVwUNfA{~0x+$X zH=AHSt;~J43Lez})RvVqikfGMR`hoz(9Q`CZ%b#n=ry{JXN@h1&z9Z*xBSo~Z!IK? z<5x$~o)farpW#Wr%%ad5#zj3{Tugo?us;$$%{Sbe->0R7GL2$vLHxEXz|dJh9TNnl zM}vbR(YGa|=@c{`*|(s_{@G#z9*~Ox`X+=S>BgpVf$KR?a?OT{vhaDKCRc!(C4M>g zbZHvNTC$l3%85|NVsN0wBhL**T!yaeKg|jAXnzs%BW}f=5;1}dk~8pXJG|zJiwD$Y z1M*^EvTkjv+Vdq9buw=xL+pvTo=Hdd$7Dmj#e!Oe-;aapzvc-+%??40uh#C;3ZZcU3>z zz)#I^!0mvs1M|9vqLeLJ#I(;1wI!gc6a3Zp?>Jh$xuALzR`D#08L(k1$-RX$67hMj z7<;kp%fkLrB(kEVP|<~#1^8dfz1lr`w1nk{NX+{xC92<`f{_r|VRK!re7b#phi1ph z_vd}Uo$OmGnauEvw_6EU1u>i?diFj+=m{|fhUtt`kwc7(CDz`MBH(2p=->#JE|`HX zn!fvvz2ez;*P?L;TQWw>d>?U_Pq;_+4IdCh6!wU`-|QO?TzxD-08ne=PbXFa6>!na zS1(;>ND{ukI1uJGGjh+1iX`1DHxReIW6}r~BGz5B41!>~J7Z2b3bY@j<;aUOd-^~R zPH%u|8BE~2(f!J1l1ML)O=luZ+F?q}iTVnBi{`xy?pZ1tG;p_z8=b2pPXR2X?{Cv? z!oKze%fcKFd-Z7sfX0BV54&(Vw@if=d}oyO+IS(K7;l%xGU8nT#;^DKFn61uD#S`i zotOucanO0N$63@*D+&LZ2u{s2A5qO1XEczM*w-er2JG_llE`(pG*VZ%X;ob}AEJZb zE@cZ@jCPr^qn($`>QcU&a?Qea5-Wn3HLCd=0=`-2dsCeupb=Howk)&pQ%}&ivl&To zgT4(t0<&VM&&d;UNk=Rty9!88 znzH{h=G;v09R_{Ep6k3TnB1)|j10@_0fhDe*otR5w&u8b({?jD5jbVmqjERIvJ1*d zyu=$An2)RkfPsR|FoO*D0BT3*DxNSCJXQWE{JVP8OXpD3a!@F}x3v&h zoMi zHfDn#`e|9ph0X_k+9x=@`EA-5vMY<~u{*X>hyVbGWwDrvifS?a5=NY=mfP3UzhCP? z{oFPSxLbixH@KOB^v`-_I85p{tuc$Ph^cu`qN6;00CYO|KN({|mD+i3lG zf(DTlN%F`Oia5$@sME8%I1V51*a4Qe9vipJCehdQ3#fvtBBogP6QKFXkRWX@3B6NL z2;AJB%lU}hG+$=$_n791G7`u1^3$x5^&FoByj(XKc)djNXLMRj#Td!|Nm?@F!nG5N z|AaOyqv*J8Ig<2V*3yd?#W_rHzB*$I2un-?Eq7%jiOW>A^<`;?W*oT%xE%gWcgks=oZWn28UHT`2h9z0T1X&hD_)QMWi>e0~X#Bq*)&T z9O!}KYE^n4dHBZDE{^o{>G~EK&$;uP4oi0b*Z9c z>dAs~rT8v%9o9t%W=VBx*)zp?M;W*HkGns?Z?2)rq6oVleHBi{i(~CI@Zahtad2jm z_QTw>oU+e1{x@Bpi+r=~$_TOYI=I@LpQ(lWm^p7ny!)WkbB>rW8D_bGzeajaG6FUBR$`!+4a>Jmf41I8nPf zC(}-S+8D$X3FgxjIhPpenc^L_eGm)&(N-1UK)7_j3CnC?+Uw!_LK1Zm76^G1@vI;| z3YVcP9J!OK2t14pwSdgp{P=nRKmk?S4^$LI<8xqgK^U!PWpEmNK*Xf^Jcc#Cd`Bm6 zeADfDiVnydle%cZkFAk;&8qj?oYDMmLAYz4#1uhuR4geq@IP5K6@3j12f64<`acB` zTQRLSXu}M6Nl1rzC~KLd!l8yzQJd8_N}?#~QshhSqMtlUy<&=e;*7%IQv3^t@KF(T z66zC$E9%~%_5^(x=SJ~GVPt{|QoaF(M`=7SFFt1%P1_tsjOMRD0H6uOGME1sGr`K4 z##juDo|YdBi~*sgqA4z`omA%fOv>PG=IlTP!yxWp?<#I(YevY*@sAau48zY)`2PVa zSh@a@BG8)V+(7t1*ckuUrRk>;1sLUjI3WN3YBr|-;Yu{IHEZI6urdE{byDYCF)AC= z|6R@UuNobho%w$m6wJ(QOpN~+6lmbgEL{I+6a_dGfan)+#hi^*@JL}tkG2>HkAL55 z47i8K+Ww7v{5}{o{&pY_*c#!$^^I%Z()nYbhMR*D_+C2yX{HMurBuoamgqE|?B7I$ zms&X5=;>}CCU7+jb08KLToM)*8eX!J&Xy{=I{{-)X}SESsFonU+djDA?7!r-gcBB^x8e z>d&sGs@LYT{(gfgW-S0|dV041_v;K9z7CvIGb4Ki3`1V4F36)O&Vs5FkQtQ0HotNS z5LSHD>FDHsU}p02^kmFj?_lKS)PY%?2j#5>=+yvK3S#Cr@y!3Z%VHE<7)E&GU=jC} z4(Lp2nc8z^gM`&UM71CUBCT&>2i@!n;N8BO`8x}w=p2w4%_}&8Z28;P@U;i=6!7~5 z(LXr;pwRy7`HNs`_nX!fk&zLUQxwsY*3v`PKe&kjrI?s(;ri@a0-3&^^~=uM;N}Db zc+YCj(%i~S4}|-v+y*10Dgt$F$knL(A|F19sCI+|`{Pm_@L> zy#V>`;&-yK$j2_f)|Un3T|xRlBKqY00>Rq&xJ2!dPVfB5V7;oz*$!Yn{AB`;*#8}; z{aXu!U~XV0JZZxk?w=c57(g}zCI)_LY6S}X>Hlm` zZwCdgowXMf$OF*)BTzKe15MY==mM7t%Gmh42`mU1=a1}RxxUS=<^u7V&tEkFr2~Gy z9?gJo7+fHIbm|070XYmwo$0ZawX{2X(Z353k=&jjzF6xSz;M-nrh!uTL`J~@A9tU7 zjK8e=eaF9v)LELpW$gg5$?Ob@Z}t!BE6o)mHw;GtBxQa5Yf~W zfyw*de?sA)`$Hg`iZ1zQ21W3O#?2m%;2l7MPhUV72(x#63du>J{iF{7ohOb%Fvf@< zAzdKy27z$ge$pSvd!TgEf5J2n`Gi0?ct7bgWCKY0KOO};P|`HPFoI#?caUJq__t8L z_VF*FA{`6>sT^ZO07^A#@t=We)B^$7WbFs!-^QwcC07>!B+9PQ|B>GRNjCo@ZT^om zD-aH8Y6Wie?SufFvUx)w929MOdH{o!>Nlmn z={I$K<6G+O-z{VM_pdD>#wkK;EBWkiBaj;K7b==5@K;`OcHgtSeZJh+5r}o+2musx z{Tt?2P4f?G{56N`Z_?kBwtWT0*u7H(`(Jt}Q-I++0~E2@a~Sb|s@2_pY64#Vc}-OR zf(xP9{(uWn+#MJoEw=zvfLoSt3{(ZLKTtD3kF624y9B;L%^E$LSib%Cw0^1r_vjqo zR7faG|A8$u{o97`<8YFPke{A5f9DFCn!Y4H`Xpu%h>xH;G4Q5;(Givj%K$=(K|d?} z01U+#dH`jBwG;5B*6(e;<5w$i=WkWSpL|04e2=rdZo&)tR`P$-X)tiqCkjUSRap}& zlh|){3&8iz&yH_tpp>CoeT3zYH@|`Tle|A{Y=r-KEkcT(bpk5^x;=kq0b@UTpR?05 z*vl+yefp&HW^V>xYXCgKe2RHEf3JZ7Ks3X0DN*y|PZQK%$f4che%g~i_KWD=a@T~iKw}WH1hQD7t@qjiam=W(UpuIgtro_D+d)a z3gVa`QO97oi^0!c2KnAhAp*kQ0FNnU49*TG5*kdSZ67#EFLng=n%FRgtBR{NfYT%q zuZEvR_)_=^B6VI7E$d9q7+H|J8DU_FSl^v!Mps9U*j%1BNrGH)&?`@j3C;7uj&Tei z{Z+qC-NNmBps0UogeQ6Z_4qxcFPW4eg5NI&IORT`t!q}B zZM3(gZ`aTFoo32jh??+;Z-65juygz|sV+-m!Aw@&iBN0D!5r6aFEcJR$FkU@;#Udun3k>%1^oSExK&Yk!LM9?68-79|$^F)aZb68Wfg0$ek8Uz^iKy{z%Fgxl z>rh5wUPV-A(q;>JzGVe0?~UwJGM~@9#zeSEFN2;sRx;0F+?^h~CJMv#*ykV0Xgs$i zobk>15?2NI(Da~Ae1(jrJ{TeUWwymiulGm>>HJcE1JRov@YTLIfS+-gtF3w1;8?48 zU$$R9eE%477PL{8q*!M=YPwqwl^`DOw>9!kYrz50VzaPj9^Wf`yB9Yv0+lqv(#U8u z6{i<9JY|J%UK5dlbl7`qe742o5Rb-N0%?I<{;F7?5$I#6z*SO!e;fkmNNKxb@hH>w z(+`V<^^b=_g)sUjpg;jkYr(T?)h!v8%Bwhvwg8#eq`;=O z8Pyi7=pKZ!XSr@|J9qNyiuO@-4Ww4(b^ zSkDH>-2B@f(Bl|^ssB9_PW8-@;}3Ds)^^)O)6kW4VTQXi(TwT$v!VGK{cN{K3z6rQ z^xslS;8l=tFM`XnXJ8lN8M*yr;E$icevV7;k|YK;Zf-xGsC4az2Oifb8`t&`a;Cob zp9&=|f+R^MJ*A3ndQW5GIyLKK%Z}HB?`rAkrp)seKsNIv8d|G@MBIuU+ytkNH(xu2 zOMgT{`X`aECU3{R7`3|e6xtH^Z8*<{Q@5-)2P7cGdKFmr7QU@`Ixw6|ezO{3leu_+ zzgU6Afp;efJxdsL#F=W{oVDFV#bfIOGxfceO;tFB=UxT0FZZfoMS-_7@s)=PW*Yr@ zWV2BQK(3K&k69Wl)1t{Ih0u{Bc{0&;7ICV#O)<$C9z z&*_uiiwjfyr~Et@d*ESxcio)LvHW5WY#FBqYC$9MnvgTNB>$C6m1p ze%Msw^gV+6QdM+Vce6OmlmMZr9(Gn9PlhG;l1f}0JQb78?Jx-~%&+I9V=Mn`tc5hv z_+Gu?L#M$8f)BITdA^INR#30Ufa)j)P-W(mN&n}OFZGD*ENADrf)m$!XE87SuAt_6 z#eTI|i!jkn6kbVxqB}Z7?=_wwIOj9YtV_}(Wj7dKn?CDc`@n0aYF=-c-OD= zK{~dE{)Kb~RCPSoYRYjn6<5$O>e|ZxR_`I0(iIXXK8V4YZTq&EHA#NMvg`RT1Fb2Z z_ejCmckXXYR9dr%7b#LFqnMA&>;?yS_NY~d69!wUWHiLTynL)feU%-aEha8pr)I1= zxz$*DdwlxSEcnNHlK|g5gCU=xo=ld!JpJP!B!YGy z8ksR^4QVj|Jc3wehHg=V&hT;WFcRo<<}5(NUX8mKY3{xrOmf*mPtZp;r6w)oNJ+m$6AQd2plveut=v!$zJxphb6{N$_)+=BEo7PMPPOvb3_W= zjjtK8VRIPwEU#rURUdZ%FC$8XYz13kD0!J4-L2{a7qpToB0;8l2YN+ZK0$ zTD^z4M;)eHgcB0hmcb>OBbWa%JNDLGD?hGX^p>&Q72_j8 zUyOF#i3ap>>{bu~#JSz{7rgh?WU2V@+%tNxrLD-2LtCMQrkO|=wGoSq&0YoTnxDnj z%hF9&J|Y(O8}MJQRU^ipYCPj)D`*K!T!pLh)KPW}b1J6StEkmW@adgN#SF+=;sg_0 zt!K3HKACUk6_Fin>{Y7`|0tu>idXEGuhWmEC_>7VWp+3MD$jH?zj>=&Si+r3kHDTT zs||=nX=6Hc79$k>zrY2kplgYgT)n?>e3)o37g^$n@jiPCw2*W)#5_^N%)O>k8a-d> z=*lGO0z+*AE-qdEt`z&x8}scZ%zk#LCG}!F|4hAZ&H}q+WyrpWzf>SKK7_18)h}BO z-oZnHn=EMo?$~A`Mfsf*XR@j=LkSw?I6ki8z8mJEPc9?j4K?JXSz!kH;68XI3cG&a zsQNlqdkuzjzoN*3h=GPSPU_!CKw>l>}Y^lBc$LuAa*wJ+0 zME4keHsrR$;-X1Ft>|1al0wIqRziIgH5hzQdD+Tw37$G_oJ(^+x8-XBNmj2;O(fPku$qzxv6>R<)(z^M zcu}BOj_xi5LdXO6_{{gC+H~FmBi2108|4fbFuH;)JDHJA&{RmVKkg{i8O5QhcJSXJ zwJuodO#{mO5{@ZE#Zf&oX>0BSkkB*iG&d-QkhH4?ey*|toNw+H1K5iov5(59?jveI zA=C(AoM|3L5e|}Yz`f249JY{Y~T+Y!|{t!gt?D~ifF>rKu)y6kIvk#7?=jP#vkd|kZ zh`*C>HK?m)?~Z67l=vzFeou%IQyAg^zeT8jzZYwD;;U-9v1A%wfC5ZF1n_pLoSgd4 zeXQc=?WdbLqSA5n5RDp`W%>k|9FKEwF2O*yC^lF_QWoY_buOkh%waSS-S@*M@so0j zh{OJ1wy(l6Zl;w2+^mL3wYh7|WnQOj@w#-fLk(W{`-Oh%U@T?f`{B+tGvzM;=S=IM z=YQJauCizKM{N0X|C|(PRfy_sQQfPw2K@KX9t|v%kHb2J7x3lXiZ=t}rK>=uyIUz8 zX2h^=F!R1L6%3l6UrnOMB`_l~4T>#c38cjpR0JA|he|$;oZj5aB@%-O$V;LOkKZC# zSr4QVQtg|Kt6m=Okl~XwfFlG|sp%r_rDpqYwld z-R40Yl=FL~1Kc5O=qL;TZ2H-)YxfOWZ03(GerNKkHrqe?qpka7hE=()b>|&-=IR{| zPsRoV&VOaMsV&?nMo7gOouC^$Ht6On|hIglJ->fk94b zK?8Wz4ni9QRZ0TUu$@IzPC^bQrJq`O-XgkO8Smf{T;7$2F z&#|}0nl%<^dJSfPJ96RdOrWO8O#Y5ilaWkLGHzIcD*LqGBeTo~Y9x)y)t|vj_3gJf z*f+YDa_>}}Pst(*Cm{g|%TB*2Y8iYQn8LA0AxF@IJQ&1Lnb5sH$%&l@C*MH&do1qr zfbA3~_YW%N0dpdh?usDuYjwQ!w%#qk3ftr36HjL>%LOtZ;cbS_L3lfoiz(WgYM7f) zYZx8=KDgk5gpYhC&ONCzF~PlxK!w-a<;32h-Wsx<*ICN5z!LP|oGke!S{HsQ$poD= zk+;CE*C-Mvdp^9VX*L!-Op8x2l4{W|NPmD@({&?^CF90 zzaT()m0keWErJ84HyaY|!xoHNOT?dqYa1}<>fQ!`vEtamF{oBN$Giki=J7d2cuWDI zuVfYsFf0x=#TV={^qe}6xOP?OmaaHAUzTM+Y@ytswx<&IPOTzq3sjNL^;aiy=9wS_ zW}9v;@Y*?_i=CG(mr*0`??R1Kqak@xAA!i{f=y3NrT51UiQQS3(bN`)JCU7wP;cB7 z`l1#9Rcs?lLo2jrN&Z1FEHoP~rpX2{+_hL-Y(+nylIcLUma+Ik@VMKeu^jH0fcG9A zR`tNr(Ai4~hw$y~xIqK!`_WHQ^i4BS*v@PLaX9vGD;Fx>sB=c^u$33i1>?~@yVabl z0Cvq)B@U+ZTqJ@M9_<0qvO<;`DRJfP6mb}!G2Aupg`}&`wZE_~A9lN#3gbq}v6G|x zpz1PTETQgjb+W9lK_NAd0Lm;#uBVT$=Mn%FKg_h2oM@0=#?$XUP?_pYx4~>`UFB+h z5%#A8ye$$>w8GzWo~-r-0lm%@UEH(_w9vxrjDVUJ8g_I3&PEISmfBSurk4&Qru!Y> z0NOUoI%0O_x3sm@qV#1xIg(uz=G0q(7zIZ_thwLYJw+)mt@Lsf6iJ?So!pf}mM5#q zU@4Z`?XxV<59naYmI);s3=`a+3ckGOQwI;fLYDlI0M{#P(LJYTgv);NNa_$p zVbn#ggnL%g$Rx(2Q)26qA{T6g@&`bt>diApmx zS`e;CWrP+3t}2fW=9f4jXoBK_Ftu(@p{Uy=&2tL#~*UeJlbJyBVzbgZVN@X z0zYC6R?J*FKMWYY6XS%|M-YyrF$$|5)iC2e-0@#I!WVp<+#2DaU9a;L^zW5|C+SS) zm@l;6t!?U72)?!$91Ot$xeNf(KMd3_^14)hXtIs{(I#Pcf~9kXiVR}#3@-r{7cTf+|u z*C}(%D+3wx51O!YET z)lV-*DoFU3Hdb(qEaU$Or7244vX0|m#C#+u{6#Q#oRFTVdjOdIhW+vfryQ`~&n~>3 zp9LHeJ){s3JTgnfWhfFeUP@e=pg?NkpB+QP6ZqUR3CObr*#Mgr<*;1kmz%o@mPK|J zNmmqB>U%xqB#KN#rJ`7%7rnP#TiP?rRz;wN%sgxz z_A176`KyW-;})uPl1yvu3u#1?kSpzGP7x!;bzrh~s4M`9>hzj-!r|?XqYW0mjI*tT zoZA9h4lw!mg{1tBIH4v=0PWn7Ai>qIauZ8)NrHS02oXb-Kvs7k!K3TzEq+$lJGIHXGFm&Ue;89<%g-0}H0%H7KR9<7-nW^_bK@>` z*UQ+8q)Lc9o&*IdXGE@xNmc(;JbmLwVB>gy9Y*Pjk_`v}7nVT&4%faRM$#}c^*F+Y zpiQ{QOLF?xV*5Vc;+`6GgcNfhQYE$sY_vcCJWe7Kx_>g4B$XqLNxwfXigHoi!g3?; zX90#)i1mCg-H1Zqzq_C9y?NItjjP7W+Y!Dh2D0Kw^-GX88jHhS9%K$FX->O>=6**D z$LV0c8T=IPwzA$MAa<9u9#ahEP2!SJKsjF1>`kJ*dnld75J^8N_Lj*lQYO`@pRiMJ zi-slBDoy$+3nz;Y3I*M+q-x<}0QBG-cEC)s5qodhwK(+>*rBR2|EA-8idk7oD9_}y zo&v+N{ZZC2& zR-x=zH)2veG zf5-e{0k8!B^;W-tIirCbrE%n0Uh~4usSEA>c;G|kJEHeg-IV zGtVC8G2wHOa?~aLX!t4 zL3&(OZe$Or_8Uc(mQ^Hi!}E+q4q)%1<+9o0)y_B|4E>e6)%9!YW6x}R!2+})HJ8c| ztfRCZflrF96FLH4msm-7Sru0TU(Zg?Jr45OG+5v*NgT~1Nj!^&M=PmXWXmpgvir^x zr*yIarr+{#Or{1Dpw+RdqSGn&(c$7hUsMalkeA@hIO}B)fvrdsKo6@n3&>U1t<_B? zR-URQViwrx^P;6JF~wnGD+&yGkx>FOL6i+-h>W=7QLz=omUWtJIgCoJ0k3%|cH1hs zUV-^*qo|fQnBHaG1RoRoF41d1ISI^LH%Jg(LU!ajF5N>Dk7M#LuE(NE&yO>p+UMyt zq`oaJ>`_9O8oXk6X$Sz11=N1GkI26yC6j(k63vtnm^e-?t~uhquDi6JKK;kAVnNK- zFnMA;?ySPQf9*?m45D8Xwm@L^T>>M6%O*?w8|ExgCj7u-rj1Y{+y<@MHrzGQ%8?Qpq}soadl;3E4mP)5%1*^Rb`zYAWq6hvf& zl|qrTSl}2M%ksdUKw^7ECsE8lFoa;jUpsjv5r{#U zkXb}eE}kS(RWOgK17J!pkME8BWeX;CIzfkkPUevMOy!NmV8AOFb61`LMnuiQ(WTUZ|ey+gP);O5U^VviDcFj6Y0eaI- zDjbyMnGk-Iy$rs)Nw3`9f#aU|){tjYHrbu@Wjp2_ht<=ZH$Vwb%>Kbdw-;4qAY&^K zB%ChdZg3W~R!t&vsIGp}dL^7*fzeJY$aI`$y*pVC;|3hoU5|iFiRXT5twJAfs<8#I z;MP-+UP2t{Q!lC?;x225FMM#%?%VaE`*(4-gY6Rwi|)*#Rymh}cF|u=ggiebgKUjY zr$_0o_DRntCXMeFM9<6q}S#L<`Y8zJ0zHl98O+~XYf`bJ@jW)Gc~!yMAa-a2Vxvy&#O zlK1?31Yn_zt4ZwbYtyYxI1&P{9od)%4}BFuq-@$J{Fo5A9ZY#D6n&mHpUP$hT}Fzy z6B4Ieh0@*c63lPckUOj@8_M*sCT%Toe&YdO?2aC?{|whPdnUMDQ^cQ)Y))Z`f5b~? z%fgA2SG1Xp0g zg8^e2*3LSi1KhEQU;I|Vj9oiDe4jbQrBN{5*&$cJ79pq4peb6pZN>!e!Cf5~X- z4?qgPI+wT@ER9vnKZ+$xm8hqRwMD8$oZc&QW^hXT$SB0d{iC$m;i0h1{#I{$czCA; zJXS5(MMsezDHdp!XXV7M-V?4>c+3{_?wRyI(fCM$$VU32O2Jc9>eyc#sXwR7Lm(gu z*xt?SA*CkvJ_OHKwI>maNOGqK+v-IMC4fVg0%zRK`-E24>E?KV|1{BO&K3Ja{w?&f z?vrJVJ|R6Pe)P+n2yIgVz0$_E6R&C9*Ymdeu8VU1hpIC5+qw4WJMe6|2T9G>OC1oH zhp1lgg$si)gD)ecoT;lTPkuSG*t(200%F1vKDcQ>{R!rMelaDwthRNk>D&Wu5TKyg zgKBR_Ew7w}X87d=DB>3N-z+Me>{1Rd62ql7=U!s zxHkLvU3x03ZKN3_qwu_}(d$TF926>QZSUaoMTh*I_59tlkQqcw4t;+N;jVVK9%}Oh zO@|^%;MV`V@C8?dMH2UvS)rEug+cYT!5mXchHe@mc_W_SV~P-7to#fT`+&*+pd^K&W=ZFy2f$2aT5cGA z$?9hZXHW5M;v6r(nWoF0Who)0tna71qnIk8f3d=zA^FnA@kwjoxhyUd^!gQ9T`Ovt zCn|V3Z7a}wc^$>b)cr3=9_RX^Ar5+51TrDhyGuXM5DQQ2-?@g^@*-&JwjwHOq@=UD z7CBx)j7gk}DoWJmlkMM50QfJ>E=IKfo2}oQp&^z>uo5m6DZj6-3305YaeW`#Io>kE zlF-hZ;AX0+el|F9n~gNlvFpe@@;UY@i@`(~_QnFwRPpT<1d7A zfQiXi%*Ob;wU7ZpMa_zVcrJgpjH2pJySQj%ruDtt;#Td3gUwHKwevv*{q2XsO`Rg1 ztjFvIS?vXBGuu+V38CvC=UxY&NMbB>p~6?y$jRYu=OdIt1DI7GR?zM={1=C9cvD3k zHNl|R+a!k`2`nTfz7Y4TeoyQlOmH{ityNMEy-jkO1sPM$5NV|K_q-f`h=MbfQtloA zV@E$0Jw&hm>j?5q8RyErS!fzmvfevg+xk$U_o#Y)RjdGmZgB6nXmer4PoO_Ul2oi) zX8kv2p2KN679awsuG>V-T9i~f+!PWnd`qc%0zM~FQA=FWl%7d@$VzGHyXhBtVs<`ebIUvg7bhPq`kt~LVX}9ikEuAAuRxJ84K%TSF4%(x(LIC$VN}*puGZ%ea ziPtMt{6^)3K)SzKq^AD-TqK}YUkd!A3V#k~9){WcSq=49dxuI}n z#~l12{n5%Cm4d7N>i4$mZ$_73EqfzO7#`CD4m!phri^nqQV+r>BKw&? z&iEN(3>dyR9p*Xog3o40#I=u#5EkIBmQ#M$&l27n%Xe&3Nd!YxqsPxROKEcFC@Rc& zRZov3{ttc-=h|Y7l1S-#z9GCDpao;XFqRv1b`&D0A8OCAz&Smvl8 zk8rPirTC8>fw#pe?m9)7gd%x9)b;LN?6ODS2cSaZ5rUWT98AVRE;ZBwfEjLnbbEf0 zcs^6jbLlS)M>5T9wPxzQM|hqwRBM;?@6Ym!Qpo1ENysf@Py{@K(-qo?vE}ddDH775 zT`^onE#t8n-Rq0$ropo`Ru5(AN5>sOkW-Q{-64f=qJG7{qxZY$zoM%~ zoW|-4o+sLsies?h_;L+Td!n>q9a;LUO^C&=ywFtHs9HYiL1m@NlpUD5ZTG^_DSK1L z5Mgy4eQ6XcvB3Qynyy5cQIiq6|5MmkM#a@^+tLIH?oMzI+B6oN;2PZBA-Dx?+}+*X zU4sR8cMI+k+yalB^X|LnoE7-mkZvzj;>~@b!s!dF_F*U&;icb`GRNdD~a=AXshG zIyB^L8Z|LjfMC{8ak_a2n3cz6tWUO^gBOKp40pKz>7y1LD1upK=34r2jiS=_hI@3Q z<8QyR(RDPPzax@^yIr_`N$smAF1(=s*oVus=XSKPTR`K9D^3O5|v*LYUZefBGf@RkM_hE+eYUc?A=LOh)mQY^& zc1-=ez|$EM4mFb`4ho! zc(&;~)qWX=e7U)?b>W&by*CNBL6Trh6BN8V2BW_fZ@AnW7VLj)}i=QvnRW z)ni%It`V9^Tu=N=*A%W)cs|97v&4{RuHb1ss2NW-gC>qE$2YR-(Rv+s#y%?m-(wE97tI7;mc){vkU z&I)njm51vKUH7PMu*zNQ9L-}dNs-YfHm*k?>{q*n(C5-9e1f;l@M@FxgcwpYp+)NC z-v)H=&h%~$JsZKTaz+_XO2E0o^oyyViXw$5pPDk95o^cDJJYrO!nLRUQZE9o?VZn~ z!oaHKS1ylJ%9tW*H5}GW^0d%He*6c7z%%Zis?xQsATdMkF9E-o)AUG7#&(BIeg%9x zEIy(2S|pZTNqw31kHyhnL327djB_wq@0}pdxk*T$$2?n`^tL=ZA?T8dx*@<{CB#4H zRz>5DXBM-N6WlC1o69=(m$h#*W9eYWuL2wFQZgIqTg!~Xl5l|uCpM2wA;i5f#sk{z z8WT~s5XbXHM ztJm_ICrr^0%fTp**hmNBVbTT;!(CZ%r^$=J{R@owc)2OY@}|3>J@S}K7!N9w<>89* z-PE_JXx+MN`2p9=>`rg0g08UQ$C}p?_2rV!t{jMT@NBCTUsfjrsHB34*F2w0NZT;V zrde1r%3jR%!wcr6B21h1TbXruX}Z9$2s&hEY=E;>0}V$OA^Bs&Nre8eD4eMPXzex9 z4n4(yUOJ28Ty6*h@#LjL_84mDS61YKe?@3c*t- zCC2Uee&rGbZH=R0tSRg<@dXLLUv$b4M`ZeWQ%9RfWXSKxag#?NN1!L`7}dd-zqFeG z)TTDA21a;M9Tsp6jO{*EMY{2q#}_q{F<*Z*mHwV8Z_~uAwm4zAd;V59F~5?IarlyA zd;X}y?_?MFqA=uK$hG3Pg2`-Jq)_g;FDlnqa;9AbL21y{n)Iu?0cPo2Tuu0-e8=UC z@+SxTt%5T>58?_n0-n~+lF3nU{X5ngaS$b$wB25=aObxf+bt8;gg_nk-nMouANTTY z*YVc+yJl_;jYOOLxM<=o6`UuR3#>_O&)Yk@6qSY}b^XU2-A6Oq9u@i=ns9Zh(_8lp z7MjH$NHU;^v&+<0{WZRX5!kd^?X6g1HY2GsQ*g_121%9&>UE*?38Mk{XS(dY8rR6l zofN3mRVl=^ht<;0fS7f-PnoB0I>Wo`M8JPiFKmNv@&`**l?b=t$LOn3yYE_}z><^% zzS7e^k&qr8uAYjfBdthj$@32!txFR_jR`xGdh~ zJhWr`r^9g9Gpq2Rbjlfn^TrrG)sG*lo1CQEZ4fk`!@hAbF%n-iUjIHHAA`=4fnD?0B-+oX{F;5?!{*ACRv^9g4tH&>P*jO zoFzuc;f2l}k@z3y;u??glHB2bAfD%)HX`RsGm|Ih%Qf?VD+hLi*CZ2jWG-gpo~O5= zFarh_;P-~65q?rGdRblIgmZ#j-Ksjm!`Ite?#9#-fI#JyHPk};cGLWc4f^|y<7$_> zh#Y@X{860v^o5(D=VcX;hq!{D*yMA$x}xNd;PgaYv6ZJHo@q}b@dnpKzxH=^$3QpgX(GA?557JNrfOTiUGR0TDn@zJ-tf%6R)|%Gb zCTJz5u8qm)@^SX%h-=hUQkUKC!Qvm2=<_8(u{q3ZP&@54Eqk4l*QE}Fi6g~?emgZ7 zFrULn`Z>}II`WZPEG9o!c?tMdH0XmBUaIrmO9Neg9}FtPHM)}au>dIgx%Xv(3{ z5v*}wgH)5i^BQXcQdFI)*5vol$Ue2X-ZC#RERvzWSeC&XvkmU`&)UZwP{fUONV|=$ z+Ult)X}XblS!~boAo6{fAL7#lC^-%=&~>cjtIN{o?V|Sk-$+TbUYq7`du8>{q^X7% zP*4&Sh?`7MF6d5n_#i6cLnV>t4zc-fy7x;5${@DDz5LSt7~~$^6;wNR?j?qV3Qa|O z2N;?{>lVSsuD-VfGlT)cf#~Crot;8LRlAiGLZZ6q#Zhw@Wedu`j!wb9^xCf3ugz=P!rTsjWnBH`7uOdI2VT@4(@^d z+4Dr;@vy4FMAWh+m zKEGYT{BM?DrwDxxpv?m;v7R)VYI}fHZ9efON?vyi{Njzh{AYHs2Mm%a?nRNN^AT5#S^YDq>~&;plOf<0@8uK4>8Yz>GXwimz;51hS z7VBoRXmZ*mXr_i^<=B;Kk4S8kaxmX5KCPeEb_^5S?m2eqdZP$DPs6uS-;_6lKe9vr zZdfz~q-xN`BpF!FEIdpd2d#2Ljt8GiLU5KD`CZ+g)Hnv6MY2B`BL#2NC zZ`U+E#&um~7OH*d(*Y^SeElBm53{w;TnkD0{OyUIA*iKdUC@LnaE?6KxPsghT(;Vl zktbO&!e6==L=ynpQ}tBq#jx89?z(Us>r3(itL>`f+lG&rue?(aD5cB>d66R!taGaL zx!nXD*K<&W20x{Ex)W0~&AdA)2UN8hSU4x{;Y^`i)K8!eBooN%#4?VneWsNVRQwtT zvjS)wfOL`1>$(EXEwxcOQS@U zS6H!uS0CCIuTWo!J(OHl-3`WU=El@ zLUI*Vvyv{<5iG~gdSy}emQa1~tz)m&sUk<8kT~h}0HQsHik27=$+13>!j;*r&NcYO zkg^y~m7X#}HD^`ZiG>VcDugFAu7llm!2Dg$c2Fh(`bZ5d&yh;;bSS|cnzDaN@Xg)$ zvl6666fA3t(v>{n<^Y)^5yLR7FWIm7;R4Y z0rB_-!mS~ENPoRk@I>p5%j}f2M6Xd4H9~Q%G_1EEypW1J@i}pfO3h5vcIJ6#vc=ZN z6rL*?%6jrT>xaEAInsDAX55+eE4T>EN6O2cM`ZOG-s3H8L zn@*|^u`)Ka`x2>$muQ!lhYm+`d6YV2LtnPkxz_ukpzw#gsW$=Z8cWdK%cGC@jvRB3 za;8?K>A>MMEjYufUL_ad&{bpqwInrTiZ{o^Q+5-u3iVYM6XnjW?IA=2Pc+SaX11Yj zFz@5stSCrF?;2u+4jAB`H7cY$lh;P^!P#F}#VCiM@mMu;)gxXDozz-BR%!3j76Ifa<*GgOX01cpi3SFj?*!)e7+1l!P|aZ=UYLTH2s zm+}>Saqs6bqTNhik^%zhnDde#sO7z!K5Cj^@{aKoq>NQns}T8+W6LY=QkiBNn&d0Q zumZvI5cNzuzS5_oI{jYzf-I-?!7O^Z!Y3V9AoRNeu)@+8Op3%~bBV7C=05ws%ZF<( z;Q7@F^1v3*@5p6GQBx` zNQFc&{|bq9{3=zs)RRSeaIunOa1|w;sP$_EQUkniA?#o#nC2?w zM>v?QCN)(-;L%+54$Hw^DqnF^0HC;4s*Vyy&8Y z_gBZ>prLP40rQQiaz-9annaIBLe(-Tw)i_hdfAXwC3ZLLOT4;~GyINNngwA3@sW6& zqKQ7@5$TeTSxg1w2q&Vh8NEPj1z_VM=s|aY;cGFmAvhx`OC_dZLqD zC50;P`LrY4F*+RA4Zri@wsWAvX0wrc!K>z11fxQL&`+taJ)vY$HbTltLhB;Nm_dz` zT@jXa839r8xSC_QKAL4!l#5G#o&*SaY{#2K-FN&fXe9eR@q$RNU3%-LEQTc;+j`)@ zF~QwQ4vS#6^d)g8rBc({!+BUkwL{^T3szEEou6(D41R2n zGxT;xYN=#ls)QiOjUtVEY@4!qt>r~>5cnf0is1c9Vy>1e5Dbvu-S`rs!pJUK2`B9K zrP(yI=<6aU`YF~bcf^hcvQagw7fBj8QaH~;@Ddjo{=Dnv;mehRY00$iggPP6NsCia zoRNxdtoSLFq4wePvn%+uj7^Ih*}Br`_wnNHEYW?oQ8agp)~lxFRH>0|?ofr5d)=wJ zi@~+}0EoIdl@jV){qaU)KhM_vS45W-TeOTm}VOoc)bw& zA|9DrZ>#5m_^H1m!)HVfs1Qb}(V3LU6yIn#Vy^CR^XuPK0AUQ@E3Vd~B9n ztts{w4vhOKTFuBcMhv=wi*m#tQn*H9sk^QrpXUoLIk=>E>U8Aa2NvtGD;4;E8*G7OrZSv|rSf7nXiDo?LzeWk+lFdJs2@DlBnElJQI z4}UzlPkCw4$Jc)mQu)AmNXNYyz(j&5h}~>O3)QmJC1u!t8*#H1S1iB~f`~RV9|-HD zhb%%%1{>2kj?pH8ERhFHxX`GsYzfn5jwyeR+Bp>CY!mWp$UvCAcc;z;Px&4tmHSQf zx^luzrce^m8{&WKK@|1fA{~NRBy72USN+hIB$-yGYj`a|64*{TpxEErY@I6jKzOAEb2*`#w771Q0*_OSE+^J1DGqPld}NFCx~V7 zFt*wVObq+9WhC7-kK@vvccKJ&wUH4T2Dd4vD>N(J2H!JNoQ!<~SL3W#;ciXFxWC@` zoWT-KIe#9E_}7C`PEt%1Bo4-r9J3MzKzB4!%G z50E0>ca|eU%)_YQJOUO)I*8?V@3rtT?h;+7c*IhN29epTkqJEv-A`(Pwx<&cG|^ij zZUyg1H7A!S`=r9M_Euysmf@%JFjO8{%XnM;?1sUV>#_42L!;5hSJ@rZf;EvutcG1_ zJU$b#3P?(HICC7!UsOl?#Wa{xT?HAI+rc`#?G8DI-1-h+RwVYX2z{OM`{9A&Op3-9 zlfs6|DOETRbji^IKyB8I(L^4v&DEYLm_|o?Uh}&|sq(Ep1eg|BFb2Z*OAptm=F!tD z#!mv`9b5lh@+bz}(Ya%Eml3Nse2+vwiDGQJYIhZ0kWnTO)LyKx zuml5h-xJju%SHS5SL;no`JK0F?Jn+s7;ZfZ86x|$M1$rXn zqIOecv)n35ehLLG*5@hp;00q`T}fgM(|rts^?x!%Vi^7qE^lw^u2jXAIN2hA-&_PL zDz%5Up-I6!@p;06C1TgNG|x*+gv2I{%BwC;bZwS#EcnrSIrC$O8_JaaDsqacoJxKL z(2y_>mJb9(Ei>E^z6NbQRWzxNp_lKkDTcOmx)XiBvs$5t=~uTrY$iiLB%TczS;}9R zWrzCeaQbCxK|h~#tn6K5gEdWHEJ;GNq@ehP7MrwhY)|Pz6axdLsABs!&ju?8;&5J# zBZuA8s%-os$TaLskRg&Jk}5*0qtBESmB<}C3O5_o*x7h7SLvHuyx=SBpj z2|mZ&kbf_bXJWKG?M~#@U=txC`U(GA+qriggSaK8VxtQ|p?iRCJVc*CK~IxV{@SFp zdA0FH|%7FcI&q)|U7@9gwL4idHM!c|l~T6pG1NI1l= zTvB4FilIT+kZJ~qZcaL~kasSmC3MYS(ZR{3OrG*|VX$h}{X~qxeiAv1JIPE|~utMJ}TyeT&!D%+#d!QRxS}Gl3ljZ4y5y2apTL?xt z2{W>B;cG5pAVp6LjkDNS5Xd+O7 z4al!We7`QM&SlyfgSgD(3`f>bh+XgX-!JG$D}2n}w&97sv!x4&giAr=@D>11%-*O8 zR&U;j?bNxG$BcKRES|V;bhlhYG>PS6NwnXo)F|hx9&Mp>fqP)NnuDjx%_pGS-SnzAX)uu=N~429JT1bxlq`d3 z{+SyC1-IxEwWxDKl;dlPVB8S+(Q)mw3!OrDTgcKd&254_rC!c{MMD}jp?+|6Dtt+) z0keoBX~2$>=apeRdq#+8i3@&z_JX#Cv!K@8D+AsM~4(fyQ zB}~%%Epl0E#7Hv?1$)IMfsgltrvsjB4h6lVd1uH4;wRw}2fULVe^M}*Z>oeQUzgVp zsWs%(aRl{|j>#nie|g?oJ%h*p6`jt%Co~s*!#V!q7kV8}H)`i5rhk_he=Q?YFUBBj zrEg1VyXEmJzE&qXdDIKhJ3F4+47M3<&j5*;ZWJAXBIJ@tcjjZSoL4~7{^!VnkV{zi zp+oJ*iW*!(m^0dGPY*9JW4D9?UzE{2HzM(|x9*$@?de3|{tdCPn>{l;>$ZMBUb_Kg ztuXN!3M7iKW^l>Ob`MYJuA-0W!BZp zGwFez5^x-O-hmj**7}&Z*CBC}Vu9OOC|I2RTlr9X4o+tJW=X5UV{F=qo2cc~&Y%x2 z+KKqa1IqFA;znSV_uVTm7{NgO7 z6pkseksSoB6#)kwyCxh3vJHHIW$95^y&h`dajOmvd5TAf-G4gy$B^#^e}D^;A;@Dk*OgadMHcms}3 zY%%?aEqq)(F5BZ!-u)#L7=kC?`L$hvNkmqc(w1GSCf%ZnHvy>hpVW86(`oQj{BEuXlJl52(Q@T4 zp<;XlyUwM)=cNBwbM}XEPd!+rv)SC#0P~YLM*gJw$Gvqsm zDMDfhwWo~gh^ATtfao5XuY6b~raXZdsso2a9{kBAYCy%mM_=7^McA>tC>jspz^$6@ zqD2j+W&AZ1HIF-;KFhl`1?nOY!5Y57xj3@Bz ze@+83wQrF4dL9s4MBO&)v$QM0=bIp>Zd; zBXz!}Cqr-zuLRTDJ?mN$olT)r%nx7ueti#c?je;RweMu5jHe4gLC2sSTv+8aBvS{n zWBDsB5ZIYJ5mkZ;DDeW&PGP-^q-mnT?o=UAgZ$|BV$swlq#S6ATrr13V)y$z@ptL& zKTLVnV=!*6u_>YO!Hux_#F*&)YvTG%!!8Wo^h#;S1>@Y^yk{IeC>S(_-$VVQQYQpL zl4zcToON?fBr9G)<-f~|0PAe0Z`_@W^LX68ea&T|_8#Ucx7tV(KcoC?nFd0^lIuCX zvl-qMoaY8qaCJgt>h+mWu0%XJHr87uKGY|noxb~M)5M~T{4&WC$p;x@huBU7885D| zzN?1i_7^diAB)SG@5&oxBIY5;cQ49tExI6OO(GZqC1oF_&`2@fC41qgBVo+Mw(n%C z>;85aH2bWPot0L#K0>j73J)s>9uW#)#4fp}VmYeJUOK?z2Gq8*10k&E^AL;1iJv9h zx9=Bw6AK{t09L1yheVu@C@UneToRu({G5z0$QS$frW89}XAeo`LEf2kX^8-9$|c&B zn6QQ<>PtAQDL;wod*|&5zHR{=&xqofp~LpW)NaQ*gw~kpZ%l!+?#f8u2r2IkXK$}s zIRkDht@dE;A@0`cxb4p8M<}STcxH`+{xzp**DOelGcx?IG`68(e!qQ(%L>E;1HyR{ zjio7mKW2Q#}%R#2kepBqw3zkwBUS2ME_={Ln5g+)k^*KlE3GUktsYiZIb=#NW&2b;aLO2n*x7 z^(%G!k)BxIpy9G1j_y>oKbw4I-XEhp-Uj%HP;N9IyUvip#nYj<^XSc>uL==ad_3Sg z?*+nEAIJIWL-rM1wf!?wP)L(YAe;fE7C^kb^y22Unu@T@NpidlmKfaH3Nf1vYxkkE zZ@ZS%23<6*9m=%Y-Uq@+^150Utxd8V9mI{VE+AJhbBVmj!1(Sc*yVp?48el7+%|Mc$Z}kLGKR zQ;;$MB>5{X%~ty+Fa_~!dUHcQQC*yJ*Oyc7OA^tLYgZUTJ7^cIeCSB_DEB4tMa_y_ z|6>DaDVUaXB-$ru8XXcL`Lu?SuG86EqjqDhRV4K4Yus!KIP_+St%4R98NiwWGI)xS zkqukU>7)4#@t~B|$~U((pNz^#@1VR~cQVpLcmAu^EG(D_Fm17Qpe1)VPfjMp$lc+O zwuizwy`PkD%XAp}gz{Bo)YBE8T-1NI%nxA}Pl?D4^Bg#L?c4`$F7njGUekEX?3R`w zA}}>0!U%;Gwu~_L&}R_$$--$GHwfSP5g7)s9K!YKe0{H{Uggto5#y4e%|qMDc+CX_I=7t zz0n>$z|y-4dh6s)F#20*AY2Vi`OsSUc3Lz-OgGDb zE=L@>buyTQFM7b-^XvR$^!EWQ!u2saoO?qUeaMXlO#|RPBaoX*Js*{Ki$8oHO^v?P zm)IMpHS+~d&B=tR10rIv;XP0%gA{QC>3y`*m6PM|uFEB1WwLc+s_T5k+;V^4eW5r4 zo7$NW0kr7odI|<^ZSJ^=)jH&Dp7s%HZeZjL3qH7m{5f;j<>E;%=yn>u*4N(e1u*YtVRa!jjE}^bLfbiV@0axvbjn+3?0NcJg)?;|Mk_io zkkI6>5=5_`VYt3`6Bn!?S|FL6_}KWKcJvQjGOKhMZ|E5|%L!rK^+wZJ7Cl2KHgdH)w4fb1}L66J?tuw{~HCL#0vA%?nR0ylPf?wPyhh|uVrMts+B zlLy90+tB)ix^?yfyD^#BM-a0UAVi;|0*w$%4=Orj$WLO(*i6%Z@OxvdnC_7dkhQwf zV9l@FI_hf{;iYS*AYK(#2P~>C$ILTdAzcYHT!qrlyI&k44dSjFk$cbm-eb8NXG7Lk zi?W}NGQ6eDUW71fHKu8Jj#mB%mDTm0!GtYc&`|1)O77Pyd();Fp`nObl+K_QB2F%N z6_sPJLvYW|WoyY7DOqe(U^jsH1nk~*@EI*dZaH_0{_Lu{SBtdpIbG#E3FZOA_+e}L zn!7B88|f5>tGuw41urVl?6|Y<@>~e3Q!O zaOImTns}qi`b2qu_3^=~~eHYb+%8D7Koak!6v;Pfnp3Z&|Zmp|1GAI>Mo z>1C1F)FP?QYUs-!wB5cz`Ib?~I{la-R^7%~t{{7BLn@<_R*a8{c|UWWg2QvjZd$*L z(sR%ppoX@UMxX5tHm7`;Kz?a!_9=YHN6UjfSKR0-{(O{nEPjb@Yk%s%--KpVI>3YytTS)H_FYMPNg9&TbYZ()#u8l z$TIQG2yRyrKvD#&6oOXH#*#qCf8`{!+w9vLJW=%NeHpI7)r#?1LK4?%odJH z0m6E@zm8~#b(k+C=VgsOjRcqHA__7Yn95&UIYdnOPN|5wa~?~1&AzJX(h0~gs661Q zsKug&AmV(R{)k<=l9O!klg(E0)0RWyDeoSwAGh~QTBCyy_uFr?+wldbv@I%w-WS&^ zr5=$tMz-0WPnap3frVORWnh&sXM-|=%Xur~3q_-}N`0GUk7?GkvrG(zt=}oM#(vWb zkiyx-uGLM*NsLc>wOu!2;Y$EQQK@6UAPi5$CXd}ZwJItE>yf%uB+#N=+PnABK|7y3 zEqlZ2dabmQBKCEH`4B}$WLa*CE9WUdKr&Y6+hJ{~_KGew%n_}@CGf??1twllf%9Na z*RAr0F7VkvywPpAngq^=2B+SJ^WAYTMpV-lj1APu@kE~WG(yf)#H*k=<$kL26cc`;F3CX*vrdB^>RPukE(A~?#UAJ66V1lf&m^`bz$unEfZ=Kvj&KW(H$t-t$)vx0YIx8o-4k(`=a;0#gl@dX->amlAug}Bx`dC+8*T56uQbf-b{ z8%L6dC0E0;UvA3c_+mC>>wt$|9c8#mSgOM5KLIi59CFrSDmpWRMvyu2oJVAtR7 z7voUE#pXY34Qz&o>XBnOjr6=whzN?>*xlB)<5{rR-pChCvcbswPUIPp-U_2w4ct5q z50;7jl|F6zKY0{=VK?+WF}93=0%@#jErDZ zxyL!EhYOK3*`GiRk9iSwy)f<)_dUZvdxDYS$PdiiU3@}NlzDM{XFbW?-eX~da}E?A zeEamPzA{exXhy7P&Goi%tD3e|yfZ2_7dh-A`W&?UnhTggh*}*hLO?BO8ZL2377hnPd>6UCmpXdkC`u{2FWY?WV*C~8lo72g z2CI(-K^OJDwX>>&ak{2D<#*MU3|Va(4qgftEeyQ!JK@uWLGf-xT(Qq#);4-(Zu)H_Y_+nf5$fRv7~daQ-z!~R`jR!}2jxc=G?=1}x<0K_ z+FTrk*y7_B_SAHz%yTGO3(OdhURa!4*wTJ=ItT?X^Ix#{VR`qp(ohOb`3W;+lqMoz zB(oQGP7?9gmk3*@eWylvK6)Q1lRPgHV^-hxi`nm2`=|C{wnS?Ss3rI$NI?U~jv}0x zfT#*rbHpKErDViP8~q20Mi>I3Y(4BHznnfEfgsUJ)Z5i%<6r0M)rv_b55ZTYUl_nUNhdckcnrJbt+s z2$F>G7YIMTk2w1;A0mIUdDMvxODtnYlxSvsKVuRUJG-P7-e4Vf_rz5c>&mX@r=d>B zq0t==jzGrQO~3Mm;g!n&CiavjmUH3LT5|UujFrXJQ6!^Aj(lIvPQm_~DNfzu4s?dK zV_sg9ZFJ+ zk%Q|tH1bgZXu|KfB^l35i%U;+UiTr;ZT7`^2>~+($lAJ>`A|iH%KqiBhV6ME9eMg? z>Q*gvz!mRdf9Fle1?IOqC-K!N)17dF5L85`-vv>G*Ul!X`Wa}|hO%ih=2`Sy;Ms9{ zEYF{1uD!PI(#@i{2W+;rNeZ!CckYqWc;tZr7IFAGZ_3p=^1{FA0^A6;X;F z+|E3HrlmZ64)8|cEf^0kW2orcwiFVia$YD*;&MjTZ3#QvXJH||NUu{%s}WnIII*(j3y4z<78DWyp;@`F9~Y#2L*gA$mjAF#jyTXV0kDA7e+T`9b$nB#+(_?xvb{>(5$Cy_9FO}*MPSQwv+ru(i)$_Ty_ z2WJ|k38=j2@whvZo` zmw`%298+p?JtC;4AvF%e!SB{(30p7@f>47hv{X1{i%TdymU~(M$(hdvdZVkiF|bHt z&j+CVn>k|s|8U5`^><)z#@RssFvJ1^{xb*`=C}I&)BYy`W@aE8^IKj1C1d6M;}`s2iY)BF zH+cV3@eL79*0=imPZ={a2*~;m#~>EqKe7k1as8$DW)H~uABp_&|JK+!{#3x9_P)Y)5%N{4_FBDjqxxjDn{H@3dV*iIhPFB!A405ot z{55oMCBXWR@qQ}{&VM}nR%ibT<}LsKm+>F0|3-m@nSQ%(42oE^JnDP|C%{(1;@hiUoyf!%LW(lZ^wURT%aV~3IHMa zZMjsiv3Xl8-wO5Z&=n>LYZDt1_P6l=)e$DqwVxT}365xOEs z8-1n^eb6%GiQ^83AZM|lgp>^tjAADgJRc${plA+dag1W2xv?OJ_n=!WV7RgP0%)2HR?vG0SD2-H{~3dz~N ztn$A$J`a7Gz4x~rC44vaw#mNwK19NT9;2#2eJQdL=&>og%k62Ym{&d+a(rts?{lUorN;0E{QTTJJuu2+jjCz{1Xm9f8|--Z`?K#fA?P@;PM~=UWMNjTigM0;-on^NiW$e zP_%uJcV(}TUCGsl9slt$J;Co}DBoL5V(e>8nn-L!IX z(bVTnzDfR=|NHrCX(K7pAcDkCh-ju%>TSl8zkmT&#cjE{SSKYR(54yi=Lpc4N`X4ZwcPiC2mFM!&3 zN%fp)M--OmvkVz2biCpM8Gww=9OS7w`*b;Tcvuz^|ybRVq*tcKU~p9) zhk6|9aj1u(GYba4?erP$HLL&@44(KQ0S9}JLrp7sLC%`J4W&m$*-{g2Apc< zWGspPxF;xrf7clAzb7b)yRd2(NTkYAuYF{FNJUULaAIuy=G75b+M>BcbSN6;H^}sD z#~k>SB99=^E^mhRuEx?JkifC*iY8xl+;UZRt3hTpjQccyrxoIe5Amzwf~TwopoIRq z8V)O|zI$4E62O&Z*)D4Q*r4q-H-9b%+_}cSx@RVDe~K+MI=n+-Ync!`njVm~;(A>T zW9u_62Neu>9Px{KvjJ>x_kf%=U{9?d2jr}FY3AJoa)x}*I5-eM-XYP6!2@B?3k{x% znFGWiq|sx1Y?)gyS95X6jRkWJ7la?^7LNzz0Ts6nCFdouynvXHy!6p!C%ED(o4Au)O> zj9wC>7Y@=0EHe+G`U&hb=4UrvV_`TrunoA!e+2thz$vhj3Cv}|a~28seS)Z<=|4{p zNfepIxx0{_lB6N^fpigb5`#Mfw5OI0)eEXuRPTtQ)h#7XkPa7Hbh%sCQpRwC0~qFt zKRA4TJrx;*Ux-wW(z{IB_zWF~^@QRJ7NjR~l)_~A`5*J?SY%Qs{G*Z!mlVi8psRzt^dD_c^}@ z#I>UgOmFFK#u3JPzS!KF7wl}Txp&?yOcpBmgyy`6Q|8LMriSc9c80?-7y-3AI!fqX9z zzP_UyHWQv&z2 zCvqOR#fUIGTOC10p%i2e#aZ63f4f6QIPwx~9^b!+xx$d0x6I&s7WvPT`LBGw6Q2s4w#8E9CAOsBVJGFx#wUiXTR53zIiZ}g{Y;n2jx>?LVz`= zFZA@r!B|ojok4nc&)bj+mfoZ+rKA#ap*0t0dp5%O6cFr*PK|=EctAH=8K*lCAM(Dd zH+fes@-E)$%6-52N&PHY{I zZ=a6Qjk*;*DN{Dq7I>qF3;$NKwsXUt61JwVZe65zeDpqikQwa0$R5QFrMIaaUvmB? zJ_tQ!3=59CH5ce)l3#5VC)`6L6g~G9dzR_I9iHq7NJ8NE!B6Qmf0}MgrR%(b@Ui5k zqm%z0bB%t!Fh<31J{}*x=eBjRY`NC1>V7>4Oc^=NIsG1iUB3$}x>em4x5wiP&91-c z)S3agt0Hf1xeSD=p^1N1LBA^aL|`QCyRNQU_?o03KWzzE91`AWrd8_X;LUDF0*vuL z2?XZ?e zg_M%`-*=9cY&o{j)DBvd4?8=v*X(e^*pDLZ)+Rb8oWAX{L3M z(ZnpMTx#pHNtL}3el*tFIPs!e*2C!S!SniPCKAlR5i0r%kU4|I*aT7cCEj{# z&ZAdH+?j*=uzzD!OH>yWTPsMmVFf3sih)Zl`tGbR=L2*7s%^<4$aF2!$1h)vq7{=T zzmJbBi^`ssd(?K(%<788O>x9UhSwXM>$>-&1ToPp`AMH>y<#z7%i zaL&C|Th%>x!8rR#IG|CmSGG*k=~a?eRbLMSs*)GtDSxSwHfh>nS+>)9|0dO%Q=DYQ z1uE06kjceIWZ)cVmn>O!JnaV6VelRN^VFZNjl%QGB~$guDE{_&9^B_4>a+J`viE*Z zgIX%n8#s97qy-%E<}5s6 zZnhZR)Zwa(%nyTntkAFEO0DElOR+o6Y9VN#)`??3fgG zX3fd4oLe*dTrH!l)VZaV#)Vya{P)a#XCjlNtn zL$~UuY3&rFVn;!49e+>zZhm_tJDxCjy1qGU+H%Io`9tX(@YVwcLqckw(6%V2C_EoI zFGb3;de~1OMBxV#HnTFp){1v^zYBv7Qc@A}yJIlsA7vLShTJWTCM!(2RqV=_DS17Kx@KfvcJHENr)gOI*i#_?(2=fene2Oc2UC zCtzy|$D6U7_5==tg?F?IoUp)~Y8q4I2}mj?D<)GWc)I3w+6u#aI_4B}#TBvV2>ysTr1llHN7VjC?V~I5C%1b>9=-IrxpR=YR&1DmD1!x8 zaj?6!>?(&Te>4L-|H-PECDCetbiTuXa~mZ1@V(>^Nbj=9;~jE{1zp^F20CfLKM#3{ z{*os*Mlxf9{^|?zN#M@m#-<>@H%gqLH}Mn~*-;B}m33ahd=e-r1xi2AE~uSRoAMH_ zC<;0-=iR__PM8~*TQZrm&@yL#n7bj^TVtdP8mt8+X}&Yq8(G9+huy7#G-iu!!&j_8 zv!&ydxsJIH%+<{G%w6zJ@xp} zr?%eVzL4#Vj$a96Ho)#G+4WJ&h^jx8^ToQTBY3f#vmbOWQyVZ-E<`DR0GcS$lrI1% zs;}a`;1ixx(i!`|!)Mg&nVc9d9TaYDy!%)E6A>B;`;{t9Q#jaNuPaTPDorZCetn*5 ztJPvbui36&{@vFrZ zdKWnv;qp+ENqF_#AyZxIyuT~JoOlx8>%=%Dd1j?wpw~Ly?yla&8-iT5(e%M z#prh<<99t=4a5_8Rox|??8tkj$Yl6OdjGnbpt|hSJi$Co;p{_cxrMe@-VhdRBG~uiGW*rqXk% zvrH=XHTLsGfkZ(uqirNsv9p{S7b%6WyOvO;6dv56@UEH<8v8CL{ocjkC4W-#F~&`B zA~61yPtQ`Ql*~YKE&c9DjKRg>W6{+WLqz~zIAVmg;<}Dh^;piPbTi^OFK+mW9i{Ku zuOx?mW|<2AjT)6Pqtf^eyK1`2H@^(>skM{0C#jRHDmfZ6Hy|(|Z(?c+TQ@g1E;wBZ zWo~3|VrmLAIFtV>X96=hvuG<{0s%0y$SrpQ0Wq^cFlPb*GLxt>{0TE4Fd%PYY6@GE zzcU__zcUiE-7|#&0W_1rwiFUMI5G+^Ol59obZ9alF*P$ZF_#gE0Tcu=HZ?Vqp*1Rh z1yEdT(*+9S?h+u_puyeU9fEuC!C`QBC%6R&?(XhRa1HM60fPJGoL6$*@Bgdrt*M&X zt9x}nt3 zrD5W1$Eap&Vebr-7W+5nU4-yQW(ITuuro0+adL10fc5~Oo3T0LUk9jvy4wN&Rx{^0$;e*Rm5|78ESRMF7l-_iZUqqMCl2*CZXB;Kp{ zpF~{#JsDL0UK?t_|DK=#dY@+?fa=fq>oT!38NYuq|9@VBzfJ!C&Hi6r{$I!c|3)O? zY;FCwp6XwO{~x`fjfJ)QzZviI?CkWu8}gv{4YB>dR1M(27Fq;D>hI zo}4$p6y$*LS4TO2H~@?ye~JD^oXh}5$v=n{z$pC(u>%-o|Dbm}xj%>tz^L#CaRV4X z{}*ww02r13pm(1te-ImhQS}dcKSAxkh?^6@X!r-c`!xP9`m0imCjWr%aRdJg-wVO` zuO|H=ya!?WhwvVRsfEiQ3+BHB)_?SWu|dub|FC~2nEeBPzQ=9;5BMIq#XsPCHLU*u z-$S?g1K&56(e}?#?^)Wuclsat_gp~#g>3J}p#M?7$7c5r_#VkW;$(i0#PN^wzYx#` z_>be>>5lLB%^!pJTK%ch`+hPynL7agQOoyeom@fxFnABx`5*8-SC@al_i$bRhW|6A z#?B57?>G2=-}lJ-2>%EF{ki}G-GIgjOYAg0D#iICkTa<7wj(Lf&AEO;dV`9Db9*S@0|_jNIT~$m9%<8CnkNkDrrO$0PMo z#B~UNDxv33^ONhsB=630HBNJ|RyUqh08oA+u7mRorYM#)O{gRrF4oT=u<(6&AtO|Y z*914A?dT!uKK-TEMdKA8gUiDlbueK=bjy#q-I?LT@%#Y8SY|jaDF>Zo3bszRtnm56 z%(zO9x481KV^n>tx z`LIqyHP#Jw;1rsECwJJ+loQJ5iSW>@!p=h>3s8mzC`hT`Ww>^aHt`A`yTd=D;nl{4fv!%&3l zu{YmR^7}rK{h`~^rE;1&`234wjlDAI%T(2mV6x{};ID4Nrlf}#Xl+?vMX8H82Z=Pk zJ8_xZ+NbZl_?y!V3O*+#e(JN;_Hc54GPL^BaF(<6+XzmtS}w9nxx^hnU1zvdxeF!x zXg>9LY2o?ckH-((hV8KW>z^o(CB&MzCCSv=3Lb=9tiBFAH8Y44czKj{Y3Ev`@n$O2 zAbpl4X5@OrBfWr|Mk|pLUgqqa7Ze~Z%goEbaXS4r?8-|sy%%Q9j@X4LA%QG^qOtqP z9IQe_@;U&K&qC91iVyR1+yFn4i$^oI)&IA(TG>a~<{;_ZYe5~?GKi1cW5)25+6M+j zc+(|Wo$J*|jwVt-iNfShADU?#_YaY0ruk!^rMGRYOQv3z&MOYxpXoX3OrqZgW4}j5kY}G zhbY@?ExjDpc(zPN+#xn!+Al8YP8gSq3v{)}IX>#p`m2e5B^zvxl+XEmN`*XG%OLi= zC0DgwimQ7=vn6!z!TPDFka8-CqcG@#C3zL*YZnDHEmhL>cPl@GT3oS>SH{{Qh$Jg2 zjN$m`7^@UCyDAhXgIm3SBayzxP~7dg8eJ)WpJOdd{o9h!`1)6DxF<|wif&XNDlC#^ z1R0kFM-)`=lpoyo^RD|-o1Qz_93dE$6OI!J=<-3S@b{ET^nG>#2cN(%yK2(sdy8^Fnql1;0JX8qOefW9q##Cxa~8aMlr8_TD;NBApLJ7&eiP6Q_Zv16X$Lf7u^!Vd!yk zYk|Wqfj^J867SKn&aEo+HVI{*2g)EG)cv>-jZK2}E#xOIk=^;wAckydTP02Ej-?rj zkF+Y*=ygxoo)gx8cVi`RXpzz0yL5^MhK1=?9eHBZ;@m5UUl=l76F&r?OFdU_am?`O zPI}%GHb(YsLzX0(MamuIGqx@nJfCbN@=y_#YBGVWk&7zkfXetb<}}bvtP8RFWlA%9 z$lB~D!J95L&kzXQJz} zB!}m#APRCJwSCe=50Vig)EJEz30t=w%_`Tw#6~y%1IvlMW1!t#>U+$ zZF@!S$r{L1Em|4St}X6078oxr_GkhHWet{xGjsaUmR|7RypPOyC%WQlQOgsA@;f30 z=B29q%6m?Ko*vFiR%~p!$Cy(e=|k`KvY)U^bkO1ECjB0r%npaPgh*R)FtM0h0U#MKq-xt(3@!KTu{U?5UEh- z=QJ=~gM{G<(jS#vin!SzJlfvE*%t0>{80h6T-1brVj0I9Mqhp`Wx~GkosX+gneE*y zKCDya8+>L-j%azw$6fI-VufbfK^(oI$5mCY_H3_$zt@*KkB!g^)#(IcT8sSH-bPN2 zCVXa#RJaTV>~=qfeP|I7=;8-v6|pKMOwoV;#NgiX z8-V(*p6@Nqo{ifL74WW{;5WbS;7B#e!)tb*NMoiEm)}&&v?lU=s(eXxM}1@k#$wSn zh6RFM^kzx~^$&;h5~OUO-8JT`?})t%G2dbNczsRis`O?#3ieDh=oGu{CW^f-Dy`ao zmAP6u8?K22ED*zB!WwIU0KKlDy7UZ%nOp*)wrX>X!wiEe9TADp&UHFDik~)W1nKRE znDrt+zjhk(YGPZE+ZL-V0PUvtN}aq@Cs(H@@+COMRE-yp?KL8*HWN zGp^25Sp0;(u3)r=(QK75HP{qK-}JbDKY4pi%oBSdSn~5Yg#OStC7I) znVS=7C%?IS%Clm)C=H`bo1|XffZk!*dMSqHyv-gwAPqNjmtd)N@oSC~5|o@MxY-N> zkFAjmeAuI0YrlQW$HX5F2bS!5{oIhH3d-trGN=a?oIvc&-?6r}6sKF0)tFj?NzOw~ z^S6V=|}o8k_;y1RQxVdZ!php72{ z;Ir-;Gklf5B!o^u0_*fc|K+%{(6YFRsz2S{|1>ctATbfqpZwJ&UMY0g5;f};{Ub#D zV`T;hHbthfA0%1+51)ou#N@A|pZB4WA%PGx;c=m#43|`xzyF>Dh646~dnFK^ksb9c zNO6yjgWc<0W9bqb0)5~`FACy)wv`9t4ch7OUo1%jX_tn|Wv!x+mDq8@(?_HOOD#vA z#X~NQRH=WVR-tB-MupS~G`JqExjfZvd6DBVupKAR2+cYQt{_<4hfUgn)f)|L>pH+k zaia*A^=)eNJ-E=8j=)rZ$%*c^B~8#46RvPU#9)0RcyNzka1)(b8qA^$=u#_A@?O%F z-uoElK%6o1ID#W%hL4ody~VS?A|{CYv19}g4@;Hy`y+Y}!?#mH_9#tdBm>5k$Btr8 zSZ;$#u1##zn27EEWeE&1O1XeBFa5b!hT-z;co)OtO_jZ5UQRWCiZLr*$Q?N(5fOu5 zPFDHe@Z!CDs11I)VN%M-gX5$UsmEuUXw{)!tL~HM&OUoe=;mcsT`p|uu(SEu;MhkP zvKp-u8C;jeiN3w8n9<-*=yO`ndW&)NX9`PH-YJCMh;s=HS8*B^W!Q%KGeP+L;I4s1 zf&^tBea6zYA=%1*0l$7VoGYM>3%K#FqYNVy`Gln#GiFO2PL|OUMUPR4*c>&|b50?B z$W-~xa{dxRb2%WM_yc55#M>1%*EY$xj~?C1aja8}B!@Qt3k}rVgWsfz^m`SqBu64V zu~vY;9qn?F>!R^1d2D8u$zB8{858j|=swZOS*LzhX?*N|NnGs*2?6fFs4nq(tRtqY z_}kTedDYS>M{AkJLKI>MrVv}p5`~*Jr9XZV!u)jw+Akjw^KJf3iTd0PQWo8o zFLb-Uvo%5vK&oOCYl#Dzfv;Me&r4Cuiw60KHFhe36wMZ1qY)2IUSK+KcOQ)S9`HHk z`5)3}IB^_*ho@{CJ_byoHBOhhvaqeAEd+O)FdF?5^UvhF^>&s2j*ZR;<_TXgS?-s|#9&mCykkkC zy%R0O7m>e@9B}*U;XZHulltw2v=*>(aU+|9Ik^*m*uAD^1DZ+w1-HbK4`vLJ>`m>L zv2);&u*rkRhhB4cezOuJ@jwip4eGrZ2t+H%+&z?(LvTxQ5WLb(z#kg6g?oM;>)7R9KwP`3?b1sHZERx}( zdcn9iHg9O!fwAH1oRo7D(Xsg)-rEx*$^OpjJiq+G0c|qj`gq)&lDhL5G@!kBivTJ_ zm$FR=PK_bg&hU4@u3o_a+Y9zE2jOfYwI$)_!ev8jK))ff9?1PAN-w*A zY=)8>b0azY2JYZT8AWavAD`=XF~5~y;soT%tEEu6q8EYH?FV1BJc-xS5Jzts&6mDK z*+R>r)GK4VFTOshTzuU^JFz_}tc`h=Eqg2(p#c<0;M|-F6BpzjKCybeJzpUNY~=dn z6n41p+`~`mdhkL{;lKcf3)C=^#A?rf)M5;R zWJIX?${zS|+GEbt_FJ2tfJe+*lp8o!^BtAbjkE(r>`ipBk%4$O7-}xK+0%Zw1d93O z-o03*FMK~i{bQz65kB*#Y5ex-9Zgs={bl81B-$&TbFyOi!!yP`cgIwFe7Tx`xIbcX z88Qxur=*TrkXfZZg#7>uE|H13>4j9}ypK;J8zqWSrfoJ>+bSbeRow!o%A_W4d={70 zGg+ai?BVUu>N+R+g14CVm`T2=9zLy*)4BL+Z8O7R&!Q_G;=7p~ z*}4ig-gTN!8YX1OO5Kl;jR>xPzaW07T(P zggLA%NJ;Sl$Grz9tW;AYSzdjq+FP__{DF9UG{daxu*8&-Zb)}={`_i_PnWU()NiF; zGZ(u;kRu*6`KxbBQvY?`FZ+4k<|2Xcwx;b=!J33>b}8fAx$@IbvAOnt%rEqz;CH)< zSEkgTPF4i%)%xvjMNSPXcbYHr1IUg*u~M=l`hf{<`Zf@+)3lF=C~EC!aOnq zLysg!RvnQnIl;*BXHsx~lw-eH0-HFBlOw)z{z@MW&M|MM@A3$NAh!=H5U*+;%=M9` zu9qcY)x4Z=?Z7|;lT*6e!|=T8NpYG0CNkjP8V~By!xaf<38(aY0%Mg&9me!ptKC@x z=9k!A*EnKh>T$_3r#!jSm@y`v_ZKg7mLIDCkoYXHbS#Gwjr(7JG+bm0;PHl5D%>2dq75k0(;>$%l*v^q+h5YH zuFiT@>gCSePuKNdE$>HDlouNL&UXO6$6Ds#92lF*dT`RrV0%{G33t|I^XRZ+dqG(2 zDpJT~vRSA&I+RF%3+1@`*Tw@#*?7>udHK>zT8Po0`f4|}2ZfhD9nlhS3Awu~shl{E zpr0pBYI?k8+8iyhx-DFXTgZ|`RX93FOvRf-)GhHl;EL903SL>a2PTcF`)ZiDudT4l zpvKlsA6l)RFr7@_BdWBvnX9bHw(LexH)BKl5&11VmVOL>PinAkHrjH$z^{Jw1V7=C z_N+Ic1gO}(&izEH18%U8B{%nUb;#2}i)^?q3?&V;zHkA-L_- zn5R+y977~u;j}zYr*dJY52yd7A)6`qYvnP${jRMld&jP=*cazZ+()ukLz>D-~}|W_dO~o8Jv;wOJw$x2D3pBA}-{cZFq)la-Y3^O5XrO{msUSJK^6 ze>dHN#KsL&OJzi3pjNM>LOqlXSFeA}5-L8|zT_<=qAeVUkGKt{iwd>9MkdJHP4MZ& zL@`Z&3KqWrfAB(Rs~%s+&<2+%>*QM9n+;4BMZIBR2TtQ88bSwmk(Sz{=+zj_UsQK) zEDgca>^%G8y`DPUoi1H^Rr2sOp{YYF#EN|GQS(3d#) zXHa@=hm?5JOV zQjSNZ%QCW~z1ykHFuRH%DR{TGjqiU9{Fo70@7&nPb%cz{x@q_AnG0Rao-Sdqlk$EI zRfkm`>3Yi%rr&9v5p%M%r&$$=_uyCjQzNPvB}Sy46nc&lu%#K0Z0Ni4wwtCnhiL}Y4t_{*~=Ndje}>K_`?$i$?|TAUX}8n11u zGhnmF^MlnV;peG4OteB1b#tm~3aUQ@uW=&tSAO{$w#k&ax%;$m;SD+4HRO6Bw+gbK zSL3~r>rgwsD46hNkVRKbZ62wW$^WF{nnET@H4^VqI+4QIgF$m*=r!dy_;@;hpVOy? zHMY)LipOu5r`PK1gN7@*^X27gx7d%EWd?`T77kprct<~MM?!{c`lat>Y?#IKx~ovf z7!92{FcSL*yeYWmaCi$?5=QQpXII6c^l~tUMD7s$NHLRSMtXPH*5T*88U;k2W}~^* zpuh$RJl56B!c2WCu1p>t12=bnb!~F|thgr_sI{+V5@CRM6;>1fnq`(~sNulyeyZ{nPP&sMo$EN3^&_5mlIYq4^@ zvd4~tQi-BOux)oC4{?0L5KvBXw%VadLK}S*!snAs%rJbySEDnIrT#*ubeY(aSvXE%Cpz_L-Nmm(T?ArEI&J`4IN4N z#8jsAH`ID0C`bmrswa6iVrb%UZr$sR?-kJC4V}gz9`O`oY$n2}AvTvl)%kjD$WxB2 z9R)>RsdQE?C>;%!jN(67ZiKt{{&0w^5<6wI$j?Ciu5DZ@M@;SklvpZq=<3C+x|NJe zR)uh=*v4CeA|a4}$wXD)pox3B*zVnQuF(8kp`-Khi#U4G%(#qIfia&e0%uJLt&e94 z?#Xh05{$9Xh`n5};xCrl{*Nz$Yp`fK>{AiAIkUW=09#FgRL(d~8Oh zesfT$IAawDD4nUhC;5STTN3rxjqJ83N^vQer3lJKY}ean6&}9Ni!^bywwl3SqaBeW zm_4lbPM|n}7!J`!F4UdAexNE4xT`5Ea%vSQ4#tIh1kMmhjdHx)!ZZ^xS(fgTPUCW5 zRAUvHJCnzM6B5gF_pI4OWP39HWMA3$v!7Du1rTy5P#dBunZ&`d2>B;xjs!4^eB$mN zh>%$e=~CSWkD>bPWZV9z?kK-1qQp^#G8hn`lYaIxS{6g_V1|+8rq!lF9`#H19{9HV-ZczkK_=ER#mQuBd$dFN7MK9#C+T6jeyjBS`wHiluDS_2YTa~~LiNMwN z$#vJQ)&OGWl~1ZalUKwX4VNb_BG9<2kkfI$9|@sSeRZ3%vtO`cTWJC5CE;@%jbmlI zR%`cvs7S&G5^lP#Q60*p5usK$0#8hy{fWV*Y4*c_%lR$q=wb7J*#tKuTTqS+*MLL`S z%3z$!V0ZFwsFRjpvgFuW(O7nPpkFdiRy^}=&5d&q#?(=jg-Bw%fwYZW%ZX$yG% z%%~788UtTkYZh0Qts1Rh>y#bGClr+|H7?^Ig1Aqkb^OT*&EjFP}N^ldjJVHRlo(RTu1Y=&m ziJt;DxEDU89myMMbmDtHVTy1i4_9~pJc!CScnYcAfzfQf^Kao(^s5+AzubYv}6 zU3BQw3oB+ix>~J1nnmYG(T{uoaQvwhB+wU$z0T3{QbyC*M=)guB=3IgU{w<=df&cI zx^jru%gfy^wMS4JYuMTw&)e*v9M|cG+8GplX==Q+&Pr*)vsq8Vf#NTJu?^eWd%h;* zJdA5j$lVt<)Axb}a6%L$^2Ihe2Hdcs7DyS>D9f1ZW$q3sZ6z=L-K<-%#Br1oId0%l z>g%)OXmqNtq;Qx^znx>0K+aCc&y|V?&W+1=7Dy+2_RE}u@Wsr%10G^NEUe{##}#(y z&J_}K8vMCWkW=g*!F0KQR_{beCFIl42Y$Uaszh{=?2Gc$-;M8i6iFk&K{lk1ay5B& zg;{FX07iVPE|1-&=3g+J1g(0LjnX`MXWB`guYIPMAU6C+=m^_Ie?==u@AOM>4zLon-RvG8Ljj@DjMcLpo#T*S;%=sYt}dL^Z^poMWA)Tp zeyRyifaK+3?WEUT;&PJ581S<7V9AYUO0IWPuEDEk$d!8b%7c$3Fe_^}bZp8%)>pCs zm1TthU~?y58d&g%^K_~G!RLDvSKO1rSRe|?BE8qYn;f;3 zVIDFue6$=Op6?rfD7<#2K~l8%@+t&%zxmi(`60RjQ$k=fTs_YSFTZ9=?!x&FA)-a+ zMj#^ZRcahVfIR<2NkVCU{{}uTY}lZf_mS=NyIIPJVj7wMBH5bw_cCoqEP6%BWzU#; zcZR_1kd-`qni~>4PxFQ`^kI^9!hFi)yGBhdiUVs3Ez_NUL86Vux)bDq$Of*`u2D=9 zBl3auZ^$&K@d2kOpW12)N6^C^wAu50-H>oZ-DT!If~T;}INGdeKh-lA+ptW1E7YZ* zghGUOC=b$X*@)4h7Vp(?(Uk&!a)~qyyI}my6638dMs`#QbG}cj^`=%2eS$J39r($5 zYrG0=(st>8&E9X@^@n}ikPH)SV&P^ypm^MfF%8Lm*H{~EvMzI5u>$o>q9o1cxG3~d zf%LQQgI1z;cO4-~_l+&?vI=kQb1tRtlE-+r@B^8n$MvcGrjN5@1KY>__{F`2zPAox zjxX2EuKqtg4SrDbT^Z$T)hyXvRG8(>ARh{}kSq>*xw6gT zxEQ1g?|b?Zg=sHW#!iSD#iHkwd=qsYF2NnDkgWy@-j;HJurhS3-yXM*nl}!%xMeam zG6EKVgkywiMm-uv`gnxVMf?+rBG|0W1VUb#+G^JQd%+pk4D_7qBUR^hN>E%|@ggaa z_7jDDsR^;#EKy7WpK@{^Wct@F&jG-($4!T9!Q~^aa&&fDEq`j88f{W^t0XYG{>R0 zvyhcRmE8>T`E)hBifkAo!ZttUM4Cp$31HAr%pnM<1$<&rdTbhG8aNeTt~Dj^5r0g7 z?lG8CI*{-M1ZrU+Uw7b!>Gzp!RP7-ok;~Tl6H6}{O+B$Pn|J#!Md1o9RL;^EqHcz` zgtx_wUO7=1)(m4pPg)7#^g~!j|H4_L@a7?f5>zbSQM)tLfg1f}u!i7R?oBF2o2>*{ z_JbibU@@e9z3wVlwTU^ZZjK|7fTFs8;g>m(>~+Co+-fa2bWYnVaB7Dqz9zvs_8c{` zL@O}=wig!L3O=^g#kKz`sOX~;JFH$?;{y(IQ9v_v(??sjm@=F>r|WEICmMWuN)9th zm(jxMJji%M%5AQE^wz3eUfV_Lfg zc7Nu%zb(~X9^|A)g22_a7s>4 z2#VYl`^sX;v#+|b_Evc=HnC@anPDFhEqNku-udcV6xR_EgxKa*w5cC7nxnW)SK03y zw2MP;b()Z&UIw8(OXv^O{TCZJ!pMb&Kh$o}^~mNasS@Y5O&mCX9s;Ib&;?vOkO-hy zK6=Cf)8A&}B>Es>>{{lcp)F1+F{AsZ@*_K7y&`WZ?0dr!{?H#@O#K4w>qIA|e(`@kUYkV3Hn>QN7Z*o4AIgzKvR zXGm(fqhS0erkjF^g)r}bUEHvrZX;(H&8sEEH>RKS66W{x3UDchingwLvXkh=eoQE7 zr4#x=;GY;b!GO6^C5g9uHLvCg?$9VAsO7y|-u=+?=6~1_!$`fw7_J;6L_ZXkXI+Wi z;g2Eo!cb!&QB65rCr3l1+5d@f`TP9=CNJ<{rQlblko*kfI=C=@Dg#CD6hvc=AroIs zhh%33M;}T*a!Z{ayy7?Rc9S?DOoIKjyhU7qp1}kk;>N*a!!}Q3QxVr?MxTyg(m<@6 zDV)lmm{BgH`lCuargQFh$jwE+x1-4cmb}9rJjFKZg5M}T$rhMPGy{?>$mRf&9 zw@eGm-!FKg6gbJ|3~Q6&y8h^+cv$!eaD+(4=<~%YkJKtP<~@e$8CNbP)S9t~=ywyu z`+VFum&F_6GW&EVSKNgMydG#?SnOcj#jP9D$2cv5Ppfi&Hl}P&Ui^$>`sO3!fe>AOdDN6dhPvQWl*hWmY$=ks%3 zC&S6{yzEAQJuit2G;V7Fm!vz(GWS}iZr9Ff6=A*6Y-yS>M%O4W3n%WCqn=2Vm(e@% zcodOeOe{QExQoP95x|Exdf#Fqb=q~;6tdTVjB3pXJ*_-=PvDCaBR^ad2oy&C3Br$! zrd}<>fpw@zv&BVnRcaGqIR2#HW}P9ug@kYz(abV`UX(Pz_?yX2#a=Ue;NvryPI=K) zq{|l>^}809n4oDE?-TtGc=29U51sd%mDP>dmZ76cKoyTOqwLzRkLWZ@dV5jcz2B0d z8Fzl=S7-?6$c&Cn+`Gakbqj->4G&#RUnI7APUP%K=VZU>6Rak_y;1&*|>2@{61OHkhK2oUjo*5t; zCy;jcVuO?8&bwwq#ktt{xGVY`wVhDgY^;)hRIBl}w=iG!Z5pP|dG0J!90vtDQH}4H zUFf+fWHd*#23gqDb-9K_J4=5CTAIiM&Q+FW$-OX@PU8S3Muw+a&(-r))+{nY2zdH& z8pgrkMu-d7Tvov&k&7guGUOGHR*yQ@H5qSEA()PsbLv!@IYJEA5`q5I!y?k{Yb0HN zOCj91s}-e@h&N#3paL+?LZ^-B9I0zg>DP&TuF$!0-z9JZ-doO%$B!FM$mF+AdfR~-Hd(|%0lhWbIME1U-(4^g2s>AySd2va$ ztJyu${ITw5kA^=Qv6A+MbYzYr6SN$2Lo-HC-u<;D&u>)wh#FYwV2D&sRc;b_LTDqx zRmn~? zj~wTfIz=nN^)achjJ~kAOb1(L?EH{1OtQoKCdb+Kxr6;Mg9A7TFDZAD7s<y6Z}fg{iq2J`7uc zMA7IuN~5nig(!nYb5L(k(6jr$UR(etq0}J@=3(&ejm@9!SO8d+-dN0g5sHwGy$FZG8 ziQBs&KN@4@wp+j_tX_$=5ruC;x+CZi$P*20Nm7c&L!J4|9&qi9ZaDgfi0me^NwjC0 ziWZe8E&2mmUjYGa(8OO)={xfpPCZ`9qDVbx?yj4R=Wvlx7Fsq0^GDO<5MHs;W^ZY> zc>(XmLRzhqCg+J~NPmIHMxn1)iPkGe;lxyoI?q(=Ky*;Dg>3)sRt}+KpRYy0Q$Gyi zni=+~B<^?59ql~A_QV_`Ra-^bXsoM|H9+AW=+}LlUH~TJY_?hdEZf})cysYr2!}xV zo)eWM)7E{~6@>GmsgS$Oi-d3*b)4Md)Qe`Mb_>7IYMK12Bbd&!&BuUi2#OZecHuPlFw`Qx1#HFR8mR2!zO**D<^Uw`9^})xZS| z9IcP3!IxVMgjK%z>U3y7ubO6d=5-q47Ex-cVoMDvJpQ%sJSW3Bt#&kONILH>m9DI) zb8pEJ5ud5k5=9@}>2yGhjQAH8c}nE3unc5}{AzU#4#M$E1g+R!7?EtxBXVYY-KXadRt`-R$or>`lAD*lv_$ML zq9yurWr$|5xO{yY+21x)#ZA>BYFz#BtqE|EdIWP=7>=P>3S55z6b=X7=&Km9<5Hci z4*>gxp@O%s2?3BairT1loe+sEUFz18{Yc|w6Vm|}`oG(azE^I>RxV?Z(?93Lir;+> zx{aV%Rpc4Mxwqdr#tCM}MT8(m32DxrE*JS}8AnpWpbRD}CV#{pSa7sA8p-6i7=Zg23i(^Iu6RQPHK#pxIm zJ-*q9NsNP7U}H=S>~o9Mj#geC2&uq0xCyx%gE$huZoDFgS!#e#Zw8@rc<{WH4M%TW+F;J|P3^|y(cu67YsuzfbDn}b;V4yE z5S-lvJ-PLQ87V2FklHJ#ficMPhXTwCYG#BNzRbHB=*+sv?(6Z9e}PqNhzulIp2y>w zSB8<%QWCwXZ>WKk@Cee~Edzg?p!`mr`|{%l*OzwB1iJ`Uh?|R8I0DCxMq_WveXM*B zle}z@)Dmsz7pqb&cXg&yl3M%mi=}hT5W&8=^z7oVJus*SIaVhv2>%0tpCp*WI66h$I&h6r|C7R`DK0>zERZz2jy2MJt_Dc@e>q zhZf@(3-)Rwk$DBc%Jx@3A5&7e{HrRh;wk#}lpC!Atj`4;PRL-unw!o5e=2BWa`U@q zyqt3&lw?`UpG!{i-HE?NKhuH;@W}kft=X}z5Ev>LXk!{5ak&2rUI}o{!^}wMmVM2a z>pj6%5r}uD@(^R5fHH+Z@mZYCT5AZl#4S@Km(bu(4%TvJw-2SSxCMAvyFUE@;+rsZ zgw#v8{I*P47h}XhkLIBOng@C?!xP^Dv%`h{7#VdH?&A_iujsicW6j*#KG{Dm%V=B{ znz!CzENEhAsN(Ao$O9m-!>!f8jmxb=ZYl`u8cf@)5rKi??kppRgrDg2X2EeBWSQZG ze1Xgk3)SZ@;?GGh`s4;dOD@e;UeNW!JV%p1bPoDemBDg=oyy;-8!bFX{GHoR=aikk z#@elWxc{i}9NATZy!dQ&F0(_?*WmNQn;5VI86fO}iB&OR{QIn)LWT7=lhNv8I(z7_fU_@HS>_1Y}poxEfZc$7j zS>;W*2W##Y2?rFbUy-hv-)8Ft5ZI-piTOT=1E_8(7AbbosCa|x!gh1nhgUpuADKhR z4$6%%ckgb9-f^3^>{yKESoh=HHz(+Lx4~-NVp_np2Fm&az+zE%T_dtGd58C-W=NJ9 zszW^@IF!66-)~Bvz!2v^ydl;*Wdbc8XBBIP8wU=vJ zxt9dpiRi`FVojOu+|j>dL-J=>8K-fS;DTLa7C%?95fz$1CxuX z%_USTrrnr4kAN%xfgHm3R%c|TpWhJf(C(PPyADR}?s}%xHQMJ(GhEQ}G;f2dZmBpG zNJHmZ6$41>m$GND`8^wTZb=z9&;gv8Dq!BOl-n`c!9|`QYnno?_3PXs5?qJm`?gMI zfD|Wj5(3jfH_;m9{Nmt3J)=3V`I~uWEWN~BgFkMSB(EPwGcV~7nKu4akadxnYeW^_ zDKrgY2=Js@38Fx6#>MA3H&DMTpIi!hD3ph<&;W!DsU+QWs5%P%wnjcX$kAwP&U%CA zMmUMPbANYgn|FLe%yIr|5tWt}=rza?R~`dg>YQLsTkKL93K$@r^krSn02kZZ=HiiA z=3q{o^oh$X57al^)kbICd<2i6F{ymz1`bbjZJpL_B3g(|8a;Y>M`L$UZHYy_NOIT6 zkO0%b9*~UoS*Ct;`=b48yA@KJ!02-IWV@(jf2LpBFB{uy4`Ph)QCp=n2R@S}y=%`{EO535CI3zK*u)fh)y9tfot00`A)q7l$8-`EmV)y>FmzZ3I=Cjm=Ri8YNN;ltt*2tphgz zZPw$5(uL)zXR11!R1~}QCn`VbG*LoQXR)u54xicL^5Kmrt7(bqp4|K}lTSE_0GT`# zSDeg-N!i^1=)eP~|K0JrO4*dz3c&Vr^LIucrHQJk)&}c{4{cN{z^@tPNdinc1Orbw-Lv?a|!@p21ZipM5cxn6QK z=ra*g4<0$QUQC|)RSd8DUT;#}@tRF@ibfCr@Sn5`*g3RMuSgm881AC8ec5Cl6DYn6aZ33Oo6;}6n8j>7 zQgTwk0X}O4F-wLE+7n&rCjgUC0Ng0r@-b{o(33giBFD%1i8J{G_+WITb8UVjp89M3 zLT3CR+&p?rx3`*wO{R@w{7ZkCH4zxQC@7tx3&p^m{ z)yVzauK0$nW@J9d`0cxgF2Za}N^#UE+IY1quYrW5EBTbJN zben;Z+$Fpfp}Y)0G*!@-^BIzq0P|JjiNmudcS--D>X{Dx`(ppI8f9b0Ma*){Czq0L zEwFiuZ)Ib=>0s(0TD~BuB0^OM34C6bJ_1zf*|IkL@H*`2*X!Ju zDHvNBtmq}=JsTGv6wpQ#3rduMplwvvW*^4ZkOgk4l zdp@@(D7D8S8SuQiUO9)(PQgC3V_n$WkzYrt^u`ew!TAo^V?AAg@maEd2OL^8zlE`$ z+tZJ7m<#t6KdA;M;d>ng=?p4ov$YwPl*sxOK_Wf#7>3 zHD+HsBc9*Ah}+is1Gew12Rz60OI^#Ozg%kzR&UYXVCL;O3kc|(=Q6OXJRmz=L0aEz6?O8@PM-n&3?7 zhYOkXFQC853vsgFO^DID#{u{R2S;|Ss?#sAK%L;-a0LT}#~uS~lJ*k2wdTevodW0$ zYAR~Aknd44WKz9?!n~YaGD3Olia^z?%l`W~d@yr%HpWe=nt!G(3Ar4|;LV33Oiy>} zTre(Mw{+^c(u`Fq#(mZ+zZh%P#cXL;()!%mLkiJ!U9lb=IPVM-+ z17OgIv*5kq#2g-oxVAp9nf>uM<5$AG1vLXO?Aq0-$z=i2YXHrg=Q1Mu`7IbKZ*Ee5 zbe9=k(SfqvOR%R4yhs7U`kXY+u@KzyATQd@*C<7OUEN;Wee(2po0}t?O;>$jBlvau zlUypPM>p=TK9Y+{wDJ7Nd-nRb_8Vr=Vn8Q+Ep}ii!kCE50r6_y7osL7$L+y{>|rYC z$P6pOH@nk2MB<&^g4yqqICk!o)T0*xUf?hwUV9A1Hm`s&7<7KR`6VJmT!^e{Il3%n zHFYqD8z5?TQVMOm&A(sz-))n7m7r)cYHQ@kA_*Uot#8&3uHaVa2U8sJNE^+gygdF} z7dC1e%T-^sA4E`SJ>Tw1@$)-T=?tE%f8|VF-U23mAZaqqY5$i)GP3($nSqrpeP0Wh z20}zuT~SFRS;*swfC`2|+`-;e+{)IBkd^fx%b*Oy&rkS2k^?LIKac^X+0GM`4}_KD zzt=YBwju)~v;W^j&gQ{38=PcKPx$mpEnvcAt%VX4R?h#E#m4xb?NFH6m{|Tl@W9N> z!omLEzymll3nw#kasw^}Am$m=HOJuv0tPbHjsj(~&FWr=rtgp@n9?}CVqB|RL6v@pmAzG3>TmeAi9h<-zTEJ7dyi+;6va&$v7{9(hU!({)_08iD+;;#|KU@alcvf^Bf13RW{ZwJ^A-9YIgg#Xx7S$)^5rEzdH1Kitx`n9b% zO!mB?cr-V@(#35wplujjSjcQRRH^~fa{zf@%$=EyLES&|%kM8{paqclYd`bA7&A-g zo`oGCv*!emBs5fqb5eDK$zVfm_EZG@%RyIznZR z_JSBd4Saxr&|=uj8cpmqFPXh8euo6wN%9)Q$<9x4E(8GQiwh0%as zDgc$CcZ>*PuJIKdu)h2+#r^3&p~HWn)z5#S*8haAegMSw1*LZcU@ffw_Dd`K5xW%3 ztt`g7-TNUiGWnouZ2vj@@gc^X{)W{G6wBn=SjX!AGy^8x{8UgZ80{y2?1y~Pxw%Bp ztr4IXl&Ad`EC?JmxNTo}R}fs;ojX*3IN1#n7+eEn^K|{_Af&^E-?ZG80zYJ=D{=TDR;+>rXZ50W80<&;+Y-WG< z_0j%R?Qwv|0j$A(yM9hazj2Vs1C|DG4P)y7+CVD@*7gox{lP=ufX&}qhYZN;fkL{0^@%?x;BD8|7MIpf z8is~c02t7nkr;b*`V&AbLIVSb!dO3U0MpjLGoJ8$2MtW{{$ybnw67WPbOe+cDoQ!qZRUbKFfIf;Z*42 z#B1^@^4A)xbdTKj~#wzG!{K;)$*o5 zBL)r1P5$VD0xkyxVsuE@i_2~%-p!7hS|p}n4yQG*zM7ACWQ^~Y(jgoTAm&;bdg8`i zZ7Kyd4*bKnzkLqUMA*BI{6NTdHz%N^^7l^*$NbmZXmXvhc1%u_tC+vwa|pwNgBU=o zrUmiTCIQL((ar@)#;^PU6b;H3;r_S8eaEl{KPR3I8UcpG-4~ z&xi?&k7=L#vbUM-7afp3;JHKAv0D`8ptQH3CY#Q`sw0CVIwMWaO<_Mw?X&ChP3WPv zdH)WPxI{6xM)nLO*+MxW31%Wku2Wh2@n!UgH(M`Xw~(SJ1pOOZqxW6zQK#>g+P~M{ zPO*uOX^`@XfN?RL0k`t4SwAUs0zpL0Q;Ui7W2N;dn#yZLhNZz7Kuf6U*5#!|+5apJ zS{ZprJJc#%AQ!J>TqyMXicUEneu1*!UsXWW7=?ixKL4;(s90p%F9%C9LAcB;So63V zJs}%3-k}zx`1s~5?0--ZOa{M_ah-k5ucw)!Js{H;X;yueGMvWc@H8|~ZndtG(rS0^1> z88Cyx%Njdmb->hC@0sK8-!^0oexvaEa``@EH*Yk- zT{Nu;h*$WWHIPb}`NbBCx`~oLa2r8G_pDYRnV3?MylbLnp0F<1aF(Qwk6-2~y^UbGSCjC(x?H;8nRF*?$C^Dh9Fy?9otY`7@jx7fGnZy6?F#6?R*kzz_ zIwC8@w-Fl0A8&dZzxW~|bo8~nYa!0a>%s1!`G`mJ(FVj8Rv)yWZX$U-7E1h#ft;Yp z8#@&-H)&-)hc>)}`$Du`oecy69dgfT%LVDaY@-kb^S;nI!0U0aHU;!gAfg=|27?1WU!7kIsA&B>71yZDssKPCC8CB9@eH zkd=lz=e0ct-u`pHbHai~@e2w%*jnRFQ*42TMA78iNK1rNNCj;7M>6<*G2Cr=pUnmr z&^0uQb z;@$rQMdum9Mo=o_?5#5j?*`o>?QbpRKKA)WMLQF*GJ}EfzN7o*f0taC0FDkxQ@50s z)HoJ{821hqw!iub{V0@6Z7!TO@m1&vSlR&d+8{zHFM!hDjh%4H*t0fMpE7}m-#H$N zi>%-h1zW-vgBb0xv*|*hud5OpnrrThaGd-nMSt57AxB+Km!M^lUNp^kJJACqx){wX=G*`-VhO{cqa z$Gzn25h5`&L?%VWsedyyLXb}-mqrzUfi;Qu7A1wWpV>fD!e!&PB%ozetdkA0tdl1Q zQFg^(0-prgab#@5tTn39FyA%;$lg2ph#7T;z59ifN@Lt>2^sZb)w#j;XnSyMWrS{5 z)41&ChLmHvu1Be*YsvDeSjqw0qmg02oOG_-) zY;-3zK;T>+u%TRx{lTnweG9v&wMvS8;nAQFQVkipb)U9m!I%=i(7lEOa9p=w_|T9l zaDen^xCZi*z_T1R#9g)Ofa~uK%VO0LQAQ7QR%A^f>#JZqjQ!OCn&kKxc@<}XzuEk) zmXfK9?5CU$bot0k5r6TIJPL{!nd&|cbcVqAb#2KE7mjW>Z>@Av?%yuWLbUMVOrKz- z6FUB;xn5rY?$R^5EpU> zQ#YfFBLF>29r}9XD>J)Zi5XZ(b&FE>uw>l2+odEQSA@$;xoAnLvKin3LB^U;bFV`2 z2ad*OtQYwO`6W}nhsJ}HvUFabjc6!yvg(8+URe6?dc(!mm7+8YAQ7oVjM6s_IPgTA z6C5_1!a6h;af@i3H~NH3yZ2Q5buW{+{g2NbaOAKFX)S@E4zrwKPk zB@!y{iOOD2WY*M+73&Ov!+3a9AP@7f(R=YivR_q4*1M=1rd%l2g;r|J7_+W=(#-~8 ztqzcLGp)JPUp(h&fV+JelbiHblGHr^L3!zbs%VVd?VeG+=|5ra41`jnN-G>N0q2yk za>P>gw%v&sH~rGxb<6?3GVnB}>lGIlB|4u8gjd z;OU7pBO$?M(kMZ-0@RqWE5VAB?Qz%z3CQ-A5SQN|uUMAfpKu-eOZ;nuHEvQiq$He%H-_*G~^Jfdk z&Hnv>TtX-10kC@ZuLN8|)E!cUC4RS%Ye)YfBDismS1iIC_WqThH9!6tVL%&%|A04_ zU?^bEZJ$p3(IOZd9ogxKE`4dVxI)}W$EOidXjn+ViAZYL656Bo1nM7l8f>O6u)!5Y zo98PPMkGD?L}>2KYaf>=2_3k*=G|3+w9C8_3)ASS2)H+fO@d(jB^DMj{_GHXbQ=lWXo(quU=9 z0UQ_=0chNQQK@$b1DDz8 zz%JFziBhsWfP~k$W}vodO%jr}OT{CK?UqVc^%wv{U|_7VJp4h`b|0v4mJ(tAbUSIl z--3;uD}8M`C9eSzVhG<$K+mR!GU|x5GQ{jN2SnyAVJ3ugWengrh`zeL_vosVIzL1W z_w-j<k+!3o9)|#%;d%? zBskMo+Z7(I%pjHUqS$0yNy#1LSBEQIt5RyyKPGxOx$|@W?V`Ekf#}|xjAACgat_&` z0N5)V=BA*3;+ai@fW01*|6q)+T5vzapkaCeN6Ly1sBDrQXjK1G@~1v7taL-^E60X3 znB10yK#AY5#Y5RJ{TOW7mo5IT_*zG2hczxyx_W2DD!1CqC0^s@hkp*R^iqwBtcS-a z!kbo>>-`LRl<0}CitVlcQQ%8YAd&XD253?3X*-U&<;pfNHPh85V30&hdczm=W?2n0 z4&|(?#wD^)tCRyEAs3wApV&yX*#10xRi)^*3vNp(VJjemd({bv|AOq)@C94xqF}Z_sAX z9q&$PSZ4n!NBQO~(?R-IiKpFfvY(RVyGCH$+ot8pBDxMG`vymq53HnR0~jxdR{(!+sl1BZ{4f4Oul;ppZto-L^HcoEZNdSwh8_gB6#^6M?vJj z9D^iXis}oRKzkVm0su%GyhS49dbdw^G?|u6TYE(5c=Szu;b}iXW$Um*Q^1uP$h8gq zn=#*AbSCYTVp8?Mn4&?S^`dN9`v_)L+wcj8XYSV3Ds^qQD(=rmGvd%HieID8dRM)n zn03GM+?ZKq;O0$Em-td41Ld09t;e|n(U|JK3logpA_y691bp%Pa*+&a>c(^1k7KiH z9uIUIPCev#u`~Bki+=IOAQkKIU46YZh|_Q%SJ#NoVi%~(OKYzg`PXG zygylro^^7b3;+n{VE^7KH$#I^KMW8pJefcwgTfav7}w?&$cN6#*`8Bc*9cDjTIEVa z>D_`Gb-ZJF1(en#0u59Y=Jc#m)}9$3eni-m8fK4aeiQ`m$gs*G|30X`Ka=kaiWK9# z(w0~?*UTeIpo`~LV1qq7MTq7jjY|pA1p}4QTO{BQ4=zh11 z3Kc)W3E;U@eNbgpESg+rv^rke-z=A=hYM{UEUUDWyZyokA#IpxB{@O2FpqE4W$c^i zOS8^yXj|!MfA+!X3~7zV5%73?rxbo0t&pJ^nvKMJ(aUA6?*85Q*_03f&z4`7I^X9j zkuvb1JU{L;5cl@n8I~~>WZJj`z|6{K!!d5Dk$ZHcdYw<;KCKc ztd9Aj0lFT;YEpuD1&4UqDNh;)CFOzb9-Sjolu|r!UU>8+8W#j3c6v`Am*K0vHUST0 z3DBMX#uxi89>^T#f zMn>Nlhq|+0pxWxqo^k%#r`WDzXG1Rx;nAekA|1h|Lsr8?3s3*Z&D5QY%xP1ha z21hR_S^gT!KnMR)^Fb_!$EXJ}+BsX~0RTKkH<+p+H(M^Z?5Huvf-qj09HMJb2WKQN0h7MAxab*Mq#+4=m(1Li%Z zG~sM#bq@EHFP3+E04Oaz6xPySlHIysE)7cq3?;MEI8UgnHwbKlOo@f|wfu+ad(Ep7 z6O-M65@8o0Z0Fdjyf8SVQ|Pzj{S0gpa(XX@Eg-$XwbCwy&GM9b)*z5c09mfanyfbJ zYy=ba8bR6)1kl8OF^9QFEbBLRGRb6^49hQCnfT_GLai$A0#qI)5?v}Otd02f{_l_{ zJ8yU0&m=Q1ZRyBn$m+CPT^|FNkUo85Fg0C%Cn*6NO;T@;d^j}G9|~BmeCLaO`vIbk z)Io&(oja(J7Q{l{md6qkbM9iA{3J4j_BtTuTAme82 z0$gQt@$+iKN6`5MN3qK^QuAEm55z%UEyj{)|22+MCLCaeKMK}7{pju8&d6u&unQGW zZkiuUS`ocMS`oier;i%J(LWk*p@59WM=2Ri+?QF`Mc30~rH`52BATv!7Ao5xt-69< zZ%LWMS*IGKa_ zh%}X^Z=iNdoWbAAb6T&Eg%7d>)qN(HxEMv)(nh4HoHEB~ap@HlJ-l);swP=cC>SGQ zJU`nve#2eVEopx677J008-Zb|b5?m-X#}EwKnsnvH-+Yr0sKsz@op`JjBG9;qB<<> z;)Uf#2%-Mu8T5m9V+$&nrq?--T;Gxunq`~(%)JHhT0>3(k=i*iiE2P=XJh(f?kf$f zPJ1+>=CMk(v1g^LB<+clFF_?MjEMDGMnBDfWFAp@nS#>EK zlv>Hs5^R<>05sghgN5~;j}q-wqq8Tplo~jtot}XMp^=?GtJK(=KyE64b{3Kyj16ql zFR?{cIfjJ!#SVfFLE#8a;p)~e%d{}k3rs&GnoMh{KTZ;~IIcA#v+HskL`x;ZlpP%U zthwf2Dk?1v-#2>$avRe{9APx2^9kJiY6Jw9G-ac>0Lk`$Bc*NjJYJ12WiUS;YfftK z7-`RB9Blcqeh5MI3MV6RaFVrK1=sm!x1SNOE6`EF1kJw8)r(qGj-m?coG zHq{nR>*kKe707gpM5@B%5sLVq(}9?{rz>wr@m0QBBaB#4m&Ou!MZr7R!W?W^{av7W z>FhUn^ZvkN#wy+1aDQ72_;xeChcJANQ2xEI1E$$Mb_os?rX(FQXMX1^||&2KVW+Y-U>Ei(nqHvul{}YQ znhTV&TI}DfJbI%}(RJ5p1WpPUEJbSVo+Do{l9UNwvJ>bEQ$%~%r79J;hT1v9O)#8A_!9IrqYq%Y#wEY}>X9u;LPNc~bGFzlt8;Lq3uwCezgcC!!1^EvzSLV^~n zQy+b1R%ajv=Biavsxi2BEJ+}20O2$v%|ANIw+pTAqz<8!NK9qlBF>56Z0TrL-y!rx zq5+AG8wt#9xT%Cin>4P$2_g?dxnnvwb$rP}^UUaROf9R3aAwARA@iQplz~U!awVO7 z3mKYUMAD!5k5`qkFsfFHH8bD5nhBM6Wp;dj7}6^MVJu2imr0Um1e>h@ASI{nFTs#I zxlL0|tx52P5T80X_o;rP#(&RmNOxI*8$DMol+8JD*j@`Pq~AwPF^0j<$vpUYY@_9S z?XKIpSM~R$49-z99oRnlCT+`Byho>C_?Q3gWt>3P32m^t=2(AFpG=|ua;!arb2`r9 zV|E72pRHee;SSOvXwH8<0M)$nnEt`)%3mNi?{LdWY=S`@QGY~stoD@}EO+0eKsrI& zZG#V{|GKoTFl@|tkS?lvGAW!?Tr@mGKbk<{=DiQ%)T=?&_VO$$2r)H%n@^a%2@lz= zE|Y#{Wok9;p7z%KiDlhVsKRm@NaJ+NvQEtH*W)S~7%O)FZUwb*3&5vVTY810-yB>x5j%d8z%qM` zMT0^rJ?kHw*wWx8K=GUt>6j;}9q(J7kM26-_zZsw=_vmCUH~7NbeV}5D>pN-PzdIZD0Q{bW3~IgF!3wi?37q^ z#Z$Jxm>JgaF@o$_q4V;or(O+*N1YosyuAp5Njoh)vWlICHAUf)Ol{VswaUBDtOfjv z!)Bc4DZB03O`?e5m1KUYhDc=*_YP-CP^NEa+H2FT?RW20og%m&JpDhi9YTj-`;=iP;!)@-*Q^EuKG#gz zd@}Kh{t2@x5pNmu*4u=(inx@ulO}MBh4Q~Lx14ZAXFp@N%=2K4U0N$kROgzXVxmcE zl=2-|oq75}_IdZ*_WE=^4}A`U1T6`RiZ-&NDHB8c%T63oI0+K`pirA^(O~7H)WypS zjpd)IyO#;1L1Z$Y6uru#s4@6B4Gmd8~%}W9207wshJ&=__J`1Z__YUrZQ(xy`-r4?1ou0p~_I zI-@i*o7yhYouohj_oP$bo|qbi2_dma2vnC5gdxO(N!f|!ynP(BX@(Ab-d(drI6-Sa z1HhJAAd^$K-URq=yRTzI!L9I zyUW!`YgBa#LC`s&yRVseE4w2o>bI~r0l4MRkP8KXi3RijYkO#tld;L!TT$fch}+ho z;Dh`Fj@$gNPb3^3x{a+5@v2z~Tg%e12!XS@y>gU~%n=?>%7qP=Cu%bV5@W*_Vw$dm82#*R4r1fspCxW`g=nmsy{h09}it zUD!p%ewu+TW`j!F8z#)kLbhWQUvv8I^W7V6#??WD6DrEQwa=DJ7>8nf`Xr;`mvN`M z=!7_nNVZThY{xZ<*vd+yoOQtd0RRUs@Kc^J!A1-XWtdnb@$Z`rp#NJq)__qaECnlt zD3FW+*SkXs2*%18AVN`@0WsA)d?MjBV1yf5so!ecWZH8p{G?Z^M z9XX*nIbptXiP#po(uXkC2lK%`zke;@ylxV=#n&)iH>IY^L<#wDsK$z>!gY8fuBW6B zzAztv^p#;fbsN0CUSB4p3n(n0j0`x>#{VrWrMNGdjf8MY$@Fz;+5`K8_-Bd;%N&pc zFWO1wokS{?hs2xhtPIlVoJNTG&0j*HjYIbOk@XoP*+*S;f$A&>;v>L2{OZz7;_GHJ-*Ci7&j-lc>DUb?1~oCaoNbVD!E7 zy_Wp>m7F#=$>R?c1?Qg-yuawNv9; zd4@$P+9J-3i2(W+6{fax3lfY2pYmmB^$+(AUOQm46pq94BPW}`EFaMn+pq-!@rgsZ z*rGNyJ8NLcMz0{R1=JNA(4i@jyiy|lM~(_p%@Z-ALrh0Pb!@5bQOHGNoDjIJbc~}l zs}WaCo}?7t9etId6Ur>Bwxl=Yjz%M^j}5LJy$<3iIRN`!ZFXJ9bDq;}x4rK7X;m}L z*xyLis@;%D4As?>v1sp^ydZZdn}cf@#|&|O^W3E&rL+)(N0P}@*5Kh4;nmO-20>_o zqQsR@{ZUh`)7ZW56JacV`hpA(+@Zszj z((CwDSaQFlfnC42`CzH|nJRS?ZUic=_wAzmOSfGgCA@Q4RXLtWtu4nIefP9?zNkSo zGk-d9V>MyVQ%~J#mFY7Yz#vGf)1v7ORNolLIiM7-y~apqT>G=w7G=b!M6{ao1D;ES zXL4rTZjPP!Mln?n;SDE7(?bi1S!t_=)ho8^2`Uh@{fcjaaApM~4x4}gy*VMFRY`4> z4wB(F=iGSXG|WpOBkmHdsPO3u3DHUST@u}ihE(8P^1fnu&)KTh7W2OWM+(LzGLRv# z8bDx`b@WJ@f~NR!QDf}R&32c)W0E7dIgo?fDA8J&pQ{%gV!1cZF#aV^v)&}=W{quY z0e1{gJZ$BH&h;S;{|=(|>1gw4w>9ol(v5_%TUrSQmDQd{-#?rSLrAF>m~7;Ge=DsO z!r|Xl;H`Epu$0+@ipBQS-bwo^SGU({-jb(QX}JI#p}Jp9%P z*N72rS~}o9y*3&FU=$brIRy96*l~M>8kP9GVqqx0(f(Rh4RvR<-LWM9ufpCkDz2^R z8l`a!?(PoVG#=dDf_rcX7Cczv9$bRE6Wm>cy9a{11$W5Dd7pc~`@A_n?)uZC=dQJ? zX07VpV|4E|tL+wFo-M3};KKa2R+mg?nPiu&*uL(L?xA#txRhIGIo6|LzA(_LWHmc< z2Z)Vqr&6;}OhDeVs|Yci?9SF+=1p6BQ8}(^`jL`CSt4IAFBicW;oZ4<#Q&r7y>un) zP4X?ds(On1G6wuRh{{U-gx4(DuvQqmgPJ>42=SbU>-v1m^01)pW>O6T`>3H&TSE3u?H{J-naBk(Pc>Tf?jb&?S?%a5whg3 z2R_|)O|h$3q+3GD7I)d?4ZHnW7`0l~yA>wz55`Y!D;di0x>a*#Nbg^ggJT?HrZAMU z-t+t93f?omH@6X9OC-BTp^3ytizpY+LT&XLefHuSg)qZuZdx=oqHxa&ikb0f0(yZn~4_PoRQTP(*o=sCE=!WQlWg|w% z*;l#NgybDkJboQ1dJEirPMi=gmNqGT-1~ML&RG0Am<0|`n5iBD`0aP@bJCFxbk<8lT*{}KFx$EsmLhD+9+JpAzVa4>?Dr&BLj1Nk7 z&3w^M&8I9vJNA3C@HJ@0H8_)La`U}Q!3o(fNmY{=yXD)V%aLDdhb+94$$b@_X@1NP z7#+jhB(1VQ^tregi_>yPXNodD^V0EjSr29vjB>l{`3iqE^`7Ct!#u2-63zUzJ(h-t zfy|T)Zl^Xl4d!XMP7S=<)v4kro2Vf_*$u`GKFzP+uOcm^y)efkw$+`6k`#=%Xery! zl?1WMQPCqE40?E?`H-gQH)Ji^O!E;vN7FkbfW{?Pd@{ZiXG4btNXhy zO)+6YSEEVSG8V#_Dy?65^9Muzv^x=-J<*WCQ10Z3;R4eX zy-O#9teZ8C$9M=hw~1!#WyUx6@?j2$MEPIoG~iq%4m1n=6e;m^FxVkTZMJN(YareW zGQJK~KVx*WzASc_VSbZL6~M`^jv1`O>>DBurkL;<@E!JgH>D38a36}JV3@GoLhIIM z?(7-VjTCrRNj!6I1ncsDGdh3O%(-V`ERgepa6U+&8PWE}Lv&H>z)T*?md+aLxTHPa zqG49{O}}((6!+1uFtfr}fD@Bnr{G@S9=oZ%;*uI|+{LE;mUSI<`AEY{=Kz1e#j1Ps z)j2t3%I+ZqFL9X*5~r)7Oy_FD;CA$RgMtl3$HfxVV{y``f@XgiT0i$0zPHo`gF2>i$KZxg zi;wP**h7!rAd62@W$5Teh=tc80X96q$s$@qP%m3_zlOIwNOv*+St zYmDDM^kl@)iyn#89lCBg{XT1Fq1-knzP8;`__-~lm_sW3a)KS}b=T6%Uwo-PV}@MU zfhPcFTs9xG;n(1cu(>UThtQHzY#!Y+-@zHau7u`uW{@j;dj{+7WB4w|>?S1FKy1wP zzc{@7Zg&M+dNsQAB-ehFEe!ryDaT;*%b82+;w9w1rS{pd;M+aTmLw@N4^R?@93pT4 zXZO@Tn{eXc$dB*4>n$Bn#OJiwWfW!C6y(bGrc+kneqvu$t~P9DDwA%b7=r3EUgAkN z*}+mOYj!Kwp>rg-n&ch(6E4`S3PLC8eK!8USYV)vIV<5ndbG5_$U=*9)sfj7c7g5h z(ZD}fo%fQT$+OeiPSN4ccx{>CI=T^|wU7*J>xtdiSgnun-bB~Encih@svWC8lXZm6 z!oBkpgFU=JH;aT^bbh!*;%=3U$o+O+r{njd@XPeR7|SU;(H-Y{KOI!)Vt?>DO$vXhKeCvj*3#S~ScOW%qm z$Exq;38M4QzU;>;;|AY4ot2$`;l6llEZUZ^l+?d3h*SbqN`Kghp1asiB&jzi4`J{# zgcgK~ln+`hnk_Pe%j?^aXM@BOE-6XrW9zY?!FXi12N&~O_&CIaaoul=11<+bI6lSr zoHh}~^sIOnw7_o#2$et8an4&kVA|yyzCt$@IUbl9RCH@ga;>r$(ve>6hxIZr zvq{E~zbYT;9v&MHg`tHE%t&q?3#vUMx|!3%c?srmP}l#YZbFF+T#jKwdXY?vqoLhB zGs_!}dtGXOPHn`!eJZN=|9LNJ{^X}tl#GP7MKCz>AY;8|-texS+-R5m%;KC%K5k=9 zZ+-lQu8-(!kNZz@<_%=|-M%3SnDf!)_oIorA>3lQ$-rKEVW3td*&!#Lc&ouD%V;5l z6ibejo90I3F=+TxRh(WS}5hBdL(E`?rziA!|qoPs2*9IL0a-otlU7fN^Ce#k9KMU!x!s|a$9T_egs>ee zl@bjNm6cBSvBp(0*Zdxquo8biUHhF}a%)v}!@hWAx^@gQz6s9~*4GJJLFPg?=rFyu z@O-}S4{w?d?gGkcU;O@w9s`l2&>AX#?YYCtBk7dXMNkbPAg7HPLtbEY+`rugu3A=U zek<0i9K&j1uI9O?0p%RrV5R?gFNi2kY<2{)s%Mp1*!z6_PN8tq?le7puW((3{A}SY zw8fA)GGY_blgwW2uj>#j2o2rhySNiASS$Gfx>vN(-x!&O;GtI+O$d%+^Q)54f+?e~%Bg^eNdy-KA;3I8xs5{F0 zNgDDFI(*%60ipEn&mAADa?~$ys6}cZTkGHXRF1UZd@L247B9H!l*)s%F6|LQ{**)i z8ssgil|BE!h{kH_Hs^RSsS7ld;=m?xpzQKK_n5iG6b?cjsJoKk__4j|oil~9NM~*0 zv0?`U(Yg8)c5LJ>fQK}3^T}yND8yVt387CQmWr3sycP8wcx`)^o`5)y{YeS)v!Ylf z2!8ao3D<*W+~iLDgJkI zu8wcgA8jb?1ws|mQGY6LkEjr%jCW*MOw`WO-X|7?_6Z3A?p}Pd=wt}cl)emC5$T@y zC4@h|D|^6rrBK^ofN~+W;qGq*_%hcx$HH-5f z-4SE9$YIhxS8$=KcGVH7WvLm1%P4=etJkD42wSd>LB1O+2c(9ROT6l)`;Xn}tB?l< zTc8{cEcT9$D(Y!rBTdY=QLJ5vmjJ%{5tk3={7=!XvDsE(ys7n-2WI;pt6(Kz5i0SN?Kug{Jqgr(Md4ucB54hgJ@_y3HR$-@ z4W-Rt7>w}xKZ_aWsyIzZ+AuF7SwgaZtaiDEId+{>xTR{39w@sv_M-d8!dx5kK9y%_ z*pPN9npN51=$v+eYFdmdea=?dYSm@Js_DxQ0Vk6~e->?7}1Whd$M(o#CZQhI7En39p>#h{t_A{OXNz z>{ET~;vjIn_t6L)#c=GygWgXD)G|BeV%nf7VcwYAoiJUt5}*D&1;`8S3PXRItz1cX zMCJ@X@!X#}psU}~>Ooz$NXkU4OT%sg-=z`qOf5ElX!bHY_{u5W?L0eoB#Y5erSn67 z?@!_FCX}MFI)KZlRZjss_oH6#i7`xkw{|da8}hI;y;=tUZ3Viev7( z8{>sgHU4D63Cv!$^bLrTj5XalY>MV{c-ldmr@l71mXSUSeUMk=&HN=u)U67BF>lFCrLFG>^NnIY)hD|-L4{O5>l&W=CEr`?1lcfUYu1jolgivm zynSXl)UQB&1MtQBM6zL`u|XC>HtD35KLk^9UmTl1XK<;BM+%&%>g4--3qOE$FDbCF zAjmWUwqB{{23TKrImvb%yJ&-Zv&?Bldr|tv?XIC28;aDwk5zO=G|ug&yf}Tjs0Asy zPNe1Bv__Q44JY_V<)}ra;V$y(4dL7g&a6TA( z+>;;PmD~+XqI6^>N>nTFspp#DgHGn}fDp&zTx-&AxfT7yi{E|9uHQ z0H6hu^R-%p`-&g7#}u&Y{h%o~jH?@zNYD+%RHJ-8NE7!|G&7)CzGkR2{pdiwq_j6<9Z!r%*uE)zV*yi~C5b zE+(c}=w8^kI2GC+w_S6pN!!EH2}!uHOfs6@wLcY-VuY0VrNl*p>4c1;6IVjn#$c57 z;1Wp8zP%u^5(%o(l{*`h%BwC6lC6#GkT+cZfmI-`+wt@D|Bhu>6~HbWhpcf1R?F(< z?OYwfypsZI!DmBp{BhTd(cRshynP?CHsBrngl?3WzCYnqMK^eK=K>OW4>?>*Ki`4l z$$rV~isN&kfIU(0|IykD7<2ICj1==!zf+ z6WNnt;fwJK-gk+^S7Eh&)q+&fum7;_j_0YrEEhi8`_b@AY2CF!`UKrx$GwS+Gi4aZV$=H17z7SV@mw4Ic&&3!cA5yjy12H|SYh6H__A+_r7-LmVb z4^8tIsp_9+YE`82caLQC^7b~5yR5VtJz0_gxM;h3^&DA;iWN#nf_Ph*55HTmGBx=nyM-S(3 zrZR>|0OFlu8!X*s{c|Sg&!FWdM2~=H^I_G?(F4B_179mQlVA^z@mnGu;C0{ZB>_+g z!Wj#!sXe-`%^WD55K?2WDPZ;crl&DDg%JV8fj1>%bN!-CT(`H--ck?ZaDzmIz@R_dS067J-2k zDN|U~UWKlZUx3b6jtO*GkGIJbo;Z;xmEwnjp76Pm}D)WzG= z`NEY}_iclW?OFc;_7S-ePF1o!^8PELU2n_=b;OD6enr-Uc2&Vb4sn3Ee-?u3%*0L6 zu8x*AWkLMaxMsaya1TDm^^To7qp!NEYkwW=aoZPul+RjTB-m8wx#cBk7?c@s(f4WL z+)^yDl;Dfs)_4IBtkt>06<$kx2Z^p|9*6HZvG0Z(uVL_TnLzz1eST&Y)k+NxnE4x9 zjn|;PsHT@;yUe5_B9}$et=4-wYlet+#|5D*lb)dYWMXne=r!jH>=GNsG%Q4dI~0-b z?H)eVksdzFg@@H{1dq%gh40d%aZdc4`Dl&THAwu^4!PYRpvD!ZsKxIrXwa2KNi!6V zUl}&n@#ONxHWo{;Yqit2C!1Ot_-1@+_OgFB3`qy{h(=iqqsb|Q3KE@#TL~SM)S{=b z9TNlSiV5=5Z#qK( z)a`4lHNR5-w=2C&I?B;vow%+gc&%1iQ$@5p{B`D=i)?;U(&*Zhea!$TS(^aL5favI z?TC^iCn})oA6qMSMmSyZ#6Q!~EmVk_g{!MAlQt*O5Tm5o=wB!6w4|9sclGysM*%|u z_Z?KSMfvNf5`o1#mM4nV)XsdccWN3y+sqD=a&DIB;8*Uo&ZW{F5fYOjf)Q4|4t@+^ z`^u-LY*DH~{7YWUk0s7Y!2S~_B!ex!pqs}DA;yFhI}uMg@nXR45|$2^CyqYt&>ySt zs!`7$kd{Y~^v3^NKt7@g(edy#TLsSfva3X;;%m^^6k#KhwxFS`RRn{k9XBl{J< z)T0eUR)ZY^nK&b8oWs688c#3gz)3n}T8dR{!z7DNz)2~WcNT`XFB_S5ypblsWi!a> z2O^_E8Uns*c29u3eNx{>V0o05JW0Et4<|VVgflECXv|{1_R+=Bp7Im_dT)PkiUsjE zQnJnNv0Gx_jn9~&nuE^Cx5;tGkh^J zw>Z(d4n54KiRn9xXN=O1%^l$jb)B#@*nns7mNupz??Y&py=#r9I*6I)L&`c{hE#d@ zkXeX3poAEn31RGyP@rN_P$$uC)-my_MeO=8TPph*so?fxJsjuJuu9iqrIm?ukry7PT zq8<#xha3}Vh`FIiT$7W(ycV_^4fz5?rh+j>$GU@Ce*B$u-x+@Nej@VfM=lQNifg@y zuzbjakQ!G-_5P`2dGJUvEMa(@nZ8}+s}}y7iq^H^P;c?Hi!{%>Z(J_f@`M_ji(io0 zIP6GXF*3p6S1Nw|?^K8*;<>ZTWGFK3L2>-7GyDs`e*er!_OIE)CQqHkWPnV^3i!*- z@wQ0Hl=~hgqqnRN^=ISv^!jR0D2&=+nUl3imiu5k84}aA(qn$`q;aAPgc>87?m@6R zXCt?3e_0er*qif_X_aw1noVl30{M}nT-k+npPwFbaEzad#_*tC{-)7*!3ohcG5|xP z(AC6$9FXA^qfkouAQvM%Wdq4Q+yx?pwEM2sJ;a}+ojEx%L#jVDF!ue*euq8`ew;PU zm183*PyHh1nk|UoF|}OR2nC%ju7o0#beq9~N_iu)`ee%YG?VZ!y~{`zA|QU#ki|E? z4UN}+-6ETgZ~P)i?6hz>tnc`~TdAq@$exa(JhaZ;il@N&Jb&IDz8JD+q*8*|qrB!# z_b_8WtmA$sRPov3GwWWe)EAfz1wT9rF|7(A*xi(Jans9eWr6F%AwKbHPFdn4w6v;# z!t}PiqM(eoV>q!eqwd1^uOfEh!q3Qo5^0j`UIcprjRCG>3+2&(kia%=kVCSAS>6p7YjNZb*C!Wog%XNaQA2?6%vK4Am!oB+DXvquso}) zBWz@eZpqC=;moN z{QTCjH-5?eVPlgk%+l(yd{U|(IT(KY!B|22YWzA7HGV*f%y#C&eqqDhsif6@kW&d}x8UHFIr@WU~ zomas_yEXC<4~!>>5HR-xHQn29EwBl*{_`90Vj*Z>*VGrgaqj@1+vU*?;=RKamQocN z9lp?Cr})}PUL?2@Lu0P;iF0XRjEYm+RXc}2_#X5Fn+LQge4h*E(bX*d{D`GC2x7_jET zf1gu9l$C-H!rCO6c^-p!H$$PYjH_tjudc+bR{pyBVf=hPlQS+^X==oDNQTcbqZMWt zH#?Z1R*($Tt$K2`|6t-n!WBOi3-_y!U99R=?omAklIU(~&X~=m$?Dq2nSc`Vb@`ba zWlxwTh&*-u!mgu#-R#LP`(2z|lD6Q2((STXEy7WpdB@{&?U4WA&qsv%RJkBL|ApLa zP1aDl8umh`uxFEmJzid&02WIne(rq6S&nWz5h2|mxeOY8mR{*fXfQstMuUvI z0g4ImkWXrZ-m2#AIf94jO%dO1Lmqm+emaJ;F<^ym72fE9GhrQZNzVPzzWfzTUGMrlvtDjBQgv;7{kdLWqX3vx7xq2Krt zZ!J;5ldo6I^-k5JP^)|ob#1I_?ggDD)Mbl23}m|zc0wDsGx=3X@Dc3Mnm8wgp_rOb z&-?L9_5@+RltY^hfp2Fj=6yKk(-}qr@rM(-8iP;$68HzB(P6X}^6IXR9`F$`(vCf4 z7_nmc^(!Y&-6GgdYP-MbFzJ$TD?+N|!w(cZW|{n(%z5>7Gr1Cz$~2wJNaUQ8_RC4X=KN-l~Hy$-6M_UdA(cG1bsXnHnBVD@7xp!1?9Hwx)@)6@$U_PnxqH z07c2P2BKzW*mBze-`0bkV#kKxh@Md)3U-fk5!StRC#CaiFNj8LnU==l*?|&NG&?-q zSp!Zp8avj7TJq0u>UF2WUpXPao2y2aQVs<%B#mn=tAany`aRiSuF}fz%Kowt)R<)A zgo^TQupz#Y_5hRnes)T(<6XBr59#}p93{D_J#8*AlYH;>G7G%T9SUj(1aIqFQpBh# zMZRNKM^P{MmT|ExKAV@Pj}wE1oSLDjS#U!ei0I#Q=DJo5wXAlu0JREfl_yOkD^4Ko zr}UQ`*5iV8VFh(JW_n`eh>)|>LEB7xN9=#akWffbDET-VpIk&Q14+L+D<^=P#zu2Os`~ z+CdX|mh|G2S5mbFazhV5)~j%e4lT;?2U1cMwK^Nfz4JKFwYLzC17X+kfuoNUk>-ENbk z2fbHMm_BO=P_FjkbG*)@D4qM*Ns?Ybidtd=`F%cLexr*>9b3*`8SOu@J^Kzc3$JIg zFAUY7lQ%BiB7tBPPUp|Z!}^L!r`(Gpe~CY8zqL58eU3)KYL)SW;kDlkG4M*MbM4_9 z0jgpf+~#LUXb~nQBvm-z)U8u7adKx=K0H6>^>!$FNgLsPXlbDGqzV*DA@e~j$O2wC z6>*WSgK*jweIvb}1bAwM;jbST>Su9!ICcoH)qM;lf0>zrE(p^=PaTztbX%`OpCeff zJAh?2kVHU=%crl6O9?FIWxXe3<-pE43+od-^T__nah~u6;x`;@Wj&ht{fT6T%8N#l zW$rurHre6Lp^j~%=gIT(4o@-K3Fw&F#gNt8?;}UQ5T}EVuJ0$qIyQAOs_^%Bl?7}F z3x`{tsA^hPSFt*`xkTf`(JVF&?78DrW2rt+nr%}D-%HOYS+yeb7K1gX3*QgV&BqD` zU+H(botVPFK-zAHR^)c1741c0HndVf_$b>e;8{O+TC1}d)DEWlJYX^|9+)VK*ysDF z%dA9QX+FDW3C6)(G=4&irUvlt(jOqj2UdLM94*OQm)K{|2AcNmH9fMLjze2ahnuAl zB-Rj9pt*Mz5>(Bh)EV>89|vvvw}!#nP%4xaO1p38&ys7(G7dOIMHhV4^z@e{7xo%- z0^CqAZ%i2S%wnx`7E{B!W0HQ$d>v9K`}(??0} zNNQyWj=ctA)xx-}@OHA7WUp4d&zxpTUZLDqJwlN(41|gSQ z9@I%THiW*cAdE5%A`XtGaYiJq9h?T^y)*!za{JNA)F>CHM1zHGmV2R~`tsEckN9z9y@ALt#{dXzRgNj z!&5#`CLND`W`lAv#)CHY%}`V^@CrcpHCJ<22=2NmJ^=AhEfoA~8ZmQ};jsoV*oep0 ztBb3&LwV+u`mCX9NE68OOJg<7J)1~Lq;A-3$b@3Pdu)t-vTZo=wGO?K7{04G_l)D7 zQtfN^Q6cb;rtG3co4D-DUp}7^krekj2N&C z5@2{wOMcBQNl^ye&2HOnulmB=Lv<%UyL@(O_}&24VAzpJ>T{|+&ATZi?)X2lv|VQV zQt8?C7H;`8X(>|$JmRLLI5?do-rQ3#knslXKgQ&7YVTrVm9M9>PmSwcEl8qwx<+=r ztl*SuW`oVJc@WWVMkQJxavVx7*BtX#W&K-6zlqmNa$v0JqI|jaladexAE@AF<(wu) zCW*<6MZ#t7?6jVQL5o5Cl9yAoT(*Xo;>dEXc;t47O<7(1u$I#U8w|uJP4b=05KkPFGjcgXB{P(WV5=3Ai6PKH21Bj^74+;&m| zA7CW1Cl&?QTExBdZk{-w$7xqL^%<<5^<^6TMF(XHf-}yXtZb5*@(;QSQU@Bl1Z`}c zQOVc3=?a{Y@qZ{sm7f|DK;S~TYa40ob3-WpP>vuTEba6YM7q16V+GnfLEv*kEvBk9 zVf#-j1-ONEYt9VTtX*Xl`qOk{`G;+mEob-;J6+Bb(L|G+2`_ru2QprPaRLnrB`+Zaot3N z0qRqcar`br!l4kzS#Pzl7((@Pf+4Zz%1Qiyx!Nbw#Sigaw+l`0-TMKLT+1k9!nS1a zmeZP(a^}c!f9EtKZqQB%$M^|~PX?NvzEzvbmKed|C{U*|!d)cAQGgPOErPjKC%3=G zH(b6&4+aoK_QRq{hG*Au3maAnO;t9(I+m;t;k4@-NG3nhg(Y571Yt3nE&JGcCVSDi z&HIj#*-X~Us5WVXp42Y5R8TN*Hd$b_<`5&_)S3bc8D?yaj95)?xLAFAFZliI?!zDa zq{(A^@9xU?l@ugT)2DS%4NitX+5-@CA9mJ7;@HAjzAfyTQ=g&&1JFu z^bJ1|ts<4(omHT-mSv!i5NU+k<}jj+t$e`jTMd@>LWg>7VCAiQcQB%BKE<*Ta_A@m!zaU)dRO> z+bBNaj)dO%eauk{?$%~19y`2iNqBpzSZp>5HaC{W9kmG2>rubm&Auyx*Rg$+QW67H zMy#c-&bVM}31Q}nH_Pgb$q+y{JzroeR+6|TcJ5>mmQPkrunnozBVjW z)I3*jUar$^nSJ0OL71o2b^Z0T4*7!KDhki0*VA_L{Lu=dYq@9Xg=U_~wKzRJiPhDz zS7*MAa`??%5ZaVm(ZPwy2(!Jp7b2|-tOnfh>ChTNEc)gWaT5qv+|3LuGf77^?d-%tLzg-9oNnUO4x0DHYu-A;Zj%H+M{ zaQb*P9`jGgSw`{h?zp5mo1FWt3|ifSKo>v9tzq}v$vudrG1Lz_$wL5mGxMj;IBX2p zEm~L-LuWU2r)cc7cl*Nz--E*j*pUYXB(qNEWg|>tU?QGB%epE~o+^0mWG0_8i*xiz}+7uonUdQv5)G zoD@C|z!(>UCT1|8ferxvXZ8*j$KN)b|6_Bk3%F(h{72(H1tknHiS@Uj zJ=Z^i_IORu;eZ=rXs-V#+NaPI0?Gi~DU*c&F^c~v60fVT8)skazC zN&)oHVBVD6QUEVB7jMc+DZmKzO+a7eqm#M43&k5ERR*AVXYgOT{cl)JDS!;Xmy-T= zDdi{(fR-{;2Eaw;`oEI=DdzZw&zy9n2&?x|mZi zNbqw2L2uVN{LI^ zH^vL%0RM07pV=VL-x!dWkMCa?7wD}FfGMLD05k{>2k*Zfg8mNdZE-H}zZL>2V@?pq zzu0qd@%?4@wjL+Pe`WI@|8IkvoAw(hM2z}$a1dBZq3|3!|Em-~O_ zzVZLR5x$iw*I(&+o6O1ccYq)u*T1&pt=9i$_f`tL9Di>eh=cQgW$=IU58~kF`#Xgo zFz8+`^I}C_SU9^UDn>hf#RR&|L2Vag`NN>kCdo5pBN9%TVFVdw@)WX zR9ut~2za`A97w?KXifSZpGnU+=(Mp+8^{{W?c BI+y?e diff --git a/doc/tutorial/tutorial.tex b/doc/tutorial/tutorial.tex index d1ba4fd..a554805 100644 --- a/doc/tutorial/tutorial.tex +++ b/doc/tutorial/tutorial.tex @@ -106,12 +106,14 @@ A GDB server must be start to interact with the STM32. Depending on the discover are using, you must run one of the 2 commands:\\ \begin{small} \begin{lstlisting}[frame=tb] -# STM32VL discovery kit -$> sudo ./st-util /dev/sg2 +# STM32VL discovery kit (onboard ST-link) +$> sudo ./st-util --stlinkv1 [-d /dev/sg2] -# STM32L discovery kit -# 2 dummy command line arguments needed, will be fixed soon -$> sudo ./st-util fu bar +# STM32L discovery kit (onboard ST-link/V2) +$> sudo ./st-util + +# Full help for other options (listen port, version) +$> ./st-util --help \end{lstlisting} \end{small} diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index 67f0be0..30ee014 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -6,6 +6,7 @@ license that can be found in the LICENSE file. */ +#include #include #include #include @@ -20,6 +21,12 @@ #include "gdb-remote.h" +#define DEFAULT_LOGGING_LEVEL 10 +#define DEFAULT_GDB_LISTEN_PORT 4242 + +#define STRINGIFY_inner(name) #name +#define STRINGIFY(name) STRINGIFY_inner(name) + #define FLASH_BASE 0x08000000 #define FLASH_PAGE (sl->flash_pgsz) #define FLASH_PAGE_MASK (~((1 << 10) - 1)) @@ -77,79 +84,168 @@ struct chip_params { { 0 } }; +typedef struct _st_state_t { + // things from command line, bleh + int stlink_version; + // "/dev/serial/by-id/usb-FTDI_TTL232R-3V3_FTE531X6-if00-port0" is only 58 chars + char devicename[100]; + int logging_level; + int listen_port; +} st_state_t; + + int serve(stlink_t *sl, int port); char* make_memory_map(const struct chip_params *params, uint32_t flash_size); + +int parse_options(int argc, char** argv, st_state_t *st) { + static struct option long_options[] = { + {"help", no_argument, NULL, 'h'}, + {"verbose", optional_argument, NULL, 'v'}, + {"device", required_argument, NULL, 'd'}, + {"stlink_version", required_argument, NULL, 's'}, + {"stlinkv1", no_argument, NULL, '1'}, + {"listen_port", required_argument, NULL, 'p'}, + {0, 0, 0, 0}, + }; + const char * help_str = "%s - usage:\n\n" + " -h, --help\t\tPrint this help\n" + " -vXX, --verbose=XX\tspecify a specific verbosity level (0..99)\n" + " -v, --verbose\tspecify generally verbose logging\n" + " -d , --device=/dev/stlink2_1\n" + "\t\t\tWhere is your stlink device connected?\n" + " -s X, --stlink_version=X\n" + "\t\t\tChoose what version of stlink to use, (defaults to 2)\n" + " -1, --stlinkv1\tForce stlink version 1\n" + " -p 4242, --listen_port=1234\n" + "\t\t\tSet the gdb server listen port. " + "(default port: " STRINGIFY(DEFAULT_GDB_LISTEN_PORT) ")\n" + ; + + + int option_index = 0; + int c; + int q; + while ((c = getopt_long(argc, argv, "hv::d:s:1p:", long_options, &option_index)) != -1) { + switch (c) { + case 0: + printf("XXXXX Shouldn't really normally come here, only if there's no corresponding option\n"); + printf("option %s", long_options[option_index].name); + if (optarg) { + printf(" with arg %s", optarg); + } + printf("\n"); + break; + case 'h': + printf(help_str, argv[0]); + exit(EXIT_SUCCESS); + break; + case 'v': + if (optarg) { + st->logging_level = atoi(optarg); + } else { + st->logging_level = DEFAULT_LOGGING_LEVEL; + } + break; + case 'd': + if (strlen(optarg) > sizeof (st->devicename)) { + fprintf(stderr, "device name too long: %ld\n", strlen(optarg)); + } else { + strcpy(st->devicename, optarg); + } + break; + case '1': + st->stlink_version = 1; + break; + case 's': + sscanf(optarg, "%i", &q); + if (q < 0 || q > 2) { + fprintf(stderr, "stlink version %d unknown!\n", q); + exit(EXIT_FAILURE); + } + st->stlink_version = q; + break; + case 'p': + sscanf(optarg, "%i", &q); + if (q < 0) { + fprintf(stderr, "Can't use a negative port to listen on: %d\n", q); + exit(EXIT_FAILURE); + } + st->listen_port = q; + break; + } + } + + if (optind < argc) { + printf("non-option ARGV-elements: "); + while (optind < argc) + printf("%s ", argv[optind++]); + printf("\n"); + } + return 0; +} + + int main(int argc, char** argv) { stlink_t *sl = NULL; - const char * HelpStr = "Usage:\n" - "\t st-util port [/dev/sgX]\n" - "\t st-util [port]\n" - "\t st-util --help\n"; - - switch(argc) { - - case 3 : { - //sl = stlink_quirk_open(argv[2], 0); - // FIXME - hardcoded to usb.... - sl = stlink_open_usb(10); - if(sl == NULL) return 1; - break; - } - - case 2 : { - if (strcmp(argv[1], "--help") == 0) { - fprintf(stdout, HelpStr, NULL); - return 1; - } - } - -#if CONFIG_USE_LIBSG - case 1 : { // Search ST-LINK (from /dev/sg0 to /dev/sg99) + st_state_t state; + memset(&state, 0, sizeof(state)); + // set defaults... + state.stlink_version = 2; + state.logging_level = 10; + state.listen_port = DEFAULT_GDB_LISTEN_PORT; + parse_options(argc, argv, &state); + switch (state.stlink_version) { + case 2: + sl = stlink_open_usb(state.logging_level); + if(sl == NULL) return 1; + break; + case 1: +#if (CONFIG_USE_LIBSG == 1) + if (strlen(state.devicename) == 0) { const int DevNumMax = 99; int ExistDevCount = 0; - for(int DevNum = 0; DevNum <= DevNumMax; DevNum++) - { - if(DevNum < 10) { + for (int DevNum = 0; DevNum <= DevNumMax; DevNum++) { + if (DevNum < 10) { char DevName[] = "/dev/sgX"; const int X_index = 7; DevName[X_index] = DevNum + '0'; - if ( !access(DevName, F_OK) ) { + if (!access(DevName, F_OK)) { sl = stlink_quirk_open(DevName, 0); ExistDevCount++; } - } - else if(DevNum < 100) { + } else if (DevNum < 100) { char DevName[] = "/dev/sgXY"; const int X_index = 7; const int Y_index = 8; - DevName[X_index] = DevNum/10 + '0'; - DevName[Y_index] = DevNum%10 + '0'; - if ( !access(DevName, F_OK) ) { + DevName[X_index] = DevNum / 10 + '0'; + DevName[Y_index] = DevNum % 10 + '0'; + if (!access(DevName, F_OK)) { sl = stlink_quirk_open(DevName, 0); ExistDevCount++; } } - if(sl != NULL) break; + if (sl != NULL) break; } - if(sl == NULL) { + if (sl == NULL) { fprintf(stdout, "\nNumber of /dev/sgX devices found: %i \n", - ExistDevCount); + ExistDevCount); fprintf(stderr, "ST-LINK not found\n"); return 1; } - break; + } else { + sl = stlink_quirk_open(state.devicename, state.logging_level); } + break; +#else + fprintf(stderr, "Support for stlink v1 disabled at build time...\n"); + fprintf(stderr, "Perhaps you're on OSX, and we haven't finished removing the libsg deps?\n"); + exit(EXIT_FAILURE); #endif - - default: { - fprintf(stderr, HelpStr, NULL); - return 1; - } } if (stlink_current_mode(sl) == STLINK_DEV_DFU_MODE) { @@ -200,9 +296,7 @@ int main(int argc, char** argv) { // memory map is in 1k blocks. current_memory_map = make_memory_map(params, flash_size * 0x400); - int port = 4242; - - while(serve(sl, port) == 0); + while(serve(sl, state.listen_port) == 0); /* Switch back to mass storage mode before closing. */ stlink_run(sl); From aa479e5b91a2dfd963fcc3063196bee7e159a2aa Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Sat, 22 Oct 2011 15:22:24 +0000 Subject: [PATCH 09/63] Update netbeans project config to reflect combined makefiles --- ...ge-gdbserver.bash => Package-Default.bash} | 2 +- nbproject/Package-library_cli.bash | 75 --- nbproject/configurations.xml | 502 ++++++++++++++++-- nbproject/project.xml | 6 +- 4 files changed, 458 insertions(+), 127 deletions(-) rename nbproject/{Package-gdbserver.bash => Package-Default.bash} (98%) delete mode 100644 nbproject/Package-library_cli.bash diff --git a/nbproject/Package-gdbserver.bash b/nbproject/Package-Default.bash similarity index 98% rename from nbproject/Package-gdbserver.bash rename to nbproject/Package-Default.bash index 722b818..f6abfb4 100644 --- a/nbproject/Package-gdbserver.bash +++ b/nbproject/Package-Default.bash @@ -7,7 +7,7 @@ # Macros TOP=`pwd` CND_PLATFORM=GNU-Linux-x86 -CND_CONF=gdbserver +CND_CONF=Default CND_DISTDIR=dist CND_BUILDDIR=build NBTMPDIR=${CND_BUILDDIR}/${CND_CONF}/${CND_PLATFORM}/tmp-packaging diff --git a/nbproject/Package-library_cli.bash b/nbproject/Package-library_cli.bash deleted file mode 100644 index 5a64472..0000000 --- a/nbproject/Package-library_cli.bash +++ /dev/null @@ -1,75 +0,0 @@ -#!/bin/bash -x - -# -# Generated - do not edit! -# - -# Macros -TOP=`pwd` -CND_PLATFORM=GNU-Linux-x86 -CND_CONF=library_cli -CND_DISTDIR=dist -CND_BUILDDIR=build -NBTMPDIR=${CND_BUILDDIR}/${CND_CONF}/${CND_PLATFORM}/tmp-packaging -TMPDIRNAME=tmp-packaging -OUTPUT_PATH=test_usb -OUTPUT_BASENAME=test_usb -PACKAGE_TOP_DIR=stlink/ - -# Functions -function checkReturnCode -{ - rc=$? - if [ $rc != 0 ] - then - exit $rc - fi -} -function makeDirectory -# $1 directory path -# $2 permission (optional) -{ - mkdir -p "$1" - checkReturnCode - if [ "$2" != "" ] - then - chmod $2 "$1" - checkReturnCode - fi -} -function copyFileToTmpDir -# $1 from-file path -# $2 to-file path -# $3 permission -{ - cp "$1" "$2" - checkReturnCode - if [ "$3" != "" ] - then - chmod $3 "$2" - checkReturnCode - fi -} - -# Setup -cd "${TOP}" -mkdir -p ${CND_DISTDIR}/${CND_CONF}/${CND_PLATFORM}/package -rm -rf ${NBTMPDIR} -mkdir -p ${NBTMPDIR} - -# Copy files and create directories and links -cd "${TOP}" -makeDirectory "${NBTMPDIR}/stlink/bin" -copyFileToTmpDir "${OUTPUT_PATH}" "${NBTMPDIR}/${PACKAGE_TOP_DIR}bin/${OUTPUT_BASENAME}" 0755 - - -# Generate tar file -cd "${TOP}" -rm -f ${CND_DISTDIR}/${CND_CONF}/${CND_PLATFORM}/package/stlink.tar -cd ${NBTMPDIR} -tar -vcf ../../../../${CND_DISTDIR}/${CND_CONF}/${CND_PLATFORM}/package/stlink.tar * -checkReturnCode - -# Cleanup -cd "${TOP}" -rm -rf ${NBTMPDIR} diff --git a/nbproject/configurations.xml b/nbproject/configurations.xml index 3d02ea8..794a3ab 100644 --- a/nbproject/configurations.xml +++ b/nbproject/configurations.xml @@ -2,7 +2,105 @@ + + + + + + main.c + + + main.c + startup_stm32l1xx_md.s + system_stm32l1xx.c + + + discover_board.h + main.c + stm32l_discovery_lcd.c + stm32l_discovery_lcd.h + + + + + + + stdint.h + + + core_cm3.c + core_cm3.h + + + stm32l1xx.h + system_stm32l1xx.h + + misc.h + stm32l1xx_adc.h + stm32l1xx_comp.h + stm32l1xx_crc.h + stm32l1xx_dac.h + stm32l1xx_dbgmcu.h + stm32l1xx_dma.h + stm32l1xx_exti.h + stm32l1xx_flash.h + stm32l1xx_gpio.h + stm32l1xx_i2c.h + stm32l1xx_iwdg.h + stm32l1xx_lcd.h + stm32l1xx_pwr.h + stm32l1xx_rcc.h + stm32l1xx_rtc.h + stm32l1xx_spi.h + stm32l1xx_syscfg.h + stm32l1xx_tim.h + stm32l1xx_usart.h + stm32l1xx_wwdg.h + + + misc.c + stm32l1xx_adc.c + stm32l1xx_comp.c + stm32l1xx_crc.c + stm32l1xx_dac.c + stm32l1xx_dbgmcu.c + stm32l1xx_dma.c + stm32l1xx_exti.c + stm32l1xx_flash.c + stm32l1xx_flash_ramfunc.c + stm32l1xx_gpio.c + stm32l1xx_i2c.c + stm32l1xx_iwdg.c + stm32l1xx_lcd.c + stm32l1xx_pwr.c + stm32l1xx_rcc.c + stm32l1xx_rtc.c + stm32l1xx_spi.c + stm32l1xx_syscfg.c + stm32l1xx_tim.c + stm32l1xx_usart.c + stm32l1xx_wwdg.c + + + + discover_board.h + discover_functions.c + discover_functions.h + icc_measure.c + icc_measure.h + icc_measure_Ram.c + main.c + stm32_tsl_conf.h + stm32l1xx_conf.h + stm32l1xx_it.c + stm32l1xx_it.h + stm32l_discovery_lcd.c + stm32l_discovery_lcd.h + system_stm32l1xx.c + + + main.c @@ -20,81 +118,393 @@ test_sg.c test_usb.c - + + + + stlink-hw.h + + + + + + + + + + + + + + + + + + - build/Makefile + Makefile ^(nbproject)$ . - build/Makefile + Makefile - + LOCAL_SOURCES default - - ${MAKE} -f Makefile - ${MAKE} -f Makefile clean - test_usb - - - stm32l/src - /usr/include/libusb-1.0 - stm32l/build - src - - - CONFIG_USE_LIBUSB=1 - __GNUC_STDC_INLINE__=1 - __OPTIMIZE__=1 - __REGISTER_PREFIX__= - __STDC_VERSION__=199901L - __USER_LABEL_PREFIX__= - - - - - - - - LOCAL_SOURCES - default - - - - gdbserver + . ${MAKE} -f Makefile ${MAKE} -f Makefile clean gdbserver/st-util - - stm32l/src - /usr/include/libusb-1.0 - stm32l/build - src - + CONFIG_USE_LIBSG=1 CONFIG_USE_LIBUSB=1 - __GNUC_STDC_INLINE__=1 - __OPTIMIZE__=1 - __REGISTER_PREFIX__= - __STDC_VERSION__=199901L - __USER_LABEL_PREFIX__= + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + src + + + + + + + . + + + DEBUG=1 + + + + + + + + + diff --git a/nbproject/project.xml b/nbproject/project.xml index 6608636..cd52486 100644 --- a/nbproject/project.xml +++ b/nbproject/project.xml @@ -14,11 +14,7 @@ - library_cli - 0 - - - gdbserver + Default 0 From 85ff6038050093c1950e0ec69cd597f848bfa4c6 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Sat, 22 Oct 2011 15:46:19 +0000 Subject: [PATCH 10/63] Make the blink example build for all platforms. Less mucking around with make parameters, it's a tiny build. Verified with a VL and L board. Removed the old obsolete bin file --- doc/tutorial/tutorial.pdf | Bin 110986 -> 110993 bytes doc/tutorial/tutorial.tex | 8 ++-- example/blink/Makefile | 37 +++++++++---------- example/blink/main.c | 76 +++++++++++++++----------------------- example/blink/o.bin | Bin 64 -> 0 bytes 5 files changed, 51 insertions(+), 70 deletions(-) delete mode 100755 example/blink/o.bin diff --git a/doc/tutorial/tutorial.pdf b/doc/tutorial/tutorial.pdf index 4ffcc3e563b3df294e331eb3fae97f9843f31817..371f805a0f1a4ddc103155c3fecc8c3a3fc972a0 100644 GIT binary patch delta 3270 zcmah|X*g638#agX6vrmew*_V;1ERm&9VMLZ3d$y8w(A$uu8e1fieW?_( z?~G8&g=DRmmT$VQ_x;iM@tr^Cy6$s7&;302{havsT*>db%6ay)gFtGyv=SuhnKbcg zmGKkKzR3+I^f5vUF2XctkC_VA+r9Rb*}~d7PIr#Wn@;ZT z0scgF^~Vx%OGgFA0^DU34t!;2nt$G$XcBN)OY8?7X=$L-+rHtYG?0fn4#5%s;jU;5L8<)dBMxwP&G~aCs z+jV-55fm_>>f!)yf1MZ^P2O^~dL|VZaIj2+a^m#rsfJHl--orMe~biKUG6vOM7QCR zyN78ZR^Nt#=C>#GdIKwLvk$II#auE!FB+KkBz72;MDg}U_8!$-3eSSB-kD#T7#eHp zM)t;=m_?9JiyVFJ)u0~yTgyc(GwL&3Lg#CoK|ogZeed$B*V#+6OHv_w5&5>d55?a_ zsQg3D8rYA+cD=|EFLXzdP9rSG{I1yz1${ zV;iI@zKH}sF8_8McZB~ZEExK2j|9;vy&Og zk-}&s)^L~Kmy~qqxf|Q8#fiWqDmit|rX@!b6!mXzz-wW@rclaUu zO2uqzu#WHQBwgP=YI-ZTSnc_dm7;k&98J@UQ8c@JL_7Pzc#bTW+vtOt; zi%VySvKW3+W2g<+=QU89Fr;4EdykRXRCeWhC+?+6=9h67bR7M8--`V76kZjjc|epG zDoJHDy?nmhYygefROWhzMmYPM05iYXU}bX}j*54BOJOFenRZ~~vcLN73I@0HE$dqE zvrv}pg+k@10IL#kI_QYVt8lE=I-ghrAUPU2)iYYZi?ZkTUGYXq`XIFedqE=7F|gdZ z#665p^Nx;AyWhr#mLQ8zm0nw=8cwa5leyWPS^7pE!H`Ed$0wwBaqpZ@hto$YSJ${M zhjwn;PnoDpfmB)Ru$tp3n97yB*P9U>>}JC2@@Gs&Vnh2Pm-o$Wn!Ae z$h#9Qp>oT`<^_o}4YFeF>v>rROzRb6S5sRJ)~3uyM649i#He?rLhux?!r$ukG-2NY z>f)XzVYa&GnrDFPe4}4@K2<9VIWSCgt`tX!k|&Bx$M_Y(rrU>IJ7wGLk^~fjo?O@- z0PWuf&Sx&Pm>6xIztYi92gfXxw=We^5n((s%u~M(9s6N(dCW4>hFagw+g?i z!yOKd_D(_jJ*{$6wcaSyem6|u@?VvUq{7_%V=ho;OpL5*68C#zl8f-k;-`@GgfulX zSzGBR;v#C4Mz#{sG~WJ6fBjkFR-y8}HHfcMgk-2(qMde{mv>(g!?jeVzAuqs)REsS zIR9afgZ3;ftph(~9e6Q@%$HgqM>sYduxBgkaNQ(2V)JZ&&ffQoHrxCYUZWXpqxq%H z@Xj0KPba;$J#xO%1ch?aryYHMGk!i=a7z@NHk}Udepklb`%TAjb)#(DX_cbrKL@=f z%C98L3iI9YqPeYI>QUsBI*c8Nk-b@C9`9m0;*j)|es94i$i(r-`pdeATbH6k86IUBJm-_qE^IdYcC$m0xbaXmib{i$vr!0Pq9t$4Y2JU%;&Erp;ZEmW zUejjVR;?d38=OaNMm9qckf+sKPqXUfZ7Lm$uuJje6E2DrL@(C7Bj~Fgs`+5>X0)-@ zNEA6%Y4_P|&ZA>wTZeI%eMmz1hUzhc$k{$eU7ne1cJtFzA;~DJKn%8yz5#@KY|W%m zEjNAmo1H>V(IFF)xw%xoC78WcpAc80fZPxxHuz*$VnP@V;@Ak#>yGReeby}s^GTM* zU_ioICHN83t1h}uey#{b-J>V~1VI3W0K!6Akh<{@MK)~R3^dq3LJNn_#sDC$s{tLlN<4 zRt+=?g@bm0I6SK`8o&@(MbH2NWW_Kz40b1mC;q)L^I*^f5d2pc`u7?EECxWcPK_sk zXqJm(nurg0vthtnZwq3}8w99mBc$NV2b6bR_yaYStlURN8ZfjIVmDfS2r4LI4)$=C0? Uud5rJ*&d6zR?qtr9$%X1AHCm}U1ChO^; z7?0buAK{&@KDnE677QPfho zBaMe^`9NW%*aVH`ov{dNuk@}++y7e#n35_p2QNR|6>|}Lz}D!r?Q^J$h;`5K?oe!E zZL0U5^$VPR!4YyyXt41857)prt@)^`f)3XM!7jGXbgtLgGO6B5_+?{~bT?L;{B^6s z`f-f(Yqb|Q-=N;wkNION&AH!t8K)eY;KY+YU#0ZY_TF;XJoWPv>9ZmfO6J@_lde2Q z6;fRZt~n&+t5;F^Y)<^)uBnJIq!o1KIZJNoYHmZ%*xdG~t>F{Nc7PSs4g}P?H)O!Y z$+5e0YTsdI#iwtnJVbY)({6e{$s3yW(PQTBk!|nmhOEE?yUB5$fw{_}JBlK+{T5Bd z64Ov{!Bsd3g3U))ljwd_+l@m&Zry1zkZ#h`fSLzYso zvCsbE6V~Ynd0j)iY)8^@vsC@W5B(CJ-<7AG)f=c^2(vGZP(M4WMAf^seLtyW*tDXf z@3}9PDBf>AI#cp_$1(4c&)bgaqJz1=%X=&@m8NJ&qU32~IhsO|vC6K6T$y1><)boN zsF63sLd-9ni>E(F?l-eT^lCdh7s|52wSMtg22xDe6|=N&P4^b++ zD3K+TCpy$#h1qLDjz9cLveMMzTwTXOp=zZCczp1@g;_?EO07bika4lx@z1O>A!A?6 z(P`Dqd4Sfprcj&yaZfFfz*-)bg*&W*e(lbjNOnY**v?bK&D8FSoS1&O=kvVg2{uQl z?`~1K-vIN~+wyAaKK{vpcT*YG$);zToM=ZY8Ht-!E|!`3S#Lf&cq~M+UV|4(_WtO+ zzeoQ4ciPQLCfj-X0_Sdi;N91(k@efOdn3DEdn(=|^m(P>%E)f%MgZN{=v8k!%5U)- z<x4kDnm(XqmHnJ#qO_c?fDv;tCra@&T`a3M!80C0O1zvIT0(L(mt0db9$ zks5yO%J#_krwF-EG{<%J5>K}uZ1ioRh}AXvctzgnSLiCTis~y2nhea?9s-cqN?|7W z>`}B;M9D&N*?ru^18+J@kLl&++%ju=hb}c&w)zq!26FXt6PoaW8gQyyo=#&?jzYr>@W_B2k666qnCZ!;XQBUq!YmQVuq4 zLqX9`o6sPWe&kvxC2>X6JWEt#=7HSwNQR>l<#ln&;I5X;&1e>Ns$865p836cdDr?3 zL;KPOn+F}kIgv`yjZNa&qcO-Bj#McFS{Lcu@*BP`Whs3*%LS@oe)exWQX+QVJ@j{j zq__bi*CAfiaHx}S!ky>oFM+0a2V%4?RLV2! zc^1W%lQmzqcUQ5L!;mktY^BZaVkjT8pHa92^YB(n3?v*`?IDHYhTT}v&dQVWdoxhF zr7C+}KtNal{bD%Q>Fmv(SLb~!ZcZEzw8iJi41e2%?5^~9=yq(vqTlGy2Ak#kP0?2z zyR1WjOX_49c^>Z8^H`d(R*#YhbMP+amlhYF-gVhO&jVU4D-6k`$uu}6^;cM@eDU$K z4yK2Ar%qI-&e`!E)$Hu}=o7NcqGQn)Gh^OZhiNY*omO~$MuwT>B)s5yt!QKNqt2+n zpl4Q2GM+!}uo-Acix$sw*zTvW0S1_F%h9o_w30M_B?ro#s54i{E@z&6tO@M-FdWYL z=}ouf$fsfp*2?2TdQZ*7o<~C(XO2$xw2yP*qIt%xv^js3ka zg`{bB&Tl==jfOqo%-7z1mFEfMW(#s|Z< zCQaUVe`Mp|u2o>Ey1NQfTRr?`arq0wxxu(9eY|Dcv8Z!et; zw^XAEE2E^5!tz_40D~LbeuT##X#Twtr|= zQ}557@Kn9t?2})9Hcd-J(mFIj}x!UBnF z_^U|?=>Le1C};}=V0bMLBCW+pL{Omj)qw$j>azYG(T_2Lf`&j42GA`vgR5~~A&i2`?5Lxlv>`VllyAekSNBfx()1OMX>A%XCJ!GB^{LE+V1 z#FB9QxnhJ49X258Lq;$J=)-tJ13W<=M>IAx!V__;`+_xrAsxki|Ci#RsH1~o`XBf6 W5B76$MXi>{ sudo ./st-util --stlinkv1 [-d /dev/sg2] -# STM32L discovery kit (onboard ST-link/V2) +# STM32L or STM32F4 discovery kit (onboard ST-link/V2) $> sudo ./st-util # Full help for other options (listen port, version) diff --git a/example/blink/Makefile b/example/blink/Makefile index e5f7045..cf7221d 100644 --- a/example/blink/Makefile +++ b/example/blink/Makefile @@ -1,35 +1,32 @@ -EXECUTABLE=blink.elf -BIN_IMAGE=blink.bin - CC=arm-none-eabi-gcc OBJCOPY=arm-none-eabi-objcopy -CFLAGS=-g -O2 -mlittle-endian -mthumb -ifeq ($(CONFIG_STM32L_DISCOVERY), 1) - CFLAGS+=-mcpu=cortex-m3 -DCONFIG_STM32L_DISCOVERY -else ifeq ($(CONFIG_STM32VL_DISCOVERY), 1) - CFLAGS+=-mcpu=cortex-m3 -DCONFIG_STM32VL_DISCOVERY=1 -else ifeq ($(CONFIG_STM32F4_DISCOVERY), 1) - CFLAGS+=-mcpu=cortex-m4 -DCONFIG_STM32F4_DISCOVERY=1 -endif - CFLAGS+=-ffreestanding -nostdlib -nostdinc +DEF_CFLAGS=-g -O2 -mlittle-endian -mthumb -ffreestanding -nostdlib -nostdinc # to run from SRAM -CFLAGS+=-Wl,-Ttext,0x20000000 -Wl,-e,0x20000000 +DEF_CFLAGS+=-Wl,-Ttext,0x20000000 -Wl,-e,0x20000000 # to write to flash then run -# CFLAGS+=-Wl,-Ttext,0x08000000 -Wl,-e,0x08000000 +# DEF_CFLAGS+=-Wl,-Ttext,0x08000000 -Wl,-e,0x08000000 -all: $(BIN_IMAGE) +CFLAGS_VL=$(DEF_CFLAGS) -mcpu=cortex-m3 -DCONFIG_STM32VL_DISCOVERY=1 +CFLAGS_L=$(DEF_CFLAGS) -mcpu=cortex-m3 -DCONFIG_STM32L_DISCOVERY +CFLAGS_F4=$(DEF_CFLAGS) -mcpu=cortex-m4 -DCONFIG_STM32F4_DISCOVERY=1 -$(BIN_IMAGE): $(EXECUTABLE) +all: blink_32VL.elf blink_32L.elf blink_F4.elf + +%.bin: %.elf $(OBJCOPY) -O binary $^ $@ -$(EXECUTABLE): main.c - $(CC) $(CFLAGS) $^ -o $@ +blink_32VL.elf: main.c + $(CC) $(CFLAGS_VL) $^ -o $@ +blink_32L.elf: main.c + $(CC) $(CFLAGS_L) $^ -o $@ +blink_F4.elf: main.c + $(CC) $(CFLAGS_F4) $^ -o $@ clean: - rm -rf $(EXECUTABLE) - rm -rf $(BIN_IMAGE) + rm -rf *.elf + rm -rf *.bin .PHONY: all clean diff --git a/example/blink/main.c b/example/blink/main.c index 0889b81..e0438a0 100644 --- a/example/blink/main.c +++ b/example/blink/main.c @@ -7,36 +7,30 @@ typedef unsigned int uint32_t; #if CONFIG_STM32VL_DISCOVERY -# define GPIOC 0x40011000 /* port C */ -# define GPIOC_CRH (GPIOC + 0x04) /* port configuration register high */ -# define GPIOC_ODR (GPIOC + 0x0c) /* port output data register */ +#define GPIOC 0x40011000 /* port C */ +#define GPIOC_CRH (GPIOC + 0x04) /* port configuration register high */ +#define LED_PORT_ODR (GPIOC + 0x0c) /* port output data register */ -# define LED_BLUE (1 << 8) /* port C, pin 8 */ -# define LED_GREEN (1 << 9) /* port C, pin 9 */ +#define LED_BLUE (1 << 8) /* port C, pin 8 */ +#define LED_GREEN (1 << 9) /* port C, pin 9 */ +#define LED_ORANGE 0 +#define LED_RED 0 static inline void setup_leds(void) { *(volatile uint32_t*)GPIOC_CRH = 0x44444411; } -static inline void switch_leds_on(void) -{ - *(volatile uint32_t*)GPIOC_ODR = LED_BLUE | LED_GREEN; -} - -static inline void switch_leds_off(void) -{ - *(volatile uint32_t*)GPIOC_ODR = 0; -} - #elif CONFIG_STM32L_DISCOVERY -# define GPIOB 0x40020400 /* port B */ -# define GPIOB_MODER (GPIOB + 0x00) /* port mode register */ -# define GPIOB_ODR (GPIOB + 0x14) /* port output data register */ +#define GPIOB 0x40020400 /* port B */ +#define GPIOB_MODER (GPIOB + 0x00) /* port mode register */ +#define LED_PORT_ODR (GPIOB + 0x14) /* port output data register */ -# define LED_BLUE (1 << 6) /* port B, pin 6 */ -# define LED_GREEN (1 << 7) /* port B, pin 7 */ +#define LED_BLUE (1 << 6) /* port B, pin 6 */ +#define LED_GREEN (1 << 7) /* port B, pin 7 */ +#define LED_ORANGE 0 +#define LED_RED 0 static inline void setup_leds(void) { @@ -44,26 +38,16 @@ static inline void setup_leds(void) *(volatile uint32_t*)GPIOB_MODER |= (1 << (7 * 2)) | (1 << (6 * 2)); } -static inline void switch_leds_on(void) -{ - *(volatile uint32_t*)GPIOB_ODR = LED_BLUE | LED_GREEN; -} - -static inline void switch_leds_off(void) -{ - *(volatile uint32_t*)GPIOB_ODR = 0; -} - #elif CONFIG_STM32F4_DISCOVERY #define GPIOD 0x40020C00 /* port D */ -# define GPIOD_MODER (GPIOD + 0x00) /* port mode register */ -# define GPIOD_ODR (GPIOD + 0x14) /* port output data register */ +#define GPIOD_MODER (GPIOD + 0x00) /* port mode register */ +#define LED_PORT_ODR (GPIOD + 0x14) /* port output data register */ -# define LED_GREEN (1 << 12) /* port B, pin 12 */ -# define LED_ORANGE (1 << 13) /* port B, pin 13 */ -# define LED_RED (1 << 14) /* port B, pin 14 */ -# define LED_BLUE (1 << 15) /* port B, pin 15 */ +#define LED_GREEN (1 << 12) /* port D, pin 12 */ +#define LED_ORANGE (1 << 13) /* port D, pin 13 */ +#define LED_RED (1 << 14) /* port D, pin 14 */ +#define LED_BLUE (1 << 15) /* port D, pin 15 */ static inline void setup_leds(void) { @@ -71,21 +55,19 @@ static inline void setup_leds(void) (1 << (13 * 2)) | (1 << (14 * 2)) | (1 << (15 * 2)); } - -static inline void switch_leds_on(void) -{ - *(volatile uint32_t*)GPIOD_ODR = LED_GREEN | LED_ORANGE | LED_RED | LED_BLUE; -} - -static inline void switch_leds_off(void) -{ - *(volatile uint32_t*)GPIOD_ODR = 0; -} - #else #error "Architecture must be defined!" #endif /* otherwise, error */ +static inline void switch_leds_on(void) +{ + *(volatile uint32_t*)LED_PORT_ODR = LED_BLUE | LED_GREEN | LED_ORANGE | LED_RED; +} + +static inline void switch_leds_off(void) +{ + *(volatile uint32_t*)LED_PORT_ODR = 0; +} #define delay() \ do { \ diff --git a/example/blink/o.bin b/example/blink/o.bin deleted file mode 100755 index 76324f796a6523d1acb35940d4d351466dd7773e..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 64 zcmZ?##KP?INzm!YCr0KYpIn?AKk+b1B>;Jh{$CslTs}D{b0i%2#LvvIpV9iyMIc{^ P8^mV<@~!?{eD@pxMXwtU From c37975c15730ac582945ea3ed85ac59284979819 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Sat, 22 Oct 2011 15:53:03 +0000 Subject: [PATCH 11/63] remove swallowing of ctrl-c No idea why this was added, but it's not necessary for anything I've found. --- gdbserver/gdb-server.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index 30ee014..e7efbf1 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -32,12 +32,6 @@ #define FLASH_PAGE_MASK (~((1 << 10) - 1)) #define FLASH_SIZE (FLASH_PAGE * 128) -volatile int do_exit = 0; -void ctrl_c(int sig) -{ - do_exit = 1; -} - static const char hex[] = "0123456789abcdef"; static const char* current_memory_map = NULL; @@ -697,7 +691,6 @@ int serve(stlink_t *sl, int port) { printf("Listening at *:%d...\n", port); - (void) signal (SIGINT, ctrl_c); int client = accept(sock, NULL, NULL); signal (SIGINT, SIG_DFL); if(client < 0) { From 076f1086fa9c0dfa043300fb1776bc10e8eaa77f Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Sat, 22 Oct 2011 18:05:24 +0000 Subject: [PATCH 12/63] Remove all #ifdefs for sg-utils. We're starting on integration from github.com/afaerber So, instead of scanning all the usb devices, just open what we want. --- Makefile | 25 +++++------------------ flash/main.c | 5 ----- gdbserver/gdb-server.c | 6 ------ src/stlink-usb.c | 45 ++++++------------------------------------ src/stlink-usb.h | 6 ------ src/test_sg.c | 4 ---- 6 files changed, 11 insertions(+), 80 deletions(-) diff --git a/Makefile b/Makefile index c5bb1d9..bbd76a8 100644 --- a/Makefile +++ b/Makefile @@ -1,28 +1,13 @@ -# make ... for both libusb and libsg -# -# make CONFIG_USE_LIBSG=0 ... -# for just libusb -# +# make ... for both stlink v1 and stlink v2 support +## VPATH=src -SOURCES_LIB=stlink-common.c stlink-usb.c +SOURCES_LIB=stlink-common.c stlink-usb.c #stlink-sg.c OBJS_LIB=$(SOURCES_LIB:.c=.o) -TEST_PROGRAMS=test_usb +TEST_PROGRAMS=test_usb #test_sg LDFLAGS=-lusb-1.0 -L. -lstlink -ifeq ($(CONFIG_USE_LIBSG),) -CONFIG_USE_LIBSG=1 -endif - -ifneq ($(CONFIG_USE_LIBSG),0) -SOURCES_LIB+=stlink-sg.c -CFLAGS+=-DCONFIG_USE_LIBSG=1 -LDFLAGS+=-lsgutils2 -TEST_PROGRAMS+=test_sg -endif - CFLAGS+=-g -CFLAGS+=-DCONFIG_USE_LIBUSB=1 CFLAGS+=-DDEBUG=1 CFLAGS+=-std=gnu99 CFLAGS+=-Wall -Wextra @@ -63,7 +48,7 @@ distclean: clean $(MAKE) -C gdbserver clean flash: - $(MAKE) -C flash CONFIG_USE_LIBSG="$(CONFIG_USE_LIBSG)" + $(MAKE) -C flash gdbserver: $(MAKE) -C gdbserver diff --git a/flash/main.c b/flash/main.c index e474174..a443f95 100644 --- a/flash/main.c +++ b/flash/main.c @@ -86,14 +86,9 @@ int main(int ac, char** av) if (o.devname != NULL) /* stlinkv1 */ { -#if CONFIG_USE_LIBSG static const int scsi_verbose = 2; sl = stlink_quirk_open(o.devname, scsi_verbose); if (sl == NULL) goto on_error; -#else - printf("not compiled for use with STLink/V1"); - goto on_error; -#endif } else /* stlinkv2 */ { diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index e7efbf1..f1da63e 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -197,7 +197,6 @@ int main(int argc, char** argv) { if(sl == NULL) return 1; break; case 1: -#if (CONFIG_USE_LIBSG == 1) if (strlen(state.devicename) == 0) { const int DevNumMax = 99; int ExistDevCount = 0; @@ -235,11 +234,6 @@ int main(int argc, char** argv) { sl = stlink_quirk_open(state.devicename, state.logging_level); } break; -#else - fprintf(stderr, "Support for stlink v1 disabled at build time...\n"); - fprintf(stderr, "Perhaps you're on OSX, and we haven't finished removing the libsg deps?\n"); - exit(EXIT_FAILURE); -#endif } if (stlink_current_mode(sl) == STLINK_DEV_DFU_MODE) { diff --git a/src/stlink-usb.c b/src/stlink-usb.c index ff9ef71..57a4a2f 100644 --- a/src/stlink-usb.c +++ b/src/stlink-usb.c @@ -604,47 +604,14 @@ stlink_t* stlink_open_usb(const int verbose) { goto on_error; } - count = libusb_get_device_list(slu->libusb_ctx, &devs); - if (count < 0) { - printf("libusb_get_device_list\n"); - goto on_libusb_error; - } - - for (i = 0; i < count; ++i) { - dev = devs[i]; - slu->protocoll = is_stlink_device(dev, 0); - if (slu->protocoll > 0) break; - } - if (i == count) goto on_libusb_error; - - if (libusb_open(dev, &(slu->usb_handle))) { - printf("libusb_open()\n"); - goto on_libusb_error; + slu->usb_handle = libusb_open_device_with_vid_pid(slu->libusb_ctx, USB_ST_VID, USB_STLINK_32L_PID); + if (slu->usb_handle == NULL) { + // TODO - free usb context too... + free(slu); + fprintf(stderr, "Couldn't find any ST-Link/V2 devices"); + return NULL; } - if (iSerial) { - unsigned char serial[256]; - struct libusb_device_descriptor desc; - int r; - - r = libusb_get_device_descriptor(dev, &desc); - if (r<0) { - printf("Can't get descriptor to match Iserial\n"); - goto on_libusb_error; - } - r = libusb_get_string_descriptor_ascii - (slu->usb_handle, desc.iSerialNumber, serial, 256); - if (r<0) { - printf("Can't get Serialnumber to match Iserial\n"); - goto on_libusb_error; - } - if (strcmp((char*)serial, iSerial)) { - printf("Mismatch in serial numbers, dev %s vs given %s\n", - serial, iSerial); - goto on_libusb_error; - } - } - if (libusb_kernel_driver_active(slu->usb_handle, 0) == 1) { int r; diff --git a/src/stlink-usb.h b/src/stlink-usb.h index c632a8c..2f3b8cc 100644 --- a/src/stlink-usb.h +++ b/src/stlink-usb.h @@ -18,7 +18,6 @@ extern "C" { #define STLINK_SG_SIZE 31 #define STLINK_CMD_SIZE 16 -#if defined(CONFIG_USE_LIBUSB) struct stlink_libusb { libusb_context* libusb_ctx; libusb_device_handle* usb_handle; @@ -30,11 +29,6 @@ extern "C" { unsigned int sg_transfer_idx; unsigned int cmd_len; }; -#else -#error "it's all bad!" - struct stlink_libusb {}; -#endif - stlink_t* stlink_open_usb(const int verbose); diff --git a/src/test_sg.c b/src/test_sg.c index 34fbe54..9efe6d8 100644 --- a/src/test_sg.c +++ b/src/test_sg.c @@ -6,10 +6,6 @@ #include #include -#if CONFIG_USE_LIBSG -#include -#include -#endif #include "stlink-common.h" int main(int argc, char *argv[]) { From 42d2da531f52ead18091a1211a5e6206e27dc178 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Sat, 22 Oct 2011 19:09:31 +0000 Subject: [PATCH 13/63] flag out the only scsi specific code Also flag out some places where code appears unused. --- Makefile | 2 +- flash/main.c | 4 +++- gdbserver/gdb-server.c | 6 +++--- src/stlink-sg.c | 13 +++++++------ src/stlink-sg.h | 6 +----- src/stlink-usb.c | 7 ++++++- src/test_sg.c | 2 +- 7 files changed, 22 insertions(+), 18 deletions(-) diff --git a/Makefile b/Makefile index bbd76a8..2c73f16 100644 --- a/Makefile +++ b/Makefile @@ -2,7 +2,7 @@ ## VPATH=src -SOURCES_LIB=stlink-common.c stlink-usb.c #stlink-sg.c +SOURCES_LIB=stlink-common.c stlink-usb.c stlink-sg.c OBJS_LIB=$(SOURCES_LIB:.c=.o) TEST_PROGRAMS=test_usb #test_sg LDFLAGS=-lusb-1.0 -L. -lstlink diff --git a/flash/main.c b/flash/main.c index a443f95..a74525a 100644 --- a/flash/main.c +++ b/flash/main.c @@ -1,5 +1,7 @@ /* simple wrapper around the stlink_flash_write function */ +// TODO - this should be done as just a simple flag to the st-util command line... + #include #include @@ -87,7 +89,7 @@ int main(int ac, char** av) if (o.devname != NULL) /* stlinkv1 */ { static const int scsi_verbose = 2; - sl = stlink_quirk_open(o.devname, scsi_verbose); + sl = stlink_v1_open(o.devname, scsi_verbose); if (sl == NULL) goto on_error; } else /* stlinkv2 */ diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index f1da63e..3e2f99a 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -207,7 +207,7 @@ int main(int argc, char** argv) { const int X_index = 7; DevName[X_index] = DevNum + '0'; if (!access(DevName, F_OK)) { - sl = stlink_quirk_open(DevName, 0); + sl = stlink_v1_open(DevName, 0); ExistDevCount++; } } else if (DevNum < 100) { @@ -217,7 +217,7 @@ int main(int argc, char** argv) { DevName[X_index] = DevNum / 10 + '0'; DevName[Y_index] = DevNum % 10 + '0'; if (!access(DevName, F_OK)) { - sl = stlink_quirk_open(DevName, 0); + sl = stlink_v1_open(DevName, 0); ExistDevCount++; } } @@ -231,7 +231,7 @@ int main(int argc, char** argv) { return 1; } } else { - sl = stlink_quirk_open(state.devicename, state.logging_level); + sl = stlink_v1_open(state.devicename, state.logging_level); } break; } diff --git a/src/stlink-sg.c b/src/stlink-sg.c index b8220de..137f6f6 100644 --- a/src/stlink-sg.c +++ b/src/stlink-sg.c @@ -82,12 +82,7 @@ #include "stlink-common.h" -#if CONFIG_USE_LIBSG -// sgutils2 (apt-get install libsgutils2-dev) -#include -#include #include "stlink-sg.h" -#endif // Suspends execution of the calling process for @@ -119,15 +114,18 @@ static void clear_buf(stlink_t *sl) { void _stlink_sg_close(stlink_t *sl) { if (sl) { +#if FINISHED_WITH_SG struct stlink_libsg *slsg = sl->backend_data; scsi_pt_close_device(slsg->sg_fd); free(slsg); +#endif } } //TODO rewrite/cleanup, save the error in sl +#if FINISHED_WITH_SG static void stlink_confirm_inq(stlink_t *stl, struct sg_pt_base *ptvp) { struct stlink_libsg *sl = stl->backend_data; const int e = sl->do_scsi_pt_err; @@ -209,8 +207,10 @@ static void stlink_confirm_inq(stlink_t *stl, struct sg_pt_base *ptvp) { "category (%d)\n", cat); } } +#endif void stlink_q(stlink_t *sl) { +#if FINISHED_WITH_SG struct stlink_libsg* sg = sl->backend_data; DD(sl, "CDB["); for (int i = 0; i < CDB_SL; i++) @@ -245,6 +245,7 @@ void stlink_q(stlink_t *sl) { stlink_confirm_inq(sl, ptvp); // TODO recycle: clear_scsi_pt_obj(struct sg_pt_base * objp); destruct_scsi_pt_obj(ptvp); +#endif } // TODO thinking, cleanup @@ -803,7 +804,7 @@ stlink_t* stlink_open(const char *dev_name, const int verbose) { -stlink_t* stlink_quirk_open(const char *dev_name, const int verbose) { +stlink_t* stlink_v1_open(const char *dev_name, const int verbose) { stlink_t *sl = stlink_open(dev_name, verbose); if (sl == NULL) { diff --git a/src/stlink-sg.h b/src/stlink-sg.h index 523b7d8..afa47c5 100644 --- a/src/stlink-sg.h +++ b/src/stlink-sg.h @@ -40,7 +40,6 @@ extern "C" { -#if defined(CONFIG_USE_LIBUSB) struct stlink_libsg { int sg_fd; int do_scsi_pt_err; @@ -63,11 +62,8 @@ extern "C" { reg reg; }; -#else - struct stlink_libsg {}; -#endif - stlink_t* stlink_quirk_open(const char *dev_name, const int verbose); + stlink_t* stlink_v1_open(const char *dev_name, const int verbose); #ifdef __cplusplus } diff --git a/src/stlink-usb.c b/src/stlink-usb.c index 57a4a2f..5269961 100644 --- a/src/stlink-usb.c +++ b/src/stlink-usb.c @@ -116,7 +116,10 @@ ssize_t send_recv(struct stlink_libusb* handle, int terminate, if (submit_wait(handle, handle->rep_trans)) return -1; res = handle->rep_trans->actual_length; } + if ((handle->protocoll == 1) && terminate) { + fprintf(stderr, "This is never used....\n"); + exit(EXIT_FAILURE); /* Read the SG reply */ unsigned char sg_buf[13]; libusb_fill_bulk_transfer @@ -172,6 +175,7 @@ static int fill_command int i = 0; memset(cmd, 0, sizeof (sl->c_buf)); if(slu->protocoll == 1) { + fprintf(stderr, "This is never used....\n"); cmd[i++] = 'U'; cmd[i++] = 'S'; cmd[i++] = 'B'; @@ -652,11 +656,12 @@ stlink_t* stlink_open_usb(const int verbose) { printf("libusb_alloc_transfer\n"); goto on_libusb_error; } - + // TODO - could use the scanning techniq from stm8 code here... slu->ep_rep = 1 /* ep rep */ | LIBUSB_ENDPOINT_IN; slu->ep_req = 2 /* ep req */ | LIBUSB_ENDPOINT_OUT; slu->sg_transfer_idx = 0; + // TODO - never used at the moment, always CMD_SIZE slu->cmd_len = (slu->protocoll == 1)? STLINK_SG_SIZE: STLINK_CMD_SIZE; /* success */ diff --git a/src/test_sg.c b/src/test_sg.c index 9efe6d8..a12ed1f 100644 --- a/src/test_sg.c +++ b/src/test_sg.c @@ -37,7 +37,7 @@ int main(int argc, char *argv[]) { fprintf(stderr, "Using sg_lib %s : scsi_pt %s\n", sg_lib_version(), scsi_pt_version()); - stlink_t *sl = stlink_quirk_open(dev_name, scsi_verbose); + stlink_t *sl = stlink_v1_open(dev_name, scsi_verbose); if (sl == NULL) return EXIT_FAILURE; From d7e37a684a3ae0c9e52e0486fe46f6d3af1c2b1d Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Sat, 22 Oct 2011 20:31:11 +0000 Subject: [PATCH 14/63] Replace all logging I needed some sanity... --- Makefile | 2 +- flash/main.c | 2 +- gdbserver/gdb-server.c | 19 +++++----- src/stlink-common.c | 84 +++++++++++++++++++----------------------- src/stlink-common.h | 4 -- src/stlink-sg.c | 75 +++++++++++++++++++------------------ src/stlink-usb.c | 46 ++++++++++++++--------- src/uglylogging.c | 58 +++++++++++++++++++++++++++++ src/uglylogging.h | 27 ++++++++++++++ 9 files changed, 202 insertions(+), 115 deletions(-) create mode 100644 src/uglylogging.c create mode 100644 src/uglylogging.h diff --git a/Makefile b/Makefile index 2c73f16..c3c345a 100644 --- a/Makefile +++ b/Makefile @@ -2,7 +2,7 @@ ## VPATH=src -SOURCES_LIB=stlink-common.c stlink-usb.c stlink-sg.c +SOURCES_LIB=stlink-common.c stlink-usb.c stlink-sg.c uglylogging.c OBJS_LIB=$(SOURCES_LIB:.c=.o) TEST_PROGRAMS=test_usb #test_sg LDFLAGS=-lusb-1.0 -L. -lstlink diff --git a/flash/main.c b/flash/main.c index a74525a..849b5d6 100644 --- a/flash/main.c +++ b/flash/main.c @@ -94,7 +94,7 @@ int main(int ac, char** av) } else /* stlinkv2 */ { - sl = stlink_open_usb(10); + sl = stlink_open_usb(100); if (sl == NULL) goto on_error; } diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index 3e2f99a..3af0d8a 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -21,7 +21,7 @@ #include "gdb-remote.h" -#define DEFAULT_LOGGING_LEVEL 10 +#define DEFAULT_LOGGING_LEVEL 100 #define DEFAULT_GDB_LISTEN_PORT 4242 #define STRINGIFY_inner(name) #name @@ -188,7 +188,7 @@ int main(int argc, char** argv) { memset(&state, 0, sizeof(state)); // set defaults... state.stlink_version = 2; - state.logging_level = 10; + state.logging_level = DEFAULT_LOGGING_LEVEL; state.listen_port = DEFAULT_GDB_LISTEN_PORT; parse_options(argc, argv, &state); switch (state.stlink_version) { @@ -234,15 +234,14 @@ int main(int argc, char** argv) { sl = stlink_v1_open(state.devicename, state.logging_level); } break; - } + } - if (stlink_current_mode(sl) == STLINK_DEV_DFU_MODE) { - stlink_exit_dfu_mode(sl); - } - - if(stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) { - stlink_enter_swd_mode(sl); - } + if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) { + if (stlink_current_mode(sl) == STLINK_DEV_DFU_MODE) { + stlink_exit_dfu_mode(sl); + } + stlink_enter_swd_mode(sl); + } uint32_t chip_id = stlink_chip_id(sl); uint32_t core_id = stlink_core_id(sl); diff --git a/src/stlink-common.c b/src/stlink-common.c index 707316c..2693eb9 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -13,21 +13,13 @@ #include "stlink-common.h" +#include "uglylogging.h" -void D(stlink_t *sl, char *txt) { - if (sl->verbose > 1) - fputs(txt, stderr); -} - -void DD(stlink_t *sl, char *format, ...) { - if (sl->verbose > 0) { - va_list list; - va_start(list, format); - vfprintf(stderr, format, list); - va_end(list); - } -} - +#define LOG_TAG __FILE__ +#define DLOG(format, args...) ugly_log(UDEBUG, LOG_TAG, format, ## args) +#define ILOG(format, args...) ugly_log(UINFO, LOG_TAG, format, ## args) +#define WLOG(format, args...) ugly_log(UWARN, LOG_TAG, format, ## args) +#define fatal(format, args...) ugly_log(UFATAL, LOG_TAG, format, ## args) /* FPEC flash controller interface, pm0063 manual @@ -256,38 +248,38 @@ static void disable_flash_read_protection(stlink_t *sl) { // Delegates to the backends... void stlink_close(stlink_t *sl) { - D(sl, "\n*** stlink_close ***\n"); + DLOG("*** stlink_close ***\n"); sl->backend->close(sl); free(sl); } void stlink_exit_debug_mode(stlink_t *sl) { - D(sl, "\n*** stlink_exit_debug_mode ***\n"); + DLOG("*** stlink_exit_debug_mode ***\n"); sl->backend->exit_debug_mode(sl); } void stlink_enter_swd_mode(stlink_t *sl) { - D(sl, "\n*** stlink_enter_swd_mode ***\n"); + DLOG("*** stlink_enter_swd_mode ***\n"); sl->backend->enter_swd_mode(sl); } // Force the core into the debug mode -> halted state. void stlink_force_debug(stlink_t *sl) { - D(sl, "\n*** stlink_force_debug_mode ***\n"); + DLOG("*** stlink_force_debug_mode ***\n"); sl->backend->force_debug(sl); } void stlink_exit_dfu_mode(stlink_t *sl) { - D(sl, "\n*** stlink_exit_dfu_mode ***\n"); + DLOG("*** stlink_exit_dfu_mode ***\n"); sl->backend->exit_dfu_mode(sl); } uint32_t stlink_core_id(stlink_t *sl) { - D(sl, "\n*** stlink_core_id ***\n"); + DLOG("*** stlink_core_id ***\n"); sl->backend->core_id(sl); if (sl->verbose > 2) stlink_print_data(sl); - DD(sl, "core_id = 0x%08x\n", sl->core_id); + DLOG("core_id = 0x%08x\n", sl->core_id); return sl->core_id; } @@ -314,17 +306,17 @@ void stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid) { } void stlink_reset(stlink_t *sl) { - D(sl, "\n*** stlink_reset ***\n"); + DLOG("*** stlink_reset ***\n"); sl->backend->reset(sl); } void stlink_run(stlink_t *sl) { - D(sl, "\n*** stlink_run ***\n"); + DLOG("*** stlink_run ***\n"); sl->backend->run(sl); } void stlink_status(stlink_t *sl) { - D(sl, "\n*** stlink_status ***\n"); + DLOG("*** stlink_status ***\n"); sl->backend->status(sl); stlink_core_stat(sl); } @@ -355,26 +347,26 @@ void _parse_version(stlink_t *sl, stlink_version_t *slv) { } void stlink_version(stlink_t *sl) { - D(sl, "*** looking up stlink version\n"); + DLOG("*** looking up stlink version\n"); stlink_version_t slv; sl->backend->version(sl); _parse_version(sl, &slv); - DD(sl, "st vid = 0x%04x (expect 0x%04x)\n", slv.st_vid, USB_ST_VID); - DD(sl, "stlink pid = 0x%04x\n", slv.stlink_pid); - DD(sl, "stlink version = 0x%x\n", slv.stlink_v); - DD(sl, "jtag version = 0x%x\n", slv.jtag_v); - DD(sl, "swim version = 0x%x\n", slv.swim_v); + DLOG("st vid = 0x%04x (expect 0x%04x)\n", slv.st_vid, USB_ST_VID); + DLOG("stlink pid = 0x%04x\n", slv.stlink_pid); + DLOG("stlink version = 0x%x\n", slv.stlink_v); + DLOG("jtag version = 0x%x\n", slv.jtag_v); + DLOG("swim version = 0x%x\n", slv.swim_v); if (slv.jtag_v == 0) { - DD(sl, " notice: the firmware doesn't support a jtag/swd interface\n"); + DLOG(" notice: the firmware doesn't support a jtag/swd interface\n"); } if (slv.swim_v == 0) { - DD(sl, " notice: the firmware doesn't support a swim interface\n"); + DLOG(" notice: the firmware doesn't support a swim interface\n"); } } void stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { - D(sl, "\n*** stlink_write_mem32 ***\n"); + DLOG("*** stlink_write_mem32 ***\n"); if (len % 4 != 0) { fprintf(stderr, "Error: Data length doesn't have a 32 bit alignment: +%d byte.\n", len % 4); return; @@ -383,7 +375,7 @@ void stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { } void stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { - D(sl, "\n*** stlink_read_mem32 ***\n"); + DLOG("*** stlink_read_mem32 ***\n"); if (len % 4 != 0) { // !!! never ever: fw gives just wrong values fprintf(stderr, "Error: Data length doesn't have a 32 bit alignment: +%d byte.\n", len % 4); @@ -393,23 +385,23 @@ void stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { } void stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { - D(sl, "\n*** stlink_write_mem8 ***\n"); + DLOG("*** stlink_write_mem8 ***\n"); sl->backend->write_mem8(sl, addr, len); } void stlink_read_all_regs(stlink_t *sl, reg *regp) { - D(sl, "\n*** stlink_read_all_regs ***\n"); + DLOG("*** stlink_read_all_regs ***\n"); sl->backend->read_all_regs(sl, regp); } void stlink_write_reg(stlink_t *sl, uint32_t reg, int idx) { - D(sl, "\n*** stlink_write_reg\n"); + DLOG("*** stlink_write_reg\n"); sl->backend->write_reg(sl, reg, idx); } void stlink_read_reg(stlink_t *sl, int r_idx, reg *regp) { - D(sl, "\n*** stlink_read_reg\n"); - DD(sl, " (%d) ***\n", r_idx); + DLOG("*** stlink_read_reg\n"); + DLOG(" (%d) ***\n", r_idx); if (r_idx > 20 || r_idx < 0) { fprintf(stderr, "Error: register index must be in [0..20]\n"); @@ -426,7 +418,7 @@ unsigned int is_core_halted(stlink_t *sl) { } void stlink_step(stlink_t *sl) { - D(sl, "\n*** stlink_step ***\n"); + DLOG("*** stlink_step ***\n"); sl->backend->step(sl); } @@ -434,16 +426,16 @@ int stlink_current_mode(stlink_t *sl) { int mode = sl->backend->current_mode(sl); switch (mode) { case STLINK_DEV_DFU_MODE: - DD(sl, "stlink current mode: dfu\n"); + DLOG("stlink current mode: dfu\n"); return mode; case STLINK_DEV_DEBUG_MODE: - DD(sl, "stlink current mode: debug (jtag or swd)\n"); + DLOG("stlink current mode: debug (jtag or swd)\n"); return mode; case STLINK_DEV_MASS_MODE: - DD(sl, "stlink current mode: mass\n"); + DLOG("stlink current mode: mass\n"); return mode; } - DD(sl, "stlink mode: unknown!\n"); + DLOG("stlink mode: unknown!\n"); return STLINK_DEV_UNKNOWN_MODE; } @@ -496,11 +488,11 @@ void stlink_core_stat(stlink_t *sl) { switch (sl->q_buf[0]) { case STLINK_CORE_RUNNING: sl->core_stat = STLINK_CORE_RUNNING; - DD(sl, " core status: running\n"); + DLOG(" core status: running\n"); return; case STLINK_CORE_HALTED: sl->core_stat = STLINK_CORE_HALTED; - DD(sl, " core status: halted\n"); + DLOG(" core status: halted\n"); return; default: sl->core_stat = STLINK_CORE_STAT_UNKNOWN; diff --git a/src/stlink-common.h b/src/stlink-common.h index 9481609..4986713 100644 --- a/src/stlink-common.h +++ b/src/stlink-common.h @@ -181,10 +181,6 @@ extern "C" { }; - // some quick and dirty logging... - void D(stlink_t *sl, char *txt); - void DD(stlink_t *sl, char *format, ...); - //stlink_t* stlink_quirk_open(const char *dev_name, const int verbose); // delegated functions... diff --git a/src/stlink-sg.c b/src/stlink-sg.c index 137f6f6..afce5ac 100644 --- a/src/stlink-sg.c +++ b/src/stlink-sg.c @@ -81,9 +81,14 @@ #include #include "stlink-common.h" - #include "stlink-sg.h" +#include "uglylogging.h" +#define LOG_TAG __FILE__ +#define DLOG(format, args...) ugly_log(UDEBUG, LOG_TAG, format, ## args) +#define ILOG(format, args...) ugly_log(UINFO, LOG_TAG, format, ## args) +#define WLOG(format, args...) ugly_log(UWARN, LOG_TAG, format, ## args) +#define fatal(format, args...) ugly_log(UFATAL, LOG_TAG, format, ## args) // Suspends execution of the calling process for // (at least) ms milliseconds. @@ -104,7 +109,7 @@ static void clear_cdb(struct stlink_libsg *sl) { // E.g. make the valgrind happy. static void clear_buf(stlink_t *sl) { - DD(sl, "*** clear_buf ***\n"); + DLOG("*** clear_buf ***\n"); for (size_t i = 0; i < sizeof (sl->q_buf); i++) sl->q_buf[i] = 0; @@ -142,7 +147,7 @@ static void stlink_confirm_inq(stlink_t *stl, struct sg_pt_base *ptvp) { } const int duration = get_scsi_pt_duration_ms(ptvp); if ((stl->verbose > 1) && (duration >= 0)) - DD(stl, " duration=%d ms\n", duration); + DLOG(" duration=%d ms\n", duration); // XXX stlink fw sends broken residue, so ignore it and use the known q_len // "usb-storage quirks=483:3744:r" @@ -159,7 +164,7 @@ static void stlink_confirm_inq(stlink_t *stl, struct sg_pt_base *ptvp) { switch (cat) { case SCSI_PT_RESULT_GOOD: if (stl->verbose && (resid > 0)) - DD(stl, " notice: requested %d bytes but " + DLOG(" notice: requested %d bytes but " "got %d bytes, ignore [broken] residue = %d\n", stl->q_len, dsize, resid); break; @@ -168,7 +173,7 @@ static void stlink_confirm_inq(stlink_t *stl, struct sg_pt_base *ptvp) { sg_get_scsi_status_str( get_scsi_pt_status_response(ptvp), sizeof (buf), buf); - DD(stl, " scsi status: %s\n", buf); + DLOG(" scsi status: %s\n", buf); } return; case SCSI_PT_RESULT_SENSE: @@ -176,11 +181,11 @@ static void stlink_confirm_inq(stlink_t *stl, struct sg_pt_base *ptvp) { if (stl->verbose) { sg_get_sense_str("", sl->sense_buf, slen, (stl->verbose > 1), sizeof (buf), buf); - DD(stl, "%s", buf); + DLOG("%s", buf); } if (stl->verbose && (resid > 0)) { if ((stl->verbose) || (stl->q_len > 0)) - DD(stl, " requested %d bytes but " + DLOG(" requested %d bytes but " "got %d bytes\n", stl->q_len, dsize); } return; @@ -193,13 +198,13 @@ static void stlink_confirm_inq(stlink_t *stl, struct sg_pt_base *ptvp) { // The 'host_status' field has the following values: // [0x07] Internal error detected in the host adapter. // This may not be fatal (and the command may have succeeded). - DD(stl, " transport: %s", buf); + DLOG(" transport: %s", buf); } return; case SCSI_PT_RESULT_OS_ERR: if (stl->verbose) { get_scsi_pt_os_err_str(ptvp, sizeof (buf), buf); - DD(stl, " os: %s", buf); + DLOG(" os: %s", buf); } return; default: @@ -212,10 +217,10 @@ static void stlink_confirm_inq(stlink_t *stl, struct sg_pt_base *ptvp) { void stlink_q(stlink_t *sl) { #if FINISHED_WITH_SG struct stlink_libsg* sg = sl->backend_data; - DD(sl, "CDB["); + DLOG("CDB["); for (int i = 0; i < CDB_SL; i++) - DD(sl, " 0x%02x", (unsigned int) sg->cdb_cmd_blk[i]); - DD(sl, "]\n"); + DLOG(" 0x%02x", (unsigned int) sg->cdb_cmd_blk[i]); + DLOG("]\n"); // Get control command descriptor of scsi structure, // (one object per command!!) @@ -258,13 +263,13 @@ void stlink_stat(stlink_t *stl, char *txt) { switch (stl->q_buf[0]) { case STLINK_OK: - DD(stl, " %s: ok\n", txt); + DLOG(" %s: ok\n", txt); return; case STLINK_FALSE: - DD(stl, " %s: false\n", txt); + DLOG(" %s: false\n", txt); return; default: - DD(stl, " %s: unknown\n", txt); + DLOG(" %s: unknown\n", txt); } } @@ -300,7 +305,7 @@ static void parse_version(stlink_t *stl) { void _stlink_sg_version(stlink_t *stl) { struct stlink_libsg *sl = stl->backend_data; - D(stl, "\n*** stlink_version ***\n"); + DLOG("\n*** stlink_version ***\n"); clear_cdb(sl); sl->cdb_cmd_blk[0] = STLINK_GET_VERSION; stl->q_len = 6; @@ -339,7 +344,7 @@ void _stlink_sg_enter_swd_mode(stlink_t *sl) { void _stlink_sg_enter_jtag_mode(stlink_t *sl) { struct stlink_libsg *sg = sl->backend_data; - D(sl, "\n*** stlink_enter_jtag_mode ***\n"); + DLOG("\n*** stlink_enter_jtag_mode ***\n"); clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_ENTER; sg->cdb_cmd_blk[2] = STLINK_DEBUG_ENTER_JTAG; @@ -351,7 +356,7 @@ void _stlink_sg_enter_jtag_mode(stlink_t *sl) { void _stlink_sg_exit_dfu_mode(stlink_t *sl) { struct stlink_libsg *sg = sl->backend_data; - D(sl, "\n*** stlink_exit_dfu_mode ***\n"); + DLOG("\n*** stlink_exit_dfu_mode ***\n"); clear_cdb(sg); sg->cdb_cmd_blk[0] = STLINK_DFU_COMMAND; sg->cdb_cmd_blk[1] = STLINK_DFU_EXIT; @@ -428,7 +433,7 @@ void _stlink_sg_reset(stlink_t *sl) { void _stlink_sg_status(stlink_t *sl) { struct stlink_libsg *sg = sl->backend_data; - D(sl, "\n*** stlink_status ***\n"); + DLOG("\n*** stlink_status ***\n"); clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_GETSTATUS; sl->q_len = 2; @@ -440,7 +445,7 @@ void _stlink_sg_status(stlink_t *sl) { void _stlink_sg_force_debug(stlink_t *sl) { struct stlink_libsg *sg = sl->backend_data; - D(sl, "\n*** stlink_force_debug ***\n"); + DLOG("\n*** stlink_force_debug ***\n"); clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_FORCEDEBUG; sl->q_len = 2; @@ -471,7 +476,7 @@ void _stlink_sg_read_all_regs(stlink_t *sl, reg *regp) { for (int i = 0; i < 16; i++) { sg->reg.r[i] = read_uint32(sl->q_buf, 4 * i); if (sl->verbose > 1) - DD(sl, "r%2d = 0x%08x\n", i, sg->reg.r[i]); + DLOG("r%2d = 0x%08x\n", i, sg->reg.r[i]); } sg->reg.xpsr = read_uint32(sl->q_buf, 64); sg->reg.main_sp = read_uint32(sl->q_buf, 68); @@ -481,11 +486,11 @@ void _stlink_sg_read_all_regs(stlink_t *sl, reg *regp) { if (sl->verbose < 2) return; - DD(sl, "xpsr = 0x%08x\n", sg->reg.xpsr); - DD(sl, "main_sp = 0x%08x\n", sg->reg.main_sp); - DD(sl, "process_sp = 0x%08x\n", sg->reg.process_sp); - DD(sl, "rw = 0x%08x\n", sg->reg.rw); - DD(sl, "rw2 = 0x%08x\n", sg->reg.rw2); + DLOG("xpsr = 0x%08x\n", sg->reg.xpsr); + DLOG("main_sp = 0x%08x\n", sg->reg.main_sp); + DLOG("process_sp = 0x%08x\n", sg->reg.process_sp); + DLOG("rw = 0x%08x\n", sg->reg.rw); + DLOG("rw2 = 0x%08x\n", sg->reg.rw2); } // Read an arm-core register, the index must be in the range 0..20. @@ -506,7 +511,7 @@ void _stlink_sg_read_reg(stlink_t *sl, int r_idx, reg *regp) { stlink_print_data(sl); uint32_t r = read_uint32(sl->q_buf, 0); - DD(sl, "r_idx (%2d) = 0x%08x\n", r_idx, r); + DLOG("r_idx (%2d) = 0x%08x\n", r_idx, r); switch (r_idx) { case 16: @@ -553,7 +558,7 @@ void _stlink_sg_write_reg(stlink_t *sl, uint32_t reg, int idx) { void stlink_write_dreg(stlink_t *sl, uint32_t reg, uint32_t addr) { struct stlink_libsg *sg = sl->backend_data; - D(sl, "\n*** stlink_write_dreg ***\n"); + DLOG("\n*** stlink_write_dreg ***\n"); clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_WRITEDEBUGREG; // 2-5: address of reg of the debug module @@ -570,7 +575,7 @@ void stlink_write_dreg(stlink_t *sl, uint32_t reg, uint32_t addr) { void _stlink_sg_run(stlink_t *sl) { struct stlink_libsg *sg = sl->backend_data; - D(sl, "\n*** stlink_run ***\n"); + DLOG("\n*** stlink_run ***\n"); clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_RUNCORE; sl->q_len = 2; @@ -595,7 +600,7 @@ void _stlink_sg_step(stlink_t *sl) { // see Cortex-M3 Technical Reference Manual // TODO make delegate! void stlink_set_hw_bp(stlink_t *sl, int fp_nr, uint32_t addr, int fp) { - D(sl, "\n*** stlink_set_hw_bp ***\n"); + DLOG("\n*** stlink_set_hw_bp ***\n"); struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_SETFP; @@ -616,7 +621,7 @@ void stlink_set_hw_bp(stlink_t *sl, int fp_nr, uint32_t addr, int fp) { // TODO make delegate! void stlink_clr_hw_bp(stlink_t *sl, int fp_nr) { struct stlink_libsg *sg = sl->backend_data; - D(sl, "\n*** stlink_clr_hw_bp ***\n"); + DLOG("\n*** stlink_clr_hw_bp ***\n"); clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_CLEARFP; sg->cdb_cmd_blk[2] = fp_nr; @@ -805,7 +810,7 @@ stlink_t* stlink_open(const char *dev_name, const int verbose) { stlink_t* stlink_v1_open(const char *dev_name, const int verbose) { - + ugly_init(verbose); stlink_t *sl = stlink_open(dev_name, verbose); if (sl == NULL) { fputs("Error: could not open stlink device\n", stderr); @@ -825,7 +830,7 @@ stlink_t* stlink_v1_open(const char *dev_name, const int verbose) { return NULL; } - D(sl, "\n*** stlink_force_open ***\n"); + DLOG("\n*** stlink_force_open ***\n"); switch (stlink_current_mode(sl)) { case STLINK_DEV_MASS_MODE: return sl; @@ -833,10 +838,10 @@ stlink_t* stlink_v1_open(const char *dev_name, const int verbose) { // TODO go to mass? return sl; } - DD(sl, "\n*** switch the stlink to mass mode ***\n"); + DLOG("\n*** switch the stlink to mass mode ***\n"); _stlink_sg_exit_dfu_mode(sl); // exit the dfu mode -> the device is gone - DD(sl, "\n*** reopen the stlink device ***\n"); + DLOG("\n*** reopen the stlink device ***\n"); delay(1000); stlink_close(sl); delay(5000); diff --git a/src/stlink-usb.c b/src/stlink-usb.c index 5269961..c0b0009 100644 --- a/src/stlink-usb.c +++ b/src/stlink-usb.c @@ -5,8 +5,17 @@ #include #include #include + #include "stlink-common.h" #include "stlink-usb.h" +#include "uglylogging.h" + +#define LOG_TAG __FILE__ +#define DLOG(format, args...) ugly_log(UDEBUG, LOG_TAG, format, ## args) +#define ILOG(format, args...) ugly_log(UINFO, LOG_TAG, format, ## args) +#define WLOG(format, args...) ugly_log(UWARN, LOG_TAG, format, ## args) +#define fatal(format, args...) ugly_log(UFATAL, LOG_TAG, format, ## args) + enum SCSI_Generic_Direction {SG_DXFER_TO_DEV=0, SG_DXFER_FROM_DEV=0x80}; @@ -472,11 +481,11 @@ void _stlink_usb_read_all_regs(stlink_t *sl, reg *regp) { if (sl->verbose < 2) return; - DD(sl, "xpsr = 0x%08x\n", read_uint32(sl->q_buf, 64)); - DD(sl, "main_sp = 0x%08x\n", read_uint32(sl->q_buf, 68)); - DD(sl, "process_sp = 0x%08x\n", read_uint32(sl->q_buf, 72)); - DD(sl, "rw = 0x%08x\n", read_uint32(sl->q_buf, 76)); - DD(sl, "rw2 = 0x%08x\n", read_uint32(sl->q_buf, 80)); + DLOG("xpsr = 0x%08x\n", read_uint32(sl->q_buf, 64)); + DLOG("main_sp = 0x%08x\n", read_uint32(sl->q_buf, 68)); + DLOG("process_sp = 0x%08x\n", read_uint32(sl->q_buf, 72)); + DLOG("rw = 0x%08x\n", read_uint32(sl->q_buf, 76)); + DLOG("rw2 = 0x%08x\n", read_uint32(sl->q_buf, 80)); } void _stlink_usb_read_reg(stlink_t *sl, int r_idx, reg *regp) { @@ -499,7 +508,7 @@ void _stlink_usb_read_reg(stlink_t *sl, int r_idx, reg *regp) { sl->q_len = (size_t) size; stlink_print_data(sl); r = read_uint32(sl->q_buf, 0); - DD(sl, "r_idx (%2d) = 0x%08x\n", r_idx, r); + DLOG("r_idx (%2d) = 0x%08x\n", r_idx, r); switch (r_idx) { case 16: @@ -584,7 +593,7 @@ stlink_t* stlink_open_usb(const int verbose) { memset(sl, 0, sizeof (stlink_t)); memset(slu, 0, sizeof (struct stlink_libusb)); - sl->verbose = verbose; + ugly_init(verbose); sl->backend = &_stlink_usb_backend; sl->backend_data = slu; @@ -604,15 +613,15 @@ stlink_t* stlink_open_usb(const int verbose) { sl->sram_size = STM32L_SRAM_SIZE; if (libusb_init(&(slu->libusb_ctx))) { - fprintf(stderr, "failed to init libusb context, wrong version of libraries?\n"); - goto on_error; + WLOG("failed to init libusb context, wrong version of libraries?\n"); + goto on_error; } slu->usb_handle = libusb_open_device_with_vid_pid(slu->libusb_ctx, USB_ST_VID, USB_STLINK_32L_PID); if (slu->usb_handle == NULL) { // TODO - free usb context too... free(slu); - fprintf(stderr, "Couldn't find any ST-Link/V2 devices"); + WLOG("Couldn't find any ST-Link/V2 devices"); return NULL; } @@ -620,14 +629,15 @@ stlink_t* stlink_open_usb(const int verbose) { int r; r = libusb_detach_kernel_driver(slu->usb_handle, 0); - if (r<0) - printf("libusb_detach_kernel_driver(() error %s\n", strerror(-r)); + if (r<0) { + WLOG("libusb_detach_kernel_driver(() error %s\n", strerror(-r)); + } goto on_libusb_error; } if (libusb_get_configuration(slu->usb_handle, &config)) { /* this may fail for a previous configured device */ - printf("libusb_get_configuration()\n"); + WLOG("libusb_get_configuration()\n"); goto on_libusb_error; } @@ -635,25 +645,25 @@ stlink_t* stlink_open_usb(const int verbose) { printf("setting new configuration (%d -> 1)\n", config); if (libusb_set_configuration(slu->usb_handle, 1)) { /* this may fail for a previous configured device */ - printf("libusb_set_configuration()\n"); + WLOG("libusb_set_configuration() failed\n"); goto on_libusb_error; } } if (libusb_claim_interface(slu->usb_handle, 0)) { - printf("libusb_claim_interface()\n"); + WLOG("libusb_claim_interface() failed\n"); goto on_libusb_error; } slu->req_trans = libusb_alloc_transfer(0); if (slu->req_trans == NULL) { - printf("libusb_alloc_transfer\n"); + WLOG("libusb_alloc_transfer failed\n"); goto on_libusb_error; } slu->rep_trans = libusb_alloc_transfer(0); if (slu->rep_trans == NULL) { - printf("libusb_alloc_transfer\n"); + WLOG("libusb_alloc_transfer failed\n"); goto on_libusb_error; } // TODO - could use the scanning techniq from stm8 code here... @@ -666,7 +676,7 @@ stlink_t* stlink_open_usb(const int verbose) { /* success */ if (stlink_current_mode(sl) == STLINK_DEV_DFU_MODE) { - printf("-- exit_dfu_mode\n"); + ILOG("-- exit_dfu_mode\n"); stlink_exit_dfu_mode(sl); } stlink_version(sl); diff --git a/src/uglylogging.c b/src/uglylogging.c new file mode 100644 index 0000000..c6d07f8 --- /dev/null +++ b/src/uglylogging.c @@ -0,0 +1,58 @@ +/* + * UglyLogging. Slow, yet another wheel reinvented, but enough to make the + * rest of our code pretty enough. + * + */ + +#include +#include +#include +#include +#include + +#include "uglylogging.h" + +static int max_level; + +int ugly_init(int maximum_threshold) { + max_level = maximum_threshold; + return 0; +} + +int ugly_log(int level, const char *tag, const char *format, ...) { + if (level > max_level) { + return 0; + } + va_list args; + va_start(args, format); + time_t mytt = time(NULL); + struct tm *tt; + tt = localtime(&mytt); + fprintf(stderr, "%d-%02d-%02dT%02d:%02d:%02d ", tt->tm_year + 1900, tt->tm_mon + 1, tt->tm_mday, tt->tm_hour, tt->tm_min, tt->tm_sec); + switch (level) { + case UDEBUG: + fprintf(stderr, "DEBUG %s: ", tag); + break; + case UINFO: + fprintf(stderr, "INFO %s: ", tag); + break; + case UWARN: + fprintf(stderr, "WARN %s: ", tag); + break; + case UERROR: + fprintf(stderr, "ERROR %s: ", tag); + break; + case UFATAL: + fprintf(stderr, "FATAL %s: ", tag); + vfprintf(stderr, format, args); + exit(EXIT_FAILURE); + // NEVER GETS HERE!!! + break; + default: + fprintf(stderr, "%d %s: ", level, tag); + break; + } + vfprintf(stderr, format, args); + va_end(args); + return 1; +} \ No newline at end of file diff --git a/src/uglylogging.h b/src/uglylogging.h new file mode 100644 index 0000000..fa34d46 --- /dev/null +++ b/src/uglylogging.h @@ -0,0 +1,27 @@ +/* + * Ugly, low performance, configurable level, logging "framework" + */ + +#ifndef UGLYLOGGING_H +#define UGLYLOGGING_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define UDEBUG 90 +#define UINFO 50 +#define UWARN 30 +#define UERROR 20 +#define UFATAL 10 + + int ugly_init(int maximum_threshold); + int ugly_log(int level, const char *tag, const char *format, ...); + + +#ifdef __cplusplus +} +#endif + +#endif /* UGLYLOGGING_H */ + From a672ee1a34f0602079c52bbd04e7d115ccb37651 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Tue, 1 Nov 2011 18:50:06 +0000 Subject: [PATCH 15/63] Ignore all elf outputs. Ignore pdflatex outputs --- .gitignore | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/.gitignore b/.gitignore index 44d2e4d..0a541c7 100644 --- a/.gitignore +++ b/.gitignore @@ -1,6 +1,9 @@ /nbproject/private/ *.o +*.elf +doc/tutorial/*.log +doc/tutorial/*.aux libstlink.a test_usb test_sg -gdbserver/st-utils \ No newline at end of file +gdbserver/st-utils From ee772151c2aca1508b906982ad30944087e8143b Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Tue, 1 Nov 2011 18:51:14 +0000 Subject: [PATCH 16/63] Remove unneeded old files --- example/blink/default_bootloader.bin | Bin 2048 -> 0 bytes example/blink/disasm.sh | 3 --- 2 files changed, 3 deletions(-) delete mode 100755 example/blink/default_bootloader.bin delete mode 100755 example/blink/disasm.sh diff --git a/example/blink/default_bootloader.bin b/example/blink/default_bootloader.bin deleted file mode 100755 index 0e3137184c083c5657dd9bd45ffdf7846fc02962..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 2048 zcmah~eQaCR6+h2@{vh?zmz8Z!$m*9b&6(UKty&RAQ6G+DKc|6oLy^*{70ftFPTDo{sI=wt;@6K8?7B9)m|t({c#+~Nt1mcBn&6BbRlZIb(%y!Xz| zH7VPFd(!#3_nhP3x#!+vaDlw3jG_xAW(IU9pIHVK5~*7l0@{D(gG}NvqU#Nxp~W{AVO{ zXy${1$lk#~8G&nWp?^ht1MgbVUPX|DS(kBA9;JGby;8x)^H0x~4;PXkUl=&zgOVU; z5*+W@t#7WKG=VU>2%|VWX?jNroqx#}Zuwe>;=XERFA~yciJrpoZ_!pT5UQOO3>d5A>OYxe*s@-eNBC;#Fx5VvXpux6(x?$a)2a|2Qq>7Z#&3tI?q)q73tjm+v^#J z_nNQ4v@|8gS5d~R&XW~SfmWNS_L8Hg6`%XlU_c}5lW(jNtx=q=@p$ejO^@7w)Wia8 z5iYr?6OSf^*u+BlQQ?xCtQ{2#4hWY-vVM{D$Ho`nY2lKGEZ(>FDQH1fi{;b%sm5W# z`y`6-u7APf$o3$~u9$)>#kCf$?Lbc_m;E>r6^lG(pA(L^PxBM{rPEvPYj5Xww^w<4 z^M!NcLT+;b*>>l??yj4C+a%2^Z_}s?O>4Bx$=>;_q-yu~2(rA#pUw(a>0b4|o|p#B zy=9~2oaui^Y-mj-#er1prYH=iHmVzv1yc;_razeUESFZ~r*~`*dEZ&f4dmj51!xJY zqw$8gnDsSJEzi#%%J$9|b{`s~?_lT6z=Ogd$Nzojni(0ERKnFDXw-j4q+ZNAnu1}_ z`dMVo(&#bN-It3y!ko)jY6D`%rlM^74iBfrx9S2`mv=({3Ox|v%XA-u2nfN?PLtbR1ISMM;OQF!e%V*`1=Z11lByS^#DuRcug>P4Hsj@>gM`5%zVS(1K|@_bhIYbr?xRPDSejU#*5empJHo9(f4i3cdtpDJixcmA3e+TJ2GEzWmt z+#QJ3r{bb<(%5OdY>XMF3C)k3vG8w;uC_JB5uZyJ%a+*uLu9Jm0#$loPOKW6^MH_U zuT}0rw#``=S}eNTR{xK$3_J7ViTegm_T_^_WZE`<;{@1PZ zX5d6Kq26N);VtuZr}*mU7P1d)411`Pc{_I+*+1>?8lLxK^{v#85ACt=fqBoVo{8Qv z?D-x|Bkx?6qW(>rSQs$#!l@f&m2;(LcH=%2pM^+8KgrS9!<#T09Yqsv8* z=VoB4s#{MNyxtO@02zx-JIQ=(sqD=qyYos?tRE_jy0r3T2(8D>mD_=WW>DLju&SVe# E2h&9CasU7T diff --git a/example/blink/disasm.sh b/example/blink/disasm.sh deleted file mode 100755 index b3b46da..0000000 --- a/example/blink/disasm.sh +++ /dev/null @@ -1,3 +0,0 @@ -#!/usr/bin/env sh -#/home/texane/sat/bin/arm-none-eabi-objdump -marm -Mforce-thumb -EL -b binary -D /tmp/barfoo -/home/texane/sat/bin/arm-none-eabi-objdump -marm -EL -b binary -D /tmp/barfoo From e8bae670d226061d567869d24fe3cbc175dff364 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Tue, 1 Nov 2011 21:23:16 +0000 Subject: [PATCH 17/63] Fix compilation for 32bit machines %Ld works for size_t only on 64 bit, the correct conversion is %zd --- gdbserver/gdb-server.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index 3af0d8a..65297bc 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -143,7 +143,7 @@ int parse_options(int argc, char** argv, st_state_t *st) { break; case 'd': if (strlen(optarg) > sizeof (st->devicename)) { - fprintf(stderr, "device name too long: %ld\n", strlen(optarg)); + fprintf(stderr, "device name too long: %zd\n", strlen(optarg)); } else { strcpy(st->devicename, optarg); } From c0c45e259e1d7efd79c22369c7160d910e4035e0 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Tue, 1 Nov 2011 21:56:43 +0000 Subject: [PATCH 18/63] More generic stlinkv2 udev naming Better support for F4, or anything else that appears as an stlinkv2 --- 49-stm32l-discovery.rules => 49-stlinkv2.rules | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) rename 49-stm32l-discovery.rules => 49-stlinkv2.rules (71%) diff --git a/49-stm32l-discovery.rules b/49-stlinkv2.rules similarity index 71% rename from 49-stm32l-discovery.rules rename to 49-stlinkv2.rules index 1f3ce77..a11215c 100644 --- a/49-stm32l-discovery.rules +++ b/49-stlinkv2.rules @@ -1,9 +1,11 @@ -# stm32l discovery board, with onboard st/linkv2 -# +# stm32 discovery boards, with onboard st/linkv2 +# ie, STM32L, STM32F4. +# STM32VL has st/linkv1, which is quite different + SUBSYSTEMS=="usb", ATTRS{idVendor}=="0483", ATTRS{idProduct}=="3748", \ MODE:="0666", \ - SYMLINK+="stm32l_stlink%n" -# + SYMLINK+="stlinkv2_%n" + # If you share your linux system with other users, or just don't like the # idea of write permission for everybody, you can replace MODE:="0666" with # OWNER:="yourusername" to create the device owned by you, or with From 66c50cec899fcb25e6a4ea670208defebe8759cd Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Thu, 3 Nov 2011 00:35:19 +0000 Subject: [PATCH 19/63] Remove sg-utils test output More bulk cleanup on the path to removing sg-utils dependencies. Trying to make test-sg as simple as possible so I can use it reliably to test on both master and my killsg branch --- src/test_sg.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/src/test_sg.c b/src/test_sg.c index 34fbe54..a4db8f2 100644 --- a/src/test_sg.c +++ b/src/test_sg.c @@ -14,7 +14,6 @@ int main(int argc, char *argv[]) { // set scpi lib debug level: 0 for no debug info, 10 for lots - const int scsi_verbose = 2; char *dev_name; switch (argc) { @@ -37,14 +36,11 @@ int main(int argc, char *argv[]) { return EXIT_FAILURE; } - fputs("*** stlink access test ***\n", stderr); - fprintf(stderr, "Using sg_lib %s : scsi_pt %s\n", sg_lib_version(), - scsi_pt_version()); - - stlink_t *sl = stlink_quirk_open(dev_name, scsi_verbose); + stlink_t *sl = stlink_quirk_open(dev_name, 10); if (sl == NULL) return EXIT_FAILURE; - + + // we are in mass mode, go to swd stlink_enter_swd_mode(sl); stlink_current_mode(sl); @@ -176,7 +172,7 @@ int main(int argc, char *argv[]) { stlink_force_debug(sl); stlink_status(sl); #endif -#if 1 /* read the system bootloader */ +#if 0 /* read the system bootloader */ fputs("\n++++++++++ reading bootloader ++++++++++++++++\n\n", stderr); stlink_fread(sl, "/tmp/barfoo", sl->sys_base, sl->sys_size); #endif @@ -202,6 +198,7 @@ int main(int argc, char *argv[]) { stlink_run_at(sl, sl->sram_base); #endif +#if 0 stlink_run(sl); stlink_status(sl); //---------------------------------------------------------------------- @@ -209,6 +206,7 @@ int main(int argc, char *argv[]) { stlink_exit_debug_mode(sl); stlink_current_mode(sl); stlink_close(sl); +#endif //fflush(stderr); fflush(stdout); return EXIT_SUCCESS; From afb487cfb627762590ee1acf750a77417cf73e18 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Thu, 3 Nov 2011 00:36:31 +0000 Subject: [PATCH 20/63] Remove -sg's private version decoding Remove duplication of stlink version decoding, and put the decoded version information into the stlink object itself. --- src/stlink-common.c | 17 ++++++++--------- src/stlink-common.h | 1 + src/stlink-sg.c | 37 +++---------------------------------- src/stlink-sg.h | 7 ------- 4 files changed, 12 insertions(+), 50 deletions(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index 707316c..6a9b938 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -356,19 +356,18 @@ void _parse_version(stlink_t *sl, stlink_version_t *slv) { void stlink_version(stlink_t *sl) { D(sl, "*** looking up stlink version\n"); - stlink_version_t slv; sl->backend->version(sl); - _parse_version(sl, &slv); + _parse_version(sl, &sl->version); - DD(sl, "st vid = 0x%04x (expect 0x%04x)\n", slv.st_vid, USB_ST_VID); - DD(sl, "stlink pid = 0x%04x\n", slv.stlink_pid); - DD(sl, "stlink version = 0x%x\n", slv.stlink_v); - DD(sl, "jtag version = 0x%x\n", slv.jtag_v); - DD(sl, "swim version = 0x%x\n", slv.swim_v); - if (slv.jtag_v == 0) { + DD(sl, "st vid = 0x%04x (expect 0x%04x)\n", sl->version.st_vid, USB_ST_VID); + DD(sl, "stlink pid = 0x%04x\n", sl->version.stlink_pid); + DD(sl, "stlink version = 0x%x\n", sl->version.stlink_v); + DD(sl, "jtag version = 0x%x\n", sl->version.jtag_v); + DD(sl, "swim version = 0x%x\n", sl->version.swim_v); + if (sl->version.jtag_v == 0) { DD(sl, " notice: the firmware doesn't support a jtag/swd interface\n"); } - if (slv.swim_v == 0) { + if (sl->version.swim_v == 0) { DD(sl, " notice: the firmware doesn't support a swim interface\n"); } } diff --git a/src/stlink-common.h b/src/stlink-common.h index 9481609..2ac56f2 100644 --- a/src/stlink-common.h +++ b/src/stlink-common.h @@ -179,6 +179,7 @@ extern "C" { stm32_addr_t sram_base; size_t sram_size; + struct stlink_version_ version; }; // some quick and dirty logging... diff --git a/src/stlink-sg.c b/src/stlink-sg.c index b8220de..e8dee5d 100644 --- a/src/stlink-sg.c +++ b/src/stlink-sg.c @@ -268,35 +268,6 @@ void stlink_stat(stlink_t *stl, char *txt) { } -static void parse_version(stlink_t *stl) { - struct stlink_libsg *sl = stl->backend_data; - - sl->st_vid = 0; - sl->stlink_pid = 0; - - if (stl->q_len <= 0) { - fprintf(stderr, "Error: could not parse the stlink version"); - return; - } - - uint32_t b0 = stl->q_buf[0]; //lsb - uint32_t b1 = stl->q_buf[1]; - uint32_t b2 = stl->q_buf[2]; - uint32_t b3 = stl->q_buf[3]; - uint32_t b4 = stl->q_buf[4]; - uint32_t b5 = stl->q_buf[5]; //msb - - // b0 b1 || b2 b3 | b4 b5 - // 4b | 6b | 6b || 2B | 2B - // stlink_v | jtag_v | swim_v || st_vid | stlink_pid - - sl->stlink_v = (b0 & 0xf0) >> 4; - sl->jtag_v = ((b0 & 0x0f) << 2) | ((b1 & 0xc0) >> 6); - sl->swim_v = b1 & 0x3f; - sl->st_vid = (b3 << 8) | b2; - sl->stlink_pid = (b5 << 8) | b4; -} - void _stlink_sg_version(stlink_t *stl) { struct stlink_libsg *sl = stl->backend_data; D(stl, "\n*** stlink_version ***\n"); @@ -305,7 +276,6 @@ void _stlink_sg_version(stlink_t *stl) { stl->q_len = 6; sl->q_addr = 0; stlink_q(stl); - parse_version(stl); } // Get stlink mode: @@ -781,7 +751,6 @@ stlink_t* stlink_open(const char *dev_name, const int verbose) { slsg->sg_fd = sg_fd; sl->core_stat = STLINK_CORE_STAT_UNKNOWN; - slsg->core_id = 0; slsg->q_addr = 0; clear_buf(sl); @@ -814,13 +783,13 @@ stlink_t* stlink_quirk_open(const char *dev_name, const int verbose) { stlink_version(sl); struct stlink_libsg *sg = sl->backend_data; - if ((sg->st_vid != USB_ST_VID) || (sg->stlink_pid != USB_STLINK_PID)) { + if ((sl->version.st_vid != USB_ST_VID) || (sl->version.stlink_pid != USB_STLINK_PID)) { fprintf(stderr, "Error: the device %s is not a stlink\n", dev_name); fprintf(stderr, " VID: got %04x expect %04x \n", - sg->st_vid, USB_ST_VID); + sl->version.st_vid, USB_ST_VID); fprintf(stderr, " PID: got %04x expect %04x \n", - sg->stlink_pid, USB_STLINK_PID); + sl->version.stlink_pid, USB_STLINK_PID); return NULL; } diff --git a/src/stlink-sg.h b/src/stlink-sg.h index 523b7d8..b3ab9c0 100644 --- a/src/stlink-sg.h +++ b/src/stlink-sg.h @@ -54,13 +54,6 @@ extern "C" { // Sense (error information) data unsigned char sense_buf[SENSE_BUF_LEN]; - uint32_t st_vid; - uint32_t stlink_pid; - uint32_t stlink_v; - uint32_t jtag_v; - uint32_t swim_v; - uint32_t core_id; - reg reg; }; #else From 7de94e5491c2a5f0bba4e374c6aad6bdd61ee235 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Thu, 3 Nov 2011 00:37:32 +0000 Subject: [PATCH 21/63] drop non shared directories from netbeans project --- nbproject/configurations.xml | 14 -------------- 1 file changed, 14 deletions(-) diff --git a/nbproject/configurations.xml b/nbproject/configurations.xml index 794a3ab..5679465 100644 --- a/nbproject/configurations.xml +++ b/nbproject/configurations.xml @@ -127,20 +127,6 @@ - - - - - - - - - - - - - - Date: Thu, 3 Nov 2011 01:07:15 +0000 Subject: [PATCH 22/63] Successfully locate and open stlinkv1 by usb Very very raw, this just finds the device and opens the usb handle. --- Makefile | 2 +- src/stlink-sg.c | 84 ++++++++++++++++++++++++++++++++++++++++++++----- src/stlink-sg.h | 3 ++ src/test_sg.c | 3 +- 4 files changed, 82 insertions(+), 10 deletions(-) diff --git a/Makefile b/Makefile index c3c345a..646dde1 100644 --- a/Makefile +++ b/Makefile @@ -4,7 +4,7 @@ VPATH=src SOURCES_LIB=stlink-common.c stlink-usb.c stlink-sg.c uglylogging.c OBJS_LIB=$(SOURCES_LIB:.c=.o) -TEST_PROGRAMS=test_usb #test_sg +TEST_PROGRAMS=test_usb test_sg LDFLAGS=-lusb-1.0 -L. -lstlink CFLAGS+=-g diff --git a/src/stlink-sg.c b/src/stlink-sg.c index 5d1f970..3b9958d 100644 --- a/src/stlink-sg.c +++ b/src/stlink-sg.c @@ -736,26 +736,94 @@ stlink_backend_t _stlink_sg_backend = { _stlink_sg_force_debug }; -stlink_t* stlink_open(const char *dev_name, const int verbose) { - fprintf(stderr, "\n*** stlink_open [%s] ***\n", dev_name); - int sg_fd = scsi_pt_open_device(dev_name, RDWR, verbose); - if (sg_fd < 0) { - fprintf(stderr, "error opening device: %s: %s\n", dev_name, - safe_strerror(-sg_fd)); +#if using_stm8_stuff_XXXX +stlink *stlink_open(libusb_context *usb_context) +{ + stlink *stl = malloc(sizeof(stlink)); + stl->handle = libusb_open_device_with_vid_pid(usb_context, USB_VID_ST, USB_PID_STLINK); + if (stl->handle == NULL) { + free(stl); return NULL; } + libusb_device *dev = libusb_get_device(stl->handle); + struct libusb_config_descriptor *conf_desc; + int ret = libusb_get_config_descriptor(dev, 0, &conf_desc); + if (ret != LIBUSB_SUCCESS) { + libusb_close(stl->handle); + free(stl); + return NULL; + } + for (int i = 0; i < conf_desc->bNumInterfaces; i++) { + printf("interface %d\n", i); + for (int j = 0; j < conf_desc->interface[i].num_altsetting; j++) { + for (int k = 0; k < conf_desc->interface[i].altsetting[j].bNumEndpoints; k++) { + const struct libusb_endpoint_descriptor *endpoint; + endpoint = &conf_desc->interface[i].altsetting[j].endpoint[k]; + if (endpoint->bEndpointAddress & LIBUSB_ENDPOINT_IN) { + stl->endpoint_in = endpoint->bEndpointAddress; + printf("Found IN endpoint\n"); + } else { + stl->endpoint_out = endpoint->bEndpointAddress; + printf("Found OUT endpoint\n"); + } + } + } + } + libusb_free_config_descriptor(conf_desc); + + ret = libusb_kernel_driver_active(stl->handle, 0); + if (ret == 1) { + printf("kernel driver active\n"); + } else if (ret == 0) { + //printf("kernel driver not active\n"); + } else { + fprintf(stderr, "libusb_kernel_driver_active = %d\n", ret); + } + ret = libusb_claim_interface(stl->handle, 0); + if (ret != LIBUSB_SUCCESS) { + fprintf(stderr, "claiming interface failed: %d\n", ret); + libusb_close(stl->handle); + free(stl); + return NULL; + } + + return stl; +} +#endif + + +static stlink_t* stlink_open(const char *dev_name, const int verbose) { + fprintf(stderr, "\n*** stlink_open [%s] ***\n", dev_name); + stlink_t *sl = malloc(sizeof (stlink_t)); struct stlink_libsg *slsg = malloc(sizeof (struct stlink_libsg)); if (sl == NULL || slsg == NULL) { - fprintf(stderr, "Couldn't malloc stlink and stlink_sg structures out of memory!\n"); + WLOG("Couldn't malloc stlink and stlink_sg structures out of memory!\n"); return NULL; } + + if (libusb_init(&(slsg->libusb_ctx))) { + WLOG("failed to init libusb context, wrong version of libraries?\n"); + free(sl); + free(slsg); + return NULL; + } + + slsg->handle = libusb_open_device_with_vid_pid(slsg->libusb_ctx, USB_ST_VID, USB_STLINK_PID); + if (slsg->handle == NULL) { + WLOG("Failed to find an stlink v1 by VID:PID\n"); + free(sl); + free(slsg); + return NULL; + } + + DLOG("Successfully opened stlinkv1 by libusb :)\n"); + sl->verbose = verbose; sl->backend_data = slsg; sl->backend = &_stlink_sg_backend; - slsg->sg_fd = sg_fd; sl->core_stat = STLINK_CORE_STAT_UNKNOWN; slsg->q_addr = 0; clear_buf(sl); diff --git a/src/stlink-sg.h b/src/stlink-sg.h index 723c66a..c9776cd 100644 --- a/src/stlink-sg.h +++ b/src/stlink-sg.h @@ -41,6 +41,9 @@ extern "C" { struct stlink_libsg { + libusb_context* libusb_ctx; + libusb_device_handle *handle; + int sg_fd; int do_scsi_pt_err; diff --git a/src/test_sg.c b/src/test_sg.c index 30f867a..742ba44 100644 --- a/src/test_sg.c +++ b/src/test_sg.c @@ -29,10 +29,11 @@ int main(int argc, char *argv[]) { dev_name = argv[1]; break; default: + fprintf(stderr, "bzzt\n"); return EXIT_FAILURE; } - stlink_t *sl = stlink_v1_open(dev_name, 10); + stlink_t *sl = stlink_v1_open(dev_name, 99); if (sl == NULL) return EXIT_FAILURE; From 3bf3bbef0ba03fa54c531b94daaf0c4029c0af8b Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Thu, 3 Nov 2011 03:45:23 +0000 Subject: [PATCH 23/63] Read stlink version info via libusb. Hooray! Stage 1 complete. The stlink version can now be read by sending the scsi commands via libusb directly, instead of using sg-utils. It's very very prototype code however, but should come together from here. Major bugs: Only works when the device has been first plugged in. I'm clearly not resetting some usb state somewhere. Now that libusb is being used directly, you can use linux usb-storage quirks to completely IGNORE the device as mass storage. We'll just grab it via libusb when we want it. --- src/stlink-sg.c | 216 ++++++++++++++++++++++++++++++++++------------- src/stlink-sg.h | 4 +- src/stlink-usb.c | 2 +- 3 files changed, 159 insertions(+), 63 deletions(-) diff --git a/src/stlink-sg.c b/src/stlink-sg.c index 3b9958d..9d71df1 100644 --- a/src/stlink-sg.c +++ b/src/stlink-sg.c @@ -281,7 +281,102 @@ void _stlink_sg_version(stlink_t *stl) { sl->cdb_cmd_blk[0] = STLINK_GET_VERSION; stl->q_len = 6; sl->q_addr = 0; - stlink_q(stl); +// stlink_q(stl); + // HACK use my own private version right now... + + int try = 0; + int ret = 0; + int real_transferred; + +/* + uint32_t dCBWSignature; + uint32_t dCBWTag; + uint32_t dCBWDataTransferLength; + uint8_t bmCBWFlags; + uint8_t bCBWLUN; + uint8_t bCBWCBLength; + uint8_t CBWCB[16]; + */ + +#if using_old_code_examples + /* + * and from old code? + cmd[i++] = 'U'; + cmd[i++] = 'S'; + cmd[i++] = 'B'; + cmd[i++] = 'C'; + write_uint32(&cmd[i], sg->sg_transfer_idx); + write_uint32(&cmd[i + 4], len); + i += 8; + cmd[i++] = (dir == SG_DXFER_FROM_DEV)?0x80:0; + cmd[i++] = 0; /* Logical unit */ + cmd[i++] = 0xa; /* Command length */ + */ +#endif + + int i = 0; + stl->c_buf[i++] = 'U'; + stl->c_buf[i++] = 'S'; + stl->c_buf[i++] = 'B'; + stl->c_buf[i++] = 'C'; + // tag is allegedly ignored... TODO - verify + write_uint32(&stl->c_buf[i], 1); + // TODO - Does this even matter? verify with more commands.... + uint32_t command_length = STLINK_CMD_SIZE; + write_uint32(&stl->c_buf[i+4], command_length); + i+= 8; + stl->c_buf[i++] = LIBUSB_ENDPOINT_IN; + // assumption: lun is always 0; + stl->c_buf[i++] = 0; + + stl->c_buf[i++] = sizeof(sl->cdb_cmd_blk); + + // duh, now the actual data... + memcpy(&(stl->c_buf[i]), sl->cdb_cmd_blk, sizeof(sl->cdb_cmd_blk)); + + int sending_length = STLINK_SG_SIZE; + DLOG("sending length set to: %d\n", sending_length); + + // send.... + do { + DLOG("attempting tx...\n"); + ret = libusb_bulk_transfer(sl->usb_handle, sl->ep_req, stl->c_buf, sending_length, + &real_transferred, 3 * 1000); + if (ret == LIBUSB_ERROR_PIPE) { + libusb_clear_halt(sl->usb_handle, sl->ep_req); + } + try++; + } while ((ret == LIBUSB_ERROR_PIPE) && (try < 3)); + if (ret != LIBUSB_SUCCESS) { + WLOG("sending failed: %d\n", ret); + return; + } + DLOG("Actually sent: %d\n", real_transferred); + + // now wait for our response... + // length copied from stlink-usb... + int rx_length = 6; + try = 0; + do { + DLOG("attempting rx\n"); + ret = libusb_bulk_transfer(sl->usb_handle, sl->ep_rep, stl->q_buf, rx_length, + &real_transferred, 3 * 1000); + if (ret == LIBUSB_ERROR_PIPE) { + libusb_clear_halt(sl->usb_handle, sl->ep_req); + } + try++; + } while ((ret == LIBUSB_ERROR_PIPE) && (try < 3)); + + if (ret != LIBUSB_SUCCESS) { + WLOG("Receiving failed: %d\n", ret); + return; + } + + if (real_transferred != rx_length) { + WLOG("received unexpected amount: %d != %d\n", real_transferred, rx_length); + } + + DLOG("Actually received: %d\n", real_transferred); } // Get stlink mode: @@ -736,65 +831,8 @@ stlink_backend_t _stlink_sg_backend = { _stlink_sg_force_debug }; -#if using_stm8_stuff_XXXX -stlink *stlink_open(libusb_context *usb_context) -{ - stlink *stl = malloc(sizeof(stlink)); - stl->handle = libusb_open_device_with_vid_pid(usb_context, USB_VID_ST, USB_PID_STLINK); - if (stl->handle == NULL) { - free(stl); - return NULL; - } - - libusb_device *dev = libusb_get_device(stl->handle); - struct libusb_config_descriptor *conf_desc; - int ret = libusb_get_config_descriptor(dev, 0, &conf_desc); - if (ret != LIBUSB_SUCCESS) { - libusb_close(stl->handle); - free(stl); - return NULL; - } - for (int i = 0; i < conf_desc->bNumInterfaces; i++) { - printf("interface %d\n", i); - for (int j = 0; j < conf_desc->interface[i].num_altsetting; j++) { - for (int k = 0; k < conf_desc->interface[i].altsetting[j].bNumEndpoints; k++) { - const struct libusb_endpoint_descriptor *endpoint; - endpoint = &conf_desc->interface[i].altsetting[j].endpoint[k]; - if (endpoint->bEndpointAddress & LIBUSB_ENDPOINT_IN) { - stl->endpoint_in = endpoint->bEndpointAddress; - printf("Found IN endpoint\n"); - } else { - stl->endpoint_out = endpoint->bEndpointAddress; - printf("Found OUT endpoint\n"); - } - } - } - } - libusb_free_config_descriptor(conf_desc); - - ret = libusb_kernel_driver_active(stl->handle, 0); - if (ret == 1) { - printf("kernel driver active\n"); - } else if (ret == 0) { - //printf("kernel driver not active\n"); - } else { - fprintf(stderr, "libusb_kernel_driver_active = %d\n", ret); - } - ret = libusb_claim_interface(stl->handle, 0); - if (ret != LIBUSB_SUCCESS) { - fprintf(stderr, "claiming interface failed: %d\n", ret); - libusb_close(stl->handle); - free(stl); - return NULL; - } - - return stl; -} -#endif - - static stlink_t* stlink_open(const char *dev_name, const int verbose) { - fprintf(stderr, "\n*** stlink_open [%s] ***\n", dev_name); + DLOG("*** stlink_open [%s] ***\n", dev_name); stlink_t *sl = malloc(sizeof (stlink_t)); struct stlink_libsg *slsg = malloc(sizeof (struct stlink_libsg)); @@ -810,14 +848,70 @@ static stlink_t* stlink_open(const char *dev_name, const int verbose) { return NULL; } - slsg->handle = libusb_open_device_with_vid_pid(slsg->libusb_ctx, USB_ST_VID, USB_STLINK_PID); - if (slsg->handle == NULL) { + libusb_set_debug(slsg->libusb_ctx, 3); + + slsg->usb_handle = libusb_open_device_with_vid_pid(slsg->libusb_ctx, USB_ST_VID, USB_STLINK_PID); + if (slsg->usb_handle == NULL) { WLOG("Failed to find an stlink v1 by VID:PID\n"); + libusb_close(slsg->usb_handle); free(sl); free(slsg); return NULL; } + // TODO + // Could read the interface config descriptor, and assert lots of the assumptions + + // assumption: numInterfaces is always 1... + if (libusb_kernel_driver_active(slsg->usb_handle, 0) == 1) { + int r = libusb_detach_kernel_driver(slsg->usb_handle, 0); + if (r < 0) { + WLOG("libusb_detach_kernel_driver(() error %s\n", strerror(-r)); + libusb_close(slsg->usb_handle); + free(sl); + free(slsg); + return NULL; + } + DLOG("Kernel driver was successfully detached\n"); + } + + int config; + if (libusb_get_configuration(slsg->usb_handle, &config)) { + /* this may fail for a previous configured device */ + WLOG("libusb_get_configuration()\n"); + libusb_close(slsg->usb_handle); + free(sl); + free(slsg); + return NULL; + + } + + // assumption: bConfigurationValue is always 1 + if (config != 1) { + WLOG("Your stlink got into a real weird configuration, trying to fix it!\n"); + DLOG("setting new configuration (%d -> 1)\n", config); + if (libusb_set_configuration(slsg->usb_handle, 1)) { + /* this may fail for a previous configured device */ + WLOG("libusb_set_configuration() failed\n"); + libusb_close(slsg->usb_handle); + free(sl); + free(slsg); + return NULL; + } + } + + if (libusb_claim_interface(slsg->usb_handle, 0)) { + WLOG("libusb_claim_interface() failed\n"); + libusb_close(slsg->usb_handle); + free(sl); + free(slsg); + return NULL; + } + + // assumption: endpoint config is fixed mang. really. + slsg->ep_rep = 1 /* ep rep */ | LIBUSB_ENDPOINT_IN; + slsg->ep_req = 2 /* ep req */ | LIBUSB_ENDPOINT_OUT; + DLOG("Successfully opened stlinkv1 by libusb :)\n"); sl->verbose = verbose; diff --git a/src/stlink-sg.h b/src/stlink-sg.h index c9776cd..2e27ceb 100644 --- a/src/stlink-sg.h +++ b/src/stlink-sg.h @@ -42,7 +42,9 @@ extern "C" { struct stlink_libsg { libusb_context* libusb_ctx; - libusb_device_handle *handle; + libusb_device_handle *usb_handle; + unsigned ep_rep; + unsigned ep_req; int sg_fd; int do_scsi_pt_err; diff --git a/src/stlink-usb.c b/src/stlink-usb.c index c0b0009..a816769 100644 --- a/src/stlink-usb.c +++ b/src/stlink-usb.c @@ -631,8 +631,8 @@ stlink_t* stlink_open_usb(const int verbose) { r = libusb_detach_kernel_driver(slu->usb_handle, 0); if (r<0) { WLOG("libusb_detach_kernel_driver(() error %s\n", strerror(-r)); + goto on_libusb_error; } - goto on_libusb_error; } if (libusb_get_configuration(slu->usb_handle, &config)) { From f587baa03ac9598130fac7f4ab58bef4030cb8df Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Thu, 3 Nov 2011 21:28:19 +0000 Subject: [PATCH 24/63] Use the libusb based sense and status reading from afaerber Before, I could a single operation (get version) after plugging in, now I can issue two at least :) I suspect there are two problems still. 1, I'm not using tags properly, as the original sg-utils code seemed to skip that. 2) I'm pretty sure I need to be sending variable lengths for the cdb field. --- src/stlink-sg.c | 334 +++++++++++++++++++++++++++++++++--------------- src/stlink-sg.h | 1 + 2 files changed, 234 insertions(+), 101 deletions(-) diff --git a/src/stlink-sg.c b/src/stlink-sg.c index 9d71df1..2c52e2a 100644 --- a/src/stlink-sg.c +++ b/src/stlink-sg.c @@ -70,6 +70,7 @@ #define __USE_GNU +#include #include #include #include @@ -214,14 +215,238 @@ static void stlink_confirm_inq(stlink_t *stl, struct sg_pt_base *ptvp) { } #endif -void stlink_q(stlink_t *sl) { -#if FINISHED_WITH_SG - struct stlink_libsg* sg = sl->backend_data; - DLOG("CDB["); - for (int i = 0; i < CDB_SL; i++) - DLOG(" 0x%02x", (unsigned int) sg->cdb_cmd_blk[i]); - DLOG("]\n"); +static int dump_CDB_command(uint8_t *cdb, uint8_t cdb_len) { + char dbugblah[100]; + char *dbugp = dbugblah; + dbugp += sprintf(dbugp, "Sending CDB ["); + for (uint8_t i = 0; i < cdb_len; i++) { + dbugp += sprintf(dbugp, " %#02x", (unsigned int) cdb[i]); + } + sprintf(dbugp, "]\n"); + DLOG(dbugblah); + return 0; +} +/** + * Wraps a CDB mass storage command in the appropriate gunk to get it down + * @param handle + * @param endpoint + * @param cdb + * @param cdb_length + * @param lun + * @param flags + * @param expected_rx_size + * @return + */ +int send_usb_mass_storage_command(libusb_device_handle *handle, uint8_t endpoint_out, + uint8_t *cdb, uint8_t cdb_length, + uint8_t lun, uint8_t flags, uint32_t expected_rx_size) { + DLOG("Sending usb m-s cmd: cdblen:%d, rxsize=%d\n", cdb_length, expected_rx_size); + dump_CDB_command(cdb, cdb_length); + + int try = 0; + int ret = 0; + int real_transferred; + int i = 0; + + uint8_t c_buf[STLINK_SG_SIZE]; + // tag is allegedly ignored... TODO - verify + uint32_t tag = 1; + c_buf[i++] = 'U'; + c_buf[i++] = 'S'; + c_buf[i++] = 'B'; + c_buf[i++] = 'C'; + write_uint32(&c_buf[i], tag); + write_uint32(&c_buf[i+4], expected_rx_size); + i+= 8; + c_buf[i++] = flags; + c_buf[i++] = lun; + + c_buf[i++] = cdb_length; + + // Now the actual CDB request + assert(cdb_length <= CDB_SL); + memcpy(&(c_buf[i]), cdb, cdb_length); + + int sending_length = STLINK_SG_SIZE; + DLOG("sending length set to: %d\n", sending_length); + + // send.... + do { + DLOG("attempting tx...\n"); + ret = libusb_bulk_transfer(handle, endpoint_out, c_buf, sending_length, + &real_transferred, SG_TIMEOUT_MSEC); + if (ret == LIBUSB_ERROR_PIPE) { + libusb_clear_halt(handle, endpoint_out); + } + try++; + } while ((ret == LIBUSB_ERROR_PIPE) && (try < 3)); + if (ret != LIBUSB_SUCCESS) { + WLOG("sending failed: %d\n", ret); + return -1; + } + DLOG("Actually sent: %d, returning tag: %d\n", real_transferred, tag); + return tag; +} + + +static int get_usb_mass_storage_status(libusb_device_handle *handle, uint8_t endpoint, uint32_t *tag) +{ + unsigned char csw[13]; + memset(csw, 0, sizeof(csw)); + int transferred; + int ret; + int try = 0; + do { + ret = libusb_bulk_transfer(handle, endpoint, (unsigned char *)&csw, sizeof(csw), + &transferred, SG_TIMEOUT_MSEC); + if (ret == LIBUSB_ERROR_PIPE) { + libusb_clear_halt(handle, endpoint); + } + try++; + } while ((ret == LIBUSB_ERROR_PIPE) && (try < 3)); + if (ret != LIBUSB_SUCCESS) { + fprintf(stderr, "%s: receiving failed: %d\n", __func__, ret); + return -1; + } + if (transferred != sizeof(csw)) { + fprintf(stderr, "%s: received unexpected amount: %d\n", __func__, transferred); + return -1; + } + + uint32_t rsig = read_uint32(csw, 0); + uint32_t rtag = read_uint32(csw, 4); + uint32_t residue = read_uint32(csw, 8); +#define USB_CSW_SIGNATURE 0x53425355 // 'U' 'S' 'B' 'S' (reversed) + if (rsig != USB_CSW_SIGNATURE) { + WLOG("status signature was invalid: %#x\n", rsig); + return -1; + } + DLOG("residue was= %#x\n", residue); + *tag = rtag; + uint8_t rstatus = csw[12]; + DLOG("rstatus = %x\n", rstatus); + return rstatus; +} + +/** + * Straight from stm8 stlink code... + * @param handle + * @param endpoint_in + * @param endpoint_out + */ +static void +get_sense(libusb_device_handle *handle, uint8_t endpoint_in, uint8_t endpoint_out) +{ + uint8_t cdb[16]; + memset(cdb, 0, sizeof(cdb)); +#define REQUEST_SENSE 0x03 +#define REQUEST_SENSE_LENGTH 18 + cdb[0] = REQUEST_SENSE; + cdb[4] = REQUEST_SENSE_LENGTH; + uint32_t tag = send_usb_mass_storage_command(handle, endpoint_out, cdb, sizeof(cdb), 0, + LIBUSB_ENDPOINT_IN, REQUEST_SENSE_LENGTH); + if (tag == 0) { + WLOG("refusing to send request sense with tag 0\n"); + return; + } + unsigned char sense[REQUEST_SENSE_LENGTH]; + int transferred; + int ret; + int try = 0; + do { + ret = libusb_bulk_transfer(handle, endpoint_in, sense, sizeof(sense), + &transferred, SG_TIMEOUT_MSEC); + if (ret == LIBUSB_ERROR_PIPE) { + libusb_clear_halt(handle, endpoint_in); + } + try++; + } while ((ret == LIBUSB_ERROR_PIPE) && (try < 3)); + if (ret != LIBUSB_SUCCESS) { + WLOG("receiving sense failed: %d\n", ret); + return; + } + if (transferred != sizeof(sense)) { + WLOG("received unexpected amount of sense: %d != %d\n", transferred, sizeof(sense)); + } + uint32_t received_tag; + int status = get_usb_mass_storage_status(handle, endpoint_in, &received_tag); + if (status != 0) { + WLOG("receiving sense failed with status: %02x\n", status); + return; + } + if (sense[0] != 0x70 && sense[0] != 0x71) { + WLOG("No sense data\n"); + } else { + WLOG("Sense KCQ: %02X %02X %02X\n", sense[2] & 0x0f, sense[12], sense[13]); + } +} + +int stlink_q(stlink_t *sl) { + struct stlink_libsg* sg = sl->backend_data; + //uint8_t cdb_len = 6; // FIXME varies!!! + uint8_t cdb_len = 10; // FIXME varies!!! + uint8_t lun = 0; // always zero... + send_usb_mass_storage_command(sg->usb_handle, sg->ep_req, sg->cdb_cmd_blk, cdb_len, lun, LIBUSB_ENDPOINT_IN, sl->q_len); + + + // now wait for our response... + // length copied from stlink-usb... + int rx_length = sl->q_len; + int try = 0; + int real_transferred; + int ret; + do { + DLOG("attempting rx\n"); + ret = libusb_bulk_transfer(sg->usb_handle, sg->ep_rep, sl->q_buf, rx_length, + &real_transferred, SG_TIMEOUT_MSEC); + if (ret == LIBUSB_ERROR_PIPE) { + libusb_clear_halt(sg->usb_handle, sg->ep_req); + } + try++; + } while ((ret == LIBUSB_ERROR_PIPE) && (try < 3)); + + if (ret != LIBUSB_SUCCESS) { + WLOG("Receiving failed: %d\n", ret); + return -1; + } + + if (real_transferred != rx_length) { + WLOG("received unexpected amount: %d != %d\n", real_transferred, rx_length); + } + + +// stm8 stuff... + + + uint32_t received_tag; + // -ve is for my errors, 0 is good, +ve is libusb sense status bytes + int status = get_usb_mass_storage_status(sg->usb_handle, sg->ep_rep, &received_tag); + if (status < 0) { + WLOG("receiving status failed: %d\n", status); + return -1; + } + if (status != 0) { + WLOG("receiving status not passed :(: %02x\n", status); + } + if (status == 1) { + get_sense(sg->usb_handle, sg->ep_rep, sg->ep_req); + return -1; + } + uint32_t tag = 1; + if (received_tag != tag) { + WLOG("received tag %d but expected %d\n", received_tag, tag); + //return -1; + } + if (rx_length > 0 && real_transferred != rx_length) { + return -1; + } + return 0; + + + DLOG("Actually received: %d\n", real_transferred); + +#if FINISHED_WITH_SG // Get control command descriptor of scsi structure, // (one object per command!!) struct sg_pt_base *ptvp = construct_scsi_pt_obj(); @@ -281,102 +506,9 @@ void _stlink_sg_version(stlink_t *stl) { sl->cdb_cmd_blk[0] = STLINK_GET_VERSION; stl->q_len = 6; sl->q_addr = 0; -// stlink_q(stl); + stlink_q(stl); // HACK use my own private version right now... - int try = 0; - int ret = 0; - int real_transferred; - -/* - uint32_t dCBWSignature; - uint32_t dCBWTag; - uint32_t dCBWDataTransferLength; - uint8_t bmCBWFlags; - uint8_t bCBWLUN; - uint8_t bCBWCBLength; - uint8_t CBWCB[16]; - */ - -#if using_old_code_examples - /* - * and from old code? - cmd[i++] = 'U'; - cmd[i++] = 'S'; - cmd[i++] = 'B'; - cmd[i++] = 'C'; - write_uint32(&cmd[i], sg->sg_transfer_idx); - write_uint32(&cmd[i + 4], len); - i += 8; - cmd[i++] = (dir == SG_DXFER_FROM_DEV)?0x80:0; - cmd[i++] = 0; /* Logical unit */ - cmd[i++] = 0xa; /* Command length */ - */ -#endif - - int i = 0; - stl->c_buf[i++] = 'U'; - stl->c_buf[i++] = 'S'; - stl->c_buf[i++] = 'B'; - stl->c_buf[i++] = 'C'; - // tag is allegedly ignored... TODO - verify - write_uint32(&stl->c_buf[i], 1); - // TODO - Does this even matter? verify with more commands.... - uint32_t command_length = STLINK_CMD_SIZE; - write_uint32(&stl->c_buf[i+4], command_length); - i+= 8; - stl->c_buf[i++] = LIBUSB_ENDPOINT_IN; - // assumption: lun is always 0; - stl->c_buf[i++] = 0; - - stl->c_buf[i++] = sizeof(sl->cdb_cmd_blk); - - // duh, now the actual data... - memcpy(&(stl->c_buf[i]), sl->cdb_cmd_blk, sizeof(sl->cdb_cmd_blk)); - - int sending_length = STLINK_SG_SIZE; - DLOG("sending length set to: %d\n", sending_length); - - // send.... - do { - DLOG("attempting tx...\n"); - ret = libusb_bulk_transfer(sl->usb_handle, sl->ep_req, stl->c_buf, sending_length, - &real_transferred, 3 * 1000); - if (ret == LIBUSB_ERROR_PIPE) { - libusb_clear_halt(sl->usb_handle, sl->ep_req); - } - try++; - } while ((ret == LIBUSB_ERROR_PIPE) && (try < 3)); - if (ret != LIBUSB_SUCCESS) { - WLOG("sending failed: %d\n", ret); - return; - } - DLOG("Actually sent: %d\n", real_transferred); - - // now wait for our response... - // length copied from stlink-usb... - int rx_length = 6; - try = 0; - do { - DLOG("attempting rx\n"); - ret = libusb_bulk_transfer(sl->usb_handle, sl->ep_rep, stl->q_buf, rx_length, - &real_transferred, 3 * 1000); - if (ret == LIBUSB_ERROR_PIPE) { - libusb_clear_halt(sl->usb_handle, sl->ep_req); - } - try++; - } while ((ret == LIBUSB_ERROR_PIPE) && (try < 3)); - - if (ret != LIBUSB_SUCCESS) { - WLOG("Receiving failed: %d\n", ret); - return; - } - - if (real_transferred != rx_length) { - WLOG("received unexpected amount: %d != %d\n", real_transferred, rx_length); - } - - DLOG("Actually received: %d\n", real_transferred); } // Get stlink mode: diff --git a/src/stlink-sg.h b/src/stlink-sg.h index 2e27ceb..8485d3d 100644 --- a/src/stlink-sg.h +++ b/src/stlink-sg.h @@ -19,6 +19,7 @@ extern "C" { #define RDWR 0 #define RO 1 #define SG_TIMEOUT_SEC 1 // actually 1 is about 2 sec +#define SG_TIMEOUT_MSEC 3 * 1000 // Each CDB can be a total of 6, 10, 12, or 16 bytes, later version // of the SCSI standard also allow for variable-length CDBs (min. CDB is 6). // the stlink needs max. 10 bytes. From 22d0777df9f4987bd60ddf6bba5ef64ac0628d8a Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Thu, 3 Nov 2011 23:16:30 +0000 Subject: [PATCH 25/63] Properly use tags. Doesn't help though. --- src/stlink-sg.c | 35 +++++++++++++++++++++++------------ 1 file changed, 23 insertions(+), 12 deletions(-) diff --git a/src/stlink-sg.c b/src/stlink-sg.c index 2c52e2a..8cf6693 100644 --- a/src/stlink-sg.c +++ b/src/stlink-sg.c @@ -244,6 +244,11 @@ int send_usb_mass_storage_command(libusb_device_handle *handle, uint8_t endpoint DLOG("Sending usb m-s cmd: cdblen:%d, rxsize=%d\n", cdb_length, expected_rx_size); dump_CDB_command(cdb, cdb_length); + static uint32_t tag; + if (tag == 0) { + tag = 1; + } + int try = 0; int ret = 0; int real_transferred; @@ -251,12 +256,12 @@ int send_usb_mass_storage_command(libusb_device_handle *handle, uint8_t endpoint uint8_t c_buf[STLINK_SG_SIZE]; // tag is allegedly ignored... TODO - verify - uint32_t tag = 1; c_buf[i++] = 'U'; c_buf[i++] = 'S'; c_buf[i++] = 'B'; c_buf[i++] = 'C'; write_uint32(&c_buf[i], tag); + uint32_t this_tag = tag++; write_uint32(&c_buf[i+4], expected_rx_size); i+= 8; c_buf[i++] = flags; @@ -286,7 +291,7 @@ int send_usb_mass_storage_command(libusb_device_handle *handle, uint8_t endpoint return -1; } DLOG("Actually sent: %d, returning tag: %d\n", real_transferred, tag); - return tag; + return this_tag; } @@ -338,6 +343,7 @@ static int get_usb_mass_storage_status(libusb_device_handle *handle, uint8_t end static void get_sense(libusb_device_handle *handle, uint8_t endpoint_in, uint8_t endpoint_out) { + DLOG("Fetching sense...\n"); uint8_t cdb[16]; memset(cdb, 0, sizeof(cdb)); #define REQUEST_SENSE 0x03 @@ -382,12 +388,18 @@ get_sense(libusb_device_handle *handle, uint8_t endpoint_in, uint8_t endpoint_ou } } +int stlink_q2(stlink_t *sl, uint8_t cdb_len); int stlink_q(stlink_t *sl) { + return stlink_q2(sl, 10); +} + +int stlink_q2(stlink_t *sl, uint8_t cdb_len) { struct stlink_libsg* sg = sl->backend_data; //uint8_t cdb_len = 6; // FIXME varies!!! - uint8_t cdb_len = 10; // FIXME varies!!! + //uint8_t cdb_len = 10; // FIXME varies!!! uint8_t lun = 0; // always zero... - send_usb_mass_storage_command(sg->usb_handle, sg->ep_req, sg->cdb_cmd_blk, cdb_len, lun, LIBUSB_ENDPOINT_IN, sl->q_len); + uint32_t tag = send_usb_mass_storage_command(sg->usb_handle, sg->ep_req, + sg->cdb_cmd_blk, cdb_len, lun, LIBUSB_ENDPOINT_IN, sl->q_len); // now wait for our response... @@ -414,11 +426,7 @@ int stlink_q(stlink_t *sl) { if (real_transferred != rx_length) { WLOG("received unexpected amount: %d != %d\n", real_transferred, rx_length); } - - -// stm8 stuff... - - + uint32_t received_tag; // -ve is for my errors, 0 is good, +ve is libusb sense status bytes int status = get_usb_mass_storage_status(sg->usb_handle, sg->ep_rep, &received_tag); @@ -433,7 +441,6 @@ int stlink_q(stlink_t *sl) { get_sense(sg->usb_handle, sg->ep_rep, sg->ep_req); return -1; } - uint32_t tag = 1; if (received_tag != tag) { WLOG("received tag %d but expected %d\n", received_tag, tag); //return -1; @@ -1093,7 +1100,7 @@ stlink_t* stlink_v1_open(const char *dev_name, const int verbose) { return NULL; } - DLOG("\n*** stlink_force_open ***\n"); + DLOG("Reading current mode...\n"); switch (stlink_current_mode(sl)) { case STLINK_DEV_MASS_MODE: return sl; @@ -1101,8 +1108,11 @@ stlink_t* stlink_v1_open(const char *dev_name, const int verbose) { // TODO go to mass? return sl; } - DLOG("\n*** switch the stlink to mass mode ***\n"); + + DLOG("Attempting to exit DFU mode\n"); _stlink_sg_exit_dfu_mode(sl); + +#if 0 // exit the dfu mode -> the device is gone DLOG("\n*** reopen the stlink device ***\n"); delay(1000); @@ -1116,6 +1126,7 @@ stlink_t* stlink_v1_open(const char *dev_name, const int verbose) { } // re-query device info stlink_version(sl); +#endif return sl; } From 87490393e86fffb812c12e871e31f970324fd677 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Thu, 3 Nov 2011 23:24:28 +0000 Subject: [PATCH 26/63] Duh, don't try and do a bulk read when we requested 0 bytes back. --- src/stlink-sg.c | 44 ++++++++++++++++++++------------------------ 1 file changed, 20 insertions(+), 24 deletions(-) diff --git a/src/stlink-sg.c b/src/stlink-sg.c index 8cf6693..2253212 100644 --- a/src/stlink-sg.c +++ b/src/stlink-sg.c @@ -388,15 +388,10 @@ get_sense(libusb_device_handle *handle, uint8_t endpoint_in, uint8_t endpoint_ou } } -int stlink_q2(stlink_t *sl, uint8_t cdb_len); int stlink_q(stlink_t *sl) { - return stlink_q2(sl, 10); -} - -int stlink_q2(stlink_t *sl, uint8_t cdb_len) { struct stlink_libsg* sg = sl->backend_data; //uint8_t cdb_len = 6; // FIXME varies!!! - //uint8_t cdb_len = 10; // FIXME varies!!! + uint8_t cdb_len = 10; // FIXME varies!!! uint8_t lun = 0; // always zero... uint32_t tag = send_usb_mass_storage_command(sg->usb_handle, sg->ep_req, sg->cdb_cmd_blk, cdb_len, lun, LIBUSB_ENDPOINT_IN, sl->q_len); @@ -408,23 +403,25 @@ int stlink_q2(stlink_t *sl, uint8_t cdb_len) { int try = 0; int real_transferred; int ret; - do { - DLOG("attempting rx\n"); - ret = libusb_bulk_transfer(sg->usb_handle, sg->ep_rep, sl->q_buf, rx_length, - &real_transferred, SG_TIMEOUT_MSEC); - if (ret == LIBUSB_ERROR_PIPE) { - libusb_clear_halt(sg->usb_handle, sg->ep_req); - } - try++; - } while ((ret == LIBUSB_ERROR_PIPE) && (try < 3)); + if (rx_length > 0) { + do { + DLOG("attempting rx\n"); + ret = libusb_bulk_transfer(sg->usb_handle, sg->ep_rep, sl->q_buf, rx_length, + &real_transferred, SG_TIMEOUT_MSEC); + if (ret == LIBUSB_ERROR_PIPE) { + libusb_clear_halt(sg->usb_handle, sg->ep_req); + } + try++; + } while ((ret == LIBUSB_ERROR_PIPE) && (try < 3)); - if (ret != LIBUSB_SUCCESS) { - WLOG("Receiving failed: %d\n", ret); - return -1; - } - - if (real_transferred != rx_length) { - WLOG("received unexpected amount: %d != %d\n", real_transferred, rx_length); + if (ret != LIBUSB_SUCCESS) { + WLOG("Receiving failed: %d\n", ret); + return -1; + } + + if (real_transferred != rx_length) { + WLOG("received unexpected amount: %d != %d\n", real_transferred, rx_length); + } } uint32_t received_tag; @@ -1112,13 +1109,13 @@ stlink_t* stlink_v1_open(const char *dev_name, const int verbose) { DLOG("Attempting to exit DFU mode\n"); _stlink_sg_exit_dfu_mode(sl); -#if 0 // exit the dfu mode -> the device is gone DLOG("\n*** reopen the stlink device ***\n"); delay(1000); stlink_close(sl); delay(5000); + DLOG("Attempting to reopen the stlink...\n"); sl = stlink_open(dev_name, verbose); if (sl == NULL) { fputs("Error: could not open stlink device\n", stderr); @@ -1126,7 +1123,6 @@ stlink_t* stlink_v1_open(const char *dev_name, const int verbose) { } // re-query device info stlink_version(sl); -#endif return sl; } From 0f376a74a51cf3e3134b0e6f2ad0415f43968ed1 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Thu, 3 Nov 2011 23:40:27 +0000 Subject: [PATCH 27/63] Remove device names, we now just find it via USB ids. In the future, we might actually want device names back again, if you have multiple stlink's connected. But that would be a new device name, not scanning for /dev/sgX looking for scsi devices. --- gdbserver/gdb-server.c | 38 ++------------------------------------ src/stlink-sg.c | 18 ++++++------------ src/stlink-sg.h | 3 ++- src/test_sg.c | 21 +++++++-------------- 4 files changed, 17 insertions(+), 63 deletions(-) diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index 65297bc..df3657a 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -197,42 +197,8 @@ int main(int argc, char** argv) { if(sl == NULL) return 1; break; case 1: - if (strlen(state.devicename) == 0) { - const int DevNumMax = 99; - int ExistDevCount = 0; - - for (int DevNum = 0; DevNum <= DevNumMax; DevNum++) { - if (DevNum < 10) { - char DevName[] = "/dev/sgX"; - const int X_index = 7; - DevName[X_index] = DevNum + '0'; - if (!access(DevName, F_OK)) { - sl = stlink_v1_open(DevName, 0); - ExistDevCount++; - } - } else if (DevNum < 100) { - char DevName[] = "/dev/sgXY"; - const int X_index = 7; - const int Y_index = 8; - DevName[X_index] = DevNum / 10 + '0'; - DevName[Y_index] = DevNum % 10 + '0'; - if (!access(DevName, F_OK)) { - sl = stlink_v1_open(DevName, 0); - ExistDevCount++; - } - } - if (sl != NULL) break; - } - - if (sl == NULL) { - fprintf(stdout, "\nNumber of /dev/sgX devices found: %i \n", - ExistDevCount); - fprintf(stderr, "ST-LINK not found\n"); - return 1; - } - } else { - sl = stlink_v1_open(state.devicename, state.logging_level); - } + sl = stlink_v1_open(NULL, state.logging_level); + if(sl == NULL) return 1; break; } diff --git a/src/stlink-sg.c b/src/stlink-sg.c index 2253212..64f1820 100644 --- a/src/stlink-sg.c +++ b/src/stlink-sg.c @@ -967,8 +967,7 @@ stlink_backend_t _stlink_sg_backend = { _stlink_sg_force_debug }; -static stlink_t* stlink_open(const char *dev_name, const int verbose) { - DLOG("*** stlink_open [%s] ***\n", dev_name); +static stlink_t* stlink_open(const int verbose) { stlink_t *sl = malloc(sizeof (stlink_t)); struct stlink_libsg *slsg = malloc(sizeof (struct stlink_libsg)); @@ -1076,24 +1075,19 @@ static stlink_t* stlink_open(const char *dev_name, const int verbose) { -stlink_t* stlink_v1_open(const char *dev_name, const int verbose) { +stlink_t* stlink_v1_open(const int verbose) { ugly_init(verbose); - stlink_t *sl = stlink_open(dev_name, verbose); + stlink_t *sl = stlink_open(verbose); if (sl == NULL) { fputs("Error: could not open stlink device\n", stderr); return NULL; } stlink_version(sl); - struct stlink_libsg *sg = sl->backend_data; if ((sl->version.st_vid != USB_ST_VID) || (sl->version.stlink_pid != USB_STLINK_PID)) { - fprintf(stderr, "Error: the device %s is not a stlink\n", - dev_name); - fprintf(stderr, " VID: got %04x expect %04x \n", - sl->version.st_vid, USB_ST_VID); - fprintf(stderr, " PID: got %04x expect %04x \n", - sl->version.stlink_pid, USB_STLINK_PID); + ugly_log(UERROR, LOG_TAG, + "WTF? successfully opened, but unable to read version details. BROKEN!\n"); return NULL; } @@ -1116,7 +1110,7 @@ stlink_t* stlink_v1_open(const char *dev_name, const int verbose) { delay(5000); DLOG("Attempting to reopen the stlink...\n"); - sl = stlink_open(dev_name, verbose); + sl = stlink_open(verbose); if (sl == NULL) { fputs("Error: could not open stlink device\n", stderr); return NULL; diff --git a/src/stlink-sg.h b/src/stlink-sg.h index 8485d3d..d4d7723 100644 --- a/src/stlink-sg.h +++ b/src/stlink-sg.h @@ -57,12 +57,13 @@ extern "C" { uint32_t q_addr; // Sense (error information) data + // obsolete, this was fed to the scsi tools unsigned char sense_buf[SENSE_BUF_LEN]; reg reg; }; - stlink_t* stlink_v1_open(const char *dev_name, const int verbose); + stlink_t* stlink_v1_open(const int verbose); #ifdef __cplusplus } diff --git a/src/test_sg.c b/src/test_sg.c index 742ba44..a8a7022 100644 --- a/src/test_sg.c +++ b/src/test_sg.c @@ -10,33 +10,26 @@ int main(int argc, char *argv[]) { // set scpi lib debug level: 0 for no debug info, 10 for lots - char *dev_name; switch (argc) { case 1: fputs( - "\nUsage: stlink-access-test /dev/sg0, sg1, ...\n" + "\nUsage: stlink-access-test [anything at all] ...\n" "\n*** Notice: The stlink firmware violates the USB standard.\n" - "*** If you plug-in the discovery's stlink, wait a several\n" - "*** minutes to let the kernel driver swallow the broken device.\n" - "*** Watch:\ntail -f /var/log/messages\n" - "*** This command sequence can shorten the waiting time and fix some issues.\n" + "*** Because we just use libusb, we can just tell the kernel's\n" + "*** driver to simply ignore the device...\n" "*** Unplug the stlink and execute once as root:\n" - "modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:lrwsro\n\n", + "modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i\n\n", stderr); return EXIT_FAILURE; - case 2: - dev_name = argv[1]; - break; default: - fprintf(stderr, "bzzt\n"); - return EXIT_FAILURE; + break; } - stlink_t *sl = stlink_v1_open(dev_name, 99); + stlink_t *sl = stlink_v1_open(99); if (sl == NULL) return EXIT_FAILURE; - + // we are in mass mode, go to swd stlink_enter_swd_mode(sl); stlink_current_mode(sl); From 8febc74cf1aeacdd57adff1eb85ea55f096ccaec Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Fri, 4 Nov 2011 00:44:18 +0000 Subject: [PATCH 28/63] Fix write_mem32. Moved some of the static methods up to the top, so they can always be used, so the changes is messier than it needs to be. --- src/stlink-sg.c | 397 +++++++++++++++++++++++++----------------------- src/test_sg.c | 41 +++-- 2 files changed, 243 insertions(+), 195 deletions(-) diff --git a/src/stlink-sg.c b/src/stlink-sg.c index 64f1820..276986e 100644 --- a/src/stlink-sg.c +++ b/src/stlink-sg.c @@ -107,15 +107,6 @@ static void clear_cdb(struct stlink_libsg *sl) { sl->q_data_dir = Q_DATA_IN; } -// E.g. make the valgrind happy. - -static void clear_buf(stlink_t *sl) { - DLOG("*** clear_buf ***\n"); - for (size_t i = 0; i < sizeof (sl->q_buf); i++) - sl->q_buf[i] = 0; - -} - // close the device, free the allocated memory void _stlink_sg_close(stlink_t *sl) { @@ -128,6 +119,179 @@ void _stlink_sg_close(stlink_t *sl) { } } +static int get_usb_mass_storage_status(libusb_device_handle *handle, uint8_t endpoint, uint32_t *tag) +{ + unsigned char csw[13]; + memset(csw, 0, sizeof(csw)); + int transferred; + int ret; + int try = 0; + do { + ret = libusb_bulk_transfer(handle, endpoint, (unsigned char *)&csw, sizeof(csw), + &transferred, SG_TIMEOUT_MSEC); + if (ret == LIBUSB_ERROR_PIPE) { + libusb_clear_halt(handle, endpoint); + } + try++; + } while ((ret == LIBUSB_ERROR_PIPE) && (try < 3)); + if (ret != LIBUSB_SUCCESS) { + fprintf(stderr, "%s: receiving failed: %d\n", __func__, ret); + return -1; + } + if (transferred != sizeof(csw)) { + fprintf(stderr, "%s: received unexpected amount: %d\n", __func__, transferred); + return -1; + } + + uint32_t rsig = read_uint32(csw, 0); + uint32_t rtag = read_uint32(csw, 4); + uint32_t residue = read_uint32(csw, 8); +#define USB_CSW_SIGNATURE 0x53425355 // 'U' 'S' 'B' 'S' (reversed) + if (rsig != USB_CSW_SIGNATURE) { + WLOG("status signature was invalid: %#x\n", rsig); + return -1; + } + DLOG("residue was= %#x\n", residue); + *tag = rtag; + uint8_t rstatus = csw[12]; + DLOG("rstatus = %x\n", rstatus); + return rstatus; +} + +static int dump_CDB_command(uint8_t *cdb, uint8_t cdb_len) { + char dbugblah[100]; + char *dbugp = dbugblah; + dbugp += sprintf(dbugp, "Sending CDB ["); + for (uint8_t i = 0; i < cdb_len; i++) { + dbugp += sprintf(dbugp, " %#02x", (unsigned int) cdb[i]); + } + sprintf(dbugp, "]\n"); + DLOG(dbugblah); + return 0; +} + +/** + * Wraps a CDB mass storage command in the appropriate gunk to get it down + * @param handle + * @param endpoint + * @param cdb + * @param cdb_length + * @param lun + * @param flags + * @param expected_rx_size + * @return + */ +int send_usb_mass_storage_command(libusb_device_handle *handle, uint8_t endpoint_out, + uint8_t *cdb, uint8_t cdb_length, + uint8_t lun, uint8_t flags, uint32_t expected_rx_size) { + DLOG("Sending usb m-s cmd: cdblen:%d, rxsize=%d\n", cdb_length, expected_rx_size); + dump_CDB_command(cdb, cdb_length); + + static uint32_t tag; + if (tag == 0) { + tag = 1; + } + + int try = 0; + int ret = 0; + int real_transferred; + int i = 0; + + uint8_t c_buf[STLINK_SG_SIZE]; + // tag is allegedly ignored... TODO - verify + c_buf[i++] = 'U'; + c_buf[i++] = 'S'; + c_buf[i++] = 'B'; + c_buf[i++] = 'C'; + write_uint32(&c_buf[i], tag); + uint32_t this_tag = tag++; + write_uint32(&c_buf[i+4], expected_rx_size); + i+= 8; + c_buf[i++] = flags; + c_buf[i++] = lun; + + c_buf[i++] = cdb_length; + + // Now the actual CDB request + assert(cdb_length <= CDB_SL); + memcpy(&(c_buf[i]), cdb, cdb_length); + + int sending_length = STLINK_SG_SIZE; + DLOG("sending length set to: %d\n", sending_length); + + // send.... + do { + DLOG("attempting tx...\n"); + ret = libusb_bulk_transfer(handle, endpoint_out, c_buf, sending_length, + &real_transferred, SG_TIMEOUT_MSEC); + if (ret == LIBUSB_ERROR_PIPE) { + libusb_clear_halt(handle, endpoint_out); + } + try++; + } while ((ret == LIBUSB_ERROR_PIPE) && (try < 3)); + if (ret != LIBUSB_SUCCESS) { + WLOG("sending failed: %d\n", ret); + return -1; + } + DLOG("Actually sent: %d, returning tag: %d\n", real_transferred, tag); + return this_tag; +} + + +/** + * Straight from stm8 stlink code... + * @param handle + * @param endpoint_in + * @param endpoint_out + */ +static void +get_sense(libusb_device_handle *handle, uint8_t endpoint_in, uint8_t endpoint_out) +{ + DLOG("Fetching sense...\n"); + uint8_t cdb[16]; + memset(cdb, 0, sizeof(cdb)); +#define REQUEST_SENSE 0x03 +#define REQUEST_SENSE_LENGTH 18 + cdb[0] = REQUEST_SENSE; + cdb[4] = REQUEST_SENSE_LENGTH; + uint32_t tag = send_usb_mass_storage_command(handle, endpoint_out, cdb, sizeof(cdb), 0, + LIBUSB_ENDPOINT_IN, REQUEST_SENSE_LENGTH); + if (tag == 0) { + WLOG("refusing to send request sense with tag 0\n"); + return; + } + unsigned char sense[REQUEST_SENSE_LENGTH]; + int transferred; + int ret; + int try = 0; + do { + ret = libusb_bulk_transfer(handle, endpoint_in, sense, sizeof(sense), + &transferred, SG_TIMEOUT_MSEC); + if (ret == LIBUSB_ERROR_PIPE) { + libusb_clear_halt(handle, endpoint_in); + } + try++; + } while ((ret == LIBUSB_ERROR_PIPE) && (try < 3)); + if (ret != LIBUSB_SUCCESS) { + WLOG("receiving sense failed: %d\n", ret); + return; + } + if (transferred != sizeof(sense)) { + WLOG("received unexpected amount of sense: %d != %d\n", transferred, sizeof(sense)); + } + uint32_t received_tag; + int status = get_usb_mass_storage_status(handle, endpoint_in, &received_tag); + if (status != 0) { + WLOG("receiving sense failed with status: %02x\n", status); + return; + } + if (sense[0] != 0x70 && sense[0] != 0x71) { + WLOG("No sense data\n"); + } else { + WLOG("Sense KCQ: %02X %02X %02X\n", sense[2] & 0x0f, sense[12], sense[13]); + } +} + //TODO rewrite/cleanup, save the error in sl @@ -215,71 +379,24 @@ static void stlink_confirm_inq(stlink_t *stl, struct sg_pt_base *ptvp) { } #endif -static int dump_CDB_command(uint8_t *cdb, uint8_t cdb_len) { - char dbugblah[100]; - char *dbugp = dbugblah; - dbugp += sprintf(dbugp, "Sending CDB ["); - for (uint8_t i = 0; i < cdb_len; i++) { - dbugp += sprintf(dbugp, " %#02x", (unsigned int) cdb[i]); - } - sprintf(dbugp, "]\n"); - DLOG(dbugblah); - return 0; -} - /** - * Wraps a CDB mass storage command in the appropriate gunk to get it down - * @param handle - * @param endpoint - * @param cdb - * @param cdb_length - * @param lun - * @param flags - * @param expected_rx_size - * @return + * Just send a buffer on an endpoint, no questions asked. + * Handles repeats, and time outs. Also handles reading status reports and sense + * @param handle libusb device * + * @param endpoint_out sends + * @param endpoint_in used to read status reports back in + * @param cbuf what to send + * @param length how much to send + * @return number of bytes actually sent, or -1 for failures. */ -int send_usb_mass_storage_command(libusb_device_handle *handle, uint8_t endpoint_out, - uint8_t *cdb, uint8_t cdb_length, - uint8_t lun, uint8_t flags, uint32_t expected_rx_size) { - DLOG("Sending usb m-s cmd: cdblen:%d, rxsize=%d\n", cdb_length, expected_rx_size); - dump_CDB_command(cdb, cdb_length); - - static uint32_t tag; - if (tag == 0) { - tag = 1; - } - - int try = 0; - int ret = 0; +int send_usb_data_only(libusb_device_handle *handle, unsigned char endpoint_out, + unsigned char endpoint_in, unsigned char *cbuf, unsigned int length) { + int ret; int real_transferred; - int i = 0; - - uint8_t c_buf[STLINK_SG_SIZE]; - // tag is allegedly ignored... TODO - verify - c_buf[i++] = 'U'; - c_buf[i++] = 'S'; - c_buf[i++] = 'B'; - c_buf[i++] = 'C'; - write_uint32(&c_buf[i], tag); - uint32_t this_tag = tag++; - write_uint32(&c_buf[i+4], expected_rx_size); - i+= 8; - c_buf[i++] = flags; - c_buf[i++] = lun; - - c_buf[i++] = cdb_length; - - // Now the actual CDB request - assert(cdb_length <= CDB_SL); - memcpy(&(c_buf[i]), cdb, cdb_length); - - int sending_length = STLINK_SG_SIZE; - DLOG("sending length set to: %d\n", sending_length); - - // send.... + int try; do { DLOG("attempting tx...\n"); - ret = libusb_bulk_transfer(handle, endpoint_out, c_buf, sending_length, + ret = libusb_bulk_transfer(handle, endpoint_out, cbuf, length, &real_transferred, SG_TIMEOUT_MSEC); if (ret == LIBUSB_ERROR_PIPE) { libusb_clear_halt(handle, endpoint_out); @@ -290,104 +407,28 @@ int send_usb_mass_storage_command(libusb_device_handle *handle, uint8_t endpoint WLOG("sending failed: %d\n", ret); return -1; } - DLOG("Actually sent: %d, returning tag: %d\n", real_transferred, tag); - return this_tag; -} - - -static int get_usb_mass_storage_status(libusb_device_handle *handle, uint8_t endpoint, uint32_t *tag) -{ - unsigned char csw[13]; - memset(csw, 0, sizeof(csw)); - int transferred; - int ret; - int try = 0; - do { - ret = libusb_bulk_transfer(handle, endpoint, (unsigned char *)&csw, sizeof(csw), - &transferred, SG_TIMEOUT_MSEC); - if (ret == LIBUSB_ERROR_PIPE) { - libusb_clear_halt(handle, endpoint); - } - try++; - } while ((ret == LIBUSB_ERROR_PIPE) && (try < 3)); - if (ret != LIBUSB_SUCCESS) { - fprintf(stderr, "%s: receiving failed: %d\n", __func__, ret); - return -1; - } - if (transferred != sizeof(csw)) { - fprintf(stderr, "%s: received unexpected amount: %d\n", __func__, transferred); - return -1; - } - - uint32_t rsig = read_uint32(csw, 0); - uint32_t rtag = read_uint32(csw, 4); - uint32_t residue = read_uint32(csw, 8); -#define USB_CSW_SIGNATURE 0x53425355 // 'U' 'S' 'B' 'S' (reversed) - if (rsig != USB_CSW_SIGNATURE) { - WLOG("status signature was invalid: %#x\n", rsig); - return -1; - } - DLOG("residue was= %#x\n", residue); - *tag = rtag; - uint8_t rstatus = csw[12]; - DLOG("rstatus = %x\n", rstatus); - return rstatus; -} - -/** - * Straight from stm8 stlink code... - * @param handle - * @param endpoint_in - * @param endpoint_out - */ -static void -get_sense(libusb_device_handle *handle, uint8_t endpoint_in, uint8_t endpoint_out) -{ - DLOG("Fetching sense...\n"); - uint8_t cdb[16]; - memset(cdb, 0, sizeof(cdb)); -#define REQUEST_SENSE 0x03 -#define REQUEST_SENSE_LENGTH 18 - cdb[0] = REQUEST_SENSE; - cdb[4] = REQUEST_SENSE_LENGTH; - uint32_t tag = send_usb_mass_storage_command(handle, endpoint_out, cdb, sizeof(cdb), 0, - LIBUSB_ENDPOINT_IN, REQUEST_SENSE_LENGTH); - if (tag == 0) { - WLOG("refusing to send request sense with tag 0\n"); - return; - } - unsigned char sense[REQUEST_SENSE_LENGTH]; - int transferred; - int ret; - int try = 0; - do { - ret = libusb_bulk_transfer(handle, endpoint_in, sense, sizeof(sense), - &transferred, SG_TIMEOUT_MSEC); - if (ret == LIBUSB_ERROR_PIPE) { - libusb_clear_halt(handle, endpoint_in); - } - try++; - } while ((ret == LIBUSB_ERROR_PIPE) && (try < 3)); - if (ret != LIBUSB_SUCCESS) { - WLOG("receiving sense failed: %d\n", ret); - return; - } - if (transferred != sizeof(sense)) { - WLOG("received unexpected amount of sense: %d != %d\n", transferred, sizeof(sense)); - } + DLOG("Actually sent: %d\n", real_transferred); + + // now, swallow up the status, so that things behave nicely... uint32_t received_tag; + // -ve is for my errors, 0 is good, +ve is libusb sense status bytes int status = get_usb_mass_storage_status(handle, endpoint_in, &received_tag); + if (status < 0) { + WLOG("receiving status failed: %d\n", status); + return -1; + } if (status != 0) { - WLOG("receiving sense failed with status: %02x\n", status); - return; + WLOG("receiving status not passed :(: %02x\n", status); } - if (sense[0] != 0x70 && sense[0] != 0x71) { - WLOG("No sense data\n"); - } else { - WLOG("Sense KCQ: %02X %02X %02X\n", sense[2] & 0x0f, sense[12], sense[13]); + if (status == 1) { + get_sense(handle, endpoint_in, endpoint_out); + return -1; } + + return real_transferred; } + int stlink_q(stlink_t *sl) { struct stlink_libsg* sg = sl->backend_data; //uint8_t cdb_len = 6; // FIXME varies!!! @@ -865,11 +906,10 @@ void _stlink_sg_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { write_uint32(sg->cdb_cmd_blk + 2, addr); write_uint16(sg->cdb_cmd_blk + 6, len); - // data_out 0-len - sl->q_len = len; - sg->q_addr = addr; - sg->q_data_dir = Q_DATA_OUT; - stlink_q(sl); + // this sends the command... + send_usb_mass_storage_command(sg->usb_handle, sg->ep_req, sg->cdb_cmd_blk, CDB_SL, 0, 0, 0); + // This sends the data... + send_usb_data_only(sg->usb_handle, sg->ep_req, sg->ep_rep, sl->q_buf, len); stlink_print_data(sl); } @@ -884,11 +924,11 @@ void _stlink_sg_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { write_uint32(sg->cdb_cmd_blk + 2, addr); write_uint16(sg->cdb_cmd_blk + 6, len); - // data_out 0-0x40-...-len - sl->q_len = len; - sg->q_addr = addr; - sg->q_data_dir = Q_DATA_OUT; - stlink_q(sl); + // this sends the command... + send_usb_mass_storage_command(sg->usb_handle, sg->ep_req, sg->cdb_cmd_blk, CDB_SL, 0, 0, 0); + // This sends the data... + send_usb_data_only(sg->usb_handle, sg->ep_req, sg->ep_rep, sl->q_buf, len); + stlink_print_data(sl); } @@ -970,6 +1010,7 @@ stlink_backend_t _stlink_sg_backend = { static stlink_t* stlink_open(const int verbose) { stlink_t *sl = malloc(sizeof (stlink_t)); + memset(sl, 0, sizeof(stlink_t)); struct stlink_libsg *slsg = malloc(sizeof (struct stlink_libsg)); if (sl == NULL || slsg == NULL) { WLOG("Couldn't malloc stlink and stlink_sg structures out of memory!\n"); @@ -1055,7 +1096,6 @@ static stlink_t* stlink_open(const int verbose) { sl->core_stat = STLINK_CORE_STAT_UNKNOWN; slsg->q_addr = 0; - clear_buf(sl); /* flash memory settings */ sl->flash_base = STM32_FLASH_BASE; @@ -1119,18 +1159,3 @@ stlink_t* stlink_v1_open(const int verbose) { stlink_version(sl); return sl; } - -static void __attribute__((unused)) mark_buf(stlink_t *sl) { - clear_buf(sl); - sl->q_buf[0] = 0x12; - sl->q_buf[1] = 0x34; - sl->q_buf[2] = 0x56; - sl->q_buf[3] = 0x78; - sl->q_buf[4] = 0x90; - sl->q_buf[15] = 0x42; - sl->q_buf[16] = 0x43; - sl->q_buf[63] = 0x42; - sl->q_buf[64] = 0x43; - sl->q_buf[1024 * 6 - 1] = 0x42; //6kB - sl->q_buf[1024 * 8 - 1] = 0x42; //8kB -} diff --git a/src/test_sg.c b/src/test_sg.c index a8a7022..d9e560c 100644 --- a/src/test_sg.c +++ b/src/test_sg.c @@ -6,7 +6,31 @@ #include #include +#include #include "stlink-common.h" +#include "uglylogging.h" + +#define LOG_TAG __FILE__ +#define DLOG(format, args...) ugly_log(UDEBUG, LOG_TAG, format, ## args) +#define ILOG(format, args...) ugly_log(UINFO, LOG_TAG, format, ## args) +#define WLOG(format, args...) ugly_log(UWARN, LOG_TAG, format, ## args) +#define fatal(format, args...) ugly_log(UFATAL, LOG_TAG, format, ## args) + +static void __attribute__((unused)) mark_buf(stlink_t *sl) { + memset(sl->q_buf, 0, sizeof(sl->q_buf)); + sl->q_buf[0] = 0xaa; + sl->q_buf[1] = 0xbb; + sl->q_buf[2] = 0xcc; + sl->q_buf[3] = 0xdd; + sl->q_buf[4] = 0x11; + sl->q_buf[15] = 0x22; + sl->q_buf[16] = 0x33; + sl->q_buf[63] = 0x44; + sl->q_buf[64] = 0x69; + sl->q_buf[1024 * 6 - 1] = 0x42; //6kB + sl->q_buf[1024 * 8 - 1] = 0x42; //8kB +} + int main(int argc, char *argv[]) { // set scpi lib debug level: 0 for no debug info, 10 for lots @@ -40,14 +64,14 @@ int main(int argc, char *argv[]) { //stlink_force_debug(sl); stlink_reset(sl); stlink_status(sl); -#if 0 // core system control block stlink_read_mem32(sl, 0xe000ed00, 4); - DD(sl, "cpu id base register: SCB_CPUID = got 0x%08x expect 0x411fc231", read_uint32(sl->q_buf, 0)); + DLOG("cpu id base register: SCB_CPUID = got 0x%08x expect 0x411fc231\n", read_uint32(sl->q_buf, 0)); // no MPU stlink_read_mem32(sl, 0xe000ed90, 4); - DD(sl, "mpu type register: MPU_TYPER = got 0x%08x expect 0x0", read_uint32(sl->q_buf, 0)); + DLOG("mpu type register: MPU_TYPER = got 0x%08x expect 0x0\n", read_uint32(sl->q_buf, 0)); +#if 0 stlink_read_mem32(sl, 0xe000edf0, 4); DD(sl, "DHCSR = 0x%08x", read_uint32(sl->q_buf, 0)); @@ -105,10 +129,10 @@ int main(int argc, char *argv[]) { #if 0 // sram 0x20000000 8kB fputs("\n++++++++++ read/write 8bit, sram at 0x2000 0000 ++++++++++++++++\n\n", stderr); - clear_buf(sl); + memset(sl->q_buf, 0, sizeof(sl->q_buf)); + mark_buf(sl); stlink_write_mem8(sl, 0x20000000, 16); - mark_buf(sl); stlink_write_mem8(sl, 0x20000000, 1); stlink_write_mem8(sl, 0x20000001, 1); stlink_write_mem8(sl, 0x2000000b, 3); @@ -117,9 +141,7 @@ int main(int argc, char *argv[]) { #if 0 // a not aligned mem32 access doesn't work indeed fputs("\n++++++++++ read/write 32bit, sram at 0x2000 0000 ++++++++++++++++\n\n", stderr); - clear_buf(sl); - stlink_write_mem8(sl, 0x20000000, 32); - + memset(sl->q_buf, 0, sizeof(sl->q_buf)); mark_buf(sl); stlink_write_mem32(sl, 0x20000000, 1); stlink_read_mem32(sl, 0x20000000, 16); @@ -134,9 +156,10 @@ int main(int argc, char *argv[]) { stlink_write_mem32(sl, 0x20000000, 17); stlink_read_mem32(sl, 0x20000000, 32); #endif -#if 0 +#if 1 // sram 0x20000000 8kB fputs("++++++++++ read/write 32bit, sram at 0x2000 0000 ++++++++++++\n", stderr); + memset(sl->q_buf, 0, sizeof(sl->q_buf)); mark_buf(sl); stlink_write_mem8(sl, 0x20000000, 64); stlink_read_mem32(sl, 0x20000000, 64); From 2dc7d9f4ec376f9c53dbb9a0413a0b0161378d0a Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Fri, 4 Nov 2011 00:51:30 +0000 Subject: [PATCH 29/63] write_mem8 works too. I just misinterpreted the test results earlier. --- src/test_sg.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/test_sg.c b/src/test_sg.c index d9e560c..19a2ef5 100644 --- a/src/test_sg.c +++ b/src/test_sg.c @@ -126,15 +126,15 @@ int main(int argc, char *argv[]) { stlink_read_mem32(sl, 0x08000c00, 256); stlink_read_mem32(sl, 0x08000c00, 256); #endif -#if 0 +#if 1 // sram 0x20000000 8kB fputs("\n++++++++++ read/write 8bit, sram at 0x2000 0000 ++++++++++++++++\n\n", stderr); memset(sl->q_buf, 0, sizeof(sl->q_buf)); mark_buf(sl); - stlink_write_mem8(sl, 0x20000000, 16); + //stlink_write_mem8(sl, 0x20000000, 16); - stlink_write_mem8(sl, 0x20000000, 1); - stlink_write_mem8(sl, 0x20000001, 1); + //stlink_write_mem8(sl, 0x20000000, 1); + //stlink_write_mem8(sl, 0x20000001, 1); stlink_write_mem8(sl, 0x2000000b, 3); stlink_read_mem32(sl, 0x20000000, 16); #endif @@ -156,7 +156,7 @@ int main(int argc, char *argv[]) { stlink_write_mem32(sl, 0x20000000, 17); stlink_read_mem32(sl, 0x20000000, 32); #endif -#if 1 +#if 0 // sram 0x20000000 8kB fputs("++++++++++ read/write 32bit, sram at 0x2000 0000 ++++++++++++\n", stderr); memset(sl->q_buf, 0, sizeof(sl->q_buf)); From 8c7b98a4cbd9848dbd029e02f367ef7b1289044a Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Fri, 4 Nov 2011 00:54:01 +0000 Subject: [PATCH 30/63] blinking LEDs via stlink also works --- src/test_sg.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/src/test_sg.c b/src/test_sg.c index 19a2ef5..899efc3 100644 --- a/src/test_sg.c +++ b/src/test_sg.c @@ -78,7 +78,7 @@ int main(int argc, char *argv[]) { stlink_read_mem32(sl, 0x4001100c, 4); DD(sl, "GPIOC_ODR = 0x%08x", read_uint32(sl->q_buf, 0)); #endif -#if 0 +#if 1 // happy new year 2011: let blink all the leds // see "RM0041 Reference manual - STM32F100xx advanced ARM-based 32-bit MCUs" @@ -89,23 +89,23 @@ int main(int argc, char *argv[]) { #define LED_GREEN (1<<9) // pin 9 stlink_read_mem32(sl, GPIOC_CRH, 4); uint32_t io_conf = read_uint32(sl->q_buf, 0); - DD(sl, "GPIOC_CRH = 0x%08x", io_conf); + DLOG("GPIOC_CRH = 0x%08x\n", io_conf); // set: general purpose output push-pull, output mode, max speed 10 MHz. write_uint32(sl->q_buf, 0x44444411); stlink_write_mem32(sl, GPIOC_CRH, 4); - clear_buf(sl); + memset(sl->q_buf, 0, sizeof(sl->q_buf)); for (int i = 0; i < 100; i++) { write_uint32(sl->q_buf, LED_BLUE | LED_GREEN); stlink_write_mem32(sl, GPIOC_ODR, 4); /* stlink_read_mem32(sl, 0x4001100c, 4); */ /* DD(sl, "GPIOC_ODR = 0x%08x", read_uint32(sl->q_buf, 0)); */ - delay(100); + usleep(100 * 1000); - clear_buf(sl); + memset(sl->q_buf, 0, sizeof(sl->q_buf)); stlink_write_mem32(sl, GPIOC_ODR, 4); // PC lo - delay(100); + usleep(100 * 1000); } write_uint32(sl->q_buf, io_conf); // set old state @@ -126,7 +126,7 @@ int main(int argc, char *argv[]) { stlink_read_mem32(sl, 0x08000c00, 256); stlink_read_mem32(sl, 0x08000c00, 256); #endif -#if 1 +#if 0 // sram 0x20000000 8kB fputs("\n++++++++++ read/write 8bit, sram at 0x2000 0000 ++++++++++++++++\n\n", stderr); memset(sl->q_buf, 0, sizeof(sl->q_buf)); From a19abbb547116f343c5dcb2b3a6d0f6d1d457dae Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Fri, 4 Nov 2011 00:56:50 +0000 Subject: [PATCH 31/63] Writing registers works too --- src/test_sg.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/src/test_sg.c b/src/test_sg.c index 899efc3..357f436 100644 --- a/src/test_sg.c +++ b/src/test_sg.c @@ -78,7 +78,7 @@ int main(int argc, char *argv[]) { stlink_read_mem32(sl, 0x4001100c, 4); DD(sl, "GPIOC_ODR = 0x%08x", read_uint32(sl->q_buf, 0)); #endif -#if 1 +#if 0 // happy new year 2011: let blink all the leds // see "RM0041 Reference manual - STM32F100xx advanced ARM-based 32-bit MCUs" @@ -169,13 +169,14 @@ int main(int argc, char *argv[]) { stlink_read_mem32(sl, 0x20000000, 1024 * 6); stlink_read_mem32(sl, 0x20000000 + 1024 * 6, 1024 * 2); #endif -#if 0 - stlink_read_all_regs(sl); +#if 1 + reg regs; + stlink_read_all_regs(sl, ®s); stlink_step(sl); fputs("++++++++++ write r0 = 0x12345678\n", stderr); stlink_write_reg(sl, 0x12345678, 0); - stlink_read_reg(sl, 0); - stlink_read_all_regs(sl); + stlink_read_reg(sl, 0, ®s); + stlink_read_all_regs(sl, ®s); #endif #if 0 stlink_run(sl); From fd5967fba684bb0f4d83b0b72559da8021e1c995 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Fri, 4 Nov 2011 01:05:27 +0000 Subject: [PATCH 32/63] Fix compilation error after removing devices. --- gdbserver/gdb-server.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index df3657a..bcb3c97 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -197,7 +197,7 @@ int main(int argc, char** argv) { if(sl == NULL) return 1; break; case 1: - sl = stlink_v1_open(NULL, state.logging_level); + sl = stlink_v1_open(state.logging_level); if(sl == NULL) return 1; break; } From 3dd1addf929f95e05fa676bab5a41515e990e16a Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Fri, 4 Nov 2011 01:05:54 +0000 Subject: [PATCH 33/63] Update netbeans project files. --- nbproject/configurations.xml | 355 ++++++++++++++++++++++++++++++++++- nbproject/project.xml | 4 + 2 files changed, 355 insertions(+), 4 deletions(-) diff --git a/nbproject/configurations.xml b/nbproject/configurations.xml index 5679465..47cfb04 100644 --- a/nbproject/configurations.xml +++ b/nbproject/configurations.xml @@ -117,6 +117,8 @@ stlink-usb.h test_sg.c test_usb.c + uglylogging.c + uglylogging.h @@ -153,9 +155,11 @@ ${MAKE} -f Makefile clean gdbserver/st-util + + . + - CONFIG_USE_LIBSG=1 - CONFIG_USE_LIBUSB=1 + DEBUG=1 @@ -473,6 +477,351 @@ src + + CONFIG_USE_LIBSG=1 + CONFIG_USE_LIBUSB=1 + + + + + + + + + + + + + + + LOCAL_SOURCES + default + + + + gdbserver + ${MAKE} -f Makefile + ${MAKE} -f Makefile clean + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + src + + + CONFIG_USE_LIBSG=1 + CONFIG_USE_LIBUSB=1 + @@ -487,8 +836,6 @@ - - diff --git a/nbproject/project.xml b/nbproject/project.xml index cd52486..580df10 100644 --- a/nbproject/project.xml +++ b/nbproject/project.xml @@ -17,6 +17,10 @@ Default 0 + + gdbserver + 0 + From b463d50c5b34935334b26a48903c68c3893b1ff2 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Fri, 4 Nov 2011 01:56:22 +0000 Subject: [PATCH 34/63] Update documentation removing all sg-utils notes Just libusb now. Verified the modprobe.conf on Ubuntu 10.04 --- 10-stlink.rules | 43 ----------------------------------- README | 50 +++++++++++++++++++++++++++++++---------- TODO | 3 --- src/stlink-sg.c | 24 ++++++++++++-------- stlink.modprobe.conf | 1 - stlink_v1.modprobe.conf | 1 + 6 files changed, 54 insertions(+), 68 deletions(-) delete mode 100644 10-stlink.rules delete mode 100644 stlink.modprobe.conf create mode 100644 stlink_v1.modprobe.conf diff --git a/10-stlink.rules b/10-stlink.rules deleted file mode 100644 index 2413acd..0000000 --- a/10-stlink.rules +++ /dev/null @@ -1,43 +0,0 @@ -# This file was taken from arm-utilites project, located at -# http://code.google.com/p/arm-utilities/, which is licensed under GPL3. -# An explicit permission to include any code from that project in -# this one under BSD license was granted by arm-utilites author, Donald Becker. - -# This file watches for a STMicro ST-Link or STM32VLDiscovery board -# and creates a device named /dev/stlink -# See udev(7) for syntax. -# -# Written 2010,2011 by Donald Becker -# -# The STLink on the Discovery has a USB ID 0483:3744 and presents itself -# as a mass storage (i.e. SCSI) device. The SCSI emulation is signficantly -# broken, and the kernel spews error reports for a while until it is -# accepted. Further problems are encountered when if it is automatically -# mounted. -# -# Options that may prevent the mount are -# ENV{UDISKS_PRESENTATION_HIDE}:="1", -# ENV{UDISKS_PRESENTATION_NOPOLICY}:="1", -# ENV{DM_UDEV_DISABLE_DISK_RULES_FLAG}:="1" - -ACTION!="add|change", GOTO="stlink_rules_end" - -SUBSYSTEMS=="usb", ATTR{idVendor}=="0483", ATTR{idProduct}=="3744", \ - MODE="0664", GROUP="tape", NAME="stlinkusb%n", ENV{STLINK}="1", \ - ENV{UDISKS_PRESENTATION_HIDE}:="1", \ - ENV{UDISKS_PRESENTATION_NOPOLICY}:="1", \ - ENV{DM_UDEV_DISABLE_DISK_RULES_FLAG}:="1", \ - OPTIONS="last_rule" - -# Other possible settings: -# OPTIONS="last_rule", ATTRS{vendor}=="STM32" - -KERNEL=="sg[0-9]*", MODE="0664", GROUP:="tape", \ - NAME+="stlink-sg%n", SYMLINK+="stlink", \ - ENV{UDISKS_PRESENTATION_HIDE}:="1", \ - ENV{UDISKS_PRESENTATION_NOPOLICY}:="1", \ - ENV{DM_UDEV_DISABLE_DISK_RULES_FLAG}:="1" - -SUBSYSTEM=="scsi", ATTR{vendor}=="STM32", MODE="0664", GROUP="tape", NAME="stlinksg-scsi%n", SYMLINK+="stlinkscsi", OPTIONS="last_rule" - -LABEL="stlink_rules_end" diff --git a/README b/README index 429b851..109aa25 100644 --- a/README +++ b/README @@ -11,22 +11,47 @@ called stlink and there are 2 versions: . STLINKv1 uses SCSI passthru commands over USB, . STLINKv2 uses raw USB commands. -It means that if you are using a STM32VL board, you have to install and load -SCSI related software. First, load the sg kernel module: -# modprobe sg +Common requirements +~~~~~~~~~~~~~~~~~~~ -Then, you need to install the package libsgutils2-dev. On Ubuntu: -# sudo apt-get install libsgutils2-dev +libusb-1.0 (You probably already have this, but you'll need the +development version to compile) -LIBUSB is required for both cases. +IF YOU HAVE AN STLINKv1 +~~~~~~~~~~~~~~~~~~~~~~~ +The STLINKv1's SCSI emulation is very broken, so the best thing to do +is tell your operating system to completely ignore it. + +Options (do one of these before you plug it in) + *) modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i +or *)1. add "options usb-storage quirks=483:3744:i" to /etc/modprobe.conf + *)2. modprobe -r usb-storage && modprobe usb-storage +or *)1. cp stlink_v1.modprobe.conf /etc/modprobe.d + *)2. modprobe -r usb-storage && modprobe usb-storage + +IF YOU HAVE AN STLINKv2 +~~~~~~~~~~~~~~~~~~~~~~~ + +You're ready to go :) To run the gdb server, do (you do not need sudo if you have set up permissions correctly): -$ make -C build && sudo ./build/st-util [/dev/sgX] +$ make && [sudo] ./gdbserver/st-util -Currently, the GDB server listening port is hardcoded to 4242: +There are a few options: -Then, in gdb: +./gdbserver/st-util - usage: + + -h, --help Print this help + -vXX, --verbose=XX specify a specific verbosity level (0..99) + -v, --verbose specify generally verbose logging + -s X, --stlink_version=X + Choose what version of stlink to use, (defaults to 2) + -1, --stlinkv1 Force stlink version 1 + -p 4242, --listen_port=1234 + Set the gdb server listen port. (default port: 4242) + +Then, in gdb: (remember, you need to run an _ARM_ gdb, not an x86 gdb) (gdb) target remote :4242 Have fun! @@ -50,13 +75,14 @@ for GDB. Setting up udev rules ===================== -For convenience, you may install udev rules file, 10-stlink.rules, located +For convenience, you may install udev rules file, 49-stlinkv2.rules, located in the root of repository. You will need to copy it to /etc/udev/rules.d, and then either reboot or execute $ udevadm control --reload-rules -Udev will now create a /dev/stlink file, which will point at appropriate -/dev/sgX device. Good to not accidentally start debugging your flash drive. +Udev will now create a /dev/stlinkv2_XX file, with the appropriate permissions. +This is currently all the device is for, (only one stlinkv2 is supported at +any time presently) Running programs from SRAM ========================== diff --git a/TODO b/TODO index e3795fc..e415e57 100644 --- a/TODO +++ b/TODO @@ -7,9 +7,6 @@ . documentation . make README points to doc/tutorial -. remove libsg dependency using: -https://github.com/afaerber/stlink/tree/master/libstlink - . compile and test a realtime kernel, for instance: http://www.chibios.org/dokuwiki/doku.php?id=chibios:articles:stm32l_discovery svn checkout https://chibios.svn.sourceforge.net/svnroot/chibios/trunk ; diff --git a/src/stlink-sg.c b/src/stlink-sg.c index 276986e..2bbbaf9 100644 --- a/src/stlink-sg.c +++ b/src/stlink-sg.c @@ -12,7 +12,6 @@ The stlink related constants kindly provided by Oliver Spencer (OpenOCD) for use in a GPL compatible license. - Code format ~ TAB = 8, K&R, linux kernel source, golang oriented Tested compatibility: linux, gcc >= 4.3.3 The communication is based on standard USB mass storage device @@ -31,10 +30,18 @@ CBW - Command Block Wrapper CSW - Command Status Wrapper RFU - Reserved for Future Use - scsi_pt - SCSI pass-through - sg - SCSI generic - * usb-storage.quirks + Originally, this driver used scsi pass through commands, which required the + usb-storage module to be loaded, providing the /dev/sgX links. The USB mass + storage implementation on the STLinkv1 is however terribly broken, and it can + take many minutes for the kernel to give up. + + However, in Nov 2011, the scsi pass through was replaced by raw libusb, so + instead of having to let usb-storage struggle with the device, and also greatly + limiting the portability of the driver, you can now tell usb-storage to simply + ignore this device completely. + + usb-storage.quirks http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=blob_plain;f=Documentation/kernel-parameters.txt Each entry has the form VID:PID:Flags where VID and PID are Vendor and Product ID values (4-digit hex numbers) and Flags is a set of characters, each corresponding @@ -54,18 +61,17 @@ Example: quirks=0419:aaf5:rl,0421:0433:rc http://permalink.gmane.org/gmane.linux.usb.general/35053 + + For the stlinkv1, you just want the following - modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:l + modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i Equivalently, you can add a line saying - options usb-storage quirks=483:3744:l + options usb-storage quirks=483:3744:i to your /etc/modprobe.conf or /etc/modprobe.d/local.conf (or add the "quirks=..." part to an existing options line for usb-storage). - - https://wiki.kubuntu.org/Kernel/Debugging/USB explains the protocoll and - would allow to replace the sg access to pure libusb access */ diff --git a/stlink.modprobe.conf b/stlink.modprobe.conf deleted file mode 100644 index e918c90..0000000 --- a/stlink.modprobe.conf +++ /dev/null @@ -1 +0,0 @@ -options usb-storage quirks=483:3744:l diff --git a/stlink_v1.modprobe.conf b/stlink_v1.modprobe.conf new file mode 100644 index 0000000..94b3786 --- /dev/null +++ b/stlink_v1.modprobe.conf @@ -0,0 +1 @@ +options usb-storage quirks=483:3744:i From 388606716eb050914a5c3af08a8ccf669f1c85a9 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Fri, 4 Nov 2011 02:23:17 +0000 Subject: [PATCH 35/63] Update tutorial docs and flash writing/reading --- doc/tutorial/tutorial.pdf | Bin 110993 -> 111736 bytes doc/tutorial/tutorial.tex | 49 ++++++++++++++++++-------------------- flash/main.c | 3 +-- 3 files changed, 24 insertions(+), 28 deletions(-) diff --git a/doc/tutorial/tutorial.pdf b/doc/tutorial/tutorial.pdf index 371f805a0f1a4ddc103155c3fecc8c3a3fc972a0..70546cb813a4c8b4f4a6d2ca15587a88e6ad88da 100644 GIT binary patch delta 55709 zcmZsCbChR2vu@kAHO=X1+wPvWZQJIr?Vh%6+qP}nwsq(I-gE9bcdh$Jp46(;s;4S@ z?Ib%piQR{IIf1B&0|Si9^wT4C98*7;5ngzFhQ?E)hzJVe-N4(IpfopX7@$!IeDH`{ z|FmCQy}h__1JB^^Q6!V_wp+BJqscjvSVq}EMxwDb0#z~lQwFiz&m}O1R7hM6tNi<; z1?*dzZ{yx38ba8K`zZjaDkys@C{q#mHsw6s z6M7SiDjxn;bz9mHPcZo^S^}dzrtP=ttYD$`{io3zN>LtsKL+NCF2B;o2`eNwT)8L} zO7~sXToHTpW|G)x)cQn!+ZWS*m~HU05Xf5Ea!=%92gc#?S@yxKa(9@Y?r#`l8zV<2 z2V;HfeRJHii~TDY$H^t2SECUt-jbDK=?+I()8AM*yD7*^;Y` zaKw8h*M-d~g+isGKu5N;S zlo6|G%U)j2TnC@=2b7hYr>|8EX>b;Ob#Q;`~*Ok4{qc%Mfo!;mw$G;|&@f*EEm@L10y;&B_(5(Wp z-j9;JHo6>g*_1M^sZIO30JPO5^{0qnI^2QYzSGSu?n4!~VjMV?wSa=Ib=)%`C%(+O z?dNpQIMFdPyfEt(Eoh=VC6 zw;bV!i(PilAqY7Rt}!0wLztVe(>E4%f=WOXx==i3STDV+9t>@F8bu6IoTd~79y$wZ zp^&Io_4oA*p+6!^0pJm&F$=OXAW@;fwkRd9ayys@*YP-P%n!eM$kR@z-L#M~f2qP| z3%Zn>j{dCu>33&Q{u1nvt6Vhj*v`n33Mq{&c&e!7$8k|Yo}R#D&hQEgZVVH4>@SiL zI%vJ5>Ez|(n=O^4woiJ&hJrK^sO?JSzN;r`OS2;(e`^#MVZgW?a<&f;6&i`J%rkON ztA!3njJ^SW!mK_!9tY9w7p3e6b_G9{LWvSo4hZdeOf*0L_-Ed$&o4J(mdXys^{k{F zwz*ui2jqmW1aeA(nbjxjbGkCFwm-WWYeXj*B-dotZPNRrLFzF6({O483M5k4&v5#a zLBLgx-X597T7ZDBebU`hI2K@|ctFRI7Bteq7VG(JmEovJiyKoF<7bR7hbK_>=Ch$D zYKQ)Vz|ChD?19U!icmg}hA9HGJ^c{4s7VuZ`BGLYfp})!j~gq2RpRDf*(7NP+~TCY z8qx{d`}4)6oQY(@pYopylz?d`d~UDZ02g{2Gq}XCG=S8XU_N_?miC7?F>q+;fmWQe zhF#^onPZFFyN)o66o^XI7)jfGRmg8YNr+e!d0ZO0uN)9WeJb}G+|gk7TOoLz`0&S@$By(gtomz%f?ARlHiC7 zV!-XwUN3LL`^ZwKF=OihW=isZy&angkiZgdPw4hB=F5(s)aRa-w5ksjjuEXxj-Q6z2Jwq9Qjmi2zbzwvY`y5-L+z&SV3+LR!dk3p z1NL=+L|Uo>MAK~M|1{P{t7f)}dbzKb7FiN(6S=zuFe@VaQ7*rb)*^guY}{z? z)9TYk{`6wz_C`DX;M+UT?eeil{~3wRJ3&`2dwY5I*g0J2e0!4in6tiX=q5LFiW8z4aIH|j_Fj;0(ZQ^)ota;d?*tD*0b6|RR zzI~oooikBDlNT1347I9K+O^&p%{KH^cGtD7N>81juIl=FB4c3eHamNwnf`NhCInp@ z-hP&aTe~C`^r78ZreY{N&eQLKwuxJOr@W~=uD|Y`0iKCj-x|j7t-mq}ohU9w6=6nm z?&cR2@4Ezel}0qqik%s4j)>ouAvF>qcMWz_LHoI8)ynaDs2W>26Lt!NFZ9G4X2WPL zv`gPOl6LWNKu#f{Msb6VyYfaHo|PY3lG z-hNy0HlvIW>3P2xGFO<=%J(vXn&gBBGM5PHngc?lgoQ!+Fd(ZTn^~G>~d&cQk;adl*@N7a6npXKjwThe>5ID~fie(E7lh7!;v7-i zfvtTe=)Plmkn%kXd?>uP|-8`Etdp^)i$Jn!&x5bXm)B`N<*8 zD8XC(S@KEy=TA3MI;im=FHM*Evhnn)a*a3ucA9+Afj)-T=7g(Ec?7iap@^aY+rEel zF)0l{POo32fY}PlB3egE>qQgp(bV_rM}^)~RL!1Of>klH^LG-*nrxn@rrY+S5RB@A zyr5||Kv)fTseLGVp{a9K6&p*Ev-(W={g`3Ksw^%K>%(G25Pq~W!g*13qG)8qYHbAo z`AZQcWv7|ZRzY+6Q!-29*xOy54AwxS&f(6oY~z8-MKBOf=mEb}-T9G>99InP++k;i zO&^+{5t82_$OQs;3qu8K3(aot8i7+-*I+hr;9FYW-4hfkbq9I$J=Y3H;ZIosoyxO#ry3Ty7BH7KY+`fyWHk%aypoGfb+KF3+IFWri&*XUVJGidBEck0ndwLju zrqiVGJ-cZWv3WQZ5AmrBjFoKAd#4zp*?RoQRrO%$t3YDa`iREMQzsGg@#F7ONmZz1 zkv8NFR=HkRpmCkDwmP1?{E{j#h(hX3uyj46zx|^A0_HXZM%fC7V~HTItV#=MADANxhXr+~_WG zi;{x5)fagU&#Ft#vXrc{PVLwq3b({Z#o`Q1IF{>DVDd}#e?0BW;o6vm6OcpkMVWzi zu%c32Ekwa#r^v0$lL~b-uFv)j4dtGZdI9_hTrpl~R>KRoh>ylFX5_-;?5{N0y-D!3P@8^| zItsC(Q*DBmrZNu~L6Cc~r)caoeNW)b@U?6rh#QVasP!ftG*;+I!tgrA>H#xqFqH{X zLzkbCT=gP7@nxHb1uOz!=)sCh<&?<4JQC%|(foRW<&K$*e1C_67RZ~G{oK<*4iQWF zyL<=Iz=S{5@Nc{bTMdRxH6D<|Br6K)r+sRQ7nJ`Z*C&U zszoi_cMWo$Zc%K0m=}vDmm$oNOBZVLK-z4lNa#8SedaW$c|B(>arv5P^Ql#5BQ&ug zuJb%~%uFZwp^ZJkqLkO~9g~=V>kT_XiVr)n%eQ;ghM~p%i)A0vpKsGQsdp(GQr8n@ z-eakt$A(ZU?ayNX>#4*p9fWPlBb&aUEQZ}RS;-ir&G>LiikRrK;qPUlO%-x(Mubwq zQEeqJ!Ee}zO^V-d2=3AwYy;AK#Nj@I54G7y*nXJcmg%AN<^=bsBtKjriaA$ylRpCG zw8XL{2?OWI0Y%*JiZPy1PMdr?d|mWwGK@52^Js8ZSg&V*l>3rCwfmh8;wzaF0}48K zR7|b%=ytEjv))qRA@Sg>yi+>F!$F=M=CYXGX9vL?>9^Y=cM;k02T(@Ny?Lrs+jR>L zDMDmOStRcln>RXMG2?|GdfnkwyKXdcZq}}Aer7u_x>P5rllg_4L1T8!xzno1SRYBl zH?b%x-a#<=&J+Ulc8s_3MlTAD;pH01R-E6XMi-jbVQw^Et&qY$)B5xhL)T@Z`SP!Js1OUkK#RA-jq4Y&|C!+F85sVZ;2TvW zZ8unvx~{8gG%Fa+K?b@KW#ee+Q_$30}6@{eI*o|*@B#yRZ0-&IaAq6qS75U9vvt}_!9f^ z8Y;?o5gao-l0G61UTXLD&phh}CInzGB73dqV5`lx1$Z^g;VKhzjiW7>4Yi^b31>T^ z)~mY3qOILwHRs7^nlX>ro#tK4=Qe%MTBw9&$RRh3Q}(?4!FZyimvyea0PPthd{S4R z)73tDg9=n4s#Mbm@6xI&rN#DPp`Va?@sgW)Qpi&?ybJ5=M+70o#6Ia5S{>>%KDtn9 z$*2N>b`z4a73h(WvP@`dSa;M;@#ncEe=&&6UmH4!GMr>s$l0m1SaxF0K@~07EO+Bmwtx`7n-Tnrf@vGO!@Anjc9mb>i9eYu-<&+SzuM-#ia6J8dReG zwN0HV_VXBSyJ{dZU1?t-NL`2r0*hs%vs~J0dd4T)!h+i zFA{ztESXAvi1b!hB4O)WY>tMO0|P1Rl;%jIH};+#%0N()yLQrv+Wna?cB1EUzoV}~ zm!-!Y`{JVm02AEh>Bz7nw@i>?<D<2}4t@z59GC{k%-pIW;$ z^`zUnyI+KB(ipbb;j=m{#;tTy0+r&1JN|{7xZ}=*m}t#%PqUXDr=vU1?s5rK9`-@+ zZF&6_VN>!_T>Fe zCXw)W(M4tJUml!}R3l~8?heg1Z0(Da;kST%)?6Hn`TJK}iehr8eC63eIjFSo)W)Ad z6UZ`LPFbxf2X*RIOMrW?PFN@i$iPu=e)=`PTAfGuY1$&z@mt?;eKTI=a|IZB=VNE0Gink8RjP`wz(#r-%wN8so2dxx$b7;q6Kpj?cz* z;=&wsY!OAriR-|i`xQ9Z@Db>7u56r~}cj+U80a;Y$(JFqXwlro)-#&-zQY4d)(~*l*tr6diS2);wq~nF9FuNcO_Rc=)JhDg5oSdXy!Szkf-tQPUDqAv|dm z;HSO{HZ#wc5Jv9qN`&8v&z8(rKy=Nmn15HzUet=dLmW`Op-yX zxN3I1n@r5GS>ayhT%T?!1Zp2#>K_1`HenYui?(=*z6No-3cpV2TzNgv z`9oE`+UF5{%u+_DN!P^B72U^+QoST37yz*SnF+OLxlp5)00N{9OlR0hNW~Bz17dJO7?6+7y554pQFvqWbICysT zIeeG$%2usBma26#Zg|!xG)A=!(`IJr)lam37QQycr@!`5A&P0CrMq~8CDj^uD~q`@ zEgOJv`^Toh#SFAMoV4Xtuk@75?=LcAsoV!a=MlhqJ#MA#Hy3lC0P$w10TxkqL279D z!{I@-NYFr|HKO_t)tpc@_lvHnNX+1P&TRo6T+7Nq^{tuJJS!oHaiQ<{$yv>aDx2?Lv0On=aCE$1k_TZ!L z)!CgX4u0w1buA!!mBiAxO4!DnYT)JO)9UqSEACS&?dh<@s4%~92Z~=wVEbagR7Fwk zy;N;J-)=`sC`70w zL+NSjctcEIDTZ@H2mlNXO$AAIi6g?Z#jP}qK^#AI`Y9;t3=*-eR!wOdQmT%)KiR~X zbXi0)1wMTU4{18CXz9~qk5e5SwM=<-DHA%RW))?=5^21lX`qZ(GGcvxJ;?49ty))4 z7H^7`K3+tpVKQ|s!L_pvg$EZ~YG|}xMmhVcf2Am|wKOkJ3LxgJ9$jq^DX2tOeRK;A zAka`C*qG-?X^mkg%ANPyb_Vy8gOD7T0d|3kWZC0j6pSz}LHn8B|HCn=&sPnMEN4W$ zFw`W8I)S8E1{8v0kjV1@zXMCgcTC9XQR1P5SsPkq(!$8J`&etAcPN(A!2*$iRJlg* zr={4ylF}bnN5G#cFxUu@vs1Jd{UEwU=3+`zIpqr03JDdr_9O2#n0`}_CN#}g{6- z428k|(*;W4GJvONPUOqoiHYSj0xsjA8IeC`ht z3{t+B3d90BC$9W@K$sD0&*{&h#}-r3#q4mK#!q>%2LnD=KCF!yFJit)StGNNOU1i;{;aeOameO_wZAH{!wHo1|r2oeQ2kSrSaQqVuJHtN#voo{(!$SX``2Koe zC1Pb{`OC=4!1xzA*#G5XqGkG<8v9>lV`TonY5wn&{~!6kI*sL@zGMFDl==UI|NQ`% z{?keSBI7^7*BeozNF%c_z|ct<+n73;F%mH_({nJ!$FQJ-u`n^RCNuo=XYmo#DZ}!) z2OctNbtQGB$$EXN;BPhGVs5qGgtKmT!D?}FG|7SJk@fvt`PgN-l$N^v)K%4ao$fEJ z9wjiav4uuyZhPF<(>F2!i=>FOXrd2J&s5LA$W-5_C|44oW##)F+plN_l9?g!VGK*-VCGk|XJo;EWv z0F|p}0|nOR{-yw9=`M_j0Hs5XZ*S+y536L#@0_O)!13_q8W}_ZTIJ(1(;fv#79Eg0{B$RKkz zyCV<3jrkE@o_B%Nu++bBueP@U;2^7?msSQQCbs8#2FK8K?_f1Rt3bdKad(ll1hfx8 zs9g8maMD&8m)oBJ=?y7p(YQ*aL8px$q#_o5SEZzYavnQXcY!N`Wsxh;(J@Xkb0%BxpbE}GbRD~dg<3c2+ zniKibZM`LO12D?=r3FGTF)^W)Apn{|26~{c|LfGRtr!4$V@o!!yZ21s)ro(B4}@`T z4dg9=(eq5`W^0PdM$|JnihgqbDLeR$!VL@CgJ*OELJ#f(vfBF{_C*V!@e#3oy$yW; zJY(oX$cF)Rubch-#pISv@94>eJI!|l&}E3P2#w1~;oj`l{Hj(^TG#^Jne6F>(9=8A z1Fos5xdi~Vu%`fbed8W?Q`}@_SKYqW_q?;TwYOY_dcVAdF21TuF>Z8WX#f_shF<_@Mq2V~ToQxl(WCBRD2F64 zcc95c0a}x!Z=AgEjXqC1+!%bh)h+CYWl+eTp1z3>fYUXXsmbS;oV`zXdAD-UbK=`} z0*Z^t(-Gj3fEtpbXJB-605$8?yGMVl;6y>(YyYG;1!e%suf629ovAM)LFn$7$LnRLL8 zXKoW9=CD(){U7n^Tja@g{h4i=Z{fO-{X@PxySx8AZ}mH0G3i<3OP*@nlV%FQ`5NJC z)58bNu{D{wovi@C+cIqXYnr@oa0>RJ*!SMR*xIuG-M{;(pau9F&t}^v=r)(#cRm8mtwAMdW8zW<{Cx}86g zH25WWOLk+#9SPG617^bKkV(Jf4pL2M_F@Fv>5=;8@;>kQ)mu8##l};8ek4if1U&OZ z=~Le=ZJI=RYdx%$D49B64U!En4iX1;h@__!K49?3Bmo9>o@iti?<2Bo_x2lZIwP;|o z6tMfKOHqg7C=Y9+StX!5Xa*jr9( z(SfY;urd}8nKcTWeP8ZSr4k&@(1eWW20ZyVlGSYES$q8ip>>|*;>)GZy-O?P_uOxS zZax5geR+3&;RvOQa3x1EAlJ?9cg*_Y_Sh3LwuON3$=DFoVr#V&u~h3}7hW#c(!Ahg zy_0F_u+#hgfiFWeb*|9GOy=FyZ?DR{@_Ce~4&QQP^$UZUjnJ0`3mwnwJHZ6~Fgh7Y zY6d0SYmg6Kq0@w9h|2?4lBTgA-R(T5B(8u9y=qW&ozOw~6a<5V!c6g@>iQHDg3CiS za2s~2L$`%f0ke;`k8BRrIgW!ax&k)e>3R1~uY|KPLx|$jN7uPhsgH?vtpEm#B*Z^t z;YvxvWcjUFFEEWxG3Ad-Nx2rj3kjq5@Di$Q0W(X(aO=FJ9kjf5%)dpqS*4JFO-uu5 zFVCj~mXh<{krHnmCu^zXY#tV0mJVf)ngM z(~5~T(205qJr6aLS_y3VUH8D@24?|*vy!+0{Q*tZ1}8skr%KVq#=)DL-DOXlEmKx6y?S<4Xy$7bApK1 z)g36E%y*-I_iC|Yu#Xhd7Ry)aLC(8w!9o-py*5~Efv0?gc1Px2l%ET>pKR;38jQgW zTjnl*JE6c5{17?9_Lrj$DLoONETxC6xd_V)+|c2Nf>+~I&tNJM(>jlC z3H|VYnDbc-M*p#cO|qmVqL*TV{$k){h2Dz4#m8d@(3Kp-rxQ|rk% ziyM=%g#dS^o}yq4Dl(*Kbxm~cwT|A;9kue?8)K_KEkw?^e1X;_bPwMI`$gsv)leG3 zz2A>UsGwisek1XxW|AZ6<({o^bv&1oeMWrGhu9**n15LUX>@B)#i<#Pb5{Ke%j{Tx zr-1^MMa8tEVr{00R%++|42hWm3WYt=VUw(JteKAuq58xGG2)d4ZheDyOT|a@oL<(D zD&xQy#tX!YBzG7q_*&yRYE(!iHSZm~zrW}d{zOJ0tX7>fw#>$2OJon^$L^0{pl7Fo zb&iS_;k0;bsXI&#KmT9=ms5MQfkT?Q);Qb}nUZLses!Z-o}$AHYq;Gls2%C~VCh-h zz2;H4bz89uvMz5ubwm!pxtaO$HrdArRQx3vjO8>JZ8ghdlcLmsHwJa8oBvGwpw2Tt z#K-YQ!FbN&!*2p;8ClK3fE3huCBe)xRSlt`CGX4%o_)@7!i);wXFQ>SV(3CPGty1L zeVO-*??r}=5%zeBUt)NRze}BzeOV>tC%+0jT2lU^|4Bk6RWXKxkQ1BoFH%2c2C^^VR4yd_`1k0x2rjez4bFYm@#4NW{-?7J%bBA%O7y+6QK+(Ny>bT|xqr|9Q~p^4ZzD^_pYXh>?3F89mCgV!&zJ9p1q`gY zb*3MO=Z-=P5bb5q(xC9on(XG~akuGrCz8Z#H}uqbq+zTr(Zw(2(Ce!}DDr<~CQc!_ z8C2BL&ArXXiGCQPOH7#>{6!IgTZ+<;>5cH`hP19znN6xwF7s3rXX3}NR_{g0G=#!i z!NviuNpP-H2eA)`BUo~ww%XFFZMMsqrE?x9~-TSGCuu{j^-q2Y zJU(qWn@<0S_8O*~pKRS_jD;Mvm|1w)dQ{wr0CGbbf8$@0ZST=qKpZ6o@KqnU&Yp=B zVR)iFhRMn45t$Z&q6z!bf}(%Vm7tbl5#2)W7EjXiC5csT*NeYmlm_e*$QM>04z51N zMPb1R4on`>${#WsHTXcSz^NsBow%sVDMVKzyCzBFtM=O3dY!>O1^am-TqtZ`*tF_b z0+t4(OH`b;(jvUO1aGg4kl=OdBfH*YWNM_k9cfY=vHrMPe+$tXM=5bywn4Z9lVQ$i z^m3AgYm_mJijZlFZF20X6NgwQD@a zsi9qrUQ^0%O1+FS$I5IaAlo)IaHM)u2?)M^rA?*I4lA#g(A&t`{hdg%bHCf9&FEKQ z#^hJCN&JFa40RvvGp+-tES|N7_edsu?RMrhwxD~UnS1-yvCo#ocW zp)N;M*x1!8j65rD-P~dDPYlb~$MRe=lmfMN34*ohh$=WmM`AV#OH{FX#2sD1FlliE z2D=kB=?)G_EcCn~Qs{%Am071J0YGasIm76M$CjLQIUAhhX+(4;TNhb0UQ|1xCSU4a zGZm$|zyoJ#6liYj`OWxksEErm;=ok~WRp2w@K$Qj?U}pw1N-SD52u7rR;9HJ+mU1J z$xb-^S;-j49A1Q*ynsE8^u#kEkbqE~7e6UOiL*$90-7`=QX4K(*dbU zUU3;DSbuVUzLnbw>8ZdWxmwfr*dgT3nkXAEMIN#-T)wGr>6n&H!)as0=W`!=RO|2M~~aEsI4>eIeSqUim@GrrEBb-C~;4wN&5+;V=Fr1;6Tq zWoAUyXD0b^L@m_58cOq%mF9#hp~{FE24QhD%m1mbJzdH4r+q@X`QL85bmNV6IMI4@lcnZx zY*=~30hggyS)1{c2mo`%srdGM*F}7MCb2#5l*f0MuXic?TBXfWvQzsa`yz?(33Lrd zNb!yD-1|a{uLp+3;HhdLd2o$ytIXSBL~di0+Gh}j#5*T=udP8EHcY!orO2oh896;1 z_yY6v&u{t2pda0q+QU`#bu0!kQa)xx?)HCHT09^s#q3^ldI65F@{E)443v;~8$sG^ zKh#mJdV8LT808!Ze(6h}axl>6yfwuip<9)??uwhEDH5iQn>ptj9gK*PwzQEpe zMT;IsZ15QuxB*l^QOm+rb*3Kirz)eH+%>VwBey?P(i5Hs;j4GuYpyz4ya*_Oj&9wi zG2sH%k*#yJ^tK%^X7cG}O@E7IhkH$#4?Jj(uR9n!JQyTUIk0{n2QJD7q+M@ZGp*Xu z1*#v{Oh-(59(3Z1JoG9Z{~9&Va|3juEgBuNaYI+Y)pvX2e+jOD z5%3A~3o{k-?z831$n5_F6l|G^L&8+vMmV2WGJ`X&2c8=ehw9HoiszTw? zH^&^ZXa<}PtqbUD!nH_d9V8wv>i73vk{t#;H@1fpWL}xB(!Ktvym7MT>Vv}cY;t+f zRDp3p!C(w+f+{Ri2xP$_EW>e*v21ytCqxsfm4w}@JCNhM-^2ByMkAvl98f`ni5dLx zvKMar)#qlqc|KXqJ(o@5#6M+})-9%Aw1$P%WC&Omzw={tyZ*@&4G9|X&UD*G5?&tb zu{7^GG zc?Xb3Nm25q{&;nM8BV{#A2+8_$}l_d2-5c3KKy&6$Ry}+dv+Yi#P^t}<7Z!*p*qqug|oHBjBC4 z1FykETClUSPBbi-4e!0;uS%vnjw#Nq*gZg$(FGJ@@7@-<@tcYl&4G(Z$&n$4QhdAv zO6aH(LKtKy`Mt2~xu^kQZLfOLL~N|?kd727Y0UDfxM%q5qt73eH$i)FJNb%+VtjBl zrrI%PO)&-K#1^5nJK0e3+|5_G`_l_@BBke*2MLergn7d)V*-rZo_xhwScvruBs9PY zCnwA@j-kk&UZ}`o*8C60y{cC&^Bsca^IC*tcfJN0JUowWEEXg$A3~e-3Ykuwv-Jh% zu(8gW7pXB(4ir(7WJ2adk=qiCZW~O@s@Aw1Lu-@EIrI(0hF2zJFVR>Jf;$a>b=!VT zoO9&uTjaEpgUu05y(Hff28|k*_8VX{&{uo_V|DA7R#CgM$WqGO^Le3X0wnlVWX@S2 zOml$^7xIW<^Me8pa(&c24rZ8L*x;-AJT`ujOL?65WrUfJBg4zDF7rPNo4-Mt2k>en zaZlR7A2-j3oCw=lDH}1q3;M)OpDJ2(ZXK;SAKVcsp5-o(wyhq0|(#1h}5sB+2CWy8s zz7)Z{dmgGH0beSDX~=y?n-T@sE%>@Z6bdUd+jcbq0g>H7ei?K6nVD-xM9Rvec>USl z(-4gc(!w5D%ZEa8y;?L~Ux49HG4<52zNzP_4_2koqr9_Sbv%oy;@Kvm7QIHJs)QRLcbHQpGy&?Zc|S%^u%K)WlOzb3FRIG4WtclK(4sgn2VJH zSn=Xk0XF;13FAFf>TBjaH-afoCkmo`AEjg=kOERs97RO{Wngmc3y_<%T(D{7OwOUaJw<1a+r*xvBO7~b2; za33aB&i@DrYzKGIc0_}6@cB63Cn#;N$|4UpO8#lGvccpMeJ~2}5FHfwRKD!q>?dJ) zcte|ro{~{&oA5D0U~av)v5JZMp@@S=-EeO_(_}}!(RG3I^I_VZS2DGEa||`X zE^a{)Y1Eq2iejetdX?ir|L-|v^RW3>_UKegaeI|z&$^xz6}=v_dZAHq^u>5@uH!Tw z15G2lK0y&_J&HzvP#TJOQm2kce~8Q)@z8P1Y{89ou8e6?ZQT zxjXdfvO%5n8R0p0pKR>Pm63gGPajgh3zM&Dgo4_Ki0O!XH>0<0D$k1aT*(n#Jx%qN zMkM~jz!~;{9&`kPVwYV1$_;T}Ps7?|ShZ!ykGmq9=1pn6(fo(hnK|QDP5fL;{$)gUt%mIddSxOs~Z6_9DxTXAX z|GUu9Mn|eR^t@kv525rJfp|RB7kCmzglfR!!IM70f;9+w+A*C^opoT%X$j0^*-uiWKBxe%TD`&=EQP zOR1yciHr5Eoo@>_)68S&0ha`7>YcIMjkq4ez)%zqCx zBaKNX-rm)Dy8y3Q`FHG+&@)~dV)-lFOq7XF-W30UTIIn?w8S>$Nl#ygl1eQ6Kw(73@FJZ-wP}BlpqrKd3O+r69ZkTz z1yuCvcQIf4*FvqGzzx*al*vK;AO!MD*wr z@^W>c4L>q(imR0E`I_l_K;UoCV@BC+SXT9s6)b$O+>xA34vojnXHii{Y4) z%Pxd=vjN$h6Dvx6N4QgC@7Q0CdDj?<)ocbAO|>xk5VTMF_X z(gD`}2N=vCSphoRS_~ zsKw}rChZtuS9=ER!t*r!E>7J57$3@qrYdTRU!zHan)3trY9pc+Gd3D?>n16LYk|}F zk-i3kfOC{7Q4}`&kUOJ`k_G^)?Hnc&hy9|hOX0y~b)(e}KF}ty&^C;r(aonjL z5|>}C?lyf*3hKqB~tWLs{W9;j@Nm|s`)M=4VVZ)er& zkqPb(5moV_9pAv%0#PLZPDgkcq#Dr>G9jYQs^JUsPYm%b}-`Fw5r@4Y=IF`brm<`XO{Z${!GjH|_pDxHB)+~6I- z>>Zzi`=BIsH-#-0*+mA)=Y7O9EaDVoC+Q_twjcKr$yTx!0+jd+<*Wb6O(Gfax=>_VY$RwNv^}Ug zpZj`0s6&6+oE{{SM$bs0Sa7sD=EHwsM5EU$e}Suaqw##JZ15W@Vr}p#YJ^?m`j=Q8 z&~nVsP%@4H)E*%HNdU!ob?33%!540Z^@ApmQU~lYKP5$~@74=?mcLw{oKOtmtYiCa zpG63H{a=|SVROBexdJ`Y7GFfDm5uvv$?|+GHK4l}=yA^+3VB6${Lx!o3(M8~UK1)y zt6JHjxmv?DwKh-S6zeaner%6j%xG{}_Rz0+>H?YohUMsDwW339!gxT(gcEGKa3R*I z@4q{uPE!k03>P7E6oNV4Hfxh81{7ZIYgx)k45KN@8lD=3A9ELT87E)6BFXs37^n*R z=#BD5AseeI4_sVF5nqdC53A4OWACz?c_Oxc1%yi$;m5*uEFL)LL0>Bl{}E&M;AYdQ zvT6tf2xn~A8#QpHJG`bvC5U^yCUroRq*HA5bZB<+7Aa#D`HgSM42<&bpBdKsg_u^A zt$3LYd?A1uQYYO6a3ghPKR#$hh7~)1+jYd#+yQGzFr*i&QBjxMc>VsPS_0;o-dYrL z&%Rhtw(t@N==ggthF6kIlU^#^jJI>M?i|}6U_rzv3SAwY*<%T3-VQvtgDc%!jF1X8 ze6nw1BaJpXmQhYGfxqPkEGRo?bb*VCIRRFmaRycmrf7_bMx5Kf@puzEDweDk?KIR5 z_h%iBVK<1bUey-F3}YPhU|*>eg@yv&f1O#g!4$KQu46ApS4wB7Cg}o1bhDS{>?N=q z(As9hl|(w_EW@X<>{)0+!!->S*(~YYAZuKC7|o=2r4Go0oFp43Pe_1j_Q_n54yG_4 zZ&Fl2Shngt4?x&@Ae$H1g>EfWp|0zYzOhgs-g&m%*5}Mm8<}8*t)V3n{k6* znv$E_f=(b2%gBey`8C0FNArBiZIBWP2x9UD7)HFdT{-=>y<)=m*CTKazNBbee$*k` z7L4uBU5FfW5k`4ut7cTu?c|DWB$_8>ZCKo_|8Z{F*+XknMaVWY;XIx=-LV=cAZ)6T zCJG&&hjFB3G%&g14%2?B-2Ky$1XgJP^p#PU$vxod`lll6{{dV;qrXQhG32mW-_8T$ z^!IYayZ;H{BS=p@j5Wpmz{aENHrk3MRRNC9CZU z*gtg30c^zge#jR@1$(4)6~}l&sWSFXA6tLuMW^0(KOt2#SQ6f?VUs{V#U1iA4|$G> zR#x=UU1DZJk7>OC=-D`_(GkE7yOjGzoTnbAwCLvn^a z0Q5NV`nat9R$EEqmzN}<+i(IPF8kS26i=9U6sU(jHE#`OeP|6iyl=2J7`OVR8GwH> zYx|*h9tHo$r4^7Z!Z@tB)M_G9p7i(l^>^AP*w!t0C^DhpNegpA<8Zewi7e!hcFeC> zS0quL!#klD_j$NKt5*3`Z@}_3U`CJAz1uHkKTKlHZ)FSH1OYNBm{dX9IVb~3FT}B$ zKVZ?yG?(h5SLYd6A$5h6i-OrxlHGp^ioH#Lra!u~%OOyZbQnY=qu0u*P8C?gsXZB&i_R>@ zj%3kQ)(@{7&{zbuyG&8lf79^&$tm7^u3apvx}h2Dq|_URe|wxOuvg(@ z{i&AQ@LIp^N+E5I$CV8%4(-k=_isAP>a)F1op5$L6;myEpcIx6?UdE}616lT{0%tg zGOKwKI@YWKr>~A_^NpDPv(tYK=itd_yLn~N1Tf-3-%jV>_~L(K8#@s~XaYZvog_G7)M&NOxziDL!vC_RrGY5kTQ3#sh-RXbt?!)oM?VGgXwECof`a}k! zP2Wg90c}56!450nDipl4;?hSzIG;K8t%T2ap^F)ncVCXE^lG`|kXe5^8lI=9|H(X9 z1qAM7o$btGSG0PZ&JYn;Pn54+uP8ePLP^u?ZP0Tq3LF=1VYarWk#B`{W9!U+!$ZPE z_Ze-Tf|?fzc_=wb(Fp&*CWdJp3b&Cy3(5?}VB!4b2F`pi@`2~e@VKFQ!BDIVJbk%l zP$q{?1|xZY7Y?@$eFlGhQ^JP_jD#{`y(1VT>sZK=1RYI`p;B$ec`u?$myS6@M!^d5=#4=Qk zwgXqqTP=bN% zX<0;PQ6=sh$vuAp6q1SFlKsKx-WDR&qRMiU{vv?x1$A)BZqR|KWNiS&NLdmw7{2?8 zWt4{gl%t@o@{N)9h5u=(yJk#C$!@RJyw0xr=o1pK$2^UoyQ-MpaPM(&+Fb^QX!ltt z0&KJMP?YBDxozlZry{a?{-P+ZsoDK^e@XA>+Q$0!zCeFIv^#;xy(Hy5ZRJ8qF0z?3 zfUMwWVH;amF8TGQiM(8pPW{U;8XR#One#BQ5J{wj706Fun`u_EAmyM!3#OvaWgq9G zoN=jd=niO7`9zjQ`78MvvW3^Cd(hPZBW0|kT(_49%*}EyP}W$Hk-eS}fkd4+O~Y^q)t1>0K}ub1ztAUsU(=GRZk?Dv`|gu&={(%qZh zeddJj+MdLQ?J}?ZEnTwSrqVvqNlU$p8|d?1fCgZcH8(Sr*4WycoWj252ZBdcfZ;SU zTmHsLBj3lGL5Bi*jNV2ktEC;3a>uEgZ_E_hp~WE~$-vO11fpfPqjk zj)RAf6m*VA7o=4ygr@PBV0kyy+vua2QyiASJyC>Qu#ORcm#1)|l>lLzw$t}%{h-+R z%e|sXCG``WA+JUSv3-twlpHQDX}z9;wS7DWYo$F}yD<+XRWxnkjkK99nu&g33%=@R zBb0x=DHa+Q?gcf<640^J$R#svUvuUj-WQv$vW4R)(p}AVcYdc*ujqSnFsG1tegY@M zz8|b^`KcU|$)f4EP~K?|z0RTR(!|k}gD?yFHFfI(9_Lch9Xh-UF=KS}LFwPk%7i~} z0r%i#2q{>g-78u57_El@zF#NvsTF~~_rHJQQMQ9d&msBE*&($HqO9s$To>w>H~0f* z9~O9u2eQ6{-ND&8;pr)T7=y3b`4O#!WlxTF+ru-{B0lXyM}GccEQ52iU(<%5oelf7 z^1_lc0kuCxMLJ`YrGV7gkiQzQAz#9@(oAkJXVX+#`Hr*xG{M1anBEj>L*C;-B3gfX zn5R-S!_ZR?!z#_f*07gb?6ogp>Li&C-E(X|rzV9(_F9a{`gvH-6W6SR7^#*;Na0pA zoJjJnx-@WzP`2JCj?Bs!29*&1ZiN~p%o2%Zl&!pP%;zo3-((I^i-r7wUq(d(qVu7U z)MqN=)YA`KQ)UNZUj}VqI!i)y-6T+J%qQ z2J`K8sD$_VwjkP<0%q=drd}dXmf!5y(SBO{S|905o&`&N839`wleLryO4sU*Dz7w+ zFK1uV`0E^zp)GaC_DT^`Jc~B&iI;5d%?IF4HF=bip*840<5F zoOixBwBC|$?2I1x8|x2lx{rT4)}kNh_A@>#O}klN=;^t2B7B6*V}8bCz}lM%YmZ(>fpZi1y{Y>OJJiVg>H-K)FCJPhraJ2ihfpgz55)%jQ- zD8gC~0>9qHI&X(tV>Y7x*=s}Rx1rCg#0rI9ckZcFKHQqk@8P9C5KjQtySuCoGlR9o z_^d7KS*QM4zUkY5%8VUZ6Ap_H>pk%E97Dr-w z%2HGJ@Z}BiT$3QA)FFT9)?kHO$?uxXK0%4h;Lhj;^{t1IULP!Q*vX7IUg0&iomgcP+xTs z^F{`CpQ_6;QI3vVHx^7!X~9;%VJ2?b2rXbuOqfOQK1V4#sZW2FScY0s@&t|d6`kJe z5kdEug9ATz;z!`lk2MtMXy3G#pb|m#Y;?1V!GSwtJi$HczO56c*i?Lvd+{CB|4xf{ zXDO%h1b!%&I?$;Z!qf?Jg zdq^DMaA2VFK%0Mn{P9@E(JCauI_%M63?FCKXNAmVlc;mB!nQi5t#d53^Rid|B*)h1 zR%;x)hS96t=R0)K+ZxpY0KNxq<#TR%Jv5WGEA}sFK!FeP^9c6cc3xIwdUdJ`-wtv` zThnJ}BjTPPP8_O6L-I@GrH~7_0a%zz1AV*3PbaBGh_infPWGR-Y@p-G;v~CHGyJ{M zLr>Or&Ic-e%cRjt_d_-78l07RuCZodu#tS`El8%CFctw@>Z?MSTO*L*NIMF(kgDbJ z*SpufnWk=NKR?<&5{1no)P}ujZF*QSir=IAXP+gTDz%F>fliqm9Q5kq2@fFU6BFN9 z1dWS(@=kvmF`PbbLEM_5&RxUb7jzmVD4kMWvXPG39t8Rtr)0?2WXW(g)704L*>w0==1O2QB52xMMy>rTes)eE& zCsh38b(qX2{LwnoDE61ir1bg$YGgOwB};c-aKMMVGIl`;B*T=lmuf8H6_eti|<8B$)_eD$6TUM>p;%4><5e#f8$N*4aErG$k?$ z`;Kmz+rMpuOPjJSmV;mO%O3GLasT7XGI;TU#g25vDcPyUByxxWECU!vQV3W$SVscp zMbe3f80)D}X&u(*?}Q@~1#1B}DN~LVl&r!DReGCIjQIpQ=z6`d0T)xPt9XBI8$$Do zW{RO3aY{}xC>Q2%lUb&N^sOl(!6wdXZ7@lX7Imt0nV9*S$y=}(L^B`nwk)zM`vixJ zZbcWU@pUdI^miO02_Lu8B?{guotv;$63k%HbNKJk&s3Ka`h!4jVfs_uJo3HOOd@jcGfrh6ML z0_M%4kT>nt6o^#Tr}(?{3!#?2rBV!g(EvTCppa-=wg7NL0SgFxRip-$`^zzSPdsJ$ z`S69$cI+ahQ9VrU6!|e)KiVYKRw5n90`A1(v%h4bS*0k z3i)s+`7GVig7mivf@TnxzqYVJj$U~??2<@-?gS;Hh3W*RXtLAodOF(#{}^alrzKKr z-@;X;4$bsRs@s+P)^$~1A5@tIt5#$a=yRcjt*_H<3x|dIi|Cgrcg8bpM_hBV0#X5c z=;9qNgquqc^=BNN0HA-Lc=wlJxYxK_>K4*gCRBxaQEF7(LvAAt6oz4wU@Nfa!pQSt zouvK4p&SV6TK%jT*6pPDS@^pCuXCQQiTGcE<_%`4($Xg3Y|89jGWSw5&}r-f#oJ?c z=M6oZ2uHkvr2K%uO!%rzsJ1d*PBjkUK>+dIBEn_ZvDs-

© COPYRIGHT 2010 STMicroelectronics

+ ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f10x + * @{ + */ + +#ifndef __STM32F10x_H +#define __STM32F10x_H + +#ifdef __cplusplus + extern "C" { +#endif + +#define assert_param(__p) + + +/** @addtogroup Library_configuration_section + * @{ + */ + +/* Uncomment the line below according to the target STM32 device used in your + application + */ + +#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL) + /* #define STM32F10X_LD */ /*!< STM32F10X_LD: STM32 Low density devices */ + /* #define STM32F10X_LD_VL */ /*!< STM32F10X_LD_VL: STM32 Low density Value Line devices */ + /* #define STM32F10X_MD */ /*!< STM32F10X_MD: STM32 Medium density devices */ + /* #define STM32F10X_MD_VL */ /*!< STM32F10X_MD_VL: STM32 Medium density Value Line devices */ + /* #define STM32F10X_HD */ /*!< STM32F10X_HD: STM32 High density devices */ + #define STM32F10X_XL /*!< STM32F10X_XL: STM32 XL-density devices */ + /* #define STM32F10X_CL */ /*!< STM32F10X_CL: STM32 Connectivity line devices */ +#endif +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + + - Low density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers + where the Flash memory density ranges between 16 and 32 Kbytes. + - Low-density value line devices are STM32F100xx microcontrollers where the Flash + memory density ranges between 16 and 32 Kbytes. + - Medium density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers + where the Flash memory density ranges between 64 and 128 Kbytes. + - Medium-density value line devices are STM32F100xx microcontrollers where the + Flash memory density ranges between 64 and 128 Kbytes. + - High density devices are STM32F101xx and STM32F103xx microcontrollers where + the Flash memory density ranges between 256 and 512 Kbytes. + - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where + the Flash memory density ranges between 512 and 1024 Kbytes. + - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. + */ + +#if !defined USE_STDPERIPH_DRIVER +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ + /*#define USE_STDPERIPH_DRIVER*/ +#endif + +/** + * @brief In the following line adjust the value of External High Speed oscillator (HSE) + used in your application + + Tip: To avoid modifying this file each time you need to use different HSE, you + can define the HSE value in your toolchain compiler preprocessor. + */ +#if !defined HSE_VALUE + #ifdef STM32F10X_CL + #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ + #else + #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ + #endif /* STM32F10X_CL */ +#endif /* HSE_VALUE */ + + +/** + * @brief In the following line adjust the External High Speed oscillator (HSE) Startup + Timeout value + */ +#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */ + +#define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/ + +/** + * @brief STM32F10x Standard Peripheral Library version number + */ +#define __STM32F10X_STDPERIPH_VERSION_MAIN (0x03) /*!< [31:16] STM32F10x Standard Peripheral Library main version */ +#define __STM32F10X_STDPERIPH_VERSION_SUB1 (0x03) /*!< [15:8] STM32F10x Standard Peripheral Library sub1 version */ +#define __STM32F10X_STDPERIPH_VERSION_SUB2 (0x00) /*!< [7:0] STM32F10x Standard Peripheral Library sub2 version */ +#define __STM32F10X_STDPERIPH_VERSION ((__STM32F10X_STDPERIPH_VERSION_MAIN << 16)\ + | (__STM32F10X_STDPERIPH_VERSION_SUB1 << 8)\ + | __STM32F10X_STDPERIPH_VERSION_SUB2) + +/** + * @} + */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M3 Processor and Core Peripherals + */ +#ifdef STM32F10X_XL + #define __MPU_PRESENT 1 /*!< STM32 XL-density devices provide an MPU */ +#else + #define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */ +#endif /* STM32F10X_XL */ +#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * @brief STM32F10x Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum IRQn +{ +/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ + +/****** STM32 specific Interrupt Numbers *********************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMPER_IRQn = 2, /*!< Tamper Interrupt */ + RTC_IRQn = 3, /*!< RTC global Interrupt */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ + +#ifdef STM32F10X_LD + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ + USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + USBWakeUp_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ +#endif /* STM32F10X_LD */ + +#ifdef STM32F10X_LD_VL + ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ + TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ + TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */ + TIM7_IRQn = 55 /*!< TIM7 Interrupt */ +#endif /* STM32F10X_LD_VL */ + +#ifdef STM32F10X_MD + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ + USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + USBWakeUp_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ +#endif /* STM32F10X_MD */ + +#ifdef STM32F10X_MD_VL + ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ + TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ + TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */ + TIM7_IRQn = 55 /*!< TIM7 Interrupt */ +#endif /* STM32F10X_MD_VL */ + +#ifdef STM32F10X_HD + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ + USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ + TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */ + TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ + TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ + FSMC_IRQn = 48, /*!< FSMC global Interrupt */ + SDIO_IRQn = 49, /*!< SDIO global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ + TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ +#endif /* STM32F10X_HD */ + +#ifdef STM32F10X_XL + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ + USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break Interrupt and TIM9 global Interrupt */ + TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global Interrupt */ + TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ + TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global Interrupt */ + TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global Interrupt */ + TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ + FSMC_IRQn = 48, /*!< FSMC global Interrupt */ + SDIO_IRQn = 49, /*!< SDIO global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ + TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ +#endif /* STM32F10X_XL */ + +#ifdef STM32F10X_CL + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ + CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS WakeUp from suspend through EXTI Line Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ + TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ + DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ + ETH_IRQn = 61, /*!< Ethernet global Interrupt */ + ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ + CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ + CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ + CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ + CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ + OTG_FS_IRQn = 67 /*!< USB OTG FS global Interrupt */ +#endif /* STM32F10X_CL */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm3.h" +#include "system_stm32f10x.h" +#include + +/** @addtogroup Exported_types + * @{ + */ + +/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */ +typedef int32_t s32; +typedef int16_t s16; +typedef int8_t s8; + +typedef const int32_t sc32; /*!< Read Only */ +typedef const int16_t sc16; /*!< Read Only */ +typedef const int8_t sc8; /*!< Read Only */ + +typedef __IO int32_t vs32; +typedef __IO int16_t vs16; +typedef __IO int8_t vs8; + +typedef __I int32_t vsc32; /*!< Read Only */ +typedef __I int16_t vsc16; /*!< Read Only */ +typedef __I int8_t vsc8; /*!< Read Only */ + +typedef uint32_t u32; +typedef uint16_t u16; +typedef uint8_t u8; + +typedef const uint32_t uc32; /*!< Read Only */ +typedef const uint16_t uc16; /*!< Read Only */ +typedef const uint8_t uc8; /*!< Read Only */ + +typedef __IO uint32_t vu32; +typedef __IO uint16_t vu16; +typedef __IO uint8_t vu8; + +typedef __I uint32_t vuc32; /*!< Read Only */ +typedef __I uint16_t vuc16; /*!< Read Only */ +typedef __I uint8_t vuc8; /*!< Read Only */ + +#ifndef __cplusplus +typedef enum {FALSE = 0, TRUE = !FALSE} bool; +#endif + +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; + +/*!< STM32F10x Standard Peripheral Library old definitions (maintained for legacy purpose) */ +#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT +#define HSE_Value HSE_VALUE +#define HSI_Value HSI_VALUE +/** + * @} + */ + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t SR; + __IO uint32_t CR1; + __IO uint32_t CR2; + __IO uint32_t SMPR1; + __IO uint32_t SMPR2; + __IO uint32_t JOFR1; + __IO uint32_t JOFR2; + __IO uint32_t JOFR3; + __IO uint32_t JOFR4; + __IO uint32_t HTR; + __IO uint32_t LTR; + __IO uint32_t SQR1; + __IO uint32_t SQR2; + __IO uint32_t SQR3; + __IO uint32_t JSQR; + __IO uint32_t JDR1; + __IO uint32_t JDR2; + __IO uint32_t JDR3; + __IO uint32_t JDR4; + __IO uint32_t DR; +} ADC_TypeDef; + +/** + * @brief Backup Registers + */ + +typedef struct +{ + uint32_t RESERVED0; + __IO uint16_t DR1; + uint16_t RESERVED1; + __IO uint16_t DR2; + uint16_t RESERVED2; + __IO uint16_t DR3; + uint16_t RESERVED3; + __IO uint16_t DR4; + uint16_t RESERVED4; + __IO uint16_t DR5; + uint16_t RESERVED5; + __IO uint16_t DR6; + uint16_t RESERVED6; + __IO uint16_t DR7; + uint16_t RESERVED7; + __IO uint16_t DR8; + uint16_t RESERVED8; + __IO uint16_t DR9; + uint16_t RESERVED9; + __IO uint16_t DR10; + uint16_t RESERVED10; + __IO uint16_t RTCCR; + uint16_t RESERVED11; + __IO uint16_t CR; + uint16_t RESERVED12; + __IO uint16_t CSR; + uint16_t RESERVED13[5]; + __IO uint16_t DR11; + uint16_t RESERVED14; + __IO uint16_t DR12; + uint16_t RESERVED15; + __IO uint16_t DR13; + uint16_t RESERVED16; + __IO uint16_t DR14; + uint16_t RESERVED17; + __IO uint16_t DR15; + uint16_t RESERVED18; + __IO uint16_t DR16; + uint16_t RESERVED19; + __IO uint16_t DR17; + uint16_t RESERVED20; + __IO uint16_t DR18; + uint16_t RESERVED21; + __IO uint16_t DR19; + uint16_t RESERVED22; + __IO uint16_t DR20; + uint16_t RESERVED23; + __IO uint16_t DR21; + uint16_t RESERVED24; + __IO uint16_t DR22; + uint16_t RESERVED25; + __IO uint16_t DR23; + uint16_t RESERVED26; + __IO uint16_t DR24; + uint16_t RESERVED27; + __IO uint16_t DR25; + uint16_t RESERVED28; + __IO uint16_t DR26; + uint16_t RESERVED29; + __IO uint16_t DR27; + uint16_t RESERVED30; + __IO uint16_t DR28; + uint16_t RESERVED31; + __IO uint16_t DR29; + uint16_t RESERVED32; + __IO uint16_t DR30; + uint16_t RESERVED33; + __IO uint16_t DR31; + uint16_t RESERVED34; + __IO uint16_t DR32; + uint16_t RESERVED35; + __IO uint16_t DR33; + uint16_t RESERVED36; + __IO uint16_t DR34; + uint16_t RESERVED37; + __IO uint16_t DR35; + uint16_t RESERVED38; + __IO uint16_t DR36; + uint16_t RESERVED39; + __IO uint16_t DR37; + uint16_t RESERVED40; + __IO uint16_t DR38; + uint16_t RESERVED41; + __IO uint16_t DR39; + uint16_t RESERVED42; + __IO uint16_t DR40; + uint16_t RESERVED43; + __IO uint16_t DR41; + uint16_t RESERVED44; + __IO uint16_t DR42; + uint16_t RESERVED45; +} BKP_TypeDef; + +/** + * @brief Controller Area Network TxMailBox + */ + +typedef struct +{ + __IO uint32_t TIR; + __IO uint32_t TDTR; + __IO uint32_t TDLR; + __IO uint32_t TDHR; +} CAN_TxMailBox_TypeDef; + +/** + * @brief Controller Area Network FIFOMailBox + */ + +typedef struct +{ + __IO uint32_t RIR; + __IO uint32_t RDTR; + __IO uint32_t RDLR; + __IO uint32_t RDHR; +} CAN_FIFOMailBox_TypeDef; + +/** + * @brief Controller Area Network FilterRegister + */ + +typedef struct +{ + __IO uint32_t FR1; + __IO uint32_t FR2; +} CAN_FilterRegister_TypeDef; + +/** + * @brief Controller Area Network + */ + +typedef struct +{ + __IO uint32_t MCR; + __IO uint32_t MSR; + __IO uint32_t TSR; + __IO uint32_t RF0R; + __IO uint32_t RF1R; + __IO uint32_t IER; + __IO uint32_t ESR; + __IO uint32_t BTR; + uint32_t RESERVED0[88]; + CAN_TxMailBox_TypeDef sTxMailBox[3]; + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; + uint32_t RESERVED1[12]; + __IO uint32_t FMR; + __IO uint32_t FM1R; + uint32_t RESERVED2; + __IO uint32_t FS1R; + uint32_t RESERVED3; + __IO uint32_t FFA1R; + uint32_t RESERVED4; + __IO uint32_t FA1R; + uint32_t RESERVED5[8]; +#ifndef STM32F10X_CL + CAN_FilterRegister_TypeDef sFilterRegister[14]; +#else + CAN_FilterRegister_TypeDef sFilterRegister[28]; +#endif /* STM32F10X_CL */ +} CAN_TypeDef; + +/** + * @brief Consumer Electronics Control (CEC) + */ +typedef struct +{ + __IO uint32_t CFGR; + __IO uint32_t OAR; + __IO uint32_t PRES; + __IO uint32_t ESR; + __IO uint32_t CSR; + __IO uint32_t TXD; + __IO uint32_t RXD; +} CEC_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; + __IO uint8_t IDR; + uint8_t RESERVED0; + uint16_t RESERVED1; + __IO uint32_t CR; +} CRC_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t SWTRIGR; + __IO uint32_t DHR12R1; + __IO uint32_t DHR12L1; + __IO uint32_t DHR8R1; + __IO uint32_t DHR12R2; + __IO uint32_t DHR12L2; + __IO uint32_t DHR8R2; + __IO uint32_t DHR12RD; + __IO uint32_t DHR12LD; + __IO uint32_t DHR8RD; + __IO uint32_t DOR1; + __IO uint32_t DOR2; +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) + __IO uint32_t SR; +#endif +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; + __IO uint32_t CR; +}DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCR; + __IO uint32_t CNDTR; + __IO uint32_t CPAR; + __IO uint32_t CMAR; +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; + __IO uint32_t IFCR; +} DMA_TypeDef; + +/** + * @brief Ethernet MAC + */ + +typedef struct +{ + __IO uint32_t MACCR; + __IO uint32_t MACFFR; + __IO uint32_t MACHTHR; + __IO uint32_t MACHTLR; + __IO uint32_t MACMIIAR; + __IO uint32_t MACMIIDR; + __IO uint32_t MACFCR; + __IO uint32_t MACVLANTR; /* 8 */ + uint32_t RESERVED0[2]; + __IO uint32_t MACRWUFFR; /* 11 */ + __IO uint32_t MACPMTCSR; + uint32_t RESERVED1[2]; + __IO uint32_t MACSR; /* 15 */ + __IO uint32_t MACIMR; + __IO uint32_t MACA0HR; + __IO uint32_t MACA0LR; + __IO uint32_t MACA1HR; + __IO uint32_t MACA1LR; + __IO uint32_t MACA2HR; + __IO uint32_t MACA2LR; + __IO uint32_t MACA3HR; + __IO uint32_t MACA3LR; /* 24 */ + uint32_t RESERVED2[40]; + __IO uint32_t MMCCR; /* 65 */ + __IO uint32_t MMCRIR; + __IO uint32_t MMCTIR; + __IO uint32_t MMCRIMR; + __IO uint32_t MMCTIMR; /* 69 */ + uint32_t RESERVED3[14]; + __IO uint32_t MMCTGFSCCR; /* 84 */ + __IO uint32_t MMCTGFMSCCR; + uint32_t RESERVED4[5]; + __IO uint32_t MMCTGFCR; + uint32_t RESERVED5[10]; + __IO uint32_t MMCRFCECR; + __IO uint32_t MMCRFAECR; + uint32_t RESERVED6[10]; + __IO uint32_t MMCRGUFCR; + uint32_t RESERVED7[334]; + __IO uint32_t PTPTSCR; + __IO uint32_t PTPSSIR; + __IO uint32_t PTPTSHR; + __IO uint32_t PTPTSLR; + __IO uint32_t PTPTSHUR; + __IO uint32_t PTPTSLUR; + __IO uint32_t PTPTSAR; + __IO uint32_t PTPTTHR; + __IO uint32_t PTPTTLR; + uint32_t RESERVED8[567]; + __IO uint32_t DMABMR; + __IO uint32_t DMATPDR; + __IO uint32_t DMARPDR; + __IO uint32_t DMARDLAR; + __IO uint32_t DMATDLAR; + __IO uint32_t DMASR; + __IO uint32_t DMAOMR; + __IO uint32_t DMAIER; + __IO uint32_t DMAMFBOCR; + uint32_t RESERVED9[9]; + __IO uint32_t DMACHTDR; + __IO uint32_t DMACHRDR; + __IO uint32_t DMACHTBAR; + __IO uint32_t DMACHRBAR; +} ETH_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; + __IO uint32_t EMR; + __IO uint32_t RTSR; + __IO uint32_t FTSR; + __IO uint32_t SWIER; + __IO uint32_t PR; +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; + __IO uint32_t KEYR; + __IO uint32_t OPTKEYR; + __IO uint32_t SR; + __IO uint32_t CR; + __IO uint32_t AR; + __IO uint32_t RESERVED; + __IO uint32_t OBR; + __IO uint32_t WRPR; +#ifdef STM32F10X_XL + uint32_t RESERVED1[8]; + __IO uint32_t KEYR2; + uint32_t RESERVED2; + __IO uint32_t SR2; + __IO uint32_t CR2; + __IO uint32_t AR2; +#endif /* STM32F10X_XL */ +} FLASH_TypeDef; + +/** + * @brief Option Bytes Registers + */ + +typedef struct +{ + __IO uint16_t RDP; + __IO uint16_t USER; + __IO uint16_t Data0; + __IO uint16_t Data1; + __IO uint16_t WRP0; + __IO uint16_t WRP1; + __IO uint16_t WRP2; + __IO uint16_t WRP3; +} OB_TypeDef; + +/** + * @brief Flexible Static Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; +} FSMC_Bank1_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; +} FSMC_Bank1E_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank2 + */ + +typedef struct +{ + __IO uint32_t PCR2; + __IO uint32_t SR2; + __IO uint32_t PMEM2; + __IO uint32_t PATT2; + uint32_t RESERVED0; + __IO uint32_t ECCR2; +} FSMC_Bank2_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR3; + __IO uint32_t SR3; + __IO uint32_t PMEM3; + __IO uint32_t PATT3; + uint32_t RESERVED0; + __IO uint32_t ECCR3; +} FSMC_Bank3_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank4 + */ + +typedef struct +{ + __IO uint32_t PCR4; + __IO uint32_t SR4; + __IO uint32_t PMEM4; + __IO uint32_t PATT4; + __IO uint32_t PIO4; +} FSMC_Bank4_TypeDef; + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t CRL; + __IO uint32_t CRH; + __IO uint32_t IDR; + __IO uint32_t ODR; + __IO uint32_t BSRR; + __IO uint32_t BRR; + __IO uint32_t LCKR; +} GPIO_TypeDef; + +/** + * @brief Alternate Function I/O + */ + +typedef struct +{ + __IO uint32_t EVCR; + __IO uint32_t MAPR; + __IO uint32_t EXTICR[4]; + uint32_t RESERVED0; + __IO uint32_t MAPR2; +} AFIO_TypeDef; +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint16_t CR1; + uint16_t RESERVED0; + __IO uint16_t CR2; + uint16_t RESERVED1; + __IO uint16_t OAR1; + uint16_t RESERVED2; + __IO uint16_t OAR2; + uint16_t RESERVED3; + __IO uint16_t DR; + uint16_t RESERVED4; + __IO uint16_t SR1; + uint16_t RESERVED5; + __IO uint16_t SR2; + uint16_t RESERVED6; + __IO uint16_t CCR; + uint16_t RESERVED7; + __IO uint16_t TRISE; + uint16_t RESERVED8; +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; + __IO uint32_t PR; + __IO uint32_t RLR; + __IO uint32_t SR; +} IWDG_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t CSR; +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t CFGR; + __IO uint32_t CIR; + __IO uint32_t APB2RSTR; + __IO uint32_t APB1RSTR; + __IO uint32_t AHBENR; + __IO uint32_t APB2ENR; + __IO uint32_t APB1ENR; + __IO uint32_t BDCR; + __IO uint32_t CSR; + +#ifdef STM32F10X_CL + __IO uint32_t AHBRSTR; + __IO uint32_t CFGR2; +#endif /* STM32F10X_CL */ + +#if defined STM32F10X_LD_VL || defined STM32F10X_MD_VL + uint32_t RESERVED0; + __IO uint32_t CFGR2; +#endif /* STM32F10X_LD_VL || STM32F10X_MD_VL */ +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ + +typedef struct +{ + __IO uint16_t CRH; + uint16_t RESERVED0; + __IO uint16_t CRL; + uint16_t RESERVED1; + __IO uint16_t PRLH; + uint16_t RESERVED2; + __IO uint16_t PRLL; + uint16_t RESERVED3; + __IO uint16_t DIVH; + uint16_t RESERVED4; + __IO uint16_t DIVL; + uint16_t RESERVED5; + __IO uint16_t CNTH; + uint16_t RESERVED6; + __IO uint16_t CNTL; + uint16_t RESERVED7; + __IO uint16_t ALRH; + uint16_t RESERVED8; + __IO uint16_t ALRL; + uint16_t RESERVED9; +} RTC_TypeDef; + +/** + * @brief SD host Interface + */ + +typedef struct +{ + __IO uint32_t POWER; + __IO uint32_t CLKCR; + __IO uint32_t ARG; + __IO uint32_t CMD; + __I uint32_t RESPCMD; + __I uint32_t RESP1; + __I uint32_t RESP2; + __I uint32_t RESP3; + __I uint32_t RESP4; + __IO uint32_t DTIMER; + __IO uint32_t DLEN; + __IO uint32_t DCTRL; + __I uint32_t DCOUNT; + __I uint32_t STA; + __IO uint32_t ICR; + __IO uint32_t MASK; + uint32_t RESERVED0[2]; + __I uint32_t FIFOCNT; + uint32_t RESERVED1[13]; + __IO uint32_t FIFO; +} SDIO_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint16_t CR1; + uint16_t RESERVED0; + __IO uint16_t CR2; + uint16_t RESERVED1; + __IO uint16_t SR; + uint16_t RESERVED2; + __IO uint16_t DR; + uint16_t RESERVED3; + __IO uint16_t CRCPR; + uint16_t RESERVED4; + __IO uint16_t RXCRCR; + uint16_t RESERVED5; + __IO uint16_t TXCRCR; + uint16_t RESERVED6; + __IO uint16_t I2SCFGR; + uint16_t RESERVED7; + __IO uint16_t I2SPR; + uint16_t RESERVED8; +} SPI_TypeDef; + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint16_t CR1; + uint16_t RESERVED0; + __IO uint16_t CR2; + uint16_t RESERVED1; + __IO uint16_t SMCR; + uint16_t RESERVED2; + __IO uint16_t DIER; + uint16_t RESERVED3; + __IO uint16_t SR; + uint16_t RESERVED4; + __IO uint16_t EGR; + uint16_t RESERVED5; + __IO uint16_t CCMR1; + uint16_t RESERVED6; + __IO uint16_t CCMR2; + uint16_t RESERVED7; + __IO uint16_t CCER; + uint16_t RESERVED8; + __IO uint16_t CNT; + uint16_t RESERVED9; + __IO uint16_t PSC; + uint16_t RESERVED10; + __IO uint16_t ARR; + uint16_t RESERVED11; + __IO uint16_t RCR; + uint16_t RESERVED12; + __IO uint16_t CCR1; + uint16_t RESERVED13; + __IO uint16_t CCR2; + uint16_t RESERVED14; + __IO uint16_t CCR3; + uint16_t RESERVED15; + __IO uint16_t CCR4; + uint16_t RESERVED16; + __IO uint16_t BDTR; + uint16_t RESERVED17; + __IO uint16_t DCR; + uint16_t RESERVED18; + __IO uint16_t DMAR; + uint16_t RESERVED19; +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint16_t SR; + uint16_t RESERVED0; + __IO uint16_t DR; + uint16_t RESERVED1; + __IO uint16_t BRR; + uint16_t RESERVED2; + __IO uint16_t CR1; + uint16_t RESERVED3; + __IO uint16_t CR2; + uint16_t RESERVED4; + __IO uint16_t CR3; + uint16_t RESERVED5; + __IO uint16_t GTPR; + uint16_t RESERVED6; +} USART_TypeDef; + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t CFR; + __IO uint32_t SR; +} WWDG_TypeDef; + +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ + */ + +#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the alias region */ +#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the alias region */ + +#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the bit-band region */ +#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the bit-band region */ + +#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) + +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) +#define TIM12_BASE (APB1PERIPH_BASE + 0x1800) +#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00) +#define TIM14_BASE (APB1PERIPH_BASE + 0x2000) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) +#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) +#define CAN2_BASE (APB1PERIPH_BASE + 0x6800) +#define BKP_BASE (APB1PERIPH_BASE + 0x6C00) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400) +#define CEC_BASE (APB1PERIPH_BASE + 0x7800) + +#define AFIO_BASE (APB2PERIPH_BASE + 0x0000) +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) +#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) +#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) +#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) +#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) +#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800) +#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00) +#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000) +#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) +#define ADC2_BASE (APB2PERIPH_BASE + 0x2800) +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) +#define TIM8_BASE (APB2PERIPH_BASE + 0x3400) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800) +#define ADC3_BASE (APB2PERIPH_BASE + 0x3C00) +#define TIM15_BASE (APB2PERIPH_BASE + 0x4000) +#define TIM16_BASE (APB2PERIPH_BASE + 0x4400) +#define TIM17_BASE (APB2PERIPH_BASE + 0x4800) +#define TIM9_BASE (APB2PERIPH_BASE + 0x4C00) +#define TIM10_BASE (APB2PERIPH_BASE + 0x5000) +#define TIM11_BASE (APB2PERIPH_BASE + 0x5400) + +#define SDIO_BASE (PERIPH_BASE + 0x18000) + +#define DMA1_BASE (AHBPERIPH_BASE + 0x0000) +#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) +#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) +#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) +#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) +#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) +#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) +#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) +#define DMA2_BASE (AHBPERIPH_BASE + 0x0400) +#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408) +#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C) +#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430) +#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444) +#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458) +#define RCC_BASE (AHBPERIPH_BASE + 0x1000) +#define CRC_BASE (AHBPERIPH_BASE + 0x3000) + +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */ +#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */ + +#define ETH_BASE (AHBPERIPH_BASE + 0x8000) +#define ETH_MAC_BASE (ETH_BASE) +#define ETH_MMC_BASE (ETH_BASE + 0x0100) +#define ETH_PTP_BASE (ETH_BASE + 0x0700) +#define ETH_DMA_BASE (ETH_BASE + 0x1000) + +#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) /*!< FSMC Bank1 registers base address */ +#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) /*!< FSMC Bank1E registers base address */ +#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) /*!< FSMC Bank2 registers base address */ +#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) /*!< FSMC Bank3 registers base address */ +#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) /*!< FSMC Bank4 registers base address */ + +#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */ + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ + +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define TIM12 ((TIM_TypeDef *) TIM12_BASE) +#define TIM13 ((TIM_TypeDef *) TIM13_BASE) +#define TIM14 ((TIM_TypeDef *) TIM14_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) +#define CAN2 ((CAN_TypeDef *) CAN2_BASE) +#define BKP ((BKP_TypeDef *) BKP_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) +#define CEC ((CEC_TypeDef *) CEC_BASE) +#define AFIO ((AFIO_TypeDef *) AFIO_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define TIM9 ((TIM_TypeDef *) TIM9_BASE) +#define TIM10 ((TIM_TypeDef *) TIM10_BASE) +#define TIM11 ((TIM_TypeDef *) TIM11_BASE) +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) +#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) +#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) +#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) +#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) +#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define OB ((OB_TypeDef *) OB_BASE) +#define ETH ((ETH_TypeDef *) ETH_BASE) +#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) +#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) +#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE) +#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE) +#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE) +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */ + + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */ + + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET ((uint8_t)0x01) /*!< RESET bit */ + +/******************************************************************************/ +/* */ +/* Power Control */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for PWR_CR register ********************/ +#define PWR_CR_LPDS ((uint16_t)0x0001) /*!< Low-Power Deepsleep */ +#define PWR_CR_PDDS ((uint16_t)0x0002) /*!< Power Down Deepsleep */ +#define PWR_CR_CWUF ((uint16_t)0x0004) /*!< Clear Wakeup Flag */ +#define PWR_CR_CSBF ((uint16_t)0x0008) /*!< Clear Standby Flag */ +#define PWR_CR_PVDE ((uint16_t)0x0010) /*!< Power Voltage Detector Enable */ + +#define PWR_CR_PLS ((uint16_t)0x00E0) /*!< PLS[2:0] bits (PVD Level Selection) */ +#define PWR_CR_PLS_0 ((uint16_t)0x0020) /*!< Bit 0 */ +#define PWR_CR_PLS_1 ((uint16_t)0x0040) /*!< Bit 1 */ +#define PWR_CR_PLS_2 ((uint16_t)0x0080) /*!< Bit 2 */ + +/*!< PVD level configuration */ +#define PWR_CR_PLS_2V2 ((uint16_t)0x0000) /*!< PVD level 2.2V */ +#define PWR_CR_PLS_2V3 ((uint16_t)0x0020) /*!< PVD level 2.3V */ +#define PWR_CR_PLS_2V4 ((uint16_t)0x0040) /*!< PVD level 2.4V */ +#define PWR_CR_PLS_2V5 ((uint16_t)0x0060) /*!< PVD level 2.5V */ +#define PWR_CR_PLS_2V6 ((uint16_t)0x0080) /*!< PVD level 2.6V */ +#define PWR_CR_PLS_2V7 ((uint16_t)0x00A0) /*!< PVD level 2.7V */ +#define PWR_CR_PLS_2V8 ((uint16_t)0x00C0) /*!< PVD level 2.8V */ +#define PWR_CR_PLS_2V9 ((uint16_t)0x00E0) /*!< PVD level 2.9V */ + +#define PWR_CR_DBP ((uint16_t)0x0100) /*!< Disable Backup Domain write protection */ + + +/******************* Bit definition for PWR_CSR register ********************/ +#define PWR_CSR_WUF ((uint16_t)0x0001) /*!< Wakeup Flag */ +#define PWR_CSR_SBF ((uint16_t)0x0002) /*!< Standby Flag */ +#define PWR_CSR_PVDO ((uint16_t)0x0004) /*!< PVD Output */ +#define PWR_CSR_EWUP ((uint16_t)0x0100) /*!< Enable WKUP pin */ + +/******************************************************************************/ +/* */ +/* Backup registers */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for BKP_DR1 register ********************/ +#define BKP_DR1_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR2 register ********************/ +#define BKP_DR2_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR3 register ********************/ +#define BKP_DR3_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR4 register ********************/ +#define BKP_DR4_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR5 register ********************/ +#define BKP_DR5_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR6 register ********************/ +#define BKP_DR6_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR7 register ********************/ +#define BKP_DR7_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR8 register ********************/ +#define BKP_DR8_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR9 register ********************/ +#define BKP_DR9_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR10 register *******************/ +#define BKP_DR10_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR11 register *******************/ +#define BKP_DR11_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR12 register *******************/ +#define BKP_DR12_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR13 register *******************/ +#define BKP_DR13_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR14 register *******************/ +#define BKP_DR14_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR15 register *******************/ +#define BKP_DR15_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR16 register *******************/ +#define BKP_DR16_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR17 register *******************/ +#define BKP_DR17_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/****************** Bit definition for BKP_DR18 register ********************/ +#define BKP_DR18_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR19 register *******************/ +#define BKP_DR19_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR20 register *******************/ +#define BKP_DR20_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR21 register *******************/ +#define BKP_DR21_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR22 register *******************/ +#define BKP_DR22_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR23 register *******************/ +#define BKP_DR23_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR24 register *******************/ +#define BKP_DR24_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR25 register *******************/ +#define BKP_DR25_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR26 register *******************/ +#define BKP_DR26_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR27 register *******************/ +#define BKP_DR27_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR28 register *******************/ +#define BKP_DR28_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR29 register *******************/ +#define BKP_DR29_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR30 register *******************/ +#define BKP_DR30_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR31 register *******************/ +#define BKP_DR31_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR32 register *******************/ +#define BKP_DR32_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR33 register *******************/ +#define BKP_DR33_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR34 register *******************/ +#define BKP_DR34_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR35 register *******************/ +#define BKP_DR35_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR36 register *******************/ +#define BKP_DR36_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR37 register *******************/ +#define BKP_DR37_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR38 register *******************/ +#define BKP_DR38_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR39 register *******************/ +#define BKP_DR39_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR40 register *******************/ +#define BKP_DR40_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR41 register *******************/ +#define BKP_DR41_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR42 register *******************/ +#define BKP_DR42_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/****************** Bit definition for BKP_RTCCR register *******************/ +#define BKP_RTCCR_CAL ((uint16_t)0x007F) /*!< Calibration value */ +#define BKP_RTCCR_CCO ((uint16_t)0x0080) /*!< Calibration Clock Output */ +#define BKP_RTCCR_ASOE ((uint16_t)0x0100) /*!< Alarm or Second Output Enable */ +#define BKP_RTCCR_ASOS ((uint16_t)0x0200) /*!< Alarm or Second Output Selection */ + +/******************** Bit definition for BKP_CR register ********************/ +#define BKP_CR_TPE ((uint8_t)0x01) /*!< TAMPER pin enable */ +#define BKP_CR_TPAL ((uint8_t)0x02) /*!< TAMPER pin active level */ + +/******************* Bit definition for BKP_CSR register ********************/ +#define BKP_CSR_CTE ((uint16_t)0x0001) /*!< Clear Tamper event */ +#define BKP_CSR_CTI ((uint16_t)0x0002) /*!< Clear Tamper Interrupt */ +#define BKP_CSR_TPIE ((uint16_t)0x0004) /*!< TAMPER Pin interrupt enable */ +#define BKP_CSR_TEF ((uint16_t)0x0100) /*!< Tamper Event Flag */ +#define BKP_CSR_TIF ((uint16_t)0x0200) /*!< Tamper Interrupt Flag */ + +/******************************************************************************/ +/* */ +/* Reset and Clock Control */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for RCC_CR register ********************/ +#define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */ +#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */ +#define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */ +#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */ +#define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */ +#define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */ +#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */ +#define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */ +#define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */ +#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */ + +#ifdef STM32F10X_CL + #define RCC_CR_PLL2ON ((uint32_t)0x04000000) /*!< PLL2 enable */ + #define RCC_CR_PLL2RDY ((uint32_t)0x08000000) /*!< PLL2 clock ready flag */ + #define RCC_CR_PLL3ON ((uint32_t)0x10000000) /*!< PLL3 enable */ + #define RCC_CR_PLL3RDY ((uint32_t)0x20000000) /*!< PLL3 clock ready flag */ +#endif /* STM32F10X_CL */ + +/******************* Bit definition for RCC_CFGR register *******************/ +/*!< SW configuration */ +#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */ +#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */ + +#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */ +#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */ +#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */ + +/*!< SWS configuration */ +#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */ +#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */ +#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */ +#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */ + +/*!< HPRE configuration */ +#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */ +#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */ +#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */ +#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */ +#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */ +#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */ +#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */ +#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */ +#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */ +#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */ + +/*!< PPRE1 configuration */ +#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */ +#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */ + +#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ +#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */ +#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */ +#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */ +#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */ + +/*!< PPRE2 configuration */ +#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */ +#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */ +#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */ +#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */ + +#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ +#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */ +#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */ +#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */ +#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */ + +/*!< ADCPPRE configuration */ +#define RCC_CFGR_ADCPRE ((uint32_t)0x0000C000) /*!< ADCPRE[1:0] bits (ADC prescaler) */ +#define RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000) /*!< Bit 0 */ +#define RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000) /*!< Bit 1 */ + +#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */ +#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */ +#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */ +#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */ + +#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */ + +#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */ + +/*!< PLLMUL configuration */ +#define RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ +#define RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) /*!< Bit 1 */ +#define RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) /*!< Bit 2 */ +#define RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) /*!< Bit 3 */ + +#ifdef STM32F10X_CL + #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ + #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */ + + #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */ + #define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */ + + #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock * 4 */ + #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock * 5 */ + #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock * 6 */ + #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock * 7 */ + #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock * 8 */ + #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock * 9 */ + #define RCC_CFGR_PLLMULL6_5 ((uint32_t)0x00340000) /*!< PLL input clock * 6.5 */ + + #define RCC_CFGR_OTGFSPRE ((uint32_t)0x00400000) /*!< USB OTG FS prescaler */ + +/*!< MCO configuration */ + #define RCC_CFGR_MCO ((uint32_t)0x0F000000) /*!< MCO[3:0] bits (Microcontroller Clock Output) */ + #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ + #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ + #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + #define RCC_CFGR_MCO_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + + #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ + #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ + #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ + #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ + #define RCC_CFGR_MCO_PLLCLK_Div2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ + #define RCC_CFGR_MCO_PLL2CLK ((uint32_t)0x08000000) /*!< PLL2 clock selected as MCO source*/ + #define RCC_CFGR_MCO_PLL3CLK_Div2 ((uint32_t)0x09000000) /*!< PLL3 clock divided by 2 selected as MCO source*/ + #define RCC_CFGR_MCO_Ext_HSE ((uint32_t)0x0A000000) /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */ + #define RCC_CFGR_MCO_PLL3CLK ((uint32_t)0x0B000000) /*!< PLL3 clock selected as MCO source */ +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) + #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ + #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */ + + #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */ + #define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */ + + #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */ + #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */ + #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */ + #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */ + #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */ + #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */ + #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */ + #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */ + #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */ + #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */ + #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */ + #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */ + #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */ + #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */ + #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */ + +/*!< MCO configuration */ + #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */ + #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ + #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ + #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + + #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ + #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ + #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ + #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ + #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ +#else + #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ + #define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) /*!< HSE clock selected as PLL entry clock source */ + + #define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */ + #define RCC_CFGR_PLLXTPRE_HSE_Div2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */ + + #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */ + #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */ + #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */ + #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */ + #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */ + #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */ + #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */ + #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */ + #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */ + #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */ + #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */ + #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */ + #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */ + #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */ + #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */ + #define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /*!< USB Device prescaler */ + +/*!< MCO configuration */ + #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */ + #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ + #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ + #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + + #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ + #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ + #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ + #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ + #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ +#endif /* STM32F10X_CL */ + +/*!<****************** Bit definition for RCC_CIR register ********************/ +#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */ +#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */ +#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */ +#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */ +#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */ +#define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */ +#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */ +#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */ +#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */ +#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */ +#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */ +#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */ +#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */ +#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */ +#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */ +#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */ +#define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */ + +#ifdef STM32F10X_CL + #define RCC_CIR_PLL2RDYF ((uint32_t)0x00000020) /*!< PLL2 Ready Interrupt flag */ + #define RCC_CIR_PLL3RDYF ((uint32_t)0x00000040) /*!< PLL3 Ready Interrupt flag */ + #define RCC_CIR_PLL2RDYIE ((uint32_t)0x00002000) /*!< PLL2 Ready Interrupt Enable */ + #define RCC_CIR_PLL3RDYIE ((uint32_t)0x00004000) /*!< PLL3 Ready Interrupt Enable */ + #define RCC_CIR_PLL2RDYC ((uint32_t)0x00200000) /*!< PLL2 Ready Interrupt Clear */ + #define RCC_CIR_PLL3RDYC ((uint32_t)0x00400000) /*!< PLL3 Ready Interrupt Clear */ +#endif /* STM32F10X_CL */ + +/***************** Bit definition for RCC_APB2RSTR register *****************/ +#define RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001) /*!< Alternate Function I/O reset */ +#define RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004) /*!< I/O port A reset */ +#define RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008) /*!< I/O port B reset */ +#define RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010) /*!< I/O port C reset */ +#define RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020) /*!< I/O port D reset */ +#define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) /*!< ADC 1 interface reset */ + +#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) +#define RCC_APB2RSTR_ADC2RST ((uint32_t)0x00000400) /*!< ADC 2 interface reset */ +#endif + +#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 Timer reset */ +#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI 1 reset */ +#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) +#define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 Timer reset */ +#define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 Timer reset */ +#define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 Timer reset */ +#endif + +#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) + #define RCC_APB2RSTR_IOPERST ((uint32_t)0x00000040) /*!< I/O port E reset */ +#endif /* STM32F10X_LD && STM32F10X_LD_VL */ + +#if defined (STM32F10X_HD) || defined (STM32F10X_XL) + #define RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) /*!< I/O port F reset */ + #define RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) /*!< I/O port G reset */ + #define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00002000) /*!< TIM8 Timer reset */ + #define RCC_APB2RSTR_ADC3RST ((uint32_t)0x00008000) /*!< ADC3 interface reset */ +#endif + +#ifdef STM32F10X_XL + #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00080000) /*!< TIM9 Timer reset */ + #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00100000) /*!< TIM10 Timer reset */ + #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00200000) /*!< TIM11 Timer reset */ +#endif /* STM32F10X_XL */ + +/***************** Bit definition for RCC_APB1RSTR register *****************/ +#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */ +#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */ +#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */ +#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */ +#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */ + +#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) +#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) /*!< CAN1 reset */ +#endif + +#define RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) /*!< Backup interface reset */ +#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */ + +#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) + #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */ + #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI 2 reset */ + #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< RUSART 3 reset */ + #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */ +#endif /* STM32F10X_LD && STM32F10X_LD_VL */ + +#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) || defined (STM32F10X_XL) + #define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB Device reset */ +#endif + +#if defined (STM32F10X_HD) || defined (STM32F10X_CL) || defined (STM32F10X_XL) + #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */ + #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */ + #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */ + #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */ + #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */ + #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */ + #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */ +#endif + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) + #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */ + #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */ + #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */ + #define RCC_APB1RSTR_CECRST ((uint32_t)0x40000000) /*!< CEC interface reset */ +#endif + +#ifdef STM32F10X_CL + #define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000) /*!< CAN2 reset */ +#endif /* STM32F10X_CL */ + +#ifdef STM32F10X_XL + #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) /*!< TIM12 Timer reset */ + #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) /*!< TIM13 Timer reset */ + #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< TIM14 Timer reset */ +#endif /* STM32F10X_XL */ + +/****************** Bit definition for RCC_AHBENR register ******************/ +#define RCC_AHBENR_DMA1EN ((uint16_t)0x0001) /*!< DMA1 clock enable */ +#define RCC_AHBENR_SRAMEN ((uint16_t)0x0004) /*!< SRAM interface clock enable */ +#define RCC_AHBENR_FLITFEN ((uint16_t)0x0010) /*!< FLITF clock enable */ +#define RCC_AHBENR_CRCEN ((uint16_t)0x0040) /*!< CRC clock enable */ + +#if defined (STM32F10X_HD) || defined (STM32F10X_CL) + #define RCC_AHBENR_DMA2EN ((uint16_t)0x0002) /*!< DMA2 clock enable */ +#endif + +#if defined (STM32F10X_HD) || defined (STM32F10X_XL) + #define RCC_AHBENR_FSMCEN ((uint16_t)0x0100) /*!< FSMC clock enable */ + #define RCC_AHBENR_SDIOEN ((uint16_t)0x0400) /*!< SDIO clock enable */ +#endif + +#ifdef STM32F10X_CL + #define RCC_AHBENR_OTGFSEN ((uint32_t)0x00001000) /*!< USB OTG FS clock enable */ + #define RCC_AHBENR_ETHMACEN ((uint32_t)0x00004000) /*!< ETHERNET MAC clock enable */ + #define RCC_AHBENR_ETHMACTXEN ((uint32_t)0x00008000) /*!< ETHERNET MAC Tx clock enable */ + #define RCC_AHBENR_ETHMACRXEN ((uint32_t)0x00010000) /*!< ETHERNET MAC Rx clock enable */ +#endif /* STM32F10X_CL */ + +/****************** Bit definition for RCC_APB2ENR register *****************/ +#define RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001) /*!< Alternate Function I/O clock enable */ +#define RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004) /*!< I/O port A clock enable */ +#define RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008) /*!< I/O port B clock enable */ +#define RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010) /*!< I/O port C clock enable */ +#define RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020) /*!< I/O port D clock enable */ +#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) /*!< ADC 1 interface clock enable */ + +#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) +#define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000400) /*!< ADC 2 interface clock enable */ +#endif + +#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 Timer clock enable */ +#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI 1 clock enable */ +#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) +#define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 Timer clock enable */ +#define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 Timer clock enable */ +#define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 Timer clock enable */ +#endif + +#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) + #define RCC_APB2ENR_IOPEEN ((uint32_t)0x00000040) /*!< I/O port E clock enable */ +#endif /* STM32F10X_LD && STM32F10X_LD_VL */ + +#if defined (STM32F10X_HD) || defined (STM32F10X_XL) + #define RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) /*!< I/O port F clock enable */ + #define RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) /*!< I/O port G clock enable */ + #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00002000) /*!< TIM8 Timer clock enable */ + #define RCC_APB2ENR_ADC3EN ((uint32_t)0x00008000) /*!< DMA1 clock enable */ +#endif + +#ifdef STM32F10X_XL + #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00080000) /*!< TIM9 Timer clock enable */ + #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00100000) /*!< TIM10 Timer clock enable */ + #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00200000) /*!< TIM11 Timer clock enable */ +#endif + +/***************** Bit definition for RCC_APB1ENR register ******************/ +#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/ +#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */ +#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */ +#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */ +#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */ + +#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) +#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) /*!< CAN1 clock enable */ +#endif + +#define RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) /*!< Backup interface clock enable */ +#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */ + +#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) + #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */ + #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI 2 clock enable */ + #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */ + #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */ +#endif /* STM32F10X_LD && STM32F10X_LD_VL */ + +#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) + #define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB Device clock enable */ +#endif + +#if defined (STM32F10X_HD) || defined (STM32F10X_CL) + #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */ + #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */ + #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */ + #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */ + #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */ + #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */ + #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */ +#endif + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) + #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */ + #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */ + #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */ + #define RCC_APB1ENR_CECEN ((uint32_t)0x40000000) /*!< CEC interface clock enable */ +#endif + +#ifdef STM32F10X_CL + #define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000) /*!< CAN2 clock enable */ +#endif /* STM32F10X_CL */ + +#ifdef STM32F10X_XL + #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) /*!< TIM12 Timer clock enable */ + #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) /*!< TIM13 Timer clock enable */ + #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< TIM14 Timer clock enable */ +#endif /* STM32F10X_XL */ + +/******************* Bit definition for RCC_BDCR register *******************/ +#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */ +#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */ +#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */ + +#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */ +#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */ + +/*!< RTC congiguration */ +#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ +#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */ +#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */ +#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */ + +#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */ +#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */ + +/******************* Bit definition for RCC_CSR register ********************/ +#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */ +#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */ +#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */ +#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */ +#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */ +#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */ +#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */ +#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */ +#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */ + +#ifdef STM32F10X_CL +/******************* Bit definition for RCC_AHBRSTR register ****************/ + #define RCC_AHBRSTR_OTGFSRST ((uint32_t)0x00001000) /*!< USB OTG FS reset */ + #define RCC_AHBRSTR_ETHMACRST ((uint32_t)0x00004000) /*!< ETHERNET MAC reset */ + +/******************* Bit definition for RCC_CFGR2 register ******************/ +/*!< PREDIV1 configuration */ + #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */ + #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ + #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ + #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ + #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + + #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */ + #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */ + #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */ + #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */ + #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */ + #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */ + #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */ + #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */ + #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */ + #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */ + #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */ + #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */ + #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */ + #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */ + #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */ + #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */ + +/*!< PREDIV2 configuration */ + #define RCC_CFGR2_PREDIV2 ((uint32_t)0x000000F0) /*!< PREDIV2[3:0] bits */ + #define RCC_CFGR2_PREDIV2_0 ((uint32_t)0x00000010) /*!< Bit 0 */ + #define RCC_CFGR2_PREDIV2_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + #define RCC_CFGR2_PREDIV2_2 ((uint32_t)0x00000040) /*!< Bit 2 */ + #define RCC_CFGR2_PREDIV2_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + + #define RCC_CFGR2_PREDIV2_DIV1 ((uint32_t)0x00000000) /*!< PREDIV2 input clock not divided */ + #define RCC_CFGR2_PREDIV2_DIV2 ((uint32_t)0x00000010) /*!< PREDIV2 input clock divided by 2 */ + #define RCC_CFGR2_PREDIV2_DIV3 ((uint32_t)0x00000020) /*!< PREDIV2 input clock divided by 3 */ + #define RCC_CFGR2_PREDIV2_DIV4 ((uint32_t)0x00000030) /*!< PREDIV2 input clock divided by 4 */ + #define RCC_CFGR2_PREDIV2_DIV5 ((uint32_t)0x00000040) /*!< PREDIV2 input clock divided by 5 */ + #define RCC_CFGR2_PREDIV2_DIV6 ((uint32_t)0x00000050) /*!< PREDIV2 input clock divided by 6 */ + #define RCC_CFGR2_PREDIV2_DIV7 ((uint32_t)0x00000060) /*!< PREDIV2 input clock divided by 7 */ + #define RCC_CFGR2_PREDIV2_DIV8 ((uint32_t)0x00000070) /*!< PREDIV2 input clock divided by 8 */ + #define RCC_CFGR2_PREDIV2_DIV9 ((uint32_t)0x00000080) /*!< PREDIV2 input clock divided by 9 */ + #define RCC_CFGR2_PREDIV2_DIV10 ((uint32_t)0x00000090) /*!< PREDIV2 input clock divided by 10 */ + #define RCC_CFGR2_PREDIV2_DIV11 ((uint32_t)0x000000A0) /*!< PREDIV2 input clock divided by 11 */ + #define RCC_CFGR2_PREDIV2_DIV12 ((uint32_t)0x000000B0) /*!< PREDIV2 input clock divided by 12 */ + #define RCC_CFGR2_PREDIV2_DIV13 ((uint32_t)0x000000C0) /*!< PREDIV2 input clock divided by 13 */ + #define RCC_CFGR2_PREDIV2_DIV14 ((uint32_t)0x000000D0) /*!< PREDIV2 input clock divided by 14 */ + #define RCC_CFGR2_PREDIV2_DIV15 ((uint32_t)0x000000E0) /*!< PREDIV2 input clock divided by 15 */ + #define RCC_CFGR2_PREDIV2_DIV16 ((uint32_t)0x000000F0) /*!< PREDIV2 input clock divided by 16 */ + +/*!< PLL2MUL configuration */ + #define RCC_CFGR2_PLL2MUL ((uint32_t)0x00000F00) /*!< PLL2MUL[3:0] bits */ + #define RCC_CFGR2_PLL2MUL_0 ((uint32_t)0x00000100) /*!< Bit 0 */ + #define RCC_CFGR2_PLL2MUL_1 ((uint32_t)0x00000200) /*!< Bit 1 */ + #define RCC_CFGR2_PLL2MUL_2 ((uint32_t)0x00000400) /*!< Bit 2 */ + #define RCC_CFGR2_PLL2MUL_3 ((uint32_t)0x00000800) /*!< Bit 3 */ + + #define RCC_CFGR2_PLL2MUL8 ((uint32_t)0x00000600) /*!< PLL2 input clock * 8 */ + #define RCC_CFGR2_PLL2MUL9 ((uint32_t)0x00000700) /*!< PLL2 input clock * 9 */ + #define RCC_CFGR2_PLL2MUL10 ((uint32_t)0x00000800) /*!< PLL2 input clock * 10 */ + #define RCC_CFGR2_PLL2MUL11 ((uint32_t)0x00000900) /*!< PLL2 input clock * 11 */ + #define RCC_CFGR2_PLL2MUL12 ((uint32_t)0x00000A00) /*!< PLL2 input clock * 12 */ + #define RCC_CFGR2_PLL2MUL13 ((uint32_t)0x00000B00) /*!< PLL2 input clock * 13 */ + #define RCC_CFGR2_PLL2MUL14 ((uint32_t)0x00000C00) /*!< PLL2 input clock * 14 */ + #define RCC_CFGR2_PLL2MUL16 ((uint32_t)0x00000E00) /*!< PLL2 input clock * 16 */ + #define RCC_CFGR2_PLL2MUL20 ((uint32_t)0x00000F00) /*!< PLL2 input clock * 20 */ + +/*!< PLL3MUL configuration */ + #define RCC_CFGR2_PLL3MUL ((uint32_t)0x0000F000) /*!< PLL3MUL[3:0] bits */ + #define RCC_CFGR2_PLL3MUL_0 ((uint32_t)0x00001000) /*!< Bit 0 */ + #define RCC_CFGR2_PLL3MUL_1 ((uint32_t)0x00002000) /*!< Bit 1 */ + #define RCC_CFGR2_PLL3MUL_2 ((uint32_t)0x00004000) /*!< Bit 2 */ + #define RCC_CFGR2_PLL3MUL_3 ((uint32_t)0x00008000) /*!< Bit 3 */ + + #define RCC_CFGR2_PLL3MUL8 ((uint32_t)0x00006000) /*!< PLL3 input clock * 8 */ + #define RCC_CFGR2_PLL3MUL9 ((uint32_t)0x00007000) /*!< PLL3 input clock * 9 */ + #define RCC_CFGR2_PLL3MUL10 ((uint32_t)0x00008000) /*!< PLL3 input clock * 10 */ + #define RCC_CFGR2_PLL3MUL11 ((uint32_t)0x00009000) /*!< PLL3 input clock * 11 */ + #define RCC_CFGR2_PLL3MUL12 ((uint32_t)0x0000A000) /*!< PLL3 input clock * 12 */ + #define RCC_CFGR2_PLL3MUL13 ((uint32_t)0x0000B000) /*!< PLL3 input clock * 13 */ + #define RCC_CFGR2_PLL3MUL14 ((uint32_t)0x0000C000) /*!< PLL3 input clock * 14 */ + #define RCC_CFGR2_PLL3MUL16 ((uint32_t)0x0000E000) /*!< PLL3 input clock * 16 */ + #define RCC_CFGR2_PLL3MUL20 ((uint32_t)0x0000F000) /*!< PLL3 input clock * 20 */ + + #define RCC_CFGR2_PREDIV1SRC ((uint32_t)0x00010000) /*!< PREDIV1 entry clock source */ + #define RCC_CFGR2_PREDIV1SRC_PLL2 ((uint32_t)0x00010000) /*!< PLL2 selected as PREDIV1 entry clock source */ + #define RCC_CFGR2_PREDIV1SRC_HSE ((uint32_t)0x00000000) /*!< HSE selected as PREDIV1 entry clock source */ + #define RCC_CFGR2_I2S2SRC ((uint32_t)0x00020000) /*!< I2S2 entry clock source */ + #define RCC_CFGR2_I2S3SRC ((uint32_t)0x00040000) /*!< I2S3 clock source */ +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) +/******************* Bit definition for RCC_CFGR2 register ******************/ +/*!< PREDIV1 configuration */ + #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */ + #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ + #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ + #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ + #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + + #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */ + #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */ + #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */ + #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */ + #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */ + #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */ + #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */ + #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */ + #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */ + #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */ + #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */ + #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */ + #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */ + #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */ + #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */ + #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */ +#endif + +/******************************************************************************/ +/* */ +/* General Purpose and Alternate Function I/O */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for GPIO_CRL register *******************/ +#define GPIO_CRL_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */ + +#define GPIO_CRL_MODE0 ((uint32_t)0x00000003) /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */ +#define GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) /*!< Bit 1 */ + +#define GPIO_CRL_MODE1 ((uint32_t)0x00000030) /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */ +#define GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define GPIO_CRL_MODE2 ((uint32_t)0x00000300) /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */ +#define GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) /*!< Bit 1 */ + +#define GPIO_CRL_MODE3 ((uint32_t)0x00003000) /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */ +#define GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) /*!< Bit 1 */ + +#define GPIO_CRL_MODE4 ((uint32_t)0x00030000) /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */ +#define GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ + +#define GPIO_CRL_MODE5 ((uint32_t)0x00300000) /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */ +#define GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) /*!< Bit 1 */ + +#define GPIO_CRL_MODE6 ((uint32_t)0x03000000) /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */ +#define GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) /*!< Bit 1 */ + +#define GPIO_CRL_MODE7 ((uint32_t)0x30000000) /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */ +#define GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +#define GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */ + +#define GPIO_CRL_CNF0 ((uint32_t)0x0000000C) /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */ +#define GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +#define GPIO_CRL_CNF1 ((uint32_t)0x000000C0) /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */ +#define GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) /*!< Bit 1 */ + +#define GPIO_CRL_CNF2 ((uint32_t)0x00000C00) /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */ +#define GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) /*!< Bit 1 */ + +#define GPIO_CRL_CNF3 ((uint32_t)0x0000C000) /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */ +#define GPIO_CRL_CNF3_0 ((uint32_t)0x00004000) /*!< Bit 0 */ +#define GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) /*!< Bit 1 */ + +#define GPIO_CRL_CNF4 ((uint32_t)0x000C0000) /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */ +#define GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define GPIO_CRL_CNF4_1 ((uint32_t)0x00080000) /*!< Bit 1 */ + +#define GPIO_CRL_CNF5 ((uint32_t)0x00C00000) /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */ +#define GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) /*!< Bit 0 */ +#define GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) /*!< Bit 1 */ + +#define GPIO_CRL_CNF6 ((uint32_t)0x0C000000) /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */ +#define GPIO_CRL_CNF6_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) /*!< Bit 1 */ + +#define GPIO_CRL_CNF7 ((uint32_t)0xC0000000) /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */ +#define GPIO_CRL_CNF7_0 ((uint32_t)0x40000000) /*!< Bit 0 */ +#define GPIO_CRL_CNF7_1 ((uint32_t)0x80000000) /*!< Bit 1 */ + +/******************* Bit definition for GPIO_CRH register *******************/ +#define GPIO_CRH_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */ + +#define GPIO_CRH_MODE8 ((uint32_t)0x00000003) /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */ +#define GPIO_CRH_MODE8_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define GPIO_CRH_MODE8_1 ((uint32_t)0x00000002) /*!< Bit 1 */ + +#define GPIO_CRH_MODE9 ((uint32_t)0x00000030) /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */ +#define GPIO_CRH_MODE9_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define GPIO_CRH_MODE9_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define GPIO_CRH_MODE10 ((uint32_t)0x00000300) /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */ +#define GPIO_CRH_MODE10_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define GPIO_CRH_MODE10_1 ((uint32_t)0x00000200) /*!< Bit 1 */ + +#define GPIO_CRH_MODE11 ((uint32_t)0x00003000) /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */ +#define GPIO_CRH_MODE11_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define GPIO_CRH_MODE11_1 ((uint32_t)0x00002000) /*!< Bit 1 */ + +#define GPIO_CRH_MODE12 ((uint32_t)0x00030000) /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */ +#define GPIO_CRH_MODE12_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define GPIO_CRH_MODE12_1 ((uint32_t)0x00020000) /*!< Bit 1 */ + +#define GPIO_CRH_MODE13 ((uint32_t)0x00300000) /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */ +#define GPIO_CRH_MODE13_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define GPIO_CRH_MODE13_1 ((uint32_t)0x00200000) /*!< Bit 1 */ + +#define GPIO_CRH_MODE14 ((uint32_t)0x03000000) /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */ +#define GPIO_CRH_MODE14_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define GPIO_CRH_MODE14_1 ((uint32_t)0x02000000) /*!< Bit 1 */ + +#define GPIO_CRH_MODE15 ((uint32_t)0x30000000) /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */ +#define GPIO_CRH_MODE15_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define GPIO_CRH_MODE15_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +#define GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */ + +#define GPIO_CRH_CNF8 ((uint32_t)0x0000000C) /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */ +#define GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +#define GPIO_CRH_CNF9 ((uint32_t)0x000000C0) /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */ +#define GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) /*!< Bit 1 */ + +#define GPIO_CRH_CNF10 ((uint32_t)0x00000C00) /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */ +#define GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) /*!< Bit 1 */ + +#define GPIO_CRH_CNF11 ((uint32_t)0x0000C000) /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */ +#define GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) /*!< Bit 0 */ +#define GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) /*!< Bit 1 */ + +#define GPIO_CRH_CNF12 ((uint32_t)0x000C0000) /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */ +#define GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) /*!< Bit 1 */ + +#define GPIO_CRH_CNF13 ((uint32_t)0x00C00000) /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */ +#define GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) /*!< Bit 0 */ +#define GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) /*!< Bit 1 */ + +#define GPIO_CRH_CNF14 ((uint32_t)0x0C000000) /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */ +#define GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) /*!< Bit 1 */ + +#define GPIO_CRH_CNF15 ((uint32_t)0xC0000000) /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */ +#define GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) /*!< Bit 0 */ +#define GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) /*!< Bit 1 */ + +/*!<****************** Bit definition for GPIO_IDR register *******************/ +#define GPIO_IDR_IDR0 ((uint16_t)0x0001) /*!< Port input data, bit 0 */ +#define GPIO_IDR_IDR1 ((uint16_t)0x0002) /*!< Port input data, bit 1 */ +#define GPIO_IDR_IDR2 ((uint16_t)0x0004) /*!< Port input data, bit 2 */ +#define GPIO_IDR_IDR3 ((uint16_t)0x0008) /*!< Port input data, bit 3 */ +#define GPIO_IDR_IDR4 ((uint16_t)0x0010) /*!< Port input data, bit 4 */ +#define GPIO_IDR_IDR5 ((uint16_t)0x0020) /*!< Port input data, bit 5 */ +#define GPIO_IDR_IDR6 ((uint16_t)0x0040) /*!< Port input data, bit 6 */ +#define GPIO_IDR_IDR7 ((uint16_t)0x0080) /*!< Port input data, bit 7 */ +#define GPIO_IDR_IDR8 ((uint16_t)0x0100) /*!< Port input data, bit 8 */ +#define GPIO_IDR_IDR9 ((uint16_t)0x0200) /*!< Port input data, bit 9 */ +#define GPIO_IDR_IDR10 ((uint16_t)0x0400) /*!< Port input data, bit 10 */ +#define GPIO_IDR_IDR11 ((uint16_t)0x0800) /*!< Port input data, bit 11 */ +#define GPIO_IDR_IDR12 ((uint16_t)0x1000) /*!< Port input data, bit 12 */ +#define GPIO_IDR_IDR13 ((uint16_t)0x2000) /*!< Port input data, bit 13 */ +#define GPIO_IDR_IDR14 ((uint16_t)0x4000) /*!< Port input data, bit 14 */ +#define GPIO_IDR_IDR15 ((uint16_t)0x8000) /*!< Port input data, bit 15 */ + +/******************* Bit definition for GPIO_ODR register *******************/ +#define GPIO_ODR_ODR0 ((uint16_t)0x0001) /*!< Port output data, bit 0 */ +#define GPIO_ODR_ODR1 ((uint16_t)0x0002) /*!< Port output data, bit 1 */ +#define GPIO_ODR_ODR2 ((uint16_t)0x0004) /*!< Port output data, bit 2 */ +#define GPIO_ODR_ODR3 ((uint16_t)0x0008) /*!< Port output data, bit 3 */ +#define GPIO_ODR_ODR4 ((uint16_t)0x0010) /*!< Port output data, bit 4 */ +#define GPIO_ODR_ODR5 ((uint16_t)0x0020) /*!< Port output data, bit 5 */ +#define GPIO_ODR_ODR6 ((uint16_t)0x0040) /*!< Port output data, bit 6 */ +#define GPIO_ODR_ODR7 ((uint16_t)0x0080) /*!< Port output data, bit 7 */ +#define GPIO_ODR_ODR8 ((uint16_t)0x0100) /*!< Port output data, bit 8 */ +#define GPIO_ODR_ODR9 ((uint16_t)0x0200) /*!< Port output data, bit 9 */ +#define GPIO_ODR_ODR10 ((uint16_t)0x0400) /*!< Port output data, bit 10 */ +#define GPIO_ODR_ODR11 ((uint16_t)0x0800) /*!< Port output data, bit 11 */ +#define GPIO_ODR_ODR12 ((uint16_t)0x1000) /*!< Port output data, bit 12 */ +#define GPIO_ODR_ODR13 ((uint16_t)0x2000) /*!< Port output data, bit 13 */ +#define GPIO_ODR_ODR14 ((uint16_t)0x4000) /*!< Port output data, bit 14 */ +#define GPIO_ODR_ODR15 ((uint16_t)0x8000) /*!< Port output data, bit 15 */ + +/****************** Bit definition for GPIO_BSRR register *******************/ +#define GPIO_BSRR_BS0 ((uint32_t)0x00000001) /*!< Port x Set bit 0 */ +#define GPIO_BSRR_BS1 ((uint32_t)0x00000002) /*!< Port x Set bit 1 */ +#define GPIO_BSRR_BS2 ((uint32_t)0x00000004) /*!< Port x Set bit 2 */ +#define GPIO_BSRR_BS3 ((uint32_t)0x00000008) /*!< Port x Set bit 3 */ +#define GPIO_BSRR_BS4 ((uint32_t)0x00000010) /*!< Port x Set bit 4 */ +#define GPIO_BSRR_BS5 ((uint32_t)0x00000020) /*!< Port x Set bit 5 */ +#define GPIO_BSRR_BS6 ((uint32_t)0x00000040) /*!< Port x Set bit 6 */ +#define GPIO_BSRR_BS7 ((uint32_t)0x00000080) /*!< Port x Set bit 7 */ +#define GPIO_BSRR_BS8 ((uint32_t)0x00000100) /*!< Port x Set bit 8 */ +#define GPIO_BSRR_BS9 ((uint32_t)0x00000200) /*!< Port x Set bit 9 */ +#define GPIO_BSRR_BS10 ((uint32_t)0x00000400) /*!< Port x Set bit 10 */ +#define GPIO_BSRR_BS11 ((uint32_t)0x00000800) /*!< Port x Set bit 11 */ +#define GPIO_BSRR_BS12 ((uint32_t)0x00001000) /*!< Port x Set bit 12 */ +#define GPIO_BSRR_BS13 ((uint32_t)0x00002000) /*!< Port x Set bit 13 */ +#define GPIO_BSRR_BS14 ((uint32_t)0x00004000) /*!< Port x Set bit 14 */ +#define GPIO_BSRR_BS15 ((uint32_t)0x00008000) /*!< Port x Set bit 15 */ + +#define GPIO_BSRR_BR0 ((uint32_t)0x00010000) /*!< Port x Reset bit 0 */ +#define GPIO_BSRR_BR1 ((uint32_t)0x00020000) /*!< Port x Reset bit 1 */ +#define GPIO_BSRR_BR2 ((uint32_t)0x00040000) /*!< Port x Reset bit 2 */ +#define GPIO_BSRR_BR3 ((uint32_t)0x00080000) /*!< Port x Reset bit 3 */ +#define GPIO_BSRR_BR4 ((uint32_t)0x00100000) /*!< Port x Reset bit 4 */ +#define GPIO_BSRR_BR5 ((uint32_t)0x00200000) /*!< Port x Reset bit 5 */ +#define GPIO_BSRR_BR6 ((uint32_t)0x00400000) /*!< Port x Reset bit 6 */ +#define GPIO_BSRR_BR7 ((uint32_t)0x00800000) /*!< Port x Reset bit 7 */ +#define GPIO_BSRR_BR8 ((uint32_t)0x01000000) /*!< Port x Reset bit 8 */ +#define GPIO_BSRR_BR9 ((uint32_t)0x02000000) /*!< Port x Reset bit 9 */ +#define GPIO_BSRR_BR10 ((uint32_t)0x04000000) /*!< Port x Reset bit 10 */ +#define GPIO_BSRR_BR11 ((uint32_t)0x08000000) /*!< Port x Reset bit 11 */ +#define GPIO_BSRR_BR12 ((uint32_t)0x10000000) /*!< Port x Reset bit 12 */ +#define GPIO_BSRR_BR13 ((uint32_t)0x20000000) /*!< Port x Reset bit 13 */ +#define GPIO_BSRR_BR14 ((uint32_t)0x40000000) /*!< Port x Reset bit 14 */ +#define GPIO_BSRR_BR15 ((uint32_t)0x80000000) /*!< Port x Reset bit 15 */ + +/******************* Bit definition for GPIO_BRR register *******************/ +#define GPIO_BRR_BR0 ((uint16_t)0x0001) /*!< Port x Reset bit 0 */ +#define GPIO_BRR_BR1 ((uint16_t)0x0002) /*!< Port x Reset bit 1 */ +#define GPIO_BRR_BR2 ((uint16_t)0x0004) /*!< Port x Reset bit 2 */ +#define GPIO_BRR_BR3 ((uint16_t)0x0008) /*!< Port x Reset bit 3 */ +#define GPIO_BRR_BR4 ((uint16_t)0x0010) /*!< Port x Reset bit 4 */ +#define GPIO_BRR_BR5 ((uint16_t)0x0020) /*!< Port x Reset bit 5 */ +#define GPIO_BRR_BR6 ((uint16_t)0x0040) /*!< Port x Reset bit 6 */ +#define GPIO_BRR_BR7 ((uint16_t)0x0080) /*!< Port x Reset bit 7 */ +#define GPIO_BRR_BR8 ((uint16_t)0x0100) /*!< Port x Reset bit 8 */ +#define GPIO_BRR_BR9 ((uint16_t)0x0200) /*!< Port x Reset bit 9 */ +#define GPIO_BRR_BR10 ((uint16_t)0x0400) /*!< Port x Reset bit 10 */ +#define GPIO_BRR_BR11 ((uint16_t)0x0800) /*!< Port x Reset bit 11 */ +#define GPIO_BRR_BR12 ((uint16_t)0x1000) /*!< Port x Reset bit 12 */ +#define GPIO_BRR_BR13 ((uint16_t)0x2000) /*!< Port x Reset bit 13 */ +#define GPIO_BRR_BR14 ((uint16_t)0x4000) /*!< Port x Reset bit 14 */ +#define GPIO_BRR_BR15 ((uint16_t)0x8000) /*!< Port x Reset bit 15 */ + +/****************** Bit definition for GPIO_LCKR register *******************/ +#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001) /*!< Port x Lock bit 0 */ +#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002) /*!< Port x Lock bit 1 */ +#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004) /*!< Port x Lock bit 2 */ +#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008) /*!< Port x Lock bit 3 */ +#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010) /*!< Port x Lock bit 4 */ +#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020) /*!< Port x Lock bit 5 */ +#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040) /*!< Port x Lock bit 6 */ +#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080) /*!< Port x Lock bit 7 */ +#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100) /*!< Port x Lock bit 8 */ +#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200) /*!< Port x Lock bit 9 */ +#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400) /*!< Port x Lock bit 10 */ +#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800) /*!< Port x Lock bit 11 */ +#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000) /*!< Port x Lock bit 12 */ +#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000) /*!< Port x Lock bit 13 */ +#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000) /*!< Port x Lock bit 14 */ +#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000) /*!< Port x Lock bit 15 */ +#define GPIO_LCKR_LCKK ((uint32_t)0x00010000) /*!< Lock key */ + +/*----------------------------------------------------------------------------*/ + +/****************** Bit definition for AFIO_EVCR register *******************/ +#define AFIO_EVCR_PIN ((uint8_t)0x0F) /*!< PIN[3:0] bits (Pin selection) */ +#define AFIO_EVCR_PIN_0 ((uint8_t)0x01) /*!< Bit 0 */ +#define AFIO_EVCR_PIN_1 ((uint8_t)0x02) /*!< Bit 1 */ +#define AFIO_EVCR_PIN_2 ((uint8_t)0x04) /*!< Bit 2 */ +#define AFIO_EVCR_PIN_3 ((uint8_t)0x08) /*!< Bit 3 */ + +/*!< PIN configuration */ +#define AFIO_EVCR_PIN_PX0 ((uint8_t)0x00) /*!< Pin 0 selected */ +#define AFIO_EVCR_PIN_PX1 ((uint8_t)0x01) /*!< Pin 1 selected */ +#define AFIO_EVCR_PIN_PX2 ((uint8_t)0x02) /*!< Pin 2 selected */ +#define AFIO_EVCR_PIN_PX3 ((uint8_t)0x03) /*!< Pin 3 selected */ +#define AFIO_EVCR_PIN_PX4 ((uint8_t)0x04) /*!< Pin 4 selected */ +#define AFIO_EVCR_PIN_PX5 ((uint8_t)0x05) /*!< Pin 5 selected */ +#define AFIO_EVCR_PIN_PX6 ((uint8_t)0x06) /*!< Pin 6 selected */ +#define AFIO_EVCR_PIN_PX7 ((uint8_t)0x07) /*!< Pin 7 selected */ +#define AFIO_EVCR_PIN_PX8 ((uint8_t)0x08) /*!< Pin 8 selected */ +#define AFIO_EVCR_PIN_PX9 ((uint8_t)0x09) /*!< Pin 9 selected */ +#define AFIO_EVCR_PIN_PX10 ((uint8_t)0x0A) /*!< Pin 10 selected */ +#define AFIO_EVCR_PIN_PX11 ((uint8_t)0x0B) /*!< Pin 11 selected */ +#define AFIO_EVCR_PIN_PX12 ((uint8_t)0x0C) /*!< Pin 12 selected */ +#define AFIO_EVCR_PIN_PX13 ((uint8_t)0x0D) /*!< Pin 13 selected */ +#define AFIO_EVCR_PIN_PX14 ((uint8_t)0x0E) /*!< Pin 14 selected */ +#define AFIO_EVCR_PIN_PX15 ((uint8_t)0x0F) /*!< Pin 15 selected */ + +#define AFIO_EVCR_PORT ((uint8_t)0x70) /*!< PORT[2:0] bits (Port selection) */ +#define AFIO_EVCR_PORT_0 ((uint8_t)0x10) /*!< Bit 0 */ +#define AFIO_EVCR_PORT_1 ((uint8_t)0x20) /*!< Bit 1 */ +#define AFIO_EVCR_PORT_2 ((uint8_t)0x40) /*!< Bit 2 */ + +/*!< PORT configuration */ +#define AFIO_EVCR_PORT_PA ((uint8_t)0x00) /*!< Port A selected */ +#define AFIO_EVCR_PORT_PB ((uint8_t)0x10) /*!< Port B selected */ +#define AFIO_EVCR_PORT_PC ((uint8_t)0x20) /*!< Port C selected */ +#define AFIO_EVCR_PORT_PD ((uint8_t)0x30) /*!< Port D selected */ +#define AFIO_EVCR_PORT_PE ((uint8_t)0x40) /*!< Port E selected */ + +#define AFIO_EVCR_EVOE ((uint8_t)0x80) /*!< Event Output Enable */ + +/****************** Bit definition for AFIO_MAPR register *******************/ +#define AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) /*!< SPI1 remapping */ +#define AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) /*!< I2C1 remapping */ +#define AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) /*!< USART1 remapping */ +#define AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) /*!< USART2 remapping */ + +#define AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) /*!< USART3_REMAP[1:0] bits (USART3 remapping) */ +#define AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +/* USART3_REMAP configuration */ +#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ +#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ +#define AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */ + +#define AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */ +#define AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) /*!< Bit 1 */ + +/*!< TIM1_REMAP configuration */ +#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ +#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ +#define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */ + +#define AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */ +#define AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) /*!< Bit 1 */ + +/*!< TIM2_REMAP configuration */ +#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ +#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ +#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ +#define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ + +#define AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */ +#define AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) /*!< Bit 1 */ + +/*!< TIM3_REMAP configuration */ +#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ +#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ +#define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ + +#define AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) /*!< TIM4_REMAP bit (TIM4 remapping) */ + +#define AFIO_MAPR_CAN_REMAP ((uint32_t)0x00006000) /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */ +#define AFIO_MAPR_CAN_REMAP_0 ((uint32_t)0x00002000) /*!< Bit 0 */ +#define AFIO_MAPR_CAN_REMAP_1 ((uint32_t)0x00004000) /*!< Bit 1 */ + +/*!< CAN_REMAP configuration */ +#define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /*!< CANRX mapped to PA11, CANTX mapped to PA12 */ +#define AFIO_MAPR_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) /*!< CANRX mapped to PB8, CANTX mapped to PB9 */ +#define AFIO_MAPR_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) /*!< CANRX mapped to PD0, CANTX mapped to PD1 */ + +#define AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ +#define AFIO_MAPR_TIM5CH4_IREMAP ((uint32_t)0x00010000) /*!< TIM5 Channel4 Internal Remap */ +#define AFIO_MAPR_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000) /*!< ADC 1 External Trigger Injected Conversion remapping */ +#define AFIO_MAPR_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000) /*!< ADC 1 External Trigger Regular Conversion remapping */ +#define AFIO_MAPR_ADC2_ETRGINJ_REMAP ((uint32_t)0x00080000) /*!< ADC 2 External Trigger Injected Conversion remapping */ +#define AFIO_MAPR_ADC2_ETRGREG_REMAP ((uint32_t)0x00100000) /*!< ADC 2 External Trigger Regular Conversion remapping */ + +/*!< SWJ_CFG configuration */ +#define AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ +#define AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + +#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */ +#define AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ +#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /*!< JTAG-DP Disabled and SW-DP Enabled */ +#define AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /*!< JTAG-DP Disabled and SW-DP Disabled */ + +#ifdef STM32F10X_CL +/*!< ETH_REMAP configuration */ + #define AFIO_MAPR_ETH_REMAP ((uint32_t)0x00200000) /*!< SPI3_REMAP bit (Ethernet MAC I/O remapping) */ + +/*!< CAN2_REMAP configuration */ + #define AFIO_MAPR_CAN2_REMAP ((uint32_t)0x00400000) /*!< CAN2_REMAP bit (CAN2 I/O remapping) */ + +/*!< MII_RMII_SEL configuration */ + #define AFIO_MAPR_MII_RMII_SEL ((uint32_t)0x00800000) /*!< MII_RMII_SEL bit (Ethernet MII or RMII selection) */ + +/*!< SPI3_REMAP configuration */ + #define AFIO_MAPR_SPI3_REMAP ((uint32_t)0x10000000) /*!< SPI3_REMAP bit (SPI3 remapping) */ + +/*!< TIM2ITR1_IREMAP configuration */ + #define AFIO_MAPR_TIM2ITR1_IREMAP ((uint32_t)0x20000000) /*!< TIM2ITR1_IREMAP bit (TIM2 internal trigger 1 remapping) */ + +/*!< PTP_PPS_REMAP configuration */ + #define AFIO_MAPR_PTP_PPS_REMAP ((uint32_t)0x20000000) /*!< PTP_PPS_REMAP bit (Ethernet PTP PPS remapping) */ +#endif + +/***************** Bit definition for AFIO_EXTICR1 register *****************/ +#define AFIO_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */ +#define AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */ +#define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */ +#define AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */ + +/*!< EXTI0 configuration */ +#define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */ +#define AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */ +#define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */ +#define AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */ +#define AFIO_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin */ +#define AFIO_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */ +#define AFIO_EXTICR1_EXTI0_PG ((uint16_t)0x0006) /*!< PG[0] pin */ + +/*!< EXTI1 configuration */ +#define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */ +#define AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */ +#define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */ +#define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */ +#define AFIO_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin */ +#define AFIO_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */ +#define AFIO_EXTICR1_EXTI1_PG ((uint16_t)0x0060) /*!< PG[1] pin */ + +/*!< EXTI2 configuration */ +#define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */ +#define AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */ +#define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */ +#define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */ +#define AFIO_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin */ +#define AFIO_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */ +#define AFIO_EXTICR1_EXTI2_PG ((uint16_t)0x0600) /*!< PG[2] pin */ + +/*!< EXTI3 configuration */ +#define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */ +#define AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */ +#define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */ +#define AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */ +#define AFIO_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!< PE[3] pin */ +#define AFIO_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */ +#define AFIO_EXTICR1_EXTI3_PG ((uint16_t)0x6000) /*!< PG[3] pin */ + +/***************** Bit definition for AFIO_EXTICR2 register *****************/ +#define AFIO_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */ +#define AFIO_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */ +#define AFIO_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */ +#define AFIO_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */ + +/*!< EXTI4 configuration */ +#define AFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */ +#define AFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */ +#define AFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */ +#define AFIO_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */ +#define AFIO_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin */ +#define AFIO_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */ +#define AFIO_EXTICR2_EXTI4_PG ((uint16_t)0x0006) /*!< PG[4] pin */ + +/* EXTI5 configuration */ +#define AFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */ +#define AFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */ +#define AFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */ +#define AFIO_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */ +#define AFIO_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin */ +#define AFIO_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */ +#define AFIO_EXTICR2_EXTI5_PG ((uint16_t)0x0060) /*!< PG[5] pin */ + +/*!< EXTI6 configuration */ +#define AFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */ +#define AFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */ +#define AFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */ +#define AFIO_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */ +#define AFIO_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin */ +#define AFIO_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */ +#define AFIO_EXTICR2_EXTI6_PG ((uint16_t)0x0600) /*!< PG[6] pin */ + +/*!< EXTI7 configuration */ +#define AFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */ +#define AFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */ +#define AFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */ +#define AFIO_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */ +#define AFIO_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!< PE[7] pin */ +#define AFIO_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */ +#define AFIO_EXTICR2_EXTI7_PG ((uint16_t)0x6000) /*!< PG[7] pin */ + +/***************** Bit definition for AFIO_EXTICR3 register *****************/ +#define AFIO_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */ +#define AFIO_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */ +#define AFIO_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */ +#define AFIO_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */ + +/*!< EXTI8 configuration */ +#define AFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */ +#define AFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */ +#define AFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */ +#define AFIO_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */ +#define AFIO_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin */ +#define AFIO_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /*!< PF[8] pin */ +#define AFIO_EXTICR3_EXTI8_PG ((uint16_t)0x0006) /*!< PG[8] pin */ + +/*!< EXTI9 configuration */ +#define AFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */ +#define AFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */ +#define AFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */ +#define AFIO_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */ +#define AFIO_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin */ +#define AFIO_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */ +#define AFIO_EXTICR3_EXTI9_PG ((uint16_t)0x0060) /*!< PG[9] pin */ + +/*!< EXTI10 configuration */ +#define AFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */ +#define AFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */ +#define AFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */ +#define AFIO_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */ +#define AFIO_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!< PE[10] pin */ +#define AFIO_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */ +#define AFIO_EXTICR3_EXTI10_PG ((uint16_t)0x0600) /*!< PG[10] pin */ + +/*!< EXTI11 configuration */ +#define AFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */ +#define AFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */ +#define AFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */ +#define AFIO_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */ +#define AFIO_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!< PE[11] pin */ +#define AFIO_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /*!< PF[11] pin */ +#define AFIO_EXTICR3_EXTI11_PG ((uint16_t)0x6000) /*!< PG[11] pin */ + +/***************** Bit definition for AFIO_EXTICR4 register *****************/ +#define AFIO_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */ +#define AFIO_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */ +#define AFIO_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */ +#define AFIO_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */ + +/* EXTI12 configuration */ +#define AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */ +#define AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */ +#define AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */ +#define AFIO_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */ +#define AFIO_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin */ +#define AFIO_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /*!< PF[12] pin */ +#define AFIO_EXTICR4_EXTI12_PG ((uint16_t)0x0006) /*!< PG[12] pin */ + +/* EXTI13 configuration */ +#define AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */ +#define AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */ +#define AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */ +#define AFIO_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */ +#define AFIO_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin */ +#define AFIO_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /*!< PF[13] pin */ +#define AFIO_EXTICR4_EXTI13_PG ((uint16_t)0x0060) /*!< PG[13] pin */ + +/*!< EXTI14 configuration */ +#define AFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */ +#define AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */ +#define AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */ +#define AFIO_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */ +#define AFIO_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin */ +#define AFIO_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /*!< PF[14] pin */ +#define AFIO_EXTICR4_EXTI14_PG ((uint16_t)0x0600) /*!< PG[14] pin */ + +/*!< EXTI15 configuration */ +#define AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */ +#define AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */ +#define AFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */ +#define AFIO_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */ +#define AFIO_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin */ +#define AFIO_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!< PF[15] pin */ +#define AFIO_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /*!< PG[15] pin */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) +/****************** Bit definition for AFIO_MAPR2 register ******************/ +#define AFIO_MAPR2_TIM15_REMAP ((uint32_t)0x00000001) /*!< TIM15 remapping */ +#define AFIO_MAPR2_TIM16_REMAP ((uint32_t)0x00000002) /*!< TIM16 remapping */ +#define AFIO_MAPR2_TIM17_REMAP ((uint32_t)0x00000004) /*!< TIM17 remapping */ +#define AFIO_MAPR2_CEC_REMAP ((uint32_t)0x00000008) /*!< CEC remapping */ +#define AFIO_MAPR2_TIM1_DMA_REMAP ((uint32_t)0x00000010) /*!< TIM1_DMA remapping */ +#endif + +#ifdef STM32F10X_XL +/****************** Bit definition for AFIO_MAPR2 register ******************/ +#define AFIO_MAPR2_TIM9_REMAP ((uint32_t)0x00000020) /*!< TIM9 remapping */ +#define AFIO_MAPR2_TIM10_REMAP ((uint32_t)0x00000040) /*!< TIM10 remapping */ +#define AFIO_MAPR2_TIM11_REMAP ((uint32_t)0x00000080) /*!< TIM11 remapping */ +#define AFIO_MAPR2_TIM13_REMAP ((uint32_t)0x00000100) /*!< TIM13 remapping */ +#define AFIO_MAPR2_TIM14_REMAP ((uint32_t)0x00000200) /*!< TIM14 remapping */ +#define AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) /*!< FSMC NADV remapping */ +#endif + +/******************************************************************************/ +/* */ +/* SystemTick */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for SysTick_CTRL register *****************/ +#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */ +#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */ +#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */ +#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */ + +/***************** Bit definition for SysTick_LOAD register *****************/ +#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */ + +/***************** Bit definition for SysTick_VAL register ******************/ +#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */ + +/***************** Bit definition for SysTick_CALIB register ****************/ +#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */ +#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */ +#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */ + +/******************************************************************************/ +/* */ +/* Nested Vectored Interrupt Controller */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for NVIC_ISER register *******************/ +#define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt set enable bits */ +#define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_ICER register *******************/ +#define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-enable bits */ +#define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_ISPR register *******************/ +#define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt set-pending bits */ +#define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_ICPR register *******************/ +#define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-pending bits */ +#define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_IABR register *******************/ +#define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /*!< Interrupt active flags */ +#define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_PRI0 register *******************/ +#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */ +#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */ +#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */ +#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */ + +/****************** Bit definition for NVIC_PRI1 register *******************/ +#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */ +#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */ +#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */ +#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */ + +/****************** Bit definition for NVIC_PRI2 register *******************/ +#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */ +#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */ +#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */ +#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */ + +/****************** Bit definition for NVIC_PRI3 register *******************/ +#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */ +#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */ +#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */ +#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */ + +/****************** Bit definition for NVIC_PRI4 register *******************/ +#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */ +#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */ +#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */ +#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */ + +/****************** Bit definition for NVIC_PRI5 register *******************/ +#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */ +#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */ +#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */ +#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */ + +/****************** Bit definition for NVIC_PRI6 register *******************/ +#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */ +#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */ +#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */ +#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */ + +/****************** Bit definition for NVIC_PRI7 register *******************/ +#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */ +#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */ +#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */ +#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */ + +/****************** Bit definition for SCB_CPUID register *******************/ +#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */ +#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */ +#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */ +#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */ +#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */ + +/******************* Bit definition for SCB_ICSR register *******************/ +#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */ +#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */ +#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */ +#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */ +#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */ +#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */ +#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */ +#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */ +#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */ +#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */ + +/******************* Bit definition for SCB_VTOR register *******************/ +#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */ +#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */ + +/*!<***************** Bit definition for SCB_AIRCR register *******************/ +#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */ +#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */ +#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */ + +#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */ +#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */ + +/* prority group configuration */ +#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */ +#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */ + +#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */ +#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */ + +/******************* Bit definition for SCB_SCR register ********************/ +#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< Sleep on exit bit */ +#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< Sleep deep bit */ +#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< Wake up from WFE */ + +/******************** Bit definition for SCB_CCR register *******************/ +#define SCB_CCR_NONBASETHRDENA ((uint16_t)0x0001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */ +#define SCB_CCR_USERSETMPEND ((uint16_t)0x0002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */ +#define SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008) /*!< Trap for unaligned access */ +#define SCB_CCR_DIV_0_TRP ((uint16_t)0x0010) /*!< Trap on Divide by 0 */ +#define SCB_CCR_BFHFNMIGN ((uint16_t)0x0100) /*!< Handlers running at priority -1 and -2 */ +#define SCB_CCR_STKALIGN ((uint16_t)0x0200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */ + +/******************* Bit definition for SCB_SHPR register ********************/ +#define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */ +#define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */ +#define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */ +#define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */ + +/****************** Bit definition for SCB_SHCSR register *******************/ +#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */ +#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */ +#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */ +#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */ +#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */ +#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */ +#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */ +#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */ +#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */ +#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */ +#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */ +#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */ +#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */ +#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */ + +/******************* Bit definition for SCB_CFSR register *******************/ +/*!< MFSR */ +#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /*!< Instruction access violation */ +#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /*!< Data access violation */ +#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /*!< Unstacking error */ +#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /*!< Stacking error */ +#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /*!< Memory Manage Address Register address valid flag */ +/*!< BFSR */ +#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /*!< Instruction bus error flag */ +#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /*!< Precise data bus error */ +#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /*!< Imprecise data bus error */ +#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /*!< Unstacking error */ +#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /*!< Stacking error */ +#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /*!< Bus Fault Address Register address valid flag */ +/*!< UFSR */ +#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to excecute an undefined instruction */ +#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /*!< Invalid combination of EPSR and instruction */ +#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /*!< Attempt to load EXC_RETURN into pc illegally */ +#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /*!< Attempt to use a coprocessor instruction */ +#define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /*!< Fault occurs when there is an attempt to make an unaligned memory access */ +#define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */ + +/******************* Bit definition for SCB_HFSR register *******************/ +#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occures because of vector table read on exception processing */ +#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */ +#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */ + +/******************* Bit definition for SCB_DFSR register *******************/ +#define SCB_DFSR_HALTED ((uint8_t)0x01) /*!< Halt request flag */ +#define SCB_DFSR_BKPT ((uint8_t)0x02) /*!< BKPT flag */ +#define SCB_DFSR_DWTTRAP ((uint8_t)0x04) /*!< Data Watchpoint and Trace (DWT) flag */ +#define SCB_DFSR_VCATCH ((uint8_t)0x08) /*!< Vector catch flag */ +#define SCB_DFSR_EXTERNAL ((uint8_t)0x10) /*!< External debug request flag */ + +/******************* Bit definition for SCB_MMFAR register ******************/ +#define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Mem Manage fault address field */ + +/******************* Bit definition for SCB_BFAR register *******************/ +#define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Bus fault address field */ + +/******************* Bit definition for SCB_afsr register *******************/ +#define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /*!< Implementation defined */ + +/******************************************************************************/ +/* */ +/* External Interrupt/Event Controller */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for EXTI_IMR register *******************/ +#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */ +#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */ +#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */ +#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */ +#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */ +#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */ +#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */ +#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */ +#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */ +#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */ +#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */ +#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */ +#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */ +#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */ +#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */ +#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */ +#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */ +#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */ +#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */ +#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */ + +/******************* Bit definition for EXTI_EMR register *******************/ +#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */ +#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */ +#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */ +#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */ +#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */ +#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */ +#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */ +#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */ +#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */ +#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */ +#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */ +#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */ +#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */ +#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */ +#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */ +#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */ +#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */ +#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */ +#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */ +#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */ + +/****************** Bit definition for EXTI_RTSR register *******************/ +#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */ +#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */ +#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */ +#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */ +#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */ +#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */ +#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */ +#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */ +#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */ +#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */ +#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */ +#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */ +#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */ +#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */ +#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */ +#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */ +#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */ +#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */ +#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */ +#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */ + +/****************** Bit definition for EXTI_FTSR register *******************/ +#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */ +#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */ +#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */ +#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */ +#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */ +#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */ +#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */ +#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */ +#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */ +#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */ +#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */ +#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */ +#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */ +#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */ +#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */ +#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */ +#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */ +#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */ +#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */ +#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */ + +/****************** Bit definition for EXTI_SWIER register ******************/ +#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */ +#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */ +#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */ +#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */ +#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */ +#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */ +#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */ +#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */ +#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */ +#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */ +#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */ +#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */ +#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */ +#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */ +#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */ +#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */ +#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */ +#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */ +#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */ +#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */ + +/******************* Bit definition for EXTI_PR register ********************/ +#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */ +#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */ +#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */ +#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */ +#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */ +#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */ +#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */ +#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */ +#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */ +#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */ +#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */ +#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */ +#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */ +#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */ +#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */ +#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */ +#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */ +#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */ +#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */ +#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */ + +/******************************************************************************/ +/* */ +/* DMA Controller */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for DMA_ISR register ********************/ +#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */ +#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */ +#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */ +#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */ +#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */ +#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */ +#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */ +#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */ +#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */ +#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */ +#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */ +#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */ +#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */ +#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */ +#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */ +#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */ +#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */ +#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */ +#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */ +#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */ +#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */ +#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */ +#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */ +#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */ +#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */ +#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */ +#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */ +#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */ + +/******************* Bit definition for DMA_IFCR register *******************/ +#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clearr */ +#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */ +#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */ +#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */ +#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */ +#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */ +#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */ +#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */ +#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */ +#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */ +#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */ +#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */ +#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */ +#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */ +#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */ +#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */ +#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */ +#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */ +#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */ +#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */ +#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */ +#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */ +#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */ +#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */ +#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */ +#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */ +#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */ +#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */ + +/******************* Bit definition for DMA_CCR1 register *******************/ +#define DMA_CCR1_EN ((uint16_t)0x0001) /*!< Channel enable*/ +#define DMA_CCR1_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CCR1_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CCR1_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CCR1_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CCR1_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CCR1_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CCR1_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CCR1_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR1_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CCR1_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CCR1_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR1_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CCR1_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CCR1_PL ((uint16_t)0x3000) /*!< PL[1:0] bits(Channel Priority level) */ +#define DMA_CCR1_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CCR1_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CCR1_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ + +/******************* Bit definition for DMA_CCR2 register *******************/ +#define DMA_CCR2_EN ((uint16_t)0x0001) /*!< Channel enable */ +#define DMA_CCR2_TCIE ((uint16_t)0x0002) /*!< ransfer complete interrupt enable */ +#define DMA_CCR2_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CCR2_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CCR2_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CCR2_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CCR2_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CCR2_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CCR2_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR2_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CCR2_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CCR2_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR2_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CCR2_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CCR2_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ +#define DMA_CCR2_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CCR2_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CCR2_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ + +/******************* Bit definition for DMA_CCR3 register *******************/ +#define DMA_CCR3_EN ((uint16_t)0x0001) /*!< Channel enable */ +#define DMA_CCR3_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CCR3_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CCR3_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CCR3_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CCR3_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CCR3_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CCR3_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CCR3_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR3_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CCR3_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CCR3_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR3_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CCR3_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CCR3_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ +#define DMA_CCR3_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CCR3_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CCR3_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ + +/*!<****************** Bit definition for DMA_CCR4 register *******************/ +#define DMA_CCR4_EN ((uint16_t)0x0001) /*!
© COPYRIGHT 2010 STMicroelectronics
+ ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f10x_system + * @{ + */ + +/** + * @brief Define to prevent recursive inclusion + */ +#ifndef __SYSTEM_STM32F10X_H +#define __SYSTEM_STM32F10X_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup STM32F10x_System_Includes + * @{ + */ + +/** + * @} + */ + + +/** @addtogroup STM32F10x_System_Exported_types + * @{ + */ + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Exported_Functions + * @{ + */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_STM32F10X_H */ + +/** + * @} + */ + +/** + * @} + */ +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32f10x/misc.h b/example/libs_stm/inc/stm32f10x/misc.h new file mode 100644 index 0000000..95c9541 --- /dev/null +++ b/example/libs_stm/inc/stm32f10x/misc.h @@ -0,0 +1,219 @@ +/** + ****************************************************************************** + * @file misc.h + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file contains all the functions prototypes for the miscellaneous + * firmware library functions (add-on to CMSIS functions). + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MISC_H +#define __MISC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup MISC + * @{ + */ + +/** @defgroup MISC_Exported_Types + * @{ + */ + +/** + * @brief NVIC Init Structure definition + */ + +typedef struct +{ + uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled. + This parameter can be a value of @ref IRQn_Type + (For the complete STM32 Devices IRQ Channels list, please + refer to stm32f10x.h file) */ + + uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel + specified in NVIC_IRQChannel. This parameter can be a value + between 0 and 15 as described in the table @ref NVIC_Priority_Table */ + + uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified + in NVIC_IRQChannel. This parameter can be a value + between 0 and 15 as described in the table @ref NVIC_Priority_Table */ + + FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel + will be enabled or disabled. + This parameter can be set either to ENABLE or DISABLE */ +} NVIC_InitTypeDef; + +/** + * @} + */ + +/** @defgroup NVIC_Priority_Table + * @{ + */ + +/** +@code + The table below gives the allowed values of the pre-emption priority and subpriority according + to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function + ============================================================================================================================ + NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description + ============================================================================================================================ + NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority + | | | 4 bits for subpriority + ---------------------------------------------------------------------------------------------------------------------------- + NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority + | | | 3 bits for subpriority + ---------------------------------------------------------------------------------------------------------------------------- + NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority + | | | 2 bits for subpriority + ---------------------------------------------------------------------------------------------------------------------------- + NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority + | | | 1 bits for subpriority + ---------------------------------------------------------------------------------------------------------------------------- + NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority + | | | 0 bits for subpriority + ============================================================================================================================ +@endcode +*/ + +/** + * @} + */ + +/** @defgroup MISC_Exported_Constants + * @{ + */ + +/** @defgroup Vector_Table_Base + * @{ + */ + +#define NVIC_VectTab_RAM ((uint32_t)0x20000000) +#define NVIC_VectTab_FLASH ((uint32_t)0x08000000) +#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \ + ((VECTTAB) == NVIC_VectTab_FLASH)) +/** + * @} + */ + +/** @defgroup System_Low_Power + * @{ + */ + +#define NVIC_LP_SEVONPEND ((uint8_t)0x10) +#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04) +#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02) +#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \ + ((LP) == NVIC_LP_SLEEPDEEP) || \ + ((LP) == NVIC_LP_SLEEPONEXIT)) +/** + * @} + */ + +/** @defgroup Preemption_Priority_Group + * @{ + */ + +#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority + 4 bits for subpriority */ +#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority + 3 bits for subpriority */ +#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority + 2 bits for subpriority */ +#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority + 1 bits for subpriority */ +#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority + 0 bits for subpriority */ + +#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \ + ((GROUP) == NVIC_PriorityGroup_1) || \ + ((GROUP) == NVIC_PriorityGroup_2) || \ + ((GROUP) == NVIC_PriorityGroup_3) || \ + ((GROUP) == NVIC_PriorityGroup_4)) + +#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) + +#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) + +#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF) + +/** + * @} + */ + +/** @defgroup SysTick_clock_source + * @{ + */ + +#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) +#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) +#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \ + ((SOURCE) == SysTick_CLKSource_HCLK_Div8)) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup MISC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup MISC_Exported_Functions + * @{ + */ + +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); +void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); +void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset); +void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState); +void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource); + +#ifdef __cplusplus +} +#endif + +#endif /* __MISC_H */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32f10x/stm32f10x_adc.h b/example/libs_stm/inc/stm32f10x/stm32f10x_adc.h new file mode 100644 index 0000000..401241c --- /dev/null +++ b/example/libs_stm/inc/stm32f10x/stm32f10x_adc.h @@ -0,0 +1,482 @@ +/** + ****************************************************************************** + * @file stm32f10x_adc.h + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file contains all the functions prototypes for the ADC firmware + * library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_ADC_H +#define __STM32F10x_ADC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup ADC + * @{ + */ + +/** @defgroup ADC_Exported_Types + * @{ + */ + +/** + * @brief ADC Init structure definition + */ + +typedef struct +{ + uint32_t ADC_Mode; /*!< Configures the ADC to operate in independent or + dual mode. + This parameter can be a value of @ref ADC_mode */ + + FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion is performed in + Scan (multichannels) or Single (one channel) mode. + This parameter can be set to ENABLE or DISABLE */ + + FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in + Continuous or Single mode. + This parameter can be set to ENABLE or DISABLE. */ + + uint32_t ADC_ExternalTrigConv; /*!< Defines the external trigger used to start the analog + to digital conversion of regular channels. This parameter + can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */ + + uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment is left or right. + This parameter can be a value of @ref ADC_data_align */ + + uint8_t ADC_NbrOfChannel; /*!< Specifies the number of ADC channels that will be converted + using the sequencer for regular channel group. + This parameter must range from 1 to 16. */ +}ADC_InitTypeDef; +/** + * @} + */ + +/** @defgroup ADC_Exported_Constants + * @{ + */ + +#define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \ + ((PERIPH) == ADC2) || \ + ((PERIPH) == ADC3)) + +#define IS_ADC_DMA_PERIPH(PERIPH) (((PERIPH) == ADC1) || \ + ((PERIPH) == ADC3)) + +/** @defgroup ADC_mode + * @{ + */ + +#define ADC_Mode_Independent ((uint32_t)0x00000000) +#define ADC_Mode_RegInjecSimult ((uint32_t)0x00010000) +#define ADC_Mode_RegSimult_AlterTrig ((uint32_t)0x00020000) +#define ADC_Mode_InjecSimult_FastInterl ((uint32_t)0x00030000) +#define ADC_Mode_InjecSimult_SlowInterl ((uint32_t)0x00040000) +#define ADC_Mode_InjecSimult ((uint32_t)0x00050000) +#define ADC_Mode_RegSimult ((uint32_t)0x00060000) +#define ADC_Mode_FastInterl ((uint32_t)0x00070000) +#define ADC_Mode_SlowInterl ((uint32_t)0x00080000) +#define ADC_Mode_AlterTrig ((uint32_t)0x00090000) + +#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \ + ((MODE) == ADC_Mode_RegInjecSimult) || \ + ((MODE) == ADC_Mode_RegSimult_AlterTrig) || \ + ((MODE) == ADC_Mode_InjecSimult_FastInterl) || \ + ((MODE) == ADC_Mode_InjecSimult_SlowInterl) || \ + ((MODE) == ADC_Mode_InjecSimult) || \ + ((MODE) == ADC_Mode_RegSimult) || \ + ((MODE) == ADC_Mode_FastInterl) || \ + ((MODE) == ADC_Mode_SlowInterl) || \ + ((MODE) == ADC_Mode_AlterTrig)) +/** + * @} + */ + +/** @defgroup ADC_external_trigger_sources_for_regular_channels_conversion + * @{ + */ + +#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000) /*!< For ADC1 and ADC2 */ +#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00020000) /*!< For ADC1 and ADC2 */ +#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x00060000) /*!< For ADC1 and ADC2 */ +#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x00080000) /*!< For ADC1 and ADC2 */ +#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x000A0000) /*!< For ADC1 and ADC2 */ +#define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO ((uint32_t)0x000C0000) /*!< For ADC1 and ADC2 */ + +#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x00040000) /*!< For ADC1, ADC2 and ADC3 */ +#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000) /*!< For ADC1, ADC2 and ADC3 */ + +#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x00000000) /*!< For ADC3 only */ +#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x00020000) /*!< For ADC3 only */ +#define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x00060000) /*!< For ADC3 only */ +#define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x00080000) /*!< For ADC3 only */ +#define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x000A0000) /*!< For ADC3 only */ +#define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x000C0000) /*!< For ADC3 only */ + +#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \ + ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO) || \ + ((REGTRIG) == ADC_ExternalTrigConv_None) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T5_CC3)) +/** + * @} + */ + +/** @defgroup ADC_data_align + * @{ + */ + +#define ADC_DataAlign_Right ((uint32_t)0x00000000) +#define ADC_DataAlign_Left ((uint32_t)0x00000800) +#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \ + ((ALIGN) == ADC_DataAlign_Left)) +/** + * @} + */ + +/** @defgroup ADC_channels + * @{ + */ + +#define ADC_Channel_0 ((uint8_t)0x00) +#define ADC_Channel_1 ((uint8_t)0x01) +#define ADC_Channel_2 ((uint8_t)0x02) +#define ADC_Channel_3 ((uint8_t)0x03) +#define ADC_Channel_4 ((uint8_t)0x04) +#define ADC_Channel_5 ((uint8_t)0x05) +#define ADC_Channel_6 ((uint8_t)0x06) +#define ADC_Channel_7 ((uint8_t)0x07) +#define ADC_Channel_8 ((uint8_t)0x08) +#define ADC_Channel_9 ((uint8_t)0x09) +#define ADC_Channel_10 ((uint8_t)0x0A) +#define ADC_Channel_11 ((uint8_t)0x0B) +#define ADC_Channel_12 ((uint8_t)0x0C) +#define ADC_Channel_13 ((uint8_t)0x0D) +#define ADC_Channel_14 ((uint8_t)0x0E) +#define ADC_Channel_15 ((uint8_t)0x0F) +#define ADC_Channel_16 ((uint8_t)0x10) +#define ADC_Channel_17 ((uint8_t)0x11) + +#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16) +#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17) + +#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || ((CHANNEL) == ADC_Channel_1) || \ + ((CHANNEL) == ADC_Channel_2) || ((CHANNEL) == ADC_Channel_3) || \ + ((CHANNEL) == ADC_Channel_4) || ((CHANNEL) == ADC_Channel_5) || \ + ((CHANNEL) == ADC_Channel_6) || ((CHANNEL) == ADC_Channel_7) || \ + ((CHANNEL) == ADC_Channel_8) || ((CHANNEL) == ADC_Channel_9) || \ + ((CHANNEL) == ADC_Channel_10) || ((CHANNEL) == ADC_Channel_11) || \ + ((CHANNEL) == ADC_Channel_12) || ((CHANNEL) == ADC_Channel_13) || \ + ((CHANNEL) == ADC_Channel_14) || ((CHANNEL) == ADC_Channel_15) || \ + ((CHANNEL) == ADC_Channel_16) || ((CHANNEL) == ADC_Channel_17)) +/** + * @} + */ + +/** @defgroup ADC_sampling_time + * @{ + */ + +#define ADC_SampleTime_1Cycles5 ((uint8_t)0x00) +#define ADC_SampleTime_7Cycles5 ((uint8_t)0x01) +#define ADC_SampleTime_13Cycles5 ((uint8_t)0x02) +#define ADC_SampleTime_28Cycles5 ((uint8_t)0x03) +#define ADC_SampleTime_41Cycles5 ((uint8_t)0x04) +#define ADC_SampleTime_55Cycles5 ((uint8_t)0x05) +#define ADC_SampleTime_71Cycles5 ((uint8_t)0x06) +#define ADC_SampleTime_239Cycles5 ((uint8_t)0x07) +#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1Cycles5) || \ + ((TIME) == ADC_SampleTime_7Cycles5) || \ + ((TIME) == ADC_SampleTime_13Cycles5) || \ + ((TIME) == ADC_SampleTime_28Cycles5) || \ + ((TIME) == ADC_SampleTime_41Cycles5) || \ + ((TIME) == ADC_SampleTime_55Cycles5) || \ + ((TIME) == ADC_SampleTime_71Cycles5) || \ + ((TIME) == ADC_SampleTime_239Cycles5)) +/** + * @} + */ + +/** @defgroup ADC_external_trigger_sources_for_injected_channels_conversion + * @{ + */ + +#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00002000) /*!< For ADC1 and ADC2 */ +#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00003000) /*!< For ADC1 and ADC2 */ +#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00004000) /*!< For ADC1 and ADC2 */ +#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00005000) /*!< For ADC1 and ADC2 */ +#define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((uint32_t)0x00006000) /*!< For ADC1 and ADC2 */ + +#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00000000) /*!< For ADC1, ADC2 and ADC3 */ +#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000) /*!< For ADC1, ADC2 and ADC3 */ +#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000) /*!< For ADC1, ADC2 and ADC3 */ + +#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00002000) /*!< For ADC3 only */ +#define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x00003000) /*!< For ADC3 only */ +#define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x00004000) /*!< For ADC3 only */ +#define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x00005000) /*!< For ADC3 only */ +#define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x00006000) /*!< For ADC3 only */ + +#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_None) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4)) +/** + * @} + */ + +/** @defgroup ADC_injected_channel_selection + * @{ + */ + +#define ADC_InjectedChannel_1 ((uint8_t)0x14) +#define ADC_InjectedChannel_2 ((uint8_t)0x18) +#define ADC_InjectedChannel_3 ((uint8_t)0x1C) +#define ADC_InjectedChannel_4 ((uint8_t)0x20) +#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \ + ((CHANNEL) == ADC_InjectedChannel_2) || \ + ((CHANNEL) == ADC_InjectedChannel_3) || \ + ((CHANNEL) == ADC_InjectedChannel_4)) +/** + * @} + */ + +/** @defgroup ADC_analog_watchdog_selection + * @{ + */ + +#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200) +#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200) +#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) +#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) +#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000) +#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000) +#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) + +#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \ + ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \ + ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \ + ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \ + ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \ + ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \ + ((WATCHDOG) == ADC_AnalogWatchdog_None)) +/** + * @} + */ + +/** @defgroup ADC_interrupts_definition + * @{ + */ + +#define ADC_IT_EOC ((uint16_t)0x0220) +#define ADC_IT_AWD ((uint16_t)0x0140) +#define ADC_IT_JEOC ((uint16_t)0x0480) + +#define IS_ADC_IT(IT) ((((IT) & (uint16_t)0xF81F) == 0x00) && ((IT) != 0x00)) + +#define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \ + ((IT) == ADC_IT_JEOC)) +/** + * @} + */ + +/** @defgroup ADC_flags_definition + * @{ + */ + +#define ADC_FLAG_AWD ((uint8_t)0x01) +#define ADC_FLAG_EOC ((uint8_t)0x02) +#define ADC_FLAG_JEOC ((uint8_t)0x04) +#define ADC_FLAG_JSTRT ((uint8_t)0x08) +#define ADC_FLAG_STRT ((uint8_t)0x10) +#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xE0) == 0x00) && ((FLAG) != 0x00)) +#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_EOC) || \ + ((FLAG) == ADC_FLAG_JEOC) || ((FLAG)== ADC_FLAG_JSTRT) || \ + ((FLAG) == ADC_FLAG_STRT)) +/** + * @} + */ + +/** @defgroup ADC_thresholds + * @{ + */ + +#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF) + +/** + * @} + */ + +/** @defgroup ADC_injected_offset + * @{ + */ + +#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF) + +/** + * @} + */ + +/** @defgroup ADC_injected_length + * @{ + */ + +#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4)) + +/** + * @} + */ + +/** @defgroup ADC_injected_rank + * @{ + */ + +#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4)) + +/** + * @} + */ + + +/** @defgroup ADC_regular_length + * @{ + */ + +#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10)) +/** + * @} + */ + +/** @defgroup ADC_regular_rank + * @{ + */ + +#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10)) + +/** + * @} + */ + +/** @defgroup ADC_regular_discontinuous_mode_number + * @{ + */ + +#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8)) + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup ADC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup ADC_Exported_Functions + * @{ + */ + +void ADC_DeInit(ADC_TypeDef* ADCx); +void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct); +void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct); +void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState); +void ADC_ResetCalibration(ADC_TypeDef* ADCx); +FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx); +void ADC_StartCalibration(ADC_TypeDef* ADCx); +FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx); +void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx); +void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number); +void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); +void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx); +uint32_t ADC_GetDualModeConversionValue(void); +void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv); +void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx); +void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); +void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length); +void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset); +uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel); +void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog); +void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, uint16_t LowThreshold); +void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel); +void ADC_TempSensorVrefintCmd(FunctionalState NewState); +FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); +void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); +ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT); +void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F10x_ADC_H */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32f10x/stm32f10x_bkp.h b/example/libs_stm/inc/stm32f10x/stm32f10x_bkp.h new file mode 100644 index 0000000..45c4e35 --- /dev/null +++ b/example/libs_stm/inc/stm32f10x/stm32f10x_bkp.h @@ -0,0 +1,194 @@ +/** + ****************************************************************************** + * @file stm32f10x_bkp.h + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file contains all the functions prototypes for the BKP firmware + * library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_BKP_H +#define __STM32F10x_BKP_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup BKP + * @{ + */ + +/** @defgroup BKP_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @defgroup BKP_Exported_Constants + * @{ + */ + +/** @defgroup Tamper_Pin_active_level + * @{ + */ + +#define BKP_TamperPinLevel_High ((uint16_t)0x0000) +#define BKP_TamperPinLevel_Low ((uint16_t)0x0001) +#define IS_BKP_TAMPER_PIN_LEVEL(LEVEL) (((LEVEL) == BKP_TamperPinLevel_High) || \ + ((LEVEL) == BKP_TamperPinLevel_Low)) +/** + * @} + */ + +/** @defgroup RTC_output_source_to_output_on_the_Tamper_pin + * @{ + */ + +#define BKP_RTCOutputSource_None ((uint16_t)0x0000) +#define BKP_RTCOutputSource_CalibClock ((uint16_t)0x0080) +#define BKP_RTCOutputSource_Alarm ((uint16_t)0x0100) +#define BKP_RTCOutputSource_Second ((uint16_t)0x0300) +#define IS_BKP_RTC_OUTPUT_SOURCE(SOURCE) (((SOURCE) == BKP_RTCOutputSource_None) || \ + ((SOURCE) == BKP_RTCOutputSource_CalibClock) || \ + ((SOURCE) == BKP_RTCOutputSource_Alarm) || \ + ((SOURCE) == BKP_RTCOutputSource_Second)) +/** + * @} + */ + +/** @defgroup Data_Backup_Register + * @{ + */ + +#define BKP_DR1 ((uint16_t)0x0004) +#define BKP_DR2 ((uint16_t)0x0008) +#define BKP_DR3 ((uint16_t)0x000C) +#define BKP_DR4 ((uint16_t)0x0010) +#define BKP_DR5 ((uint16_t)0x0014) +#define BKP_DR6 ((uint16_t)0x0018) +#define BKP_DR7 ((uint16_t)0x001C) +#define BKP_DR8 ((uint16_t)0x0020) +#define BKP_DR9 ((uint16_t)0x0024) +#define BKP_DR10 ((uint16_t)0x0028) +#define BKP_DR11 ((uint16_t)0x0040) +#define BKP_DR12 ((uint16_t)0x0044) +#define BKP_DR13 ((uint16_t)0x0048) +#define BKP_DR14 ((uint16_t)0x004C) +#define BKP_DR15 ((uint16_t)0x0050) +#define BKP_DR16 ((uint16_t)0x0054) +#define BKP_DR17 ((uint16_t)0x0058) +#define BKP_DR18 ((uint16_t)0x005C) +#define BKP_DR19 ((uint16_t)0x0060) +#define BKP_DR20 ((uint16_t)0x0064) +#define BKP_DR21 ((uint16_t)0x0068) +#define BKP_DR22 ((uint16_t)0x006C) +#define BKP_DR23 ((uint16_t)0x0070) +#define BKP_DR24 ((uint16_t)0x0074) +#define BKP_DR25 ((uint16_t)0x0078) +#define BKP_DR26 ((uint16_t)0x007C) +#define BKP_DR27 ((uint16_t)0x0080) +#define BKP_DR28 ((uint16_t)0x0084) +#define BKP_DR29 ((uint16_t)0x0088) +#define BKP_DR30 ((uint16_t)0x008C) +#define BKP_DR31 ((uint16_t)0x0090) +#define BKP_DR32 ((uint16_t)0x0094) +#define BKP_DR33 ((uint16_t)0x0098) +#define BKP_DR34 ((uint16_t)0x009C) +#define BKP_DR35 ((uint16_t)0x00A0) +#define BKP_DR36 ((uint16_t)0x00A4) +#define BKP_DR37 ((uint16_t)0x00A8) +#define BKP_DR38 ((uint16_t)0x00AC) +#define BKP_DR39 ((uint16_t)0x00B0) +#define BKP_DR40 ((uint16_t)0x00B4) +#define BKP_DR41 ((uint16_t)0x00B8) +#define BKP_DR42 ((uint16_t)0x00BC) + +#define IS_BKP_DR(DR) (((DR) == BKP_DR1) || ((DR) == BKP_DR2) || ((DR) == BKP_DR3) || \ + ((DR) == BKP_DR4) || ((DR) == BKP_DR5) || ((DR) == BKP_DR6) || \ + ((DR) == BKP_DR7) || ((DR) == BKP_DR8) || ((DR) == BKP_DR9) || \ + ((DR) == BKP_DR10) || ((DR) == BKP_DR11) || ((DR) == BKP_DR12) || \ + ((DR) == BKP_DR13) || ((DR) == BKP_DR14) || ((DR) == BKP_DR15) || \ + ((DR) == BKP_DR16) || ((DR) == BKP_DR17) || ((DR) == BKP_DR18) || \ + ((DR) == BKP_DR19) || ((DR) == BKP_DR20) || ((DR) == BKP_DR21) || \ + ((DR) == BKP_DR22) || ((DR) == BKP_DR23) || ((DR) == BKP_DR24) || \ + ((DR) == BKP_DR25) || ((DR) == BKP_DR26) || ((DR) == BKP_DR27) || \ + ((DR) == BKP_DR28) || ((DR) == BKP_DR29) || ((DR) == BKP_DR30) || \ + ((DR) == BKP_DR31) || ((DR) == BKP_DR32) || ((DR) == BKP_DR33) || \ + ((DR) == BKP_DR34) || ((DR) == BKP_DR35) || ((DR) == BKP_DR36) || \ + ((DR) == BKP_DR37) || ((DR) == BKP_DR38) || ((DR) == BKP_DR39) || \ + ((DR) == BKP_DR40) || ((DR) == BKP_DR41) || ((DR) == BKP_DR42)) + +#define IS_BKP_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7F) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup BKP_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup BKP_Exported_Functions + * @{ + */ + +void BKP_DeInit(void); +void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel); +void BKP_TamperPinCmd(FunctionalState NewState); +void BKP_ITConfig(FunctionalState NewState); +void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource); +void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue); +void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data); +uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR); +FlagStatus BKP_GetFlagStatus(void); +void BKP_ClearFlag(void); +ITStatus BKP_GetITStatus(void); +void BKP_ClearITPendingBit(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_BKP_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32f10x/stm32f10x_can.h b/example/libs_stm/inc/stm32f10x/stm32f10x_can.h new file mode 100644 index 0000000..d9ae067 --- /dev/null +++ b/example/libs_stm/inc/stm32f10x/stm32f10x_can.h @@ -0,0 +1,535 @@ +/** + ****************************************************************************** + * @file stm32f10x_can.h + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file contains all the functions prototypes for the CAN firmware + * library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_CAN_H +#define __STM32F10x_CAN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup CAN + * @{ + */ + +/** @defgroup CAN_Exported_Types + * @{ + */ + +#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1) || \ + ((PERIPH) == CAN2)) + +/** + * @brief CAN init structure definition + */ + +typedef struct +{ + uint16_t CAN_Prescaler; /*!< Specifies the length of a time quantum. It ranges from 1 to 1024. */ + + uint8_t CAN_Mode; /*!< Specifies the CAN operating mode. + This parameter can be a value of @ref CAN_operating_mode */ + + uint8_t CAN_SJW; /*!< Specifies the maximum number of time quanta the CAN hardware + is allowed to lengthen or shorten a bit to perform resynchronization. + This parameter can be a value of @ref CAN_synchronisation_jump_width */ + + uint8_t CAN_BS1; /*!< Specifies the number of time quanta in Bit Segment 1. + This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */ + + uint8_t CAN_BS2; /*!< Specifies the number of time quanta in Bit Segment 2. + This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */ + + FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered communication mode. + This parameter can be set either to ENABLE or DISABLE. */ + + FunctionalState CAN_ABOM; /*!< Enable or disable the automatic bus-off management. + This parameter can be set either to ENABLE or DISABLE. */ + + FunctionalState CAN_AWUM; /*!< Enable or disable the automatic wake-up mode. + This parameter can be set either to ENABLE or DISABLE. */ + + FunctionalState CAN_NART; /*!< Enable or disable the no-automatic retransmission mode. + This parameter can be set either to ENABLE or DISABLE. */ + + FunctionalState CAN_RFLM; /*!< Enable or disable the Receive FIFO Locked mode. + This parameter can be set either to ENABLE or DISABLE. */ + + FunctionalState CAN_TXFP; /*!< Enable or disable the transmit FIFO priority. + This parameter can be set either to ENABLE or DISABLE. */ +} CAN_InitTypeDef; + +/** + * @brief CAN filter init structure definition + */ + +typedef struct +{ + uint16_t CAN_FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit + configuration, first one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit + configuration, second one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number, + according to the mode (MSBs for a 32-bit configuration, + first one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterMaskIdLow; /*!< Specifies the filter mask number or identification number, + according to the mode (LSBs for a 32-bit configuration, + second one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter. + This parameter can be a value of @ref CAN_filter_FIFO */ + + uint8_t CAN_FilterNumber; /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */ + + uint8_t CAN_FilterMode; /*!< Specifies the filter mode to be initialized. + This parameter can be a value of @ref CAN_filter_mode */ + + uint8_t CAN_FilterScale; /*!< Specifies the filter scale. + This parameter can be a value of @ref CAN_filter_scale */ + + FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter. + This parameter can be set either to ENABLE or DISABLE. */ +} CAN_FilterInitTypeDef; + +/** + * @brief CAN Tx message structure definition + */ + +typedef struct +{ + uint32_t StdId; /*!< Specifies the standard identifier. + This parameter can be a value between 0 to 0x7FF. */ + + uint32_t ExtId; /*!< Specifies the extended identifier. + This parameter can be a value between 0 to 0x1FFFFFFF. */ + + uint8_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted. + This parameter can be a value of @ref CAN_identifier_type */ + + uint8_t RTR; /*!< Specifies the type of frame for the message that will be transmitted. + This parameter can be a value of @ref CAN_remote_transmission_request */ + + uint8_t DLC; /*!< Specifies the length of the frame that will be transmitted. + This parameter can be a value between 0 to 8 */ + + uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0 to 0xFF. */ +} CanTxMsg; + +/** + * @brief CAN Rx message structure definition + */ + +typedef struct +{ + uint32_t StdId; /*!< Specifies the standard identifier. + This parameter can be a value between 0 to 0x7FF. */ + + uint32_t ExtId; /*!< Specifies the extended identifier. + This parameter can be a value between 0 to 0x1FFFFFFF. */ + + uint8_t IDE; /*!< Specifies the type of identifier for the message that will be received. + This parameter can be a value of @ref CAN_identifier_type */ + + uint8_t RTR; /*!< Specifies the type of frame for the received message. + This parameter can be a value of @ref CAN_remote_transmission_request */ + + uint8_t DLC; /*!< Specifies the length of the frame that will be received. + This parameter can be a value between 0 to 8 */ + + uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to 0xFF. */ + + uint8_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through. + This parameter can be a value between 0 to 0xFF */ +} CanRxMsg; + +/** + * @} + */ + +/** @defgroup CAN_Exported_Constants + * @{ + */ + +/** @defgroup CAN_sleep_constants + * @{ + */ + +#define CANINITFAILED ((uint8_t)0x00) /*!< CAN initialization failed */ +#define CANINITOK ((uint8_t)0x01) /*!< CAN initialization failed */ + +/** + * @} + */ + +/** @defgroup CAN_operating_mode + * @{ + */ + +#define CAN_Mode_Normal ((uint8_t)0x00) /*!< normal mode */ +#define CAN_Mode_LoopBack ((uint8_t)0x01) /*!< loopback mode */ +#define CAN_Mode_Silent ((uint8_t)0x02) /*!< silent mode */ +#define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /*!< loopback combined with silent mode */ + +#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || ((MODE) == CAN_Mode_LoopBack)|| \ + ((MODE) == CAN_Mode_Silent) || ((MODE) == CAN_Mode_Silent_LoopBack)) +/** + * @} + */ + +/** @defgroup CAN_synchronisation_jump_width + * @{ + */ + +#define CAN_SJW_1tq ((uint8_t)0x00) /*!< 1 time quantum */ +#define CAN_SJW_2tq ((uint8_t)0x01) /*!< 2 time quantum */ +#define CAN_SJW_3tq ((uint8_t)0x02) /*!< 3 time quantum */ +#define CAN_SJW_4tq ((uint8_t)0x03) /*!< 4 time quantum */ + +#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \ + ((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq)) +/** + * @} + */ + +/** @defgroup CAN_time_quantum_in_bit_segment_1 + * @{ + */ + +#define CAN_BS1_1tq ((uint8_t)0x00) /*!< 1 time quantum */ +#define CAN_BS1_2tq ((uint8_t)0x01) /*!< 2 time quantum */ +#define CAN_BS1_3tq ((uint8_t)0x02) /*!< 3 time quantum */ +#define CAN_BS1_4tq ((uint8_t)0x03) /*!< 4 time quantum */ +#define CAN_BS1_5tq ((uint8_t)0x04) /*!< 5 time quantum */ +#define CAN_BS1_6tq ((uint8_t)0x05) /*!< 6 time quantum */ +#define CAN_BS1_7tq ((uint8_t)0x06) /*!< 7 time quantum */ +#define CAN_BS1_8tq ((uint8_t)0x07) /*!< 8 time quantum */ +#define CAN_BS1_9tq ((uint8_t)0x08) /*!< 9 time quantum */ +#define CAN_BS1_10tq ((uint8_t)0x09) /*!< 10 time quantum */ +#define CAN_BS1_11tq ((uint8_t)0x0A) /*!< 11 time quantum */ +#define CAN_BS1_12tq ((uint8_t)0x0B) /*!< 12 time quantum */ +#define CAN_BS1_13tq ((uint8_t)0x0C) /*!< 13 time quantum */ +#define CAN_BS1_14tq ((uint8_t)0x0D) /*!< 14 time quantum */ +#define CAN_BS1_15tq ((uint8_t)0x0E) /*!< 15 time quantum */ +#define CAN_BS1_16tq ((uint8_t)0x0F) /*!< 16 time quantum */ + +#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq) +/** + * @} + */ + +/** @defgroup CAN_time_quantum_in_bit_segment_2 + * @{ + */ + +#define CAN_BS2_1tq ((uint8_t)0x00) /*!< 1 time quantum */ +#define CAN_BS2_2tq ((uint8_t)0x01) /*!< 2 time quantum */ +#define CAN_BS2_3tq ((uint8_t)0x02) /*!< 3 time quantum */ +#define CAN_BS2_4tq ((uint8_t)0x03) /*!< 4 time quantum */ +#define CAN_BS2_5tq ((uint8_t)0x04) /*!< 5 time quantum */ +#define CAN_BS2_6tq ((uint8_t)0x05) /*!< 6 time quantum */ +#define CAN_BS2_7tq ((uint8_t)0x06) /*!< 7 time quantum */ +#define CAN_BS2_8tq ((uint8_t)0x07) /*!< 8 time quantum */ + +#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq) + +/** + * @} + */ + +/** @defgroup CAN_clock_prescaler + * @{ + */ + +#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024)) + +/** + * @} + */ + +/** @defgroup CAN_filter_number + * @{ + */ +#ifndef STM32F10X_CL + #define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 13) +#else + #define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27) +#endif /* STM32F10X_CL */ +/** + * @} + */ + +/** @defgroup CAN_filter_mode + * @{ + */ + +#define CAN_FilterMode_IdMask ((uint8_t)0x00) /*!< id/mask mode */ +#define CAN_FilterMode_IdList ((uint8_t)0x01) /*!< identifier list mode */ + +#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \ + ((MODE) == CAN_FilterMode_IdList)) +/** + * @} + */ + +/** @defgroup CAN_filter_scale + * @{ + */ + +#define CAN_FilterScale_16bit ((uint8_t)0x00) /*!< Two 16-bit filters */ +#define CAN_FilterScale_32bit ((uint8_t)0x01) /*!< One 32-bit filter */ + +#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \ + ((SCALE) == CAN_FilterScale_32bit)) + +/** + * @} + */ + +/** @defgroup CAN_filter_FIFO + * @{ + */ + +#define CAN_FilterFIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */ +#define CAN_FilterFIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */ +#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \ + ((FIFO) == CAN_FilterFIFO1)) + +/** + * @} + */ + +/** @defgroup Start_bank_filter_for_slave_CAN + * @{ + */ +#define IS_CAN_BANKNUMBER(BANKNUMBER) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27)) +/** + * @} + */ + +/** @defgroup CAN_Tx + * @{ + */ + +#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02)) +#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF)) +#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF)) +#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08)) + +/** + * @} + */ + +/** @defgroup CAN_identifier_type + * @{ + */ + +#define CAN_ID_STD ((uint32_t)0x00000000) /*!< Standard Id */ +#define CAN_ID_EXT ((uint32_t)0x00000004) /*!< Extended Id */ +#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || ((IDTYPE) == CAN_ID_EXT)) + +/** + * @} + */ + +/** @defgroup CAN_remote_transmission_request + * @{ + */ + +#define CAN_RTR_DATA ((uint32_t)0x00000000) /*!< Data frame */ +#define CAN_RTR_REMOTE ((uint32_t)0x00000002) /*!< Remote frame */ +#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE)) + +/** + * @} + */ + +/** @defgroup CAN_transmit_constants + * @{ + */ + +#define CANTXFAILED ((uint8_t)0x00) /*!< CAN transmission failed */ +#define CANTXOK ((uint8_t)0x01) /*!< CAN transmission succeeded */ +#define CANTXPENDING ((uint8_t)0x02) /*!< CAN transmission pending */ +#define CAN_NO_MB ((uint8_t)0x04) /*!< CAN cell did not provide an empty mailbox */ + +/** + * @} + */ + +/** @defgroup CAN_receive_FIFO_number_constants + * @{ + */ + +#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO0 used to receive */ +#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO1 used to receive */ + +#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1)) + +/** + * @} + */ + +/** @defgroup CAN_sleep_constants + * @{ + */ + +#define CANSLEEPFAILED ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */ +#define CANSLEEPOK ((uint8_t)0x01) /*!< CAN entered the sleep mode */ + +/** + * @} + */ + +/** @defgroup CAN_wake_up_constants + * @{ + */ + +#define CANWAKEUPFAILED ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */ +#define CANWAKEUPOK ((uint8_t)0x01) /*!< CAN leaved the sleep mode */ + +/** + * @} + */ + +/** @defgroup CAN_flags + * @{ + */ + +#define CAN_FLAG_EWG ((uint32_t)0x00000001) /*!< Error Warning Flag */ +#define CAN_FLAG_EPV ((uint32_t)0x00000002) /*!< Error Passive Flag */ +#define CAN_FLAG_BOF ((uint32_t)0x00000004) /*!< Bus-Off Flag */ + +#define IS_CAN_FLAG(FLAG) (((FLAG) == CAN_FLAG_EWG) || ((FLAG) == CAN_FLAG_EPV) ||\ + ((FLAG) == CAN_FLAG_BOF)) + +/** + * @} + */ + +/** @defgroup CAN_interrupts + * @{ + */ + +#define CAN_IT_RQCP0 ((uint32_t)0x00000005) /*!< Request completed mailbox 0 */ +#define CAN_IT_RQCP1 ((uint32_t)0x00000006) /*!< Request completed mailbox 1 */ +#define CAN_IT_RQCP2 ((uint32_t)0x00000007) /*!< Request completed mailbox 2 */ +#define CAN_IT_TME ((uint32_t)0x00000001) /*!< Transmit mailbox empty */ +#define CAN_IT_FMP0 ((uint32_t)0x00000002) /*!< FIFO 0 message pending */ +#define CAN_IT_FF0 ((uint32_t)0x00000004) /*!< FIFO 0 full */ +#define CAN_IT_FOV0 ((uint32_t)0x00000008) /*!< FIFO 0 overrun */ +#define CAN_IT_FMP1 ((uint32_t)0x00000010) /*!< FIFO 1 message pending */ +#define CAN_IT_FF1 ((uint32_t)0x00000020) /*!< FIFO 1 full */ +#define CAN_IT_FOV1 ((uint32_t)0x00000040) /*!< FIFO 1 overrun */ +#define CAN_IT_EWG ((uint32_t)0x00000100) /*!< Error warning */ +#define CAN_IT_EPV ((uint32_t)0x00000200) /*!< Error passive */ +#define CAN_IT_BOF ((uint32_t)0x00000400) /*!< Bus-off */ +#define CAN_IT_LEC ((uint32_t)0x00000800) /*!< Last error code */ +#define CAN_IT_ERR ((uint32_t)0x00008000) /*!< Error */ +#define CAN_IT_WKU ((uint32_t)0x00010000) /*!< Wake-up */ +#define CAN_IT_SLK ((uint32_t)0x00020000) /*!< Sleep */ + +#define IS_CAN_ITConfig(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\ + ((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\ + ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\ + ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\ + ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ + ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\ + ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) + +#define IS_CAN_ITStatus(IT) (((IT) == CAN_IT_RQCP0) || ((IT) == CAN_IT_RQCP1) ||\ + ((IT) == CAN_IT_RQCP2) || ((IT) == CAN_IT_FF0) ||\ + ((IT) == CAN_IT_FOV0) || ((IT) == CAN_IT_FF1) ||\ + ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\ + ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ + ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup CAN_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup CAN_Exported_Functions + * @{ + */ + +void CAN_DeInit(CAN_TypeDef* CANx); +uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct); +void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct); +void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct); +void CAN_SlaveStartBank(uint8_t CAN_BankNumber); +void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState); +uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage); +uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox); +void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox); +void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber); +uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber); +void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage); +void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState); +uint8_t CAN_Sleep(CAN_TypeDef* CANx); +uint8_t CAN_WakeUp(CAN_TypeDef* CANx); +FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG); +void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG); +ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT); +void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_CAN_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32f10x/stm32f10x_cec.h b/example/libs_stm/inc/stm32f10x/stm32f10x_cec.h new file mode 100644 index 0000000..233a094 --- /dev/null +++ b/example/libs_stm/inc/stm32f10x/stm32f10x_cec.h @@ -0,0 +1,209 @@ +/** + ****************************************************************************** + * @file stm32f10x_cec.h + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file contains all the functions prototypes for the CEC firmware + * library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_CEC_H +#define __STM32F10x_CEC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup CEC + * @{ + */ + + +/** @defgroup CEC_Exported_Types + * @{ + */ + +/** + * @brief CEC Init structure definition + */ +typedef struct +{ + uint16_t CEC_BitTimingMode; /*!< Configures the CEC Bit Timing Error Mode. + This parameter can be a value of @ref CEC_BitTiming_Mode */ + uint16_t CEC_BitPeriodMode; /*!< Configures the CEC Bit Period Error Mode. + This parameter can be a value of @ref CEC_BitPeriod_Mode */ +}CEC_InitTypeDef; + +/** + * @} + */ + +/** @defgroup CEC_Exported_Constants + * @{ + */ + +/** @defgroup CEC_BitTiming_Mode + * @{ + */ +#define CEC_BitTimingStdMode ((uint16_t)0x00) /*!< Bit timing error Standard Mode */ +#define CEC_BitTimingErrFreeMode CEC_CFGR_BTEM /*!< Bit timing error Free Mode */ + +#define IS_CEC_BIT_TIMING_ERROR_MODE(MODE) (((MODE) == CEC_BitTimingStdMode) || \ + ((MODE) == CEC_BitTimingErrFreeMode)) +/** + * @} + */ + +/** @defgroup CEC_BitPeriod_Mode + * @{ + */ +#define CEC_BitPeriodStdMode ((uint16_t)0x00) /*!< Bit period error Standard Mode */ +#define CEC_BitPeriodFlexibleMode CEC_CFGR_BPEM /*!< Bit period error Flexible Mode */ + +#define IS_CEC_BIT_PERIOD_ERROR_MODE(MODE) (((MODE) == CEC_BitPeriodStdMode) || \ + ((MODE) == CEC_BitPeriodFlexibleMode)) +/** + * @} + */ + + +/** @defgroup CEC_interrupts_definition + * @{ + */ +#define CEC_IT_TERR CEC_CSR_TERR +#define CEC_IT_TBTRF CEC_CSR_TBTRF +#define CEC_IT_RERR CEC_CSR_RERR +#define CEC_IT_RBTF CEC_CSR_RBTF +#define IS_CEC_GET_IT(IT) (((IT) == CEC_IT_TERR) || ((IT) == CEC_IT_TBTRF) || \ + ((IT) == CEC_IT_RERR) || ((IT) == CEC_IT_RBTF)) +/** + * @} + */ + + +/** @defgroup CEC_Own_Addres + * @{ + */ +#define IS_CEC_ADDRESS(ADDRESS) ((ADDRESS) < 0x10) +/** + * @} + */ + +/** @defgroup CEC_Prescaler + * @{ + */ +#define IS_CEC_PRESCALER(PRESCALER) ((PRESCALER) <= 0x3FFF) + +/** + * @} + */ + +/** @defgroup CEC_flags_definition + * @{ + */ + +/** + * @brief ESR register flags + */ +#define CEC_FLAG_BTE ((uint32_t)0x10010000) +#define CEC_FLAG_BPE ((uint32_t)0x10020000) +#define CEC_FLAG_RBTFE ((uint32_t)0x10040000) +#define CEC_FLAG_SBE ((uint32_t)0x10080000) +#define CEC_FLAG_ACKE ((uint32_t)0x10100000) +#define CEC_FLAG_LINE ((uint32_t)0x10200000) +#define CEC_FLAG_TBTFE ((uint32_t)0x10400000) + +/** + * @brief CSR register flags + */ +#define CEC_FLAG_TEOM ((uint32_t)0x00000002) +#define CEC_FLAG_TERR ((uint32_t)0x00000004) +#define CEC_FLAG_TBTRF ((uint32_t)0x00000008) +#define CEC_FLAG_RSOM ((uint32_t)0x00000010) +#define CEC_FLAG_REOM ((uint32_t)0x00000020) +#define CEC_FLAG_RERR ((uint32_t)0x00000040) +#define CEC_FLAG_RBTF ((uint32_t)0x00000080) + +#define IS_CEC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFF03) == 0x00) && ((FLAG) != 0x00)) + +#define IS_CEC_GET_FLAG(FLAG) (((FLAG) == CEC_FLAG_BTE) || ((FLAG) == CEC_FLAG_BPE) || \ + ((FLAG) == CEC_FLAG_RBTFE) || ((FLAG)== CEC_FLAG_SBE) || \ + ((FLAG) == CEC_FLAG_ACKE) || ((FLAG) == CEC_FLAG_LINE) || \ + ((FLAG) == CEC_FLAG_TBTFE) || ((FLAG) == CEC_FLAG_TEOM) || \ + ((FLAG) == CEC_FLAG_TERR) || ((FLAG) == CEC_FLAG_TBTRF) || \ + ((FLAG) == CEC_FLAG_RSOM) || ((FLAG) == CEC_FLAG_REOM) || \ + ((FLAG) == CEC_FLAG_RERR) || ((FLAG) == CEC_FLAG_RBTF)) + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup CEC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup CEC_Exported_Functions + * @{ + */ +void CEC_DeInit(void); +void CEC_Init(CEC_InitTypeDef* CEC_InitStruct); +void CEC_Cmd(FunctionalState NewState); +void CEC_ITConfig(FunctionalState NewState); +void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress); +void CEC_SetPrescaler(uint16_t CEC_Prescaler); +void CEC_SendDataByte(uint8_t Data); +uint8_t CEC_ReceiveDataByte(void); +void CEC_StartOfMessage(void); +void CEC_EndOfMessageCmd(FunctionalState NewState); +FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG); +void CEC_ClearFlag(uint32_t CEC_FLAG); +ITStatus CEC_GetITStatus(uint8_t CEC_IT); +void CEC_ClearITPendingBit(uint16_t CEC_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_CEC_H */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32f10x/stm32f10x_crc.h b/example/libs_stm/inc/stm32f10x/stm32f10x_crc.h new file mode 100644 index 0000000..f7b2678 --- /dev/null +++ b/example/libs_stm/inc/stm32f10x/stm32f10x_crc.h @@ -0,0 +1,93 @@ +/** + ****************************************************************************** + * @file stm32f10x_crc.h + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file contains all the functions prototypes for the CRC firmware + * library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_CRC_H +#define __STM32F10x_CRC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup CRC + * @{ + */ + +/** @defgroup CRC_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @defgroup CRC_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @defgroup CRC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup CRC_Exported_Functions + * @{ + */ + +void CRC_ResetDR(void); +uint32_t CRC_CalcCRC(uint32_t Data); +uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength); +uint32_t CRC_GetCRC(void); +void CRC_SetIDRegister(uint8_t IDValue); +uint8_t CRC_GetIDRegister(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_CRC_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32f10x/stm32f10x_dac.h b/example/libs_stm/inc/stm32f10x/stm32f10x_dac.h new file mode 100644 index 0000000..16afbce --- /dev/null +++ b/example/libs_stm/inc/stm32f10x/stm32f10x_dac.h @@ -0,0 +1,316 @@ +/** + ****************************************************************************** + * @file stm32f10x_dac.h + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file contains all the functions prototypes for the DAC firmware + * library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_DAC_H +#define __STM32F10x_DAC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup DAC + * @{ + */ + +/** @defgroup DAC_Exported_Types + * @{ + */ + +/** + * @brief DAC Init structure definition + */ + +typedef struct +{ + uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel. + This parameter can be a value of @ref DAC_trigger_selection */ + + uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves + are generated, or whether no wave is generated. + This parameter can be a value of @ref DAC_wave_generation */ + + uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or + the maximum amplitude triangle generation for the DAC channel. + This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */ + + uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled. + This parameter can be a value of @ref DAC_output_buffer */ +}DAC_InitTypeDef; + +/** + * @} + */ + +/** @defgroup DAC_Exported_Constants + * @{ + */ + +/** @defgroup DAC_trigger_selection + * @{ + */ + +#define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register + has been loaded, and not by external trigger */ +#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel + only in High-density devices*/ +#define DAC_Trigger_T3_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel + only in Connectivity line, Medium-density and Low-density Value Line devices */ +#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T15_TRGO ((uint32_t)0x0000001C) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel + only in Medium-density and Low-density Value Line devices*/ +#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */ + +#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \ + ((TRIGGER) == DAC_Trigger_T6_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T8_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T7_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T5_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T2_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T4_TRGO) || \ + ((TRIGGER) == DAC_Trigger_Ext_IT9) || \ + ((TRIGGER) == DAC_Trigger_Software)) + +/** + * @} + */ + +/** @defgroup DAC_wave_generation + * @{ + */ + +#define DAC_WaveGeneration_None ((uint32_t)0x00000000) +#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040) +#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080) +#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \ + ((WAVE) == DAC_WaveGeneration_Noise) || \ + ((WAVE) == DAC_WaveGeneration_Triangle)) +/** + * @} + */ + +/** @defgroup DAC_lfsrunmask_triangleamplitude + * @{ + */ + +#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */ +#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */ +#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */ +#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */ +#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */ +#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */ +#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */ +#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */ +#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */ +#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */ +#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */ +#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */ +#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */ +#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */ + +#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \ + ((VALUE) == DAC_TriangleAmplitude_1) || \ + ((VALUE) == DAC_TriangleAmplitude_3) || \ + ((VALUE) == DAC_TriangleAmplitude_7) || \ + ((VALUE) == DAC_TriangleAmplitude_15) || \ + ((VALUE) == DAC_TriangleAmplitude_31) || \ + ((VALUE) == DAC_TriangleAmplitude_63) || \ + ((VALUE) == DAC_TriangleAmplitude_127) || \ + ((VALUE) == DAC_TriangleAmplitude_255) || \ + ((VALUE) == DAC_TriangleAmplitude_511) || \ + ((VALUE) == DAC_TriangleAmplitude_1023) || \ + ((VALUE) == DAC_TriangleAmplitude_2047) || \ + ((VALUE) == DAC_TriangleAmplitude_4095)) +/** + * @} + */ + +/** @defgroup DAC_output_buffer + * @{ + */ + +#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000) +#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002) +#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \ + ((STATE) == DAC_OutputBuffer_Disable)) +/** + * @} + */ + +/** @defgroup DAC_Channel_selection + * @{ + */ + +#define DAC_Channel_1 ((uint32_t)0x00000000) +#define DAC_Channel_2 ((uint32_t)0x00000010) +#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \ + ((CHANNEL) == DAC_Channel_2)) +/** + * @} + */ + +/** @defgroup DAC_data_alignement + * @{ + */ + +#define DAC_Align_12b_R ((uint32_t)0x00000000) +#define DAC_Align_12b_L ((uint32_t)0x00000004) +#define DAC_Align_8b_R ((uint32_t)0x00000008) +#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \ + ((ALIGN) == DAC_Align_12b_L) || \ + ((ALIGN) == DAC_Align_8b_R)) +/** + * @} + */ + +/** @defgroup DAC_wave_generation + * @{ + */ + +#define DAC_Wave_Noise ((uint32_t)0x00000040) +#define DAC_Wave_Triangle ((uint32_t)0x00000080) +#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \ + ((WAVE) == DAC_Wave_Triangle)) +/** + * @} + */ + +/** @defgroup DAC_data + * @{ + */ + +#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) +/** + * @} + */ +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) +/** @defgroup DAC_interrupts_definition + * @{ + */ + +#define DAC_IT_DMAUDR ((uint32_t)0x00002000) +#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR)) + +/** + * @} + */ + +/** @defgroup DAC_flags_definition + * @{ + */ + +#define DAC_FLAG_DMAUDR ((uint32_t)0x00002000) +#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR)) + +/** + * @} + */ +#endif + +/** + * @} + */ + +/** @defgroup DAC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup DAC_Exported_Functions + * @{ + */ + +void DAC_DeInit(void); +void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct); +void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct); +void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState); +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) +void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState); +#endif +void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState); +void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState); +void DAC_DualSoftwareTriggerCmd(FunctionalState NewState); +void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState); +void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data); +void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data); +void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1); +uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel); +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) +FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG); +void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG); +ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT); +void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F10x_DAC_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32f10x/stm32f10x_dbgmcu.h b/example/libs_stm/inc/stm32f10x/stm32f10x_dbgmcu.h new file mode 100644 index 0000000..5a78f73 --- /dev/null +++ b/example/libs_stm/inc/stm32f10x/stm32f10x_dbgmcu.h @@ -0,0 +1,118 @@ +/** + ****************************************************************************** + * @file stm32f10x_dbgmcu.h + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file contains all the functions prototypes for the DBGMCU + * firmware library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_DBGMCU_H +#define __STM32F10x_DBGMCU_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup DBGMCU + * @{ + */ + +/** @defgroup DBGMCU_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @defgroup DBGMCU_Exported_Constants + * @{ + */ + +#define DBGMCU_SLEEP ((uint32_t)0x00000001) +#define DBGMCU_STOP ((uint32_t)0x00000002) +#define DBGMCU_STANDBY ((uint32_t)0x00000004) +#define DBGMCU_IWDG_STOP ((uint32_t)0x00000100) +#define DBGMCU_WWDG_STOP ((uint32_t)0x00000200) +#define DBGMCU_TIM1_STOP ((uint32_t)0x00000400) +#define DBGMCU_TIM2_STOP ((uint32_t)0x00000800) +#define DBGMCU_TIM3_STOP ((uint32_t)0x00001000) +#define DBGMCU_TIM4_STOP ((uint32_t)0x00002000) +#define DBGMCU_CAN1_STOP ((uint32_t)0x00004000) +#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) +#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) +#define DBGMCU_TIM8_STOP ((uint32_t)0x00020000) +#define DBGMCU_TIM5_STOP ((uint32_t)0x00040000) +#define DBGMCU_TIM6_STOP ((uint32_t)0x00080000) +#define DBGMCU_TIM7_STOP ((uint32_t)0x00100000) +#define DBGMCU_CAN2_STOP ((uint32_t)0x00200000) +#define DBGMCU_TIM15_STOP ((uint32_t)0x00400000) +#define DBGMCU_TIM16_STOP ((uint32_t)0x00800000) +#define DBGMCU_TIM17_STOP ((uint32_t)0x01000000) +#define DBGMCU_TIM12_STOP ((uint32_t)0x02000000) +#define DBGMCU_TIM13_STOP ((uint32_t)0x04000000) +#define DBGMCU_TIM14_STOP ((uint32_t)0x08000000) +#define DBGMCU_TIM9_STOP ((uint32_t)0x10000000) +#define DBGMCU_TIM10_STOP ((uint32_t)0x20000000) +#define DBGMCU_TIM11_STOP ((uint32_t)0x40000000) + +#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0x800000F8) == 0x00) && ((PERIPH) != 0x00)) +/** + * @} + */ + +/** @defgroup DBGMCU_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup DBGMCU_Exported_Functions + * @{ + */ + +uint32_t DBGMCU_GetREVID(void); +uint32_t DBGMCU_GetDEVID(void); +void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_DBGMCU_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32f10x/stm32f10x_dma.h b/example/libs_stm/inc/stm32f10x/stm32f10x_dma.h new file mode 100644 index 0000000..35769ab --- /dev/null +++ b/example/libs_stm/inc/stm32f10x/stm32f10x_dma.h @@ -0,0 +1,437 @@ +/** + ****************************************************************************** + * @file stm32f10x_dma.h + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file contains all the functions prototypes for the DMA firmware + * library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_DMA_H +#define __STM32F10x_DMA_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup DMA + * @{ + */ + +/** @defgroup DMA_Exported_Types + * @{ + */ + +/** + * @brief DMA Init structure definition + */ + +typedef struct +{ + uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */ + + uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */ + + uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination. + This parameter can be a value of @ref DMA_data_transfer_direction */ + + uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Channel. + The data unit is equal to the configuration set in DMA_PeripheralDataSize + or DMA_MemoryDataSize members depending in the transfer direction. */ + + uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not. + This parameter can be a value of @ref DMA_peripheral_incremented_mode */ + + uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not. + This parameter can be a value of @ref DMA_memory_incremented_mode */ + + uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width. + This parameter can be a value of @ref DMA_peripheral_data_size */ + + uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width. + This parameter can be a value of @ref DMA_memory_data_size */ + + uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx. + This parameter can be a value of @ref DMA_circular_normal_mode. + @note: The circular buffer mode cannot be used if the memory-to-memory + data transfer is configured on the selected Channel */ + + uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx. + This parameter can be a value of @ref DMA_priority_level */ + + uint32_t DMA_M2M; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer. + This parameter can be a value of @ref DMA_memory_to_memory */ +}DMA_InitTypeDef; + +/** + * @} + */ + +/** @defgroup DMA_Exported_Constants + * @{ + */ + +#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \ + ((PERIPH) == DMA1_Channel2) || \ + ((PERIPH) == DMA1_Channel3) || \ + ((PERIPH) == DMA1_Channel4) || \ + ((PERIPH) == DMA1_Channel5) || \ + ((PERIPH) == DMA1_Channel6) || \ + ((PERIPH) == DMA1_Channel7) || \ + ((PERIPH) == DMA2_Channel1) || \ + ((PERIPH) == DMA2_Channel2) || \ + ((PERIPH) == DMA2_Channel3) || \ + ((PERIPH) == DMA2_Channel4) || \ + ((PERIPH) == DMA2_Channel5)) + +/** @defgroup DMA_data_transfer_direction + * @{ + */ + +#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010) +#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000) +#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || \ + ((DIR) == DMA_DIR_PeripheralSRC)) +/** + * @} + */ + +/** @defgroup DMA_peripheral_incremented_mode + * @{ + */ + +#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040) +#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) +#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \ + ((STATE) == DMA_PeripheralInc_Disable)) +/** + * @} + */ + +/** @defgroup DMA_memory_incremented_mode + * @{ + */ + +#define DMA_MemoryInc_Enable ((uint32_t)0x00000080) +#define DMA_MemoryInc_Disable ((uint32_t)0x00000000) +#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \ + ((STATE) == DMA_MemoryInc_Disable)) +/** + * @} + */ + +/** @defgroup DMA_peripheral_data_size + * @{ + */ + +#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) +#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100) +#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200) +#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \ + ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \ + ((SIZE) == DMA_PeripheralDataSize_Word)) +/** + * @} + */ + +/** @defgroup DMA_memory_data_size + * @{ + */ + +#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) +#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400) +#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800) +#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \ + ((SIZE) == DMA_MemoryDataSize_HalfWord) || \ + ((SIZE) == DMA_MemoryDataSize_Word)) +/** + * @} + */ + +/** @defgroup DMA_circular_normal_mode + * @{ + */ + +#define DMA_Mode_Circular ((uint32_t)0x00000020) +#define DMA_Mode_Normal ((uint32_t)0x00000000) +#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal)) +/** + * @} + */ + +/** @defgroup DMA_priority_level + * @{ + */ + +#define DMA_Priority_VeryHigh ((uint32_t)0x00003000) +#define DMA_Priority_High ((uint32_t)0x00002000) +#define DMA_Priority_Medium ((uint32_t)0x00001000) +#define DMA_Priority_Low ((uint32_t)0x00000000) +#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \ + ((PRIORITY) == DMA_Priority_High) || \ + ((PRIORITY) == DMA_Priority_Medium) || \ + ((PRIORITY) == DMA_Priority_Low)) +/** + * @} + */ + +/** @defgroup DMA_memory_to_memory + * @{ + */ + +#define DMA_M2M_Enable ((uint32_t)0x00004000) +#define DMA_M2M_Disable ((uint32_t)0x00000000) +#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable)) + +/** + * @} + */ + +/** @defgroup DMA_interrupts_definition + * @{ + */ + +#define DMA_IT_TC ((uint32_t)0x00000002) +#define DMA_IT_HT ((uint32_t)0x00000004) +#define DMA_IT_TE ((uint32_t)0x00000008) +#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00)) + +#define DMA1_IT_GL1 ((uint32_t)0x00000001) +#define DMA1_IT_TC1 ((uint32_t)0x00000002) +#define DMA1_IT_HT1 ((uint32_t)0x00000004) +#define DMA1_IT_TE1 ((uint32_t)0x00000008) +#define DMA1_IT_GL2 ((uint32_t)0x00000010) +#define DMA1_IT_TC2 ((uint32_t)0x00000020) +#define DMA1_IT_HT2 ((uint32_t)0x00000040) +#define DMA1_IT_TE2 ((uint32_t)0x00000080) +#define DMA1_IT_GL3 ((uint32_t)0x00000100) +#define DMA1_IT_TC3 ((uint32_t)0x00000200) +#define DMA1_IT_HT3 ((uint32_t)0x00000400) +#define DMA1_IT_TE3 ((uint32_t)0x00000800) +#define DMA1_IT_GL4 ((uint32_t)0x00001000) +#define DMA1_IT_TC4 ((uint32_t)0x00002000) +#define DMA1_IT_HT4 ((uint32_t)0x00004000) +#define DMA1_IT_TE4 ((uint32_t)0x00008000) +#define DMA1_IT_GL5 ((uint32_t)0x00010000) +#define DMA1_IT_TC5 ((uint32_t)0x00020000) +#define DMA1_IT_HT5 ((uint32_t)0x00040000) +#define DMA1_IT_TE5 ((uint32_t)0x00080000) +#define DMA1_IT_GL6 ((uint32_t)0x00100000) +#define DMA1_IT_TC6 ((uint32_t)0x00200000) +#define DMA1_IT_HT6 ((uint32_t)0x00400000) +#define DMA1_IT_TE6 ((uint32_t)0x00800000) +#define DMA1_IT_GL7 ((uint32_t)0x01000000) +#define DMA1_IT_TC7 ((uint32_t)0x02000000) +#define DMA1_IT_HT7 ((uint32_t)0x04000000) +#define DMA1_IT_TE7 ((uint32_t)0x08000000) + +#define DMA2_IT_GL1 ((uint32_t)0x10000001) +#define DMA2_IT_TC1 ((uint32_t)0x10000002) +#define DMA2_IT_HT1 ((uint32_t)0x10000004) +#define DMA2_IT_TE1 ((uint32_t)0x10000008) +#define DMA2_IT_GL2 ((uint32_t)0x10000010) +#define DMA2_IT_TC2 ((uint32_t)0x10000020) +#define DMA2_IT_HT2 ((uint32_t)0x10000040) +#define DMA2_IT_TE2 ((uint32_t)0x10000080) +#define DMA2_IT_GL3 ((uint32_t)0x10000100) +#define DMA2_IT_TC3 ((uint32_t)0x10000200) +#define DMA2_IT_HT3 ((uint32_t)0x10000400) +#define DMA2_IT_TE3 ((uint32_t)0x10000800) +#define DMA2_IT_GL4 ((uint32_t)0x10001000) +#define DMA2_IT_TC4 ((uint32_t)0x10002000) +#define DMA2_IT_HT4 ((uint32_t)0x10004000) +#define DMA2_IT_TE4 ((uint32_t)0x10008000) +#define DMA2_IT_GL5 ((uint32_t)0x10010000) +#define DMA2_IT_TC5 ((uint32_t)0x10020000) +#define DMA2_IT_HT5 ((uint32_t)0x10040000) +#define DMA2_IT_TE5 ((uint32_t)0x10080000) + +#define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00)) + +#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \ + ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \ + ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \ + ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \ + ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \ + ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \ + ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \ + ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \ + ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \ + ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \ + ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \ + ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \ + ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \ + ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \ + ((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \ + ((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \ + ((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \ + ((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \ + ((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \ + ((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \ + ((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \ + ((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \ + ((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \ + ((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5)) + +/** + * @} + */ + +/** @defgroup DMA_flags_definition + * @{ + */ +#define DMA1_FLAG_GL1 ((uint32_t)0x00000001) +#define DMA1_FLAG_TC1 ((uint32_t)0x00000002) +#define DMA1_FLAG_HT1 ((uint32_t)0x00000004) +#define DMA1_FLAG_TE1 ((uint32_t)0x00000008) +#define DMA1_FLAG_GL2 ((uint32_t)0x00000010) +#define DMA1_FLAG_TC2 ((uint32_t)0x00000020) +#define DMA1_FLAG_HT2 ((uint32_t)0x00000040) +#define DMA1_FLAG_TE2 ((uint32_t)0x00000080) +#define DMA1_FLAG_GL3 ((uint32_t)0x00000100) +#define DMA1_FLAG_TC3 ((uint32_t)0x00000200) +#define DMA1_FLAG_HT3 ((uint32_t)0x00000400) +#define DMA1_FLAG_TE3 ((uint32_t)0x00000800) +#define DMA1_FLAG_GL4 ((uint32_t)0x00001000) +#define DMA1_FLAG_TC4 ((uint32_t)0x00002000) +#define DMA1_FLAG_HT4 ((uint32_t)0x00004000) +#define DMA1_FLAG_TE4 ((uint32_t)0x00008000) +#define DMA1_FLAG_GL5 ((uint32_t)0x00010000) +#define DMA1_FLAG_TC5 ((uint32_t)0x00020000) +#define DMA1_FLAG_HT5 ((uint32_t)0x00040000) +#define DMA1_FLAG_TE5 ((uint32_t)0x00080000) +#define DMA1_FLAG_GL6 ((uint32_t)0x00100000) +#define DMA1_FLAG_TC6 ((uint32_t)0x00200000) +#define DMA1_FLAG_HT6 ((uint32_t)0x00400000) +#define DMA1_FLAG_TE6 ((uint32_t)0x00800000) +#define DMA1_FLAG_GL7 ((uint32_t)0x01000000) +#define DMA1_FLAG_TC7 ((uint32_t)0x02000000) +#define DMA1_FLAG_HT7 ((uint32_t)0x04000000) +#define DMA1_FLAG_TE7 ((uint32_t)0x08000000) + +#define DMA2_FLAG_GL1 ((uint32_t)0x10000001) +#define DMA2_FLAG_TC1 ((uint32_t)0x10000002) +#define DMA2_FLAG_HT1 ((uint32_t)0x10000004) +#define DMA2_FLAG_TE1 ((uint32_t)0x10000008) +#define DMA2_FLAG_GL2 ((uint32_t)0x10000010) +#define DMA2_FLAG_TC2 ((uint32_t)0x10000020) +#define DMA2_FLAG_HT2 ((uint32_t)0x10000040) +#define DMA2_FLAG_TE2 ((uint32_t)0x10000080) +#define DMA2_FLAG_GL3 ((uint32_t)0x10000100) +#define DMA2_FLAG_TC3 ((uint32_t)0x10000200) +#define DMA2_FLAG_HT3 ((uint32_t)0x10000400) +#define DMA2_FLAG_TE3 ((uint32_t)0x10000800) +#define DMA2_FLAG_GL4 ((uint32_t)0x10001000) +#define DMA2_FLAG_TC4 ((uint32_t)0x10002000) +#define DMA2_FLAG_HT4 ((uint32_t)0x10004000) +#define DMA2_FLAG_TE4 ((uint32_t)0x10008000) +#define DMA2_FLAG_GL5 ((uint32_t)0x10010000) +#define DMA2_FLAG_TC5 ((uint32_t)0x10020000) +#define DMA2_FLAG_HT5 ((uint32_t)0x10040000) +#define DMA2_FLAG_TE5 ((uint32_t)0x10080000) + +#define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00)) + +#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \ + ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \ + ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \ + ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \ + ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \ + ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \ + ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \ + ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \ + ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \ + ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \ + ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \ + ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \ + ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \ + ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \ + ((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \ + ((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \ + ((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \ + ((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \ + ((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \ + ((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \ + ((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \ + ((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \ + ((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \ + ((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5)) +/** + * @} + */ + +/** @defgroup DMA_Buffer_Size + * @{ + */ + +#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup DMA_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup DMA_Exported_Functions + * @{ + */ + +void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx); +void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct); +void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct); +void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState); +void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState); +uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx); +FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG); +void DMA_ClearFlag(uint32_t DMA_FLAG); +ITStatus DMA_GetITStatus(uint32_t DMA_IT); +void DMA_ClearITPendingBit(uint32_t DMA_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F10x_DMA_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32f10x/stm32f10x_exti.h b/example/libs_stm/inc/stm32f10x/stm32f10x_exti.h new file mode 100644 index 0000000..e5f1c5a --- /dev/null +++ b/example/libs_stm/inc/stm32f10x/stm32f10x_exti.h @@ -0,0 +1,183 @@ +/** + ****************************************************************************** + * @file stm32f10x_exti.h + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file contains all the functions prototypes for the EXTI firmware + * library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_EXTI_H +#define __STM32F10x_EXTI_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup EXTI + * @{ + */ + +/** @defgroup EXTI_Exported_Types + * @{ + */ + +/** + * @brief EXTI mode enumeration + */ + +typedef enum +{ + EXTI_Mode_Interrupt = 0x00, + EXTI_Mode_Event = 0x04 +}EXTIMode_TypeDef; + +#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event)) + +/** + * @brief EXTI Trigger enumeration + */ + +typedef enum +{ + EXTI_Trigger_Rising = 0x08, + EXTI_Trigger_Falling = 0x0C, + EXTI_Trigger_Rising_Falling = 0x10 +}EXTITrigger_TypeDef; + +#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \ + ((TRIGGER) == EXTI_Trigger_Falling) || \ + ((TRIGGER) == EXTI_Trigger_Rising_Falling)) +/** + * @brief EXTI Init Structure definition + */ + +typedef struct +{ + uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled. + This parameter can be any combination of @ref EXTI_Lines */ + + EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines. + This parameter can be a value of @ref EXTIMode_TypeDef */ + + EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. + This parameter can be a value of @ref EXTIMode_TypeDef */ + + FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines. + This parameter can be set either to ENABLE or DISABLE */ +}EXTI_InitTypeDef; + +/** + * @} + */ + +/** @defgroup EXTI_Exported_Constants + * @{ + */ + +/** @defgroup EXTI_Lines + * @{ + */ + +#define EXTI_Line0 ((uint32_t)0x00001) /*!< External interrupt line 0 */ +#define EXTI_Line1 ((uint32_t)0x00002) /*!< External interrupt line 1 */ +#define EXTI_Line2 ((uint32_t)0x00004) /*!< External interrupt line 2 */ +#define EXTI_Line3 ((uint32_t)0x00008) /*!< External interrupt line 3 */ +#define EXTI_Line4 ((uint32_t)0x00010) /*!< External interrupt line 4 */ +#define EXTI_Line5 ((uint32_t)0x00020) /*!< External interrupt line 5 */ +#define EXTI_Line6 ((uint32_t)0x00040) /*!< External interrupt line 6 */ +#define EXTI_Line7 ((uint32_t)0x00080) /*!< External interrupt line 7 */ +#define EXTI_Line8 ((uint32_t)0x00100) /*!< External interrupt line 8 */ +#define EXTI_Line9 ((uint32_t)0x00200) /*!< External interrupt line 9 */ +#define EXTI_Line10 ((uint32_t)0x00400) /*!< External interrupt line 10 */ +#define EXTI_Line11 ((uint32_t)0x00800) /*!< External interrupt line 11 */ +#define EXTI_Line12 ((uint32_t)0x01000) /*!< External interrupt line 12 */ +#define EXTI_Line13 ((uint32_t)0x02000) /*!< External interrupt line 13 */ +#define EXTI_Line14 ((uint32_t)0x04000) /*!< External interrupt line 14 */ +#define EXTI_Line15 ((uint32_t)0x08000) /*!< External interrupt line 15 */ +#define EXTI_Line16 ((uint32_t)0x10000) /*!< External interrupt line 16 Connected to the PVD Output */ +#define EXTI_Line17 ((uint32_t)0x20000) /*!< External interrupt line 17 Connected to the RTC Alarm event */ +#define EXTI_Line18 ((uint32_t)0x40000) /*!< External interrupt line 18 Connected to the USB Device/USB OTG FS + Wakeup from suspend event */ +#define EXTI_Line19 ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */ + +#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFFF00000) == 0x00) && ((LINE) != (uint16_t)0x00)) +#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \ + ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \ + ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \ + ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \ + ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \ + ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \ + ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \ + ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \ + ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \ + ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19)) + + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup EXTI_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup EXTI_Exported_Functions + * @{ + */ + +void EXTI_DeInit(void); +void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct); +void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct); +void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); +FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line); +void EXTI_ClearFlag(uint32_t EXTI_Line); +ITStatus EXTI_GetITStatus(uint32_t EXTI_Line); +void EXTI_ClearITPendingBit(uint32_t EXTI_Line); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_EXTI_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32f10x/stm32f10x_flash.h b/example/libs_stm/inc/stm32f10x/stm32f10x_flash.h new file mode 100644 index 0000000..7194301 --- /dev/null +++ b/example/libs_stm/inc/stm32f10x/stm32f10x_flash.h @@ -0,0 +1,425 @@ +/** + ****************************************************************************** + * @file stm32f10x_flash.h + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file contains all the functions prototypes for the FLASH + * firmware library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_FLASH_H +#define __STM32F10x_FLASH_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup FLASH + * @{ + */ + +/** @defgroup FLASH_Exported_Types + * @{ + */ + +/** + * @brief FLASH Status + */ + +typedef enum +{ + FLASH_BUSY = 1, + FLASH_ERROR_PG, + FLASH_ERROR_WRP, + FLASH_COMPLETE, + FLASH_TIMEOUT +}FLASH_Status; + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Constants + * @{ + */ + +/** @defgroup Flash_Latency + * @{ + */ + +#define FLASH_Latency_0 ((uint32_t)0x00000000) /*!< FLASH Zero Latency cycle */ +#define FLASH_Latency_1 ((uint32_t)0x00000001) /*!< FLASH One Latency cycle */ +#define FLASH_Latency_2 ((uint32_t)0x00000002) /*!< FLASH Two Latency cycles */ +#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \ + ((LATENCY) == FLASH_Latency_1) || \ + ((LATENCY) == FLASH_Latency_2)) +/** + * @} + */ + +/** @defgroup Half_Cycle_Enable_Disable + * @{ + */ + +#define FLASH_HalfCycleAccess_Enable ((uint32_t)0x00000008) /*!< FLASH Half Cycle Enable */ +#define FLASH_HalfCycleAccess_Disable ((uint32_t)0x00000000) /*!< FLASH Half Cycle Disable */ +#define IS_FLASH_HALFCYCLEACCESS_STATE(STATE) (((STATE) == FLASH_HalfCycleAccess_Enable) || \ + ((STATE) == FLASH_HalfCycleAccess_Disable)) +/** + * @} + */ + +/** @defgroup Prefetch_Buffer_Enable_Disable + * @{ + */ + +#define FLASH_PrefetchBuffer_Enable ((uint32_t)0x00000010) /*!< FLASH Prefetch Buffer Enable */ +#define FLASH_PrefetchBuffer_Disable ((uint32_t)0x00000000) /*!< FLASH Prefetch Buffer Disable */ +#define IS_FLASH_PREFETCHBUFFER_STATE(STATE) (((STATE) == FLASH_PrefetchBuffer_Enable) || \ + ((STATE) == FLASH_PrefetchBuffer_Disable)) +/** + * @} + */ + +/** @defgroup Option_Bytes_Write_Protection + * @{ + */ + +/* Values to be used with STM32 Low and Medium density devices */ +#define FLASH_WRProt_Pages0to3 ((uint32_t)0x00000001) /*!< STM32 Low and Medium density devices: Write protection of page 0 to 3 */ +#define FLASH_WRProt_Pages4to7 ((uint32_t)0x00000002) /*!< STM32 Low and Medium density devices: Write protection of page 4 to 7 */ +#define FLASH_WRProt_Pages8to11 ((uint32_t)0x00000004) /*!< STM32 Low and Medium density devices: Write protection of page 8 to 11 */ +#define FLASH_WRProt_Pages12to15 ((uint32_t)0x00000008) /*!< STM32 Low and Medium density devices: Write protection of page 12 to 15 */ +#define FLASH_WRProt_Pages16to19 ((uint32_t)0x00000010) /*!< STM32 Low and Medium density devices: Write protection of page 16 to 19 */ +#define FLASH_WRProt_Pages20to23 ((uint32_t)0x00000020) /*!< STM32 Low and Medium density devices: Write protection of page 20 to 23 */ +#define FLASH_WRProt_Pages24to27 ((uint32_t)0x00000040) /*!< STM32 Low and Medium density devices: Write protection of page 24 to 27 */ +#define FLASH_WRProt_Pages28to31 ((uint32_t)0x00000080) /*!< STM32 Low and Medium density devices: Write protection of page 28 to 31 */ + +/* Values to be used with STM32 Medium-density devices */ +#define FLASH_WRProt_Pages32to35 ((uint32_t)0x00000100) /*!< STM32 Medium-density devices: Write protection of page 32 to 35 */ +#define FLASH_WRProt_Pages36to39 ((uint32_t)0x00000200) /*!< STM32 Medium-density devices: Write protection of page 36 to 39 */ +#define FLASH_WRProt_Pages40to43 ((uint32_t)0x00000400) /*!< STM32 Medium-density devices: Write protection of page 40 to 43 */ +#define FLASH_WRProt_Pages44to47 ((uint32_t)0x00000800) /*!< STM32 Medium-density devices: Write protection of page 44 to 47 */ +#define FLASH_WRProt_Pages48to51 ((uint32_t)0x00001000) /*!< STM32 Medium-density devices: Write protection of page 48 to 51 */ +#define FLASH_WRProt_Pages52to55 ((uint32_t)0x00002000) /*!< STM32 Medium-density devices: Write protection of page 52 to 55 */ +#define FLASH_WRProt_Pages56to59 ((uint32_t)0x00004000) /*!< STM32 Medium-density devices: Write protection of page 56 to 59 */ +#define FLASH_WRProt_Pages60to63 ((uint32_t)0x00008000) /*!< STM32 Medium-density devices: Write protection of page 60 to 63 */ +#define FLASH_WRProt_Pages64to67 ((uint32_t)0x00010000) /*!< STM32 Medium-density devices: Write protection of page 64 to 67 */ +#define FLASH_WRProt_Pages68to71 ((uint32_t)0x00020000) /*!< STM32 Medium-density devices: Write protection of page 68 to 71 */ +#define FLASH_WRProt_Pages72to75 ((uint32_t)0x00040000) /*!< STM32 Medium-density devices: Write protection of page 72 to 75 */ +#define FLASH_WRProt_Pages76to79 ((uint32_t)0x00080000) /*!< STM32 Medium-density devices: Write protection of page 76 to 79 */ +#define FLASH_WRProt_Pages80to83 ((uint32_t)0x00100000) /*!< STM32 Medium-density devices: Write protection of page 80 to 83 */ +#define FLASH_WRProt_Pages84to87 ((uint32_t)0x00200000) /*!< STM32 Medium-density devices: Write protection of page 84 to 87 */ +#define FLASH_WRProt_Pages88to91 ((uint32_t)0x00400000) /*!< STM32 Medium-density devices: Write protection of page 88 to 91 */ +#define FLASH_WRProt_Pages92to95 ((uint32_t)0x00800000) /*!< STM32 Medium-density devices: Write protection of page 92 to 95 */ +#define FLASH_WRProt_Pages96to99 ((uint32_t)0x01000000) /*!< STM32 Medium-density devices: Write protection of page 96 to 99 */ +#define FLASH_WRProt_Pages100to103 ((uint32_t)0x02000000) /*!< STM32 Medium-density devices: Write protection of page 100 to 103 */ +#define FLASH_WRProt_Pages104to107 ((uint32_t)0x04000000) /*!< STM32 Medium-density devices: Write protection of page 104 to 107 */ +#define FLASH_WRProt_Pages108to111 ((uint32_t)0x08000000) /*!< STM32 Medium-density devices: Write protection of page 108 to 111 */ +#define FLASH_WRProt_Pages112to115 ((uint32_t)0x10000000) /*!< STM32 Medium-density devices: Write protection of page 112 to 115 */ +#define FLASH_WRProt_Pages116to119 ((uint32_t)0x20000000) /*!< STM32 Medium-density devices: Write protection of page 115 to 119 */ +#define FLASH_WRProt_Pages120to123 ((uint32_t)0x40000000) /*!< STM32 Medium-density devices: Write protection of page 120 to 123 */ +#define FLASH_WRProt_Pages124to127 ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 124 to 127 */ + +/* Values to be used with STM32 High-density and STM32F10X Connectivity line devices */ +#define FLASH_WRProt_Pages0to1 ((uint32_t)0x00000001) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 0 to 1 */ +#define FLASH_WRProt_Pages2to3 ((uint32_t)0x00000002) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 2 to 3 */ +#define FLASH_WRProt_Pages4to5 ((uint32_t)0x00000004) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 4 to 5 */ +#define FLASH_WRProt_Pages6to7 ((uint32_t)0x00000008) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 6 to 7 */ +#define FLASH_WRProt_Pages8to9 ((uint32_t)0x00000010) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 8 to 9 */ +#define FLASH_WRProt_Pages10to11 ((uint32_t)0x00000020) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 10 to 11 */ +#define FLASH_WRProt_Pages12to13 ((uint32_t)0x00000040) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 12 to 13 */ +#define FLASH_WRProt_Pages14to15 ((uint32_t)0x00000080) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 14 to 15 */ +#define FLASH_WRProt_Pages16to17 ((uint32_t)0x00000100) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 16 to 17 */ +#define FLASH_WRProt_Pages18to19 ((uint32_t)0x00000200) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 18 to 19 */ +#define FLASH_WRProt_Pages20to21 ((uint32_t)0x00000400) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 20 to 21 */ +#define FLASH_WRProt_Pages22to23 ((uint32_t)0x00000800) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 22 to 23 */ +#define FLASH_WRProt_Pages24to25 ((uint32_t)0x00001000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 24 to 25 */ +#define FLASH_WRProt_Pages26to27 ((uint32_t)0x00002000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 26 to 27 */ +#define FLASH_WRProt_Pages28to29 ((uint32_t)0x00004000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 28 to 29 */ +#define FLASH_WRProt_Pages30to31 ((uint32_t)0x00008000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 30 to 31 */ +#define FLASH_WRProt_Pages32to33 ((uint32_t)0x00010000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 32 to 33 */ +#define FLASH_WRProt_Pages34to35 ((uint32_t)0x00020000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 34 to 35 */ +#define FLASH_WRProt_Pages36to37 ((uint32_t)0x00040000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 36 to 37 */ +#define FLASH_WRProt_Pages38to39 ((uint32_t)0x00080000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 38 to 39 */ +#define FLASH_WRProt_Pages40to41 ((uint32_t)0x00100000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 40 to 41 */ +#define FLASH_WRProt_Pages42to43 ((uint32_t)0x00200000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 42 to 43 */ +#define FLASH_WRProt_Pages44to45 ((uint32_t)0x00400000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 44 to 45 */ +#define FLASH_WRProt_Pages46to47 ((uint32_t)0x00800000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 46 to 47 */ +#define FLASH_WRProt_Pages48to49 ((uint32_t)0x01000000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 48 to 49 */ +#define FLASH_WRProt_Pages50to51 ((uint32_t)0x02000000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 50 to 51 */ +#define FLASH_WRProt_Pages52to53 ((uint32_t)0x04000000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 52 to 53 */ +#define FLASH_WRProt_Pages54to55 ((uint32_t)0x08000000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 54 to 55 */ +#define FLASH_WRProt_Pages56to57 ((uint32_t)0x10000000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 56 to 57 */ +#define FLASH_WRProt_Pages58to59 ((uint32_t)0x20000000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 58 to 59 */ +#define FLASH_WRProt_Pages60to61 ((uint32_t)0x40000000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 60 to 61 */ +#define FLASH_WRProt_Pages62to127 ((uint32_t)0x80000000) /*!< STM32 Connectivity line devices: Write protection of page 62 to 127 */ +#define FLASH_WRProt_Pages62to255 ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 62 to 255 */ +#define FLASH_WRProt_Pages62to511 ((uint32_t)0x80000000) /*!< STM32 XL-density devices: Write protection of page 62 to 511 */ + +#define FLASH_WRProt_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Pages */ + +#define IS_FLASH_WRPROT_PAGE(PAGE) (((PAGE) != 0x00000000)) + +#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x080FFFFF)) + +#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806)) + +/** + * @} + */ + +/** @defgroup Option_Bytes_IWatchdog + * @{ + */ + +#define OB_IWDG_SW ((uint16_t)0x0001) /*!< Software IWDG selected */ +#define OB_IWDG_HW ((uint16_t)0x0000) /*!< Hardware IWDG selected */ +#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) + +/** + * @} + */ + +/** @defgroup Option_Bytes_nRST_STOP + * @{ + */ + +#define OB_STOP_NoRST ((uint16_t)0x0002) /*!< No reset generated when entering in STOP */ +#define OB_STOP_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STOP */ +#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST)) + +/** + * @} + */ + +/** @defgroup Option_Bytes_nRST_STDBY + * @{ + */ + +#define OB_STDBY_NoRST ((uint16_t)0x0004) /*!< No reset generated when entering in STANDBY */ +#define OB_STDBY_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STANDBY */ +#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST)) + +#ifdef STM32F10X_XL +/** + * @} + */ +/** @defgroup FLASH_Boot + * @{ + */ +#define FLASH_BOOT_Bank1 ((uint16_t)0x0000) /*!< At startup, if boot pins are set in boot from user Flash position + and this parameter is selected the device will boot from Bank1(Default) */ +#define FLASH_BOOT_Bank2 ((uint16_t)0x0001) /*!< At startup, if boot pins are set in boot from user Flash position + and this parameter is selected the device will boot from Bank 2 or Bank 1, + depending on the activation of the bank */ +#define IS_FLASH_BOOT(BOOT) (((BOOT) == FLASH_BOOT_Bank1) || ((BOOT) == FLASH_BOOT_Bank2)) +#endif +/** + * @} + */ +/** @defgroup FLASH_Interrupts + * @{ + */ +#ifdef STM32F10X_XL +#define FLASH_IT_BANK2_ERROR ((uint32_t)0x80000400) /*!< FPEC BANK2 error interrupt source */ +#define FLASH_IT_BANK2_EOP ((uint32_t)0x80001000) /*!< End of FLASH BANK2 Operation Interrupt source */ + +#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /*!< FPEC BANK1 error interrupt source */ +#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /*!< End of FLASH BANK1 Operation Interrupt source */ + +#define FLASH_IT_ERROR ((uint32_t)0x00000400) /*!< FPEC BANK1 error interrupt source */ +#define FLASH_IT_EOP ((uint32_t)0x00001000) /*!< End of FLASH BANK1 Operation Interrupt source */ +#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0x7FFFEBFF) == 0x00000000) && (((IT) != 0x00000000))) +#else +#define FLASH_IT_ERROR ((uint32_t)0x00000400) /*!< FPEC error interrupt source */ +#define FLASH_IT_EOP ((uint32_t)0x00001000) /*!< End of FLASH Operation Interrupt source */ +#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /*!< FPEC BANK1 error interrupt source */ +#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /*!< End of FLASH BANK1 Operation Interrupt source */ + +#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000))) +#endif + +/** + * @} + */ + +/** @defgroup FLASH_Flags + * @{ + */ +#ifdef STM32F10X_XL +#define FLASH_FLAG_BANK2_BSY ((uint32_t)0x80000001) /*!< FLASH BANK2 Busy flag */ +#define FLASH_FLAG_BANK2_EOP ((uint32_t)0x80000020) /*!< FLASH BANK2 End of Operation flag */ +#define FLASH_FLAG_BANK2_PGERR ((uint32_t)0x80000004) /*!< FLASH BANK2 Program error flag */ +#define FLASH_FLAG_BANK2_WRPRTERR ((uint32_t)0x80000010) /*!< FLASH BANK2 Write protected error flag */ + +#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /*!< FLASH BANK1 Busy flag*/ +#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /*!< FLASH BANK1 End of Operation flag */ +#define FLASH_FLAG_BANK1_PGERR FLASH_FLAG_PGERR /*!< FLASH BANK1 Program error flag */ +#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /*!< FLASH BANK1 Write protected error flag */ + +#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /*!< FLASH Busy flag */ +#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */ +#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /*!< FLASH Program error flag */ +#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */ +#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */ + +#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0x7FFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000)) +#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \ + ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \ + ((FLAG) == FLASH_FLAG_OPTERR)|| \ + ((FLAG) == FLASH_FLAG_BANK1_BSY) || ((FLAG) == FLASH_FLAG_BANK1_EOP) || \ + ((FLAG) == FLASH_FLAG_BANK1_PGERR) || ((FLAG) == FLASH_FLAG_BANK1_WRPRTERR) || \ + ((FLAG) == FLASH_FLAG_BANK2_BSY) || ((FLAG) == FLASH_FLAG_BANK2_EOP) || \ + ((FLAG) == FLASH_FLAG_BANK2_PGERR) || ((FLAG) == FLASH_FLAG_BANK2_WRPRTERR)) +#else +#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /*!< FLASH Busy flag */ +#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */ +#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /*!< FLASH Program error flag */ +#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */ +#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */ + +#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /*!< FLASH BANK1 Busy flag*/ +#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /*!< FLASH BANK1 End of Operation flag */ +#define FLASH_FLAG_BANK1_PGERR FLASH_FLAG_PGERR /*!< FLASH BANK1 Program error flag */ +#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /*!< FLASH BANK1 Write protected error flag */ + +#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000)) +#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \ + ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \ + ((FLAG) == FLASH_FLAG_BANK1_BSY) || ((FLAG) == FLASH_FLAG_BANK1_EOP) || \ + ((FLAG) == FLASH_FLAG_BANK1_PGERR) || ((FLAG) == FLASH_FLAG_BANK1_WRPRTERR) || \ + ((FLAG) == FLASH_FLAG_OPTERR)) +#endif + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Functions + * @{ + */ + +/*------------ Functions used for all STM32F10x devices -----*/ +void FLASH_SetLatency(uint32_t FLASH_Latency); +void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess); +void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer); +void FLASH_Unlock(void); +void FLASH_Lock(void); +FLASH_Status FLASH_ErasePage(uint32_t Page_Address); +FLASH_Status FLASH_EraseAllPages(void); +FLASH_Status FLASH_EraseOptionBytes(void); +FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data); +FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data); +FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data); +FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages); +FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState); +FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY); +uint32_t FLASH_GetUserOptionByte(void); +uint32_t FLASH_GetWriteProtectionOptionByte(void); +FlagStatus FLASH_GetReadOutProtectionStatus(void); +FlagStatus FLASH_GetPrefetchBufferStatus(void); +void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState); +FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG); +void FLASH_ClearFlag(uint32_t FLASH_FLAG); +FLASH_Status FLASH_GetStatus(void); +FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout); + +/*------------ New function used for all STM32F10x devices -----*/ +void FLASH_UnlockBank1(void); +void FLASH_LockBank1(void); +FLASH_Status FLASH_EraseAllBank1Pages(void); +FLASH_Status FLASH_GetBank1Status(void); +FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout); + +#ifdef STM32F10X_XL +/*---- New Functions used only with STM32F10x_XL density devices -----*/ +void FLASH_UnlockBank2(void); +void FLASH_LockBank2(void); +FLASH_Status FLASH_EraseAllBank2Pages(void); +FLASH_Status FLASH_GetBank2Status(void); +FLASH_Status FLASH_WaitForLastBank2Operation(uint32_t Timeout); +FLASH_Status FLASH_BootConfig(uint16_t FLASH_BOOT); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_FLASH_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32f10x/stm32f10x_fsmc.h b/example/libs_stm/inc/stm32f10x/stm32f10x_fsmc.h new file mode 100644 index 0000000..944f077 --- /dev/null +++ b/example/libs_stm/inc/stm32f10x/stm32f10x_fsmc.h @@ -0,0 +1,716 @@ +/** + ****************************************************************************** + * @file stm32f10x_fsmc.h + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file contains all the functions prototypes for the FSMC firmware + * library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_FSMC_H +#define __STM32F10x_FSMC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup FSMC + * @{ + */ + +/** @defgroup FSMC_Exported_Types + * @{ + */ + +/** + * @brief Timing parameters For NOR/SRAM Banks + */ + +typedef struct +{ + uint32_t FSMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure + the duration of the address setup time. + This parameter can be a value between 0 and 0xF. + @note: It is not used with synchronous NOR Flash memories. */ + + uint32_t FSMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure + the duration of the address hold time. + This parameter can be a value between 0 and 0xF. + @note: It is not used with synchronous NOR Flash memories.*/ + + uint32_t FSMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure + the duration of the data setup time. + This parameter can be a value between 0 and 0xFF. + @note: It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */ + + uint32_t FSMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure + the duration of the bus turnaround. + This parameter can be a value between 0 and 0xF. + @note: It is only used for multiplexed NOR Flash memories. */ + + uint32_t FSMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles. + This parameter can be a value between 1 and 0xF. + @note: This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */ + + uint32_t FSMC_DataLatency; /*!< Defines the number of memory clock cycles to issue + to the memory before getting the first data. + The value of this parameter depends on the memory type as shown below: + - It must be set to 0 in case of a CRAM + - It is don’t care in asynchronous NOR, SRAM or ROM accesses + - It may assume a value between 0 and 0xF in NOR Flash memories + with synchronous burst mode enable */ + + uint32_t FSMC_AccessMode; /*!< Specifies the asynchronous access mode. + This parameter can be a value of @ref FSMC_Access_Mode */ +}FSMC_NORSRAMTimingInitTypeDef; + +/** + * @brief FSMC NOR/SRAM Init structure definition + */ + +typedef struct +{ + uint32_t FSMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used. + This parameter can be a value of @ref FSMC_NORSRAM_Bank */ + + uint32_t FSMC_DataAddressMux; /*!< Specifies whether the address and data values are + multiplexed on the databus or not. + This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */ + + uint32_t FSMC_MemoryType; /*!< Specifies the type of external memory attached to + the corresponding memory bank. + This parameter can be a value of @ref FSMC_Memory_Type */ + + uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width. + This parameter can be a value of @ref FSMC_Data_Width */ + + uint32_t FSMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, + valid only with synchronous burst Flash memories. + This parameter can be a value of @ref FSMC_Burst_Access_Mode */ + + uint32_t FSMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing + the Flash memory in burst mode. + This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */ + + uint32_t FSMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash + memory, valid only when accessing Flash memories in burst mode. + This parameter can be a value of @ref FSMC_Wrap_Mode */ + + uint32_t FSMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one + clock cycle before the wait state or during the wait state, + valid only when accessing memories in burst mode. + This parameter can be a value of @ref FSMC_Wait_Timing */ + + uint32_t FSMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FSMC. + This parameter can be a value of @ref FSMC_Write_Operation */ + + uint32_t FSMC_WaitSignal; /*!< Enables or disables the wait-state insertion via wait + signal, valid for Flash memory access in burst mode. + This parameter can be a value of @ref FSMC_Wait_Signal */ + + uint32_t FSMC_ExtendedMode; /*!< Enables or disables the extended mode. + This parameter can be a value of @ref FSMC_Extended_Mode */ + + uint32_t FSMC_WriteBurst; /*!< Enables or disables the write burst operation. + This parameter can be a value of @ref FSMC_Write_Burst */ + + FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the ExtendedMode is not used*/ + + FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /*!< Timing Parameters for write access if the ExtendedMode is used*/ +}FSMC_NORSRAMInitTypeDef; + +/** + * @brief Timing parameters For FSMC NAND and PCCARD Banks + */ + +typedef struct +{ + uint32_t FSMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before + the command assertion for NAND-Flash read or write access + to common/Attribute or I/O memory space (depending on + the memory space timing to be configured). + This parameter can be a value between 0 and 0xFF.*/ + + uint32_t FSMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the + command for NAND-Flash read or write access to + common/Attribute or I/O memory space (depending on the + memory space timing to be configured). + This parameter can be a number between 0x00 and 0xFF */ + + uint32_t FSMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address + (and data for write access) after the command deassertion + for NAND-Flash read or write access to common/Attribute + or I/O memory space (depending on the memory space timing + to be configured). + This parameter can be a number between 0x00 and 0xFF */ + + uint32_t FSMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the + databus is kept in HiZ after the start of a NAND-Flash + write access to common/Attribute or I/O memory space (depending + on the memory space timing to be configured). + This parameter can be a number between 0x00 and 0xFF */ +}FSMC_NAND_PCCARDTimingInitTypeDef; + +/** + * @brief FSMC NAND Init structure definition + */ + +typedef struct +{ + uint32_t FSMC_Bank; /*!< Specifies the NAND memory bank that will be used. + This parameter can be a value of @ref FSMC_NAND_Bank */ + + uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory Bank. + This parameter can be any value of @ref FSMC_Wait_feature */ + + uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width. + This parameter can be any value of @ref FSMC_Data_Width */ + + uint32_t FSMC_ECC; /*!< Enables or disables the ECC computation. + This parameter can be any value of @ref FSMC_ECC */ + + uint32_t FSMC_ECCPageSize; /*!< Defines the page size for the extended ECC. + This parameter can be any value of @ref FSMC_ECC_Page_Size */ + + uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the + delay between CLE low and RE low. + This parameter can be a value between 0 and 0xFF. */ + + uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the + delay between ALE low and RE low. + This parameter can be a number between 0x0 and 0xFF */ + + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */ + + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */ +}FSMC_NANDInitTypeDef; + +/** + * @brief FSMC PCCARD Init structure definition + */ + +typedef struct +{ + uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the Memory Bank. + This parameter can be any value of @ref FSMC_Wait_feature */ + + uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the + delay between CLE low and RE low. + This parameter can be a value between 0 and 0xFF. */ + + uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the + delay between ALE low and RE low. + This parameter can be a number between 0x0 and 0xFF */ + + + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */ + + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */ + + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct; /*!< FSMC IO Space Timing */ +}FSMC_PCCARDInitTypeDef; + +/** + * @} + */ + +/** @defgroup FSMC_Exported_Constants + * @{ + */ + +/** @defgroup FSMC_NORSRAM_Bank + * @{ + */ +#define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000) +#define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002) +#define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004) +#define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006) +/** + * @} + */ + +/** @defgroup FSMC_NAND_Bank + * @{ + */ +#define FSMC_Bank2_NAND ((uint32_t)0x00000010) +#define FSMC_Bank3_NAND ((uint32_t)0x00000100) +/** + * @} + */ + +/** @defgroup FSMC_PCCARD_Bank + * @{ + */ +#define FSMC_Bank4_PCCARD ((uint32_t)0x00001000) +/** + * @} + */ + +#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \ + ((BANK) == FSMC_Bank1_NORSRAM2) || \ + ((BANK) == FSMC_Bank1_NORSRAM3) || \ + ((BANK) == FSMC_Bank1_NORSRAM4)) + +#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ + ((BANK) == FSMC_Bank3_NAND)) + +#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ + ((BANK) == FSMC_Bank3_NAND) || \ + ((BANK) == FSMC_Bank4_PCCARD)) + +#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ + ((BANK) == FSMC_Bank3_NAND) || \ + ((BANK) == FSMC_Bank4_PCCARD)) + +/** @defgroup NOR_SRAM_Controller + * @{ + */ + +/** @defgroup FSMC_Data_Address_Bus_Multiplexing + * @{ + */ + +#define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000) +#define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002) +#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \ + ((MUX) == FSMC_DataAddressMux_Enable)) + +/** + * @} + */ + +/** @defgroup FSMC_Memory_Type + * @{ + */ + +#define FSMC_MemoryType_SRAM ((uint32_t)0x00000000) +#define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004) +#define FSMC_MemoryType_NOR ((uint32_t)0x00000008) +#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \ + ((MEMORY) == FSMC_MemoryType_PSRAM)|| \ + ((MEMORY) == FSMC_MemoryType_NOR)) + +/** + * @} + */ + +/** @defgroup FSMC_Data_Width + * @{ + */ + +#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000) +#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010) +#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \ + ((WIDTH) == FSMC_MemoryDataWidth_16b)) + +/** + * @} + */ + +/** @defgroup FSMC_Burst_Access_Mode + * @{ + */ + +#define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000) +#define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100) +#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \ + ((STATE) == FSMC_BurstAccessMode_Enable)) +/** + * @} + */ + +/** @defgroup FSMC_Wait_Signal_Polarity + * @{ + */ + +#define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000) +#define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200) +#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \ + ((POLARITY) == FSMC_WaitSignalPolarity_High)) + +/** + * @} + */ + +/** @defgroup FSMC_Wrap_Mode + * @{ + */ + +#define FSMC_WrapMode_Disable ((uint32_t)0x00000000) +#define FSMC_WrapMode_Enable ((uint32_t)0x00000400) +#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \ + ((MODE) == FSMC_WrapMode_Enable)) + +/** + * @} + */ + +/** @defgroup FSMC_Wait_Timing + * @{ + */ + +#define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000) +#define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800) +#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \ + ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState)) + +/** + * @} + */ + +/** @defgroup FSMC_Write_Operation + * @{ + */ + +#define FSMC_WriteOperation_Disable ((uint32_t)0x00000000) +#define FSMC_WriteOperation_Enable ((uint32_t)0x00001000) +#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \ + ((OPERATION) == FSMC_WriteOperation_Enable)) + +/** + * @} + */ + +/** @defgroup FSMC_Wait_Signal + * @{ + */ + +#define FSMC_WaitSignal_Disable ((uint32_t)0x00000000) +#define FSMC_WaitSignal_Enable ((uint32_t)0x00002000) +#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \ + ((SIGNAL) == FSMC_WaitSignal_Enable)) +/** + * @} + */ + +/** @defgroup FSMC_Extended_Mode + * @{ + */ + +#define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000) +#define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000) + +#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \ + ((MODE) == FSMC_ExtendedMode_Enable)) + +/** + * @} + */ + +/** @defgroup FSMC_Write_Burst + * @{ + */ + +#define FSMC_WriteBurst_Disable ((uint32_t)0x00000000) +#define FSMC_WriteBurst_Enable ((uint32_t)0x00080000) +#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \ + ((BURST) == FSMC_WriteBurst_Enable)) +/** + * @} + */ + +/** @defgroup FSMC_Address_Setup_Time + * @{ + */ + +#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF) + +/** + * @} + */ + +/** @defgroup FSMC_Address_Hold_Time + * @{ + */ + +#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF) + +/** + * @} + */ + +/** @defgroup FSMC_Data_Setup_Time + * @{ + */ + +#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF)) + +/** + * @} + */ + +/** @defgroup FSMC_Bus_Turn_around_Duration + * @{ + */ + +#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF) + +/** + * @} + */ + +/** @defgroup FSMC_CLK_Division + * @{ + */ + +#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF) + +/** + * @} + */ + +/** @defgroup FSMC_Data_Latency + * @{ + */ + +#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF) + +/** + * @} + */ + +/** @defgroup FSMC_Access_Mode + * @{ + */ + +#define FSMC_AccessMode_A ((uint32_t)0x00000000) +#define FSMC_AccessMode_B ((uint32_t)0x10000000) +#define FSMC_AccessMode_C ((uint32_t)0x20000000) +#define FSMC_AccessMode_D ((uint32_t)0x30000000) +#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \ + ((MODE) == FSMC_AccessMode_B) || \ + ((MODE) == FSMC_AccessMode_C) || \ + ((MODE) == FSMC_AccessMode_D)) + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup NAND_PCCARD_Controller + * @{ + */ + +/** @defgroup FSMC_Wait_feature + * @{ + */ + +#define FSMC_Waitfeature_Disable ((uint32_t)0x00000000) +#define FSMC_Waitfeature_Enable ((uint32_t)0x00000002) +#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \ + ((FEATURE) == FSMC_Waitfeature_Enable)) + +/** + * @} + */ + + +/** @defgroup FSMC_ECC + * @{ + */ + +#define FSMC_ECC_Disable ((uint32_t)0x00000000) +#define FSMC_ECC_Enable ((uint32_t)0x00000040) +#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \ + ((STATE) == FSMC_ECC_Enable)) + +/** + * @} + */ + +/** @defgroup FSMC_ECC_Page_Size + * @{ + */ + +#define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000) +#define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000) +#define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000) +#define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000) +#define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000) +#define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000) +#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \ + ((SIZE) == FSMC_ECCPageSize_512Bytes) || \ + ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \ + ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \ + ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \ + ((SIZE) == FSMC_ECCPageSize_8192Bytes)) + +/** + * @} + */ + +/** @defgroup FSMC_TCLR_Setup_Time + * @{ + */ + +#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF) + +/** + * @} + */ + +/** @defgroup FSMC_TAR_Setup_Time + * @{ + */ + +#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF) + +/** + * @} + */ + +/** @defgroup FSMC_Setup_Time + * @{ + */ + +#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF) + +/** + * @} + */ + +/** @defgroup FSMC_Wait_Setup_Time + * @{ + */ + +#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF) + +/** + * @} + */ + +/** @defgroup FSMC_Hold_Setup_Time + * @{ + */ + +#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF) + +/** + * @} + */ + +/** @defgroup FSMC_HiZ_Setup_Time + * @{ + */ + +#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF) + +/** + * @} + */ + +/** @defgroup FSMC_Interrupt_sources + * @{ + */ + +#define FSMC_IT_RisingEdge ((uint32_t)0x00000008) +#define FSMC_IT_Level ((uint32_t)0x00000010) +#define FSMC_IT_FallingEdge ((uint32_t)0x00000020) +#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000)) +#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \ + ((IT) == FSMC_IT_Level) || \ + ((IT) == FSMC_IT_FallingEdge)) +/** + * @} + */ + +/** @defgroup FSMC_Flags + * @{ + */ + +#define FSMC_FLAG_RisingEdge ((uint32_t)0x00000001) +#define FSMC_FLAG_Level ((uint32_t)0x00000002) +#define FSMC_FLAG_FallingEdge ((uint32_t)0x00000004) +#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040) +#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \ + ((FLAG) == FSMC_FLAG_Level) || \ + ((FLAG) == FSMC_FLAG_FallingEdge) || \ + ((FLAG) == FSMC_FLAG_FEMPT)) + +#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000)) + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup FSMC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup FSMC_Exported_Functions + * @{ + */ + +void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank); +void FSMC_NANDDeInit(uint32_t FSMC_Bank); +void FSMC_PCCARDDeInit(void); +void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); +void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); +void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct); +void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); +void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); +void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct); +void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState); +void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState); +void FSMC_PCCARDCmd(FunctionalState NewState); +void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState); +uint32_t FSMC_GetECC(uint32_t FSMC_Bank); +void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState); +FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG); +void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG); +ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT); +void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F10x_FSMC_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32f10x/stm32f10x_gpio.h b/example/libs_stm/inc/stm32f10x/stm32f10x_gpio.h new file mode 100644 index 0000000..aff7a5c --- /dev/null +++ b/example/libs_stm/inc/stm32f10x/stm32f10x_gpio.h @@ -0,0 +1,379 @@ +/** + ****************************************************************************** + * @file stm32f10x_gpio.h + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file contains all the functions prototypes for the GPIO + * firmware library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_GPIO_H +#define __STM32F10x_GPIO_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup GPIO + * @{ + */ + +/** @defgroup GPIO_Exported_Types + * @{ + */ + +#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \ + ((PERIPH) == GPIOB) || \ + ((PERIPH) == GPIOC) || \ + ((PERIPH) == GPIOD) || \ + ((PERIPH) == GPIOE) || \ + ((PERIPH) == GPIOF) || \ + ((PERIPH) == GPIOG)) + +/** + * @brief Output Maximum frequency selection + */ + +typedef enum +{ + GPIO_Speed_10MHz = 1, + GPIO_Speed_2MHz, + GPIO_Speed_50MHz +}GPIOSpeed_TypeDef; +#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_10MHz) || ((SPEED) == GPIO_Speed_2MHz) || \ + ((SPEED) == GPIO_Speed_50MHz)) + +/** + * @brief Configuration Mode enumeration + */ + +typedef enum +{ GPIO_Mode_AIN = 0x0, + GPIO_Mode_IN_FLOATING = 0x04, + GPIO_Mode_IPD = 0x28, + GPIO_Mode_IPU = 0x48, + GPIO_Mode_Out_OD = 0x14, + GPIO_Mode_Out_PP = 0x10, + GPIO_Mode_AF_OD = 0x1C, + GPIO_Mode_AF_PP = 0x18 +}GPIOMode_TypeDef; + +#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_AIN) || ((MODE) == GPIO_Mode_IN_FLOATING) || \ + ((MODE) == GPIO_Mode_IPD) || ((MODE) == GPIO_Mode_IPU) || \ + ((MODE) == GPIO_Mode_Out_OD) || ((MODE) == GPIO_Mode_Out_PP) || \ + ((MODE) == GPIO_Mode_AF_OD) || ((MODE) == GPIO_Mode_AF_PP)) + +/** + * @brief GPIO Init structure definition + */ + +typedef struct +{ + uint16_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_pins_define */ + + GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIOSpeed_TypeDef */ + + GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIOMode_TypeDef */ +}GPIO_InitTypeDef; + + +/** + * @brief Bit_SET and Bit_RESET enumeration + */ + +typedef enum +{ Bit_RESET = 0, + Bit_SET +}BitAction; + +#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET)) + +/** + * @} + */ + +/** @defgroup GPIO_Exported_Constants + * @{ + */ + +/** @defgroup GPIO_pins_define + * @{ + */ + +#define GPIO_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */ +#define GPIO_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */ +#define GPIO_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */ +#define GPIO_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */ +#define GPIO_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */ +#define GPIO_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */ +#define GPIO_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */ +#define GPIO_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */ +#define GPIO_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */ +#define GPIO_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */ +#define GPIO_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */ +#define GPIO_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */ +#define GPIO_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */ +#define GPIO_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */ +#define GPIO_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */ +#define GPIO_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */ +#define GPIO_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */ + +#define IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00)) + +#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \ + ((PIN) == GPIO_Pin_1) || \ + ((PIN) == GPIO_Pin_2) || \ + ((PIN) == GPIO_Pin_3) || \ + ((PIN) == GPIO_Pin_4) || \ + ((PIN) == GPIO_Pin_5) || \ + ((PIN) == GPIO_Pin_6) || \ + ((PIN) == GPIO_Pin_7) || \ + ((PIN) == GPIO_Pin_8) || \ + ((PIN) == GPIO_Pin_9) || \ + ((PIN) == GPIO_Pin_10) || \ + ((PIN) == GPIO_Pin_11) || \ + ((PIN) == GPIO_Pin_12) || \ + ((PIN) == GPIO_Pin_13) || \ + ((PIN) == GPIO_Pin_14) || \ + ((PIN) == GPIO_Pin_15)) + +/** + * @} + */ + +/** @defgroup GPIO_Remap_define + * @{ + */ + +#define GPIO_Remap_SPI1 ((uint32_t)0x00000001) /*!< SPI1 Alternate Function mapping */ +#define GPIO_Remap_I2C1 ((uint32_t)0x00000002) /*!< I2C1 Alternate Function mapping */ +#define GPIO_Remap_USART1 ((uint32_t)0x00000004) /*!< USART1 Alternate Function mapping */ +#define GPIO_Remap_USART2 ((uint32_t)0x00000008) /*!< USART2 Alternate Function mapping */ +#define GPIO_PartialRemap_USART3 ((uint32_t)0x00140010) /*!< USART3 Partial Alternate Function mapping */ +#define GPIO_FullRemap_USART3 ((uint32_t)0x00140030) /*!< USART3 Full Alternate Function mapping */ +#define GPIO_PartialRemap_TIM1 ((uint32_t)0x00160040) /*!< TIM1 Partial Alternate Function mapping */ +#define GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0) /*!< TIM1 Full Alternate Function mapping */ +#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /*!< TIM2 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200) /*!< TIM2 Partial2 Alternate Function mapping */ +#define GPIO_FullRemap_TIM2 ((uint32_t)0x00180300) /*!< TIM2 Full Alternate Function mapping */ +#define GPIO_PartialRemap_TIM3 ((uint32_t)0x001A0800) /*!< TIM3 Partial Alternate Function mapping */ +#define GPIO_FullRemap_TIM3 ((uint32_t)0x001A0C00) /*!< TIM3 Full Alternate Function mapping */ +#define GPIO_Remap_TIM4 ((uint32_t)0x00001000) /*!< TIM4 Alternate Function mapping */ +#define GPIO_Remap1_CAN1 ((uint32_t)0x001D4000) /*!< CAN1 Alternate Function mapping */ +#define GPIO_Remap2_CAN1 ((uint32_t)0x001D6000) /*!< CAN1 Alternate Function mapping */ +#define GPIO_Remap_PD01 ((uint32_t)0x00008000) /*!< PD01 Alternate Function mapping */ +#define GPIO_Remap_TIM5CH4_LSI ((uint32_t)0x00200001) /*!< LSI connected to TIM5 Channel4 input capture for calibration */ +#define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /*!< ADC1 External Trigger Injected Conversion remapping */ +#define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /*!< ADC1 External Trigger Regular Conversion remapping */ +#define GPIO_Remap_ADC2_ETRGINJ ((uint32_t)0x00200008) /*!< ADC2 External Trigger Injected Conversion remapping */ +#define GPIO_Remap_ADC2_ETRGREG ((uint32_t)0x00200010) /*!< ADC2 External Trigger Regular Conversion remapping */ +#define GPIO_Remap_ETH ((uint32_t)0x00200020) /*!< Ethernet remapping (only for Connectivity line devices) */ +#define GPIO_Remap_CAN2 ((uint32_t)0x00200040) /*!< CAN2 remapping (only for Connectivity line devices) */ +#define GPIO_Remap_SWJ_NoJTRST ((uint32_t)0x00300100) /*!< Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */ +#define GPIO_Remap_SWJ_JTAGDisable ((uint32_t)0x00300200) /*!< JTAG-DP Disabled and SW-DP Enabled */ +#define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /*!< Full SWJ Disabled (JTAG-DP + SW-DP) */ +#define GPIO_Remap_SPI3 ((uint32_t)0x00201000) /*!< SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices) */ +#define GPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000) /*!< Ethernet PTP output or USB OTG SOF (Start of Frame) connected + to TIM2 Internal Trigger 1 for calibration + (only for Connectivity line devices) */ +#define GPIO_Remap_PTP_PPS ((uint32_t)0x00204000) /*!< Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices) */ + +#define GPIO_Remap_TIM15 ((uint32_t)0x80000001) /*!< TIM15 Alternate Function mapping (only for Value line devices) */ +#define GPIO_Remap_TIM16 ((uint32_t)0x80000002) /*!< TIM16 Alternate Function mapping (only for Value line devices) */ +#define GPIO_Remap_TIM17 ((uint32_t)0x80000004) /*!< TIM17 Alternate Function mapping (only for Value line devices) */ +#define GPIO_Remap_CEC ((uint32_t)0x80000008) /*!< CEC Alternate Function mapping (only for Value line devices) */ +#define GPIO_Remap_TIM1_DMA ((uint32_t)0x80000010) /*!< TIM1 DMA requests mapping (only for Value line devices) */ + +#define GPIO_Remap_TIM9 ((uint32_t)0x80000020) /*!< TIM9 Alternate Function mapping (only for XL-density devices) */ +#define GPIO_Remap_TIM10 ((uint32_t)0x80000040) /*!< TIM10 Alternate Function mapping (only for XL-density devices) */ +#define GPIO_Remap_TIM11 ((uint32_t)0x80000080) /*!< TIM11 Alternate Function mapping (only for XL-density devices) */ +#define GPIO_Remap_TIM13 ((uint32_t)0x80000100) /*!< TIM13 Alternate Function mapping (only for XL-density devices) */ +#define GPIO_Remap_TIM14 ((uint32_t)0x80000200) /*!< TIM14 Alternate Function mapping (only for XL-density devices) */ +#define GPIO_Remap_FSMC_NADV ((uint32_t)0x80000400) /*!< FSMC_NADV Alternate Function mapping (only for XL-density devices) */ + + +#define IS_GPIO_REMAP(REMAP) (((REMAP) == GPIO_Remap_SPI1) || ((REMAP) == GPIO_Remap_I2C1) || \ + ((REMAP) == GPIO_Remap_USART1) || ((REMAP) == GPIO_Remap_USART2) || \ + ((REMAP) == GPIO_PartialRemap_USART3) || ((REMAP) == GPIO_FullRemap_USART3) || \ + ((REMAP) == GPIO_PartialRemap_TIM1) || ((REMAP) == GPIO_FullRemap_TIM1) || \ + ((REMAP) == GPIO_PartialRemap1_TIM2) || ((REMAP) == GPIO_PartialRemap2_TIM2) || \ + ((REMAP) == GPIO_FullRemap_TIM2) || ((REMAP) == GPIO_PartialRemap_TIM3) || \ + ((REMAP) == GPIO_FullRemap_TIM3) || ((REMAP) == GPIO_Remap_TIM4) || \ + ((REMAP) == GPIO_Remap1_CAN1) || ((REMAP) == GPIO_Remap2_CAN1) || \ + ((REMAP) == GPIO_Remap_PD01) || ((REMAP) == GPIO_Remap_TIM5CH4_LSI) || \ + ((REMAP) == GPIO_Remap_ADC1_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC1_ETRGREG) || \ + ((REMAP) == GPIO_Remap_ADC2_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC2_ETRGREG) || \ + ((REMAP) == GPIO_Remap_ETH) ||((REMAP) == GPIO_Remap_CAN2) || \ + ((REMAP) == GPIO_Remap_SWJ_NoJTRST) || ((REMAP) == GPIO_Remap_SWJ_JTAGDisable) || \ + ((REMAP) == GPIO_Remap_SWJ_Disable)|| ((REMAP) == GPIO_Remap_SPI3) || \ + ((REMAP) == GPIO_Remap_TIM2ITR1_PTP_SOF) || ((REMAP) == GPIO_Remap_PTP_PPS) || \ + ((REMAP) == GPIO_Remap_TIM15) || ((REMAP) == GPIO_Remap_TIM16) || \ + ((REMAP) == GPIO_Remap_TIM17) || ((REMAP) == GPIO_Remap_CEC) || \ + ((REMAP) == GPIO_Remap_TIM1_DMA) || ((REMAP) == GPIO_Remap_TIM9) || \ + ((REMAP) == GPIO_Remap_TIM10) || ((REMAP) == GPIO_Remap_TIM11) || \ + ((REMAP) == GPIO_Remap_TIM13) || ((REMAP) == GPIO_Remap_TIM14) || \ + ((REMAP) == GPIO_Remap_FSMC_NADV)) + +/** + * @} + */ + +/** @defgroup GPIO_Port_Sources + * @{ + */ + +#define GPIO_PortSourceGPIOA ((uint8_t)0x00) +#define GPIO_PortSourceGPIOB ((uint8_t)0x01) +#define GPIO_PortSourceGPIOC ((uint8_t)0x02) +#define GPIO_PortSourceGPIOD ((uint8_t)0x03) +#define GPIO_PortSourceGPIOE ((uint8_t)0x04) +#define GPIO_PortSourceGPIOF ((uint8_t)0x05) +#define GPIO_PortSourceGPIOG ((uint8_t)0x06) +#define IS_GPIO_EVENTOUT_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOE)) + +#define IS_GPIO_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOE) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOF) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOG)) + +/** + * @} + */ + +/** @defgroup GPIO_Pin_sources + * @{ + */ + +#define GPIO_PinSource0 ((uint8_t)0x00) +#define GPIO_PinSource1 ((uint8_t)0x01) +#define GPIO_PinSource2 ((uint8_t)0x02) +#define GPIO_PinSource3 ((uint8_t)0x03) +#define GPIO_PinSource4 ((uint8_t)0x04) +#define GPIO_PinSource5 ((uint8_t)0x05) +#define GPIO_PinSource6 ((uint8_t)0x06) +#define GPIO_PinSource7 ((uint8_t)0x07) +#define GPIO_PinSource8 ((uint8_t)0x08) +#define GPIO_PinSource9 ((uint8_t)0x09) +#define GPIO_PinSource10 ((uint8_t)0x0A) +#define GPIO_PinSource11 ((uint8_t)0x0B) +#define GPIO_PinSource12 ((uint8_t)0x0C) +#define GPIO_PinSource13 ((uint8_t)0x0D) +#define GPIO_PinSource14 ((uint8_t)0x0E) +#define GPIO_PinSource15 ((uint8_t)0x0F) + +#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \ + ((PINSOURCE) == GPIO_PinSource1) || \ + ((PINSOURCE) == GPIO_PinSource2) || \ + ((PINSOURCE) == GPIO_PinSource3) || \ + ((PINSOURCE) == GPIO_PinSource4) || \ + ((PINSOURCE) == GPIO_PinSource5) || \ + ((PINSOURCE) == GPIO_PinSource6) || \ + ((PINSOURCE) == GPIO_PinSource7) || \ + ((PINSOURCE) == GPIO_PinSource8) || \ + ((PINSOURCE) == GPIO_PinSource9) || \ + ((PINSOURCE) == GPIO_PinSource10) || \ + ((PINSOURCE) == GPIO_PinSource11) || \ + ((PINSOURCE) == GPIO_PinSource12) || \ + ((PINSOURCE) == GPIO_PinSource13) || \ + ((PINSOURCE) == GPIO_PinSource14) || \ + ((PINSOURCE) == GPIO_PinSource15)) + +/** + * @} + */ + +/** @defgroup Ethernet_Media_Interface + * @{ + */ +#define GPIO_ETH_MediaInterface_MII ((u32)0x00000000) +#define GPIO_ETH_MediaInterface_RMII ((u32)0x00000001) + +#define IS_GPIO_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == GPIO_ETH_MediaInterface_MII) || \ + ((INTERFACE) == GPIO_ETH_MediaInterface_RMII)) + +/** + * @} + */ +/** + * @} + */ + +/** @defgroup GPIO_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup GPIO_Exported_Functions + * @{ + */ + +void GPIO_DeInit(GPIO_TypeDef* GPIOx); +void GPIO_AFIODeInit(void); +void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct); +void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct); +uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx); +uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx); +void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal); +void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal); +void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); +void GPIO_EventOutputCmd(FunctionalState NewState); +void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState); +void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); +void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_GPIO_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32f10x/stm32f10x_i2c.h b/example/libs_stm/inc/stm32f10x/stm32f10x_i2c.h new file mode 100644 index 0000000..d9c9346 --- /dev/null +++ b/example/libs_stm/inc/stm32f10x/stm32f10x_i2c.h @@ -0,0 +1,670 @@ +/** + ****************************************************************************** + * @file stm32f10x_i2c.h + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file contains all the functions prototypes for the I2C firmware + * library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_I2C_H +#define __STM32F10x_I2C_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup I2C + * @{ + */ + +/** @defgroup I2C_Exported_Types + * @{ + */ + +/** + * @brief I2C Init structure definition + */ + +typedef struct +{ + uint32_t I2C_ClockSpeed; /*!< Specifies the clock frequency. + This parameter must be set to a value lower than 400kHz */ + + uint16_t I2C_Mode; /*!< Specifies the I2C mode. + This parameter can be a value of @ref I2C_mode */ + + uint16_t I2C_DutyCycle; /*!< Specifies the I2C fast mode duty cycle. + This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ + + uint16_t I2C_OwnAddress1; /*!< Specifies the first device own address. + This parameter can be a 7-bit or 10-bit address. */ + + uint16_t I2C_Ack; /*!< Enables or disables the acknowledgement. + This parameter can be a value of @ref I2C_acknowledgement */ + + uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged. + This parameter can be a value of @ref I2C_acknowledged_address */ +}I2C_InitTypeDef; + +/** + * @} + */ + + +/** @defgroup I2C_Exported_Constants + * @{ + */ + +#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \ + ((PERIPH) == I2C2)) +/** @defgroup I2C_mode + * @{ + */ + +#define I2C_Mode_I2C ((uint16_t)0x0000) +#define I2C_Mode_SMBusDevice ((uint16_t)0x0002) +#define I2C_Mode_SMBusHost ((uint16_t)0x000A) +#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \ + ((MODE) == I2C_Mode_SMBusDevice) || \ + ((MODE) == I2C_Mode_SMBusHost)) +/** + * @} + */ + +/** @defgroup I2C_duty_cycle_in_fast_mode + * @{ + */ + +#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */ +#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */ +#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \ + ((CYCLE) == I2C_DutyCycle_2)) +/** + * @} + */ + +/** @defgroup I2C_acknowledgement + * @{ + */ + +#define I2C_Ack_Enable ((uint16_t)0x0400) +#define I2C_Ack_Disable ((uint16_t)0x0000) +#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \ + ((STATE) == I2C_Ack_Disable)) +/** + * @} + */ + +/** @defgroup I2C_transfer_direction + * @{ + */ + +#define I2C_Direction_Transmitter ((uint8_t)0x00) +#define I2C_Direction_Receiver ((uint8_t)0x01) +#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \ + ((DIRECTION) == I2C_Direction_Receiver)) +/** + * @} + */ + +/** @defgroup I2C_acknowledged_address + * @{ + */ + +#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000) +#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000) +#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \ + ((ADDRESS) == I2C_AcknowledgedAddress_10bit)) +/** + * @} + */ + +/** @defgroup I2C_registers + * @{ + */ + +#define I2C_Register_CR1 ((uint8_t)0x00) +#define I2C_Register_CR2 ((uint8_t)0x04) +#define I2C_Register_OAR1 ((uint8_t)0x08) +#define I2C_Register_OAR2 ((uint8_t)0x0C) +#define I2C_Register_DR ((uint8_t)0x10) +#define I2C_Register_SR1 ((uint8_t)0x14) +#define I2C_Register_SR2 ((uint8_t)0x18) +#define I2C_Register_CCR ((uint8_t)0x1C) +#define I2C_Register_TRISE ((uint8_t)0x20) +#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \ + ((REGISTER) == I2C_Register_CR2) || \ + ((REGISTER) == I2C_Register_OAR1) || \ + ((REGISTER) == I2C_Register_OAR2) || \ + ((REGISTER) == I2C_Register_DR) || \ + ((REGISTER) == I2C_Register_SR1) || \ + ((REGISTER) == I2C_Register_SR2) || \ + ((REGISTER) == I2C_Register_CCR) || \ + ((REGISTER) == I2C_Register_TRISE)) +/** + * @} + */ + +/** @defgroup I2C_SMBus_alert_pin_level + * @{ + */ + +#define I2C_SMBusAlert_Low ((uint16_t)0x2000) +#define I2C_SMBusAlert_High ((uint16_t)0xDFFF) +#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \ + ((ALERT) == I2C_SMBusAlert_High)) +/** + * @} + */ + +/** @defgroup I2C_PEC_position + * @{ + */ + +#define I2C_PECPosition_Next ((uint16_t)0x0800) +#define I2C_PECPosition_Current ((uint16_t)0xF7FF) +#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \ + ((POSITION) == I2C_PECPosition_Current)) +/** + * @} + */ + +/** @defgroup I2C_interrupts_definition + * @{ + */ + +#define I2C_IT_BUF ((uint16_t)0x0400) +#define I2C_IT_EVT ((uint16_t)0x0200) +#define I2C_IT_ERR ((uint16_t)0x0100) +#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00)) +/** + * @} + */ + +/** @defgroup I2C_interrupts_definition + * @{ + */ + +#define I2C_IT_SMBALERT ((uint32_t)0x01008000) +#define I2C_IT_TIMEOUT ((uint32_t)0x01004000) +#define I2C_IT_PECERR ((uint32_t)0x01001000) +#define I2C_IT_OVR ((uint32_t)0x01000800) +#define I2C_IT_AF ((uint32_t)0x01000400) +#define I2C_IT_ARLO ((uint32_t)0x01000200) +#define I2C_IT_BERR ((uint32_t)0x01000100) +#define I2C_IT_TXE ((uint32_t)0x06000080) +#define I2C_IT_RXNE ((uint32_t)0x06000040) +#define I2C_IT_STOPF ((uint32_t)0x02000010) +#define I2C_IT_ADD10 ((uint32_t)0x02000008) +#define I2C_IT_BTF ((uint32_t)0x02000004) +#define I2C_IT_ADDR ((uint32_t)0x02000002) +#define I2C_IT_SB ((uint32_t)0x02000001) + +#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00)) + +#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \ + ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \ + ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \ + ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \ + ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \ + ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \ + ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB)) +/** + * @} + */ + +/** @defgroup I2C_flags_definition + * @{ + */ + +/** + * @brief SR2 register flags + */ + +#define I2C_FLAG_DUALF ((uint32_t)0x00800000) +#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000) +#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000) +#define I2C_FLAG_GENCALL ((uint32_t)0x00100000) +#define I2C_FLAG_TRA ((uint32_t)0x00040000) +#define I2C_FLAG_BUSY ((uint32_t)0x00020000) +#define I2C_FLAG_MSL ((uint32_t)0x00010000) + +/** + * @brief SR1 register flags + */ + +#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000) +#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000) +#define I2C_FLAG_PECERR ((uint32_t)0x10001000) +#define I2C_FLAG_OVR ((uint32_t)0x10000800) +#define I2C_FLAG_AF ((uint32_t)0x10000400) +#define I2C_FLAG_ARLO ((uint32_t)0x10000200) +#define I2C_FLAG_BERR ((uint32_t)0x10000100) +#define I2C_FLAG_TXE ((uint32_t)0x10000080) +#define I2C_FLAG_RXNE ((uint32_t)0x10000040) +#define I2C_FLAG_STOPF ((uint32_t)0x10000010) +#define I2C_FLAG_ADD10 ((uint32_t)0x10000008) +#define I2C_FLAG_BTF ((uint32_t)0x10000004) +#define I2C_FLAG_ADDR ((uint32_t)0x10000002) +#define I2C_FLAG_SB ((uint32_t)0x10000001) + +#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00)) + +#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \ + ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \ + ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \ + ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \ + ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \ + ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \ + ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \ + ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \ + ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \ + ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \ + ((FLAG) == I2C_FLAG_SB)) +/** + * @} + */ + +/** @defgroup I2C_Events + * @{ + */ + +/*======================================== + + I2C Master Events (Events grouped in order of communication) + ==========================================*/ +/** + * @brief Communication start + * + * After sending the START condition (I2C_GenerateSTART() function) the master + * has to wait for this event. It means that the Start condition has been correctly + * released on the I2C bus (the bus is free, no other devices is communicating). + * + */ +/* --EV5 */ +#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */ + +/** + * @brief Address Acknowledge + * + * After checking on EV5 (start condition correctly released on the bus), the + * master sends the address of the slave(s) with which it will communicate + * (I2C_Send7bitAddress() function, it also determines the direction of the communication: + * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges + * his address. If an acknowledge is sent on the bus, one of the following events will + * be set: + * + * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED + * event is set. + * + * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED + * is set + * + * 3) In case of 10-Bit addressing mode, the master (just after generating the START + * and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData() + * function). Then master should wait on EV9. It means that the 10-bit addressing + * header has been correctly sent on the bus. Then master should send the second part of + * the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master + * should wait for event EV6. + * + */ + +/* --EV6 */ +#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ +#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */ +/* --EV9 */ +#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */ + +/** + * @brief Communication events + * + * If a communication is established (START condition generated and slave address + * acknowledged) then the master has to check on one of the following events for + * communication procedures: + * + * 1) Master Receiver mode: The master has to wait on the event EV7 then to read + * the data received from the slave (I2C_ReceiveData() function). + * + * 2) Master Transmitter mode: The master has to send data (I2C_SendData() + * function) then to wait on event EV8 or EV8_2. + * These two events are similar: + * - EV8 means that the data has been written in the data register and is + * being shifted out. + * - EV8_2 means that the data has been physically shifted out and output + * on the bus. + * In most cases, using EV8 is sufficient for the application. + * Using EV8_2 leads to a slower communication but ensure more reliable test. + * EV8_2 is also more suitable than EV8 for testing on the last data transmission + * (before Stop condition generation). + * + * @note In case the user software does not guarantee that this event EV7 is + * managed before the current byte end of transfer, then user may check on EV7 + * and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)). + * In this case the communication may be slower. + * + */ + +/* Master RECEIVER mode -----------------------------*/ +/* --EV7 */ +#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */ + +/* Master TRANSMITTER mode --------------------------*/ +/* --EV8 */ +#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */ +/* --EV8_2 */ +#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ + + +/*======================================== + + I2C Slave Events (Events grouped in order of communication) + ==========================================*/ + +/** + * @brief Communication start events + * + * Wait on one of these events at the start of the communication. It means that + * the I2C peripheral detected a Start condition on the bus (generated by master + * device) followed by the peripheral address. The peripheral generates an ACK + * condition on the bus (if the acknowledge feature is enabled through function + * I2C_AcknowledgeConfig()) and the events listed above are set : + * + * 1) In normal case (only one address managed by the slave), when the address + * sent by the master matches the own address of the peripheral (configured by + * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set + * (where XXX could be TRANSMITTER or RECEIVER). + * + * 2) In case the address sent by the master matches the second address of the + * peripheral (configured by the function I2C_OwnAddress2Config() and enabled + * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED + * (where XXX could be TRANSMITTER or RECEIVER) are set. + * + * 3) In case the address sent by the master is General Call (address 0x00) and + * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) + * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED. + * + */ + +/* --EV1 (all the events below are variants of EV1) */ +/* 1) Case of One Single Address managed by the slave */ +#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */ +#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */ + +/* 2) Case of Dual address managed by the slave */ +#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */ +#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */ + +/* 3) Case of General Call enabled for the slave */ +#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */ + +/** + * @brief Communication events + * + * Wait on one of these events when EV1 has already been checked and: + * + * - Slave RECEIVER mode: + * - EV2: When the application is expecting a data byte to be received. + * - EV4: When the application is expecting the end of the communication: master + * sends a stop condition and data transmission is stopped. + * + * - Slave Transmitter mode: + * - EV3: When a byte has been transmitted by the slave and the application is expecting + * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and + * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be + * used when the user software doesn't guarantee the EV3 is managed before the + * current byte end of tranfer. + * - EV3_2: When the master sends a NACK in order to tell slave that data transmission + * shall end (before sending the STOP condition). In this case slave has to stop sending + * data bytes and expect a Stop condition on the bus. + * + * @note In case the user software does not guarantee that the event EV2 is + * managed before the current byte end of transfer, then user may check on EV2 + * and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)). + * In this case the communication may be slower. + * + */ + +/* Slave RECEIVER mode --------------------------*/ +/* --EV2 */ +#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */ +/* --EV4 */ +#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */ + +/* Slave TRANSMITTER mode -----------------------*/ +/* --EV3 */ +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */ +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */ +/* --EV3_2 */ +#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */ + +/*=========================== End of Events Description ==========================================*/ + +#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \ + ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \ + ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \ + ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \ + ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \ + ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \ + ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \ + ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \ + ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \ + ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \ + ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \ + ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \ + ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \ + ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \ + ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \ + ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \ + ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \ + ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \ + ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \ + ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE)) +/** + * @} + */ + +/** @defgroup I2C_own_address1 + * @{ + */ + +#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF) +/** + * @} + */ + +/** @defgroup I2C_clock_speed + * @{ + */ + +#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000)) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup I2C_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup I2C_Exported_Functions + * @{ + */ + +void I2C_DeInit(I2C_TypeDef* I2Cx); +void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct); +void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct); +void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address); +void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState); +void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data); +uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx); +void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction); +uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register); +void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert); +void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition); +void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState); +uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx); +void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle); + +/** + * @brief + **************************************************************************************** + * + * I2C State Monitoring Functions + * + **************************************************************************************** + * This I2C driver provides three different ways for I2C state monitoring + * depending on the application requirements and constraints: + * + * + * 1) Basic state monitoring: + * Using I2C_CheckEvent() function: + * It compares the status registers (SR1 and SR2) content to a given event + * (can be the combination of one or more flags). + * It returns SUCCESS if the current status includes the given flags + * and returns ERROR if one or more flags are missing in the current status. + * - When to use: + * - This function is suitable for most applications as well as for startup + * activity since the events are fully described in the product reference manual + * (RM0008). + * - It is also suitable for users who need to define their own events. + * - Limitations: + * - If an error occurs (ie. error flags are set besides to the monitored flags), + * the I2C_CheckEvent() function may return SUCCESS despite the communication + * hold or corrupted real state. + * In this case, it is advised to use error interrupts to monitor the error + * events and handle them in the interrupt IRQ handler. + * + * @note + * For error management, it is advised to use the following functions: + * - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR). + * - I2Cx_ER_IRQHandler() which is called when the error interurpt occurs. + * Where x is the peripheral instance (I2C1, I2C2 ...) + * - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into I2Cx_ER_IRQHandler() + * in order to determine which error occured. + * - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() + * and/or I2C_GenerateStop() in order to clear the error flag and source, + * and return to correct communication status. + * + * + * 2) Advanced state monitoring: + * Using the function I2C_GetLastEvent() which returns the image of both status + * registers in a single word (uint32_t) (Status Register 2 value is shifted left + * by 16 bits and concatenated to Status Register 1). + * - When to use: + * - This function is suitable for the same applications above but it allows to + * overcome the limitations of I2C_GetFlagStatus() function (see below). + * The returned value could be compared to events already defined in the + * library (stm32f10x_i2c.h) or to custom values defined by user. + * - This function is suitable when multiple flags are monitored at the same time. + * - At the opposite of I2C_CheckEvent() function, this function allows user to + * choose when an event is accepted (when all events flags are set and no + * other flags are set or just when the needed flags are set like + * I2C_CheckEvent() function). + * - Limitations: + * - User may need to define his own events. + * - Same remark concerning the error management is applicable for this + * function if user decides to check only regular communication flags (and + * ignores error flags). + * + * + * 3) Flag-based state monitoring: + * Using the function I2C_GetFlagStatus() which simply returns the status of + * one single flag (ie. I2C_FLAG_RXNE ...). + * - When to use: + * - This function could be used for specific applications or in debug phase. + * - It is suitable when only one flag checking is needed (most I2C events + * are monitored through multiple flags). + * - Limitations: + * - When calling this function, the Status register is accessed. Some flags are + * cleared when the status register is accessed. So checking the status + * of one Flag, may clear other ones. + * - Function may need to be called twice or more in order to monitor one + * single event. + * + */ + +/** + * + * 1) Basic state monitoring + ******************************************************************************* + */ +ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT); +/** + * + * 2) Advanced state monitoring + ******************************************************************************* + */ +uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx); +/** + * + * 3) Flag-based state monitoring + ******************************************************************************* + */ +FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); +/** + * + ******************************************************************************* + */ + +void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); +ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT); +void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F10x_I2C_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32f10x/stm32f10x_iwdg.h b/example/libs_stm/inc/stm32f10x/stm32f10x_iwdg.h new file mode 100644 index 0000000..f9a26bf --- /dev/null +++ b/example/libs_stm/inc/stm32f10x/stm32f10x_iwdg.h @@ -0,0 +1,139 @@ +/** + ****************************************************************************** + * @file stm32f10x_iwdg.h + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file contains all the functions prototypes for the IWDG + * firmware library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_IWDG_H +#define __STM32F10x_IWDG_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup IWDG + * @{ + */ + +/** @defgroup IWDG_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @defgroup IWDG_Exported_Constants + * @{ + */ + +/** @defgroup IWDG_WriteAccess + * @{ + */ + +#define IWDG_WriteAccess_Enable ((uint16_t)0x5555) +#define IWDG_WriteAccess_Disable ((uint16_t)0x0000) +#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \ + ((ACCESS) == IWDG_WriteAccess_Disable)) +/** + * @} + */ + +/** @defgroup IWDG_prescaler + * @{ + */ + +#define IWDG_Prescaler_4 ((uint8_t)0x00) +#define IWDG_Prescaler_8 ((uint8_t)0x01) +#define IWDG_Prescaler_16 ((uint8_t)0x02) +#define IWDG_Prescaler_32 ((uint8_t)0x03) +#define IWDG_Prescaler_64 ((uint8_t)0x04) +#define IWDG_Prescaler_128 ((uint8_t)0x05) +#define IWDG_Prescaler_256 ((uint8_t)0x06) +#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \ + ((PRESCALER) == IWDG_Prescaler_8) || \ + ((PRESCALER) == IWDG_Prescaler_16) || \ + ((PRESCALER) == IWDG_Prescaler_32) || \ + ((PRESCALER) == IWDG_Prescaler_64) || \ + ((PRESCALER) == IWDG_Prescaler_128)|| \ + ((PRESCALER) == IWDG_Prescaler_256)) +/** + * @} + */ + +/** @defgroup IWDG_Flag + * @{ + */ + +#define IWDG_FLAG_PVU ((uint16_t)0x0001) +#define IWDG_FLAG_RVU ((uint16_t)0x0002) +#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU)) +#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup IWDG_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup IWDG_Exported_Functions + * @{ + */ + +void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess); +void IWDG_SetPrescaler(uint8_t IWDG_Prescaler); +void IWDG_SetReload(uint16_t Reload); +void IWDG_ReloadCounter(void); +void IWDG_Enable(void); +FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_IWDG_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32f10x/stm32f10x_pwr.h b/example/libs_stm/inc/stm32f10x/stm32f10x_pwr.h new file mode 100644 index 0000000..ce168da --- /dev/null +++ b/example/libs_stm/inc/stm32f10x/stm32f10x_pwr.h @@ -0,0 +1,155 @@ +/** + ****************************************************************************** + * @file stm32f10x_pwr.h + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file contains all the functions prototypes for the PWR firmware + * library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_PWR_H +#define __STM32F10x_PWR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup PWR + * @{ + */ + +/** @defgroup PWR_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @defgroup PWR_Exported_Constants + * @{ + */ + +/** @defgroup PVD_detection_level + * @{ + */ + +#define PWR_PVDLevel_2V2 ((uint32_t)0x00000000) +#define PWR_PVDLevel_2V3 ((uint32_t)0x00000020) +#define PWR_PVDLevel_2V4 ((uint32_t)0x00000040) +#define PWR_PVDLevel_2V5 ((uint32_t)0x00000060) +#define PWR_PVDLevel_2V6 ((uint32_t)0x00000080) +#define PWR_PVDLevel_2V7 ((uint32_t)0x000000A0) +#define PWR_PVDLevel_2V8 ((uint32_t)0x000000C0) +#define PWR_PVDLevel_2V9 ((uint32_t)0x000000E0) +#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_2V2) || ((LEVEL) == PWR_PVDLevel_2V3)|| \ + ((LEVEL) == PWR_PVDLevel_2V4) || ((LEVEL) == PWR_PVDLevel_2V5)|| \ + ((LEVEL) == PWR_PVDLevel_2V6) || ((LEVEL) == PWR_PVDLevel_2V7)|| \ + ((LEVEL) == PWR_PVDLevel_2V8) || ((LEVEL) == PWR_PVDLevel_2V9)) +/** + * @} + */ + +/** @defgroup Regulator_state_is_STOP_mode + * @{ + */ + +#define PWR_Regulator_ON ((uint32_t)0x00000000) +#define PWR_Regulator_LowPower ((uint32_t)0x00000001) +#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \ + ((REGULATOR) == PWR_Regulator_LowPower)) +/** + * @} + */ + +/** @defgroup STOP_mode_entry + * @{ + */ + +#define PWR_STOPEntry_WFI ((uint8_t)0x01) +#define PWR_STOPEntry_WFE ((uint8_t)0x02) +#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE)) + +/** + * @} + */ + +/** @defgroup PWR_Flag + * @{ + */ + +#define PWR_FLAG_WU ((uint32_t)0x00000001) +#define PWR_FLAG_SB ((uint32_t)0x00000002) +#define PWR_FLAG_PVDO ((uint32_t)0x00000004) +#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \ + ((FLAG) == PWR_FLAG_PVDO)) + +#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB)) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup PWR_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup PWR_Exported_Functions + * @{ + */ + +void PWR_DeInit(void); +void PWR_BackupAccessCmd(FunctionalState NewState); +void PWR_PVDCmd(FunctionalState NewState); +void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); +void PWR_WakeUpPinCmd(FunctionalState NewState); +void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); +void PWR_EnterSTANDBYMode(void); +FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); +void PWR_ClearFlag(uint32_t PWR_FLAG); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_PWR_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32f10x/stm32f10x_rcc.h b/example/libs_stm/inc/stm32f10x/stm32f10x_rcc.h new file mode 100644 index 0000000..19afe3e --- /dev/null +++ b/example/libs_stm/inc/stm32f10x/stm32f10x_rcc.h @@ -0,0 +1,726 @@ +/** + ****************************************************************************** + * @file stm32f10x_rcc.h + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file contains all the functions prototypes for the RCC firmware + * library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_RCC_H +#define __STM32F10x_RCC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup RCC + * @{ + */ + +/** @defgroup RCC_Exported_Types + * @{ + */ + +typedef struct +{ + uint32_t SYSCLK_Frequency; /*!< returns SYSCLK clock frequency expressed in Hz */ + uint32_t HCLK_Frequency; /*!< returns HCLK clock frequency expressed in Hz */ + uint32_t PCLK1_Frequency; /*!< returns PCLK1 clock frequency expressed in Hz */ + uint32_t PCLK2_Frequency; /*!< returns PCLK2 clock frequency expressed in Hz */ + uint32_t ADCCLK_Frequency; /*!< returns ADCCLK clock frequency expressed in Hz */ +}RCC_ClocksTypeDef; + +/** + * @} + */ + +/** @defgroup RCC_Exported_Constants + * @{ + */ + +/** @defgroup HSE_configuration + * @{ + */ + +#define RCC_HSE_OFF ((uint32_t)0x00000000) +#define RCC_HSE_ON ((uint32_t)0x00010000) +#define RCC_HSE_Bypass ((uint32_t)0x00040000) +#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ + ((HSE) == RCC_HSE_Bypass)) + +/** + * @} + */ + +/** @defgroup PLL_entry_clock_source + * @{ + */ + +#define RCC_PLLSource_HSI_Div2 ((uint32_t)0x00000000) + +#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_CL) + #define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000) + #define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000) + #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \ + ((SOURCE) == RCC_PLLSource_HSE_Div1) || \ + ((SOURCE) == RCC_PLLSource_HSE_Div2)) +#else + #define RCC_PLLSource_PREDIV1 ((uint32_t)0x00010000) + #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \ + ((SOURCE) == RCC_PLLSource_PREDIV1)) +#endif /* STM32F10X_CL */ + +/** + * @} + */ + +/** @defgroup PLL_multiplication_factor + * @{ + */ +#ifndef STM32F10X_CL + #define RCC_PLLMul_2 ((uint32_t)0x00000000) + #define RCC_PLLMul_3 ((uint32_t)0x00040000) + #define RCC_PLLMul_4 ((uint32_t)0x00080000) + #define RCC_PLLMul_5 ((uint32_t)0x000C0000) + #define RCC_PLLMul_6 ((uint32_t)0x00100000) + #define RCC_PLLMul_7 ((uint32_t)0x00140000) + #define RCC_PLLMul_8 ((uint32_t)0x00180000) + #define RCC_PLLMul_9 ((uint32_t)0x001C0000) + #define RCC_PLLMul_10 ((uint32_t)0x00200000) + #define RCC_PLLMul_11 ((uint32_t)0x00240000) + #define RCC_PLLMul_12 ((uint32_t)0x00280000) + #define RCC_PLLMul_13 ((uint32_t)0x002C0000) + #define RCC_PLLMul_14 ((uint32_t)0x00300000) + #define RCC_PLLMul_15 ((uint32_t)0x00340000) + #define RCC_PLLMul_16 ((uint32_t)0x00380000) + #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \ + ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \ + ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \ + ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \ + ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \ + ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \ + ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \ + ((MUL) == RCC_PLLMul_16)) + +#else + #define RCC_PLLMul_4 ((uint32_t)0x00080000) + #define RCC_PLLMul_5 ((uint32_t)0x000C0000) + #define RCC_PLLMul_6 ((uint32_t)0x00100000) + #define RCC_PLLMul_7 ((uint32_t)0x00140000) + #define RCC_PLLMul_8 ((uint32_t)0x00180000) + #define RCC_PLLMul_9 ((uint32_t)0x001C0000) + #define RCC_PLLMul_6_5 ((uint32_t)0x00340000) + + #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \ + ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \ + ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \ + ((MUL) == RCC_PLLMul_6_5)) +#endif /* STM32F10X_CL */ +/** + * @} + */ + +/** @defgroup PREDIV1_division_factor + * @{ + */ +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_CL) + #define RCC_PREDIV1_Div1 ((uint32_t)0x00000000) + #define RCC_PREDIV1_Div2 ((uint32_t)0x00000001) + #define RCC_PREDIV1_Div3 ((uint32_t)0x00000002) + #define RCC_PREDIV1_Div4 ((uint32_t)0x00000003) + #define RCC_PREDIV1_Div5 ((uint32_t)0x00000004) + #define RCC_PREDIV1_Div6 ((uint32_t)0x00000005) + #define RCC_PREDIV1_Div7 ((uint32_t)0x00000006) + #define RCC_PREDIV1_Div8 ((uint32_t)0x00000007) + #define RCC_PREDIV1_Div9 ((uint32_t)0x00000008) + #define RCC_PREDIV1_Div10 ((uint32_t)0x00000009) + #define RCC_PREDIV1_Div11 ((uint32_t)0x0000000A) + #define RCC_PREDIV1_Div12 ((uint32_t)0x0000000B) + #define RCC_PREDIV1_Div13 ((uint32_t)0x0000000C) + #define RCC_PREDIV1_Div14 ((uint32_t)0x0000000D) + #define RCC_PREDIV1_Div15 ((uint32_t)0x0000000E) + #define RCC_PREDIV1_Div16 ((uint32_t)0x0000000F) + + #define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \ + ((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \ + ((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \ + ((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \ + ((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \ + ((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \ + ((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \ + ((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16)) +#endif +/** + * @} + */ + + +/** @defgroup PREDIV1_clock_source + * @{ + */ +#ifdef STM32F10X_CL +/* PREDIV1 clock source (for STM32 connectivity line devices) */ + #define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000) + #define RCC_PREDIV1_Source_PLL2 ((uint32_t)0x00010000) + + #define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE) || \ + ((SOURCE) == RCC_PREDIV1_Source_PLL2)) +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) +/* PREDIV1 clock source (for STM32 Value line devices) */ + #define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000) + + #define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE)) +#endif +/** + * @} + */ + +#ifdef STM32F10X_CL +/** @defgroup PREDIV2_division_factor + * @{ + */ + + #define RCC_PREDIV2_Div1 ((uint32_t)0x00000000) + #define RCC_PREDIV2_Div2 ((uint32_t)0x00000010) + #define RCC_PREDIV2_Div3 ((uint32_t)0x00000020) + #define RCC_PREDIV2_Div4 ((uint32_t)0x00000030) + #define RCC_PREDIV2_Div5 ((uint32_t)0x00000040) + #define RCC_PREDIV2_Div6 ((uint32_t)0x00000050) + #define RCC_PREDIV2_Div7 ((uint32_t)0x00000060) + #define RCC_PREDIV2_Div8 ((uint32_t)0x00000070) + #define RCC_PREDIV2_Div9 ((uint32_t)0x00000080) + #define RCC_PREDIV2_Div10 ((uint32_t)0x00000090) + #define RCC_PREDIV2_Div11 ((uint32_t)0x000000A0) + #define RCC_PREDIV2_Div12 ((uint32_t)0x000000B0) + #define RCC_PREDIV2_Div13 ((uint32_t)0x000000C0) + #define RCC_PREDIV2_Div14 ((uint32_t)0x000000D0) + #define RCC_PREDIV2_Div15 ((uint32_t)0x000000E0) + #define RCC_PREDIV2_Div16 ((uint32_t)0x000000F0) + + #define IS_RCC_PREDIV2(PREDIV2) (((PREDIV2) == RCC_PREDIV2_Div1) || ((PREDIV2) == RCC_PREDIV2_Div2) || \ + ((PREDIV2) == RCC_PREDIV2_Div3) || ((PREDIV2) == RCC_PREDIV2_Div4) || \ + ((PREDIV2) == RCC_PREDIV2_Div5) || ((PREDIV2) == RCC_PREDIV2_Div6) || \ + ((PREDIV2) == RCC_PREDIV2_Div7) || ((PREDIV2) == RCC_PREDIV2_Div8) || \ + ((PREDIV2) == RCC_PREDIV2_Div9) || ((PREDIV2) == RCC_PREDIV2_Div10) || \ + ((PREDIV2) == RCC_PREDIV2_Div11) || ((PREDIV2) == RCC_PREDIV2_Div12) || \ + ((PREDIV2) == RCC_PREDIV2_Div13) || ((PREDIV2) == RCC_PREDIV2_Div14) || \ + ((PREDIV2) == RCC_PREDIV2_Div15) || ((PREDIV2) == RCC_PREDIV2_Div16)) +/** + * @} + */ + + +/** @defgroup PLL2_multiplication_factor + * @{ + */ + + #define RCC_PLL2Mul_8 ((uint32_t)0x00000600) + #define RCC_PLL2Mul_9 ((uint32_t)0x00000700) + #define RCC_PLL2Mul_10 ((uint32_t)0x00000800) + #define RCC_PLL2Mul_11 ((uint32_t)0x00000900) + #define RCC_PLL2Mul_12 ((uint32_t)0x00000A00) + #define RCC_PLL2Mul_13 ((uint32_t)0x00000B00) + #define RCC_PLL2Mul_14 ((uint32_t)0x00000C00) + #define RCC_PLL2Mul_16 ((uint32_t)0x00000E00) + #define RCC_PLL2Mul_20 ((uint32_t)0x00000F00) + + #define IS_RCC_PLL2_MUL(MUL) (((MUL) == RCC_PLL2Mul_8) || ((MUL) == RCC_PLL2Mul_9) || \ + ((MUL) == RCC_PLL2Mul_10) || ((MUL) == RCC_PLL2Mul_11) || \ + ((MUL) == RCC_PLL2Mul_12) || ((MUL) == RCC_PLL2Mul_13) || \ + ((MUL) == RCC_PLL2Mul_14) || ((MUL) == RCC_PLL2Mul_16) || \ + ((MUL) == RCC_PLL2Mul_20)) +/** + * @} + */ + + +/** @defgroup PLL3_multiplication_factor + * @{ + */ + + #define RCC_PLL3Mul_8 ((uint32_t)0x00006000) + #define RCC_PLL3Mul_9 ((uint32_t)0x00007000) + #define RCC_PLL3Mul_10 ((uint32_t)0x00008000) + #define RCC_PLL3Mul_11 ((uint32_t)0x00009000) + #define RCC_PLL3Mul_12 ((uint32_t)0x0000A000) + #define RCC_PLL3Mul_13 ((uint32_t)0x0000B000) + #define RCC_PLL3Mul_14 ((uint32_t)0x0000C000) + #define RCC_PLL3Mul_16 ((uint32_t)0x0000E000) + #define RCC_PLL3Mul_20 ((uint32_t)0x0000F000) + + #define IS_RCC_PLL3_MUL(MUL) (((MUL) == RCC_PLL3Mul_8) || ((MUL) == RCC_PLL3Mul_9) || \ + ((MUL) == RCC_PLL3Mul_10) || ((MUL) == RCC_PLL3Mul_11) || \ + ((MUL) == RCC_PLL3Mul_12) || ((MUL) == RCC_PLL3Mul_13) || \ + ((MUL) == RCC_PLL3Mul_14) || ((MUL) == RCC_PLL3Mul_16) || \ + ((MUL) == RCC_PLL3Mul_20)) +/** + * @} + */ + +#endif /* STM32F10X_CL */ + + +/** @defgroup System_clock_source + * @{ + */ + +#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) +#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) +#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) +#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ + ((SOURCE) == RCC_SYSCLKSource_HSE) || \ + ((SOURCE) == RCC_SYSCLKSource_PLLCLK)) +/** + * @} + */ + +/** @defgroup AHB_clock_source + * @{ + */ + +#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) +#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080) +#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090) +#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0) +#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) +#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0) +#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0) +#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0) +#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0) +#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \ + ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \ + ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \ + ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \ + ((HCLK) == RCC_SYSCLK_Div512)) +/** + * @} + */ + +/** @defgroup APB1_APB2_clock_source + * @{ + */ + +#define RCC_HCLK_Div1 ((uint32_t)0x00000000) +#define RCC_HCLK_Div2 ((uint32_t)0x00000400) +#define RCC_HCLK_Div4 ((uint32_t)0x00000500) +#define RCC_HCLK_Div8 ((uint32_t)0x00000600) +#define RCC_HCLK_Div16 ((uint32_t)0x00000700) +#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \ + ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \ + ((PCLK) == RCC_HCLK_Div16)) +/** + * @} + */ + +/** @defgroup RCC_Interrupt_source + * @{ + */ + +#define RCC_IT_LSIRDY ((uint8_t)0x01) +#define RCC_IT_LSERDY ((uint8_t)0x02) +#define RCC_IT_HSIRDY ((uint8_t)0x04) +#define RCC_IT_HSERDY ((uint8_t)0x08) +#define RCC_IT_PLLRDY ((uint8_t)0x10) +#define RCC_IT_CSS ((uint8_t)0x80) + +#ifndef STM32F10X_CL + #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xE0) == 0x00) && ((IT) != 0x00)) + #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ + ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ + ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS)) + #define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x60) == 0x00) && ((IT) != 0x00)) +#else + #define RCC_IT_PLL2RDY ((uint8_t)0x20) + #define RCC_IT_PLL3RDY ((uint8_t)0x40) + #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00)) + #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ + ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ + ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \ + ((IT) == RCC_IT_PLL2RDY) || ((IT) == RCC_IT_PLL3RDY)) + #define IS_RCC_CLEAR_IT(IT) ((IT) != 0x00) +#endif /* STM32F10X_CL */ + + +/** + * @} + */ + +#ifndef STM32F10X_CL +/** @defgroup USB_Device_clock_source + * @{ + */ + + #define RCC_USBCLKSource_PLLCLK_1Div5 ((uint8_t)0x00) + #define RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x01) + + #define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \ + ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1)) +/** + * @} + */ +#else +/** @defgroup USB_OTG_FS_clock_source + * @{ + */ + #define RCC_OTGFSCLKSource_PLLVCO_Div3 ((uint8_t)0x00) + #define RCC_OTGFSCLKSource_PLLVCO_Div2 ((uint8_t)0x01) + + #define IS_RCC_OTGFSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div3) || \ + ((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div2)) +/** + * @} + */ +#endif /* STM32F10X_CL */ + + +#ifdef STM32F10X_CL +/** @defgroup I2S2_clock_source + * @{ + */ + #define RCC_I2S2CLKSource_SYSCLK ((uint8_t)0x00) + #define RCC_I2S2CLKSource_PLL3_VCO ((uint8_t)0x01) + + #define IS_RCC_I2S2CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_SYSCLK) || \ + ((SOURCE) == RCC_I2S2CLKSource_PLL3_VCO)) +/** + * @} + */ + +/** @defgroup I2S3_clock_source + * @{ + */ + #define RCC_I2S3CLKSource_SYSCLK ((uint8_t)0x00) + #define RCC_I2S3CLKSource_PLL3_VCO ((uint8_t)0x01) + + #define IS_RCC_I2S3CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S3CLKSource_SYSCLK) || \ + ((SOURCE) == RCC_I2S3CLKSource_PLL3_VCO)) +/** + * @} + */ +#endif /* STM32F10X_CL */ + + +/** @defgroup ADC_clock_source + * @{ + */ + +#define RCC_PCLK2_Div2 ((uint32_t)0x00000000) +#define RCC_PCLK2_Div4 ((uint32_t)0x00004000) +#define RCC_PCLK2_Div6 ((uint32_t)0x00008000) +#define RCC_PCLK2_Div8 ((uint32_t)0x0000C000) +#define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_PCLK2_Div2) || ((ADCCLK) == RCC_PCLK2_Div4) || \ + ((ADCCLK) == RCC_PCLK2_Div6) || ((ADCCLK) == RCC_PCLK2_Div8)) +/** + * @} + */ + +/** @defgroup LSE_configuration + * @{ + */ + +#define RCC_LSE_OFF ((uint8_t)0x00) +#define RCC_LSE_ON ((uint8_t)0x01) +#define RCC_LSE_Bypass ((uint8_t)0x04) +#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ + ((LSE) == RCC_LSE_Bypass)) +/** + * @} + */ + +/** @defgroup RTC_clock_source + * @{ + */ + +#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100) +#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200) +#define RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300) +#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \ + ((SOURCE) == RCC_RTCCLKSource_LSI) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div128)) +/** + * @} + */ + +/** @defgroup AHB_peripheral + * @{ + */ + +#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001) +#define RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002) +#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004) +#define RCC_AHBPeriph_FLITF ((uint32_t)0x00000010) +#define RCC_AHBPeriph_CRC ((uint32_t)0x00000040) + +#ifndef STM32F10X_CL + #define RCC_AHBPeriph_FSMC ((uint32_t)0x00000100) + #define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400) + #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFAA8) == 0x00) && ((PERIPH) != 0x00)) +#else + #define RCC_AHBPeriph_OTG_FS ((uint32_t)0x00001000) + #define RCC_AHBPeriph_ETH_MAC ((uint32_t)0x00004000) + #define RCC_AHBPeriph_ETH_MAC_Tx ((uint32_t)0x00008000) + #define RCC_AHBPeriph_ETH_MAC_Rx ((uint32_t)0x00010000) + + #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFE2FA8) == 0x00) && ((PERIPH) != 0x00)) + #define IS_RCC_AHB_PERIPH_RESET(PERIPH) ((((PERIPH) & 0xFFFFAFFF) == 0x00) && ((PERIPH) != 0x00)) +#endif /* STM32F10X_CL */ +/** + * @} + */ + +/** @defgroup APB2_peripheral + * @{ + */ + +#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001) +#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004) +#define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008) +#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010) +#define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020) +#define RCC_APB2Periph_GPIOE ((uint32_t)0x00000040) +#define RCC_APB2Periph_GPIOF ((uint32_t)0x00000080) +#define RCC_APB2Periph_GPIOG ((uint32_t)0x00000100) +#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200) +#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000400) +#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800) +#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) +#define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000) +#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000) +#define RCC_APB2Periph_ADC3 ((uint32_t)0x00008000) +#define RCC_APB2Periph_TIM15 ((uint32_t)0x00010000) +#define RCC_APB2Periph_TIM16 ((uint32_t)0x00020000) +#define RCC_APB2Periph_TIM17 ((uint32_t)0x00040000) +#define RCC_APB2Periph_TIM9 ((uint32_t)0x00080000) +#define RCC_APB2Periph_TIM10 ((uint32_t)0x00100000) +#define RCC_APB2Periph_TIM11 ((uint32_t)0x00200000) + +#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFC00002) == 0x00) && ((PERIPH) != 0x00)) +/** + * @} + */ + +/** @defgroup APB1_peripheral + * @{ + */ + +#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) +#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002) +#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004) +#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008) +#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010) +#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020) +#define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040) +#define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080) +#define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100) +#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) +#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000) +#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000) +#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000) +#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000) +#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000) +#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000) +#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) +#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000) +#define RCC_APB1Periph_USB ((uint32_t)0x00800000) +#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000) +#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000) +#define RCC_APB1Periph_BKP ((uint32_t)0x08000000) +#define RCC_APB1Periph_PWR ((uint32_t)0x10000000) +#define RCC_APB1Periph_DAC ((uint32_t)0x20000000) +#define RCC_APB1Periph_CEC ((uint32_t)0x40000000) + +#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x81013600) == 0x00) && ((PERIPH) != 0x00)) + +/** + * @} + */ + +/** @defgroup Clock_source_to_output_on_MCO_pin + * @{ + */ + +#define RCC_MCO_NoClock ((uint8_t)0x00) +#define RCC_MCO_SYSCLK ((uint8_t)0x04) +#define RCC_MCO_HSI ((uint8_t)0x05) +#define RCC_MCO_HSE ((uint8_t)0x06) +#define RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07) + +#ifndef STM32F10X_CL + #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \ + ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \ + ((MCO) == RCC_MCO_PLLCLK_Div2)) +#else + #define RCC_MCO_PLL2CLK ((uint8_t)0x08) + #define RCC_MCO_PLL3CLK_Div2 ((uint8_t)0x09) + #define RCC_MCO_XT1 ((uint8_t)0x0A) + #define RCC_MCO_PLL3CLK ((uint8_t)0x0B) + + #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \ + ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \ + ((MCO) == RCC_MCO_PLLCLK_Div2) || ((MCO) == RCC_MCO_PLL2CLK) || \ + ((MCO) == RCC_MCO_PLL3CLK_Div2) || ((MCO) == RCC_MCO_XT1) || \ + ((MCO) == RCC_MCO_PLL3CLK)) +#endif /* STM32F10X_CL */ + +/** + * @} + */ + +/** @defgroup RCC_Flag + * @{ + */ + +#define RCC_FLAG_HSIRDY ((uint8_t)0x21) +#define RCC_FLAG_HSERDY ((uint8_t)0x31) +#define RCC_FLAG_PLLRDY ((uint8_t)0x39) +#define RCC_FLAG_LSERDY ((uint8_t)0x41) +#define RCC_FLAG_LSIRDY ((uint8_t)0x61) +#define RCC_FLAG_PINRST ((uint8_t)0x7A) +#define RCC_FLAG_PORRST ((uint8_t)0x7B) +#define RCC_FLAG_SFTRST ((uint8_t)0x7C) +#define RCC_FLAG_IWDGRST ((uint8_t)0x7D) +#define RCC_FLAG_WWDGRST ((uint8_t)0x7E) +#define RCC_FLAG_LPWRRST ((uint8_t)0x7F) + +#ifndef STM32F10X_CL + #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ + ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ + ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \ + ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \ + ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \ + ((FLAG) == RCC_FLAG_LPWRRST)) +#else + #define RCC_FLAG_PLL2RDY ((uint8_t)0x3B) + #define RCC_FLAG_PLL3RDY ((uint8_t)0x3D) + #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ + ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ + ((FLAG) == RCC_FLAG_PLL2RDY) || ((FLAG) == RCC_FLAG_PLL3RDY) || \ + ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \ + ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \ + ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \ + ((FLAG) == RCC_FLAG_LPWRRST)) +#endif /* STM32F10X_CL */ + +#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup RCC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup RCC_Exported_Functions + * @{ + */ + +void RCC_DeInit(void); +void RCC_HSEConfig(uint32_t RCC_HSE); +ErrorStatus RCC_WaitForHSEStartUp(void); +void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); +void RCC_HSICmd(FunctionalState NewState); +void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul); +void RCC_PLLCmd(FunctionalState NewState); + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_CL) + void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div); +#endif + +#ifdef STM32F10X_CL + void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div); + void RCC_PLL2Config(uint32_t RCC_PLL2Mul); + void RCC_PLL2Cmd(FunctionalState NewState); + void RCC_PLL3Config(uint32_t RCC_PLL3Mul); + void RCC_PLL3Cmd(FunctionalState NewState); +#endif /* STM32F10X_CL */ + +void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); +uint8_t RCC_GetSYSCLKSource(void); +void RCC_HCLKConfig(uint32_t RCC_SYSCLK); +void RCC_PCLK1Config(uint32_t RCC_HCLK); +void RCC_PCLK2Config(uint32_t RCC_HCLK); +void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); + +#ifndef STM32F10X_CL + void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource); +#else + void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource); +#endif /* STM32F10X_CL */ + +void RCC_ADCCLKConfig(uint32_t RCC_PCLK2); + +#ifdef STM32F10X_CL + void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource); + void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource); +#endif /* STM32F10X_CL */ + +void RCC_LSEConfig(uint8_t RCC_LSE); +void RCC_LSICmd(FunctionalState NewState); +void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); +void RCC_RTCCLKCmd(FunctionalState NewState); +void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); +void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); +void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); +void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); + +#ifdef STM32F10X_CL +void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); +#endif /* STM32F10X_CL */ + +void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); +void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); +void RCC_BackupResetCmd(FunctionalState NewState); +void RCC_ClockSecuritySystemCmd(FunctionalState NewState); +void RCC_MCOConfig(uint8_t RCC_MCO); +FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); +void RCC_ClearFlag(void); +ITStatus RCC_GetITStatus(uint8_t RCC_IT); +void RCC_ClearITPendingBit(uint8_t RCC_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_RCC_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32f10x/stm32f10x_rtc.h b/example/libs_stm/inc/stm32f10x/stm32f10x_rtc.h new file mode 100644 index 0000000..833f2fe --- /dev/null +++ b/example/libs_stm/inc/stm32f10x/stm32f10x_rtc.h @@ -0,0 +1,134 @@ +/** + ****************************************************************************** + * @file stm32f10x_rtc.h + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file contains all the functions prototypes for the RTC firmware + * library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_RTC_H +#define __STM32F10x_RTC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup RTC + * @{ + */ + +/** @defgroup RTC_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @defgroup RTC_Exported_Constants + * @{ + */ + +/** @defgroup RTC_interrupts_define + * @{ + */ + +#define RTC_IT_OW ((uint16_t)0x0004) /*!< Overflow interrupt */ +#define RTC_IT_ALR ((uint16_t)0x0002) /*!< Alarm interrupt */ +#define RTC_IT_SEC ((uint16_t)0x0001) /*!< Second interrupt */ +#define IS_RTC_IT(IT) ((((IT) & (uint16_t)0xFFF8) == 0x00) && ((IT) != 0x00)) +#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_OW) || ((IT) == RTC_IT_ALR) || \ + ((IT) == RTC_IT_SEC)) +/** + * @} + */ + +/** @defgroup RTC_interrupts_flags + * @{ + */ + +#define RTC_FLAG_RTOFF ((uint16_t)0x0020) /*!< RTC Operation OFF flag */ +#define RTC_FLAG_RSF ((uint16_t)0x0008) /*!< Registers Synchronized flag */ +#define RTC_FLAG_OW ((uint16_t)0x0004) /*!< Overflow flag */ +#define RTC_FLAG_ALR ((uint16_t)0x0002) /*!< Alarm flag */ +#define RTC_FLAG_SEC ((uint16_t)0x0001) /*!< Second flag */ +#define IS_RTC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFF0) == 0x00) && ((FLAG) != 0x00)) +#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_RTOFF) || ((FLAG) == RTC_FLAG_RSF) || \ + ((FLAG) == RTC_FLAG_OW) || ((FLAG) == RTC_FLAG_ALR) || \ + ((FLAG) == RTC_FLAG_SEC)) +#define IS_RTC_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFFFF) + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup RTC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup RTC_Exported_Functions + * @{ + */ + +void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState); +void RTC_EnterConfigMode(void); +void RTC_ExitConfigMode(void); +uint32_t RTC_GetCounter(void); +void RTC_SetCounter(uint32_t CounterValue); +void RTC_SetPrescaler(uint32_t PrescalerValue); +void RTC_SetAlarm(uint32_t AlarmValue); +uint32_t RTC_GetDivider(void); +void RTC_WaitForLastTask(void); +void RTC_WaitForSynchro(void); +FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG); +void RTC_ClearFlag(uint16_t RTC_FLAG); +ITStatus RTC_GetITStatus(uint16_t RTC_IT); +void RTC_ClearITPendingBit(uint16_t RTC_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_RTC_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32f10x/stm32f10x_sdio.h b/example/libs_stm/inc/stm32f10x/stm32f10x_sdio.h new file mode 100644 index 0000000..a6c62cd --- /dev/null +++ b/example/libs_stm/inc/stm32f10x/stm32f10x_sdio.h @@ -0,0 +1,530 @@ +/** + ****************************************************************************** + * @file stm32f10x_sdio.h + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file contains all the functions prototypes for the SDIO firmware + * library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_SDIO_H +#define __STM32F10x_SDIO_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup SDIO + * @{ + */ + +/** @defgroup SDIO_Exported_Types + * @{ + */ + +typedef struct +{ + uint32_t SDIO_ClockEdge; /*!< Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref SDIO_Clock_Edge */ + + uint32_t SDIO_ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is + enabled or disabled. + This parameter can be a value of @ref SDIO_Clock_Bypass */ + + uint32_t SDIO_ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or + disabled when the bus is idle. + This parameter can be a value of @ref SDIO_Clock_Power_Save */ + + uint32_t SDIO_BusWide; /*!< Specifies the SDIO bus width. + This parameter can be a value of @ref SDIO_Bus_Wide */ + + uint32_t SDIO_HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled. + This parameter can be a value of @ref SDIO_Hardware_Flow_Control */ + + uint8_t SDIO_ClockDiv; /*!< Specifies the clock frequency of the SDIO controller. + This parameter can be a value between 0x00 and 0xFF. */ + +} SDIO_InitTypeDef; + +typedef struct +{ + uint32_t SDIO_Argument; /*!< Specifies the SDIO command argument which is sent + to a card as part of a command message. If a command + contains an argument, it must be loaded into this register + before writing the command to the command register */ + + uint32_t SDIO_CmdIndex; /*!< Specifies the SDIO command index. It must be lower than 0x40. */ + + uint32_t SDIO_Response; /*!< Specifies the SDIO response type. + This parameter can be a value of @ref SDIO_Response_Type */ + + uint32_t SDIO_Wait; /*!< Specifies whether SDIO wait-for-interrupt request is enabled or disabled. + This parameter can be a value of @ref SDIO_Wait_Interrupt_State */ + + uint32_t SDIO_CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM) + is enabled or disabled. + This parameter can be a value of @ref SDIO_CPSM_State */ +} SDIO_CmdInitTypeDef; + +typedef struct +{ + uint32_t SDIO_DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */ + + uint32_t SDIO_DataLength; /*!< Specifies the number of data bytes to be transferred. */ + + uint32_t SDIO_DataBlockSize; /*!< Specifies the data block size for block transfer. + This parameter can be a value of @ref SDIO_Data_Block_Size */ + + uint32_t SDIO_TransferDir; /*!< Specifies the data transfer direction, whether the transfer + is a read or write. + This parameter can be a value of @ref SDIO_Transfer_Direction */ + + uint32_t SDIO_TransferMode; /*!< Specifies whether data transfer is in stream or block mode. + This parameter can be a value of @ref SDIO_Transfer_Type */ + + uint32_t SDIO_DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM) + is enabled or disabled. + This parameter can be a value of @ref SDIO_DPSM_State */ +} SDIO_DataInitTypeDef; + +/** + * @} + */ + +/** @defgroup SDIO_Exported_Constants + * @{ + */ + +/** @defgroup SDIO_Clock_Edge + * @{ + */ + +#define SDIO_ClockEdge_Rising ((uint32_t)0x00000000) +#define SDIO_ClockEdge_Falling ((uint32_t)0x00002000) +#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || \ + ((EDGE) == SDIO_ClockEdge_Falling)) +/** + * @} + */ + +/** @defgroup SDIO_Clock_Bypass + * @{ + */ + +#define SDIO_ClockBypass_Disable ((uint32_t)0x00000000) +#define SDIO_ClockBypass_Enable ((uint32_t)0x00000400) +#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || \ + ((BYPASS) == SDIO_ClockBypass_Enable)) +/** + * @} + */ + +/** @defgroup SDIO_Clock_Power_Save + * @{ + */ + +#define SDIO_ClockPowerSave_Disable ((uint32_t)0x00000000) +#define SDIO_ClockPowerSave_Enable ((uint32_t)0x00000200) +#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || \ + ((SAVE) == SDIO_ClockPowerSave_Enable)) +/** + * @} + */ + +/** @defgroup SDIO_Bus_Wide + * @{ + */ + +#define SDIO_BusWide_1b ((uint32_t)0x00000000) +#define SDIO_BusWide_4b ((uint32_t)0x00000800) +#define SDIO_BusWide_8b ((uint32_t)0x00001000) +#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \ + ((WIDE) == SDIO_BusWide_8b)) + +/** + * @} + */ + +/** @defgroup SDIO_Hardware_Flow_Control + * @{ + */ + +#define SDIO_HardwareFlowControl_Disable ((uint32_t)0x00000000) +#define SDIO_HardwareFlowControl_Enable ((uint32_t)0x00004000) +#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \ + ((CONTROL) == SDIO_HardwareFlowControl_Enable)) +/** + * @} + */ + +/** @defgroup SDIO_Power_State + * @{ + */ + +#define SDIO_PowerState_OFF ((uint32_t)0x00000000) +#define SDIO_PowerState_ON ((uint32_t)0x00000003) +#define IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON)) +/** + * @} + */ + + +/** @defgroup SDIO_Interrupt_soucres + * @{ + */ + +#define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001) +#define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002) +#define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004) +#define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008) +#define SDIO_IT_TXUNDERR ((uint32_t)0x00000010) +#define SDIO_IT_RXOVERR ((uint32_t)0x00000020) +#define SDIO_IT_CMDREND ((uint32_t)0x00000040) +#define SDIO_IT_CMDSENT ((uint32_t)0x00000080) +#define SDIO_IT_DATAEND ((uint32_t)0x00000100) +#define SDIO_IT_STBITERR ((uint32_t)0x00000200) +#define SDIO_IT_DBCKEND ((uint32_t)0x00000400) +#define SDIO_IT_CMDACT ((uint32_t)0x00000800) +#define SDIO_IT_TXACT ((uint32_t)0x00001000) +#define SDIO_IT_RXACT ((uint32_t)0x00002000) +#define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000) +#define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000) +#define SDIO_IT_TXFIFOF ((uint32_t)0x00010000) +#define SDIO_IT_RXFIFOF ((uint32_t)0x00020000) +#define SDIO_IT_TXFIFOE ((uint32_t)0x00040000) +#define SDIO_IT_RXFIFOE ((uint32_t)0x00080000) +#define SDIO_IT_TXDAVL ((uint32_t)0x00100000) +#define SDIO_IT_RXDAVL ((uint32_t)0x00200000) +#define SDIO_IT_SDIOIT ((uint32_t)0x00400000) +#define SDIO_IT_CEATAEND ((uint32_t)0x00800000) +#define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00)) +/** + * @} + */ + +/** @defgroup SDIO_Command_Index + * @{ + */ + +#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40) +/** + * @} + */ + +/** @defgroup SDIO_Response_Type + * @{ + */ + +#define SDIO_Response_No ((uint32_t)0x00000000) +#define SDIO_Response_Short ((uint32_t)0x00000040) +#define SDIO_Response_Long ((uint32_t)0x000000C0) +#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \ + ((RESPONSE) == SDIO_Response_Short) || \ + ((RESPONSE) == SDIO_Response_Long)) +/** + * @} + */ + +/** @defgroup SDIO_Wait_Interrupt_State + * @{ + */ + +#define SDIO_Wait_No ((uint32_t)0x00000000) /*!< SDIO No Wait, TimeOut is enabled */ +#define SDIO_Wait_IT ((uint32_t)0x00000100) /*!< SDIO Wait Interrupt Request */ +#define SDIO_Wait_Pend ((uint32_t)0x00000200) /*!< SDIO Wait End of transfer */ +#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \ + ((WAIT) == SDIO_Wait_Pend)) +/** + * @} + */ + +/** @defgroup SDIO_CPSM_State + * @{ + */ + +#define SDIO_CPSM_Disable ((uint32_t)0x00000000) +#define SDIO_CPSM_Enable ((uint32_t)0x00000400) +#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable)) +/** + * @} + */ + +/** @defgroup SDIO_Response_Registers + * @{ + */ + +#define SDIO_RESP1 ((uint32_t)0x00000000) +#define SDIO_RESP2 ((uint32_t)0x00000004) +#define SDIO_RESP3 ((uint32_t)0x00000008) +#define SDIO_RESP4 ((uint32_t)0x0000000C) +#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \ + ((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4)) +/** + * @} + */ + +/** @defgroup SDIO_Data_Length + * @{ + */ + +#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF) +/** + * @} + */ + +/** @defgroup SDIO_Data_Block_Size + * @{ + */ + +#define SDIO_DataBlockSize_1b ((uint32_t)0x00000000) +#define SDIO_DataBlockSize_2b ((uint32_t)0x00000010) +#define SDIO_DataBlockSize_4b ((uint32_t)0x00000020) +#define SDIO_DataBlockSize_8b ((uint32_t)0x00000030) +#define SDIO_DataBlockSize_16b ((uint32_t)0x00000040) +#define SDIO_DataBlockSize_32b ((uint32_t)0x00000050) +#define SDIO_DataBlockSize_64b ((uint32_t)0x00000060) +#define SDIO_DataBlockSize_128b ((uint32_t)0x00000070) +#define SDIO_DataBlockSize_256b ((uint32_t)0x00000080) +#define SDIO_DataBlockSize_512b ((uint32_t)0x00000090) +#define SDIO_DataBlockSize_1024b ((uint32_t)0x000000A0) +#define SDIO_DataBlockSize_2048b ((uint32_t)0x000000B0) +#define SDIO_DataBlockSize_4096b ((uint32_t)0x000000C0) +#define SDIO_DataBlockSize_8192b ((uint32_t)0x000000D0) +#define SDIO_DataBlockSize_16384b ((uint32_t)0x000000E0) +#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || \ + ((SIZE) == SDIO_DataBlockSize_2b) || \ + ((SIZE) == SDIO_DataBlockSize_4b) || \ + ((SIZE) == SDIO_DataBlockSize_8b) || \ + ((SIZE) == SDIO_DataBlockSize_16b) || \ + ((SIZE) == SDIO_DataBlockSize_32b) || \ + ((SIZE) == SDIO_DataBlockSize_64b) || \ + ((SIZE) == SDIO_DataBlockSize_128b) || \ + ((SIZE) == SDIO_DataBlockSize_256b) || \ + ((SIZE) == SDIO_DataBlockSize_512b) || \ + ((SIZE) == SDIO_DataBlockSize_1024b) || \ + ((SIZE) == SDIO_DataBlockSize_2048b) || \ + ((SIZE) == SDIO_DataBlockSize_4096b) || \ + ((SIZE) == SDIO_DataBlockSize_8192b) || \ + ((SIZE) == SDIO_DataBlockSize_16384b)) +/** + * @} + */ + +/** @defgroup SDIO_Transfer_Direction + * @{ + */ + +#define SDIO_TransferDir_ToCard ((uint32_t)0x00000000) +#define SDIO_TransferDir_ToSDIO ((uint32_t)0x00000002) +#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \ + ((DIR) == SDIO_TransferDir_ToSDIO)) +/** + * @} + */ + +/** @defgroup SDIO_Transfer_Type + * @{ + */ + +#define SDIO_TransferMode_Block ((uint32_t)0x00000000) +#define SDIO_TransferMode_Stream ((uint32_t)0x00000004) +#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || \ + ((MODE) == SDIO_TransferMode_Block)) +/** + * @} + */ + +/** @defgroup SDIO_DPSM_State + * @{ + */ + +#define SDIO_DPSM_Disable ((uint32_t)0x00000000) +#define SDIO_DPSM_Enable ((uint32_t)0x00000001) +#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable)) +/** + * @} + */ + +/** @defgroup SDIO_Flags + * @{ + */ + +#define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001) +#define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002) +#define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004) +#define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008) +#define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010) +#define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020) +#define SDIO_FLAG_CMDREND ((uint32_t)0x00000040) +#define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080) +#define SDIO_FLAG_DATAEND ((uint32_t)0x00000100) +#define SDIO_FLAG_STBITERR ((uint32_t)0x00000200) +#define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400) +#define SDIO_FLAG_CMDACT ((uint32_t)0x00000800) +#define SDIO_FLAG_TXACT ((uint32_t)0x00001000) +#define SDIO_FLAG_RXACT ((uint32_t)0x00002000) +#define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000) +#define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000) +#define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000) +#define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000) +#define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000) +#define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000) +#define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000) +#define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000) +#define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000) +#define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000) +#define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || \ + ((FLAG) == SDIO_FLAG_DCRCFAIL) || \ + ((FLAG) == SDIO_FLAG_CTIMEOUT) || \ + ((FLAG) == SDIO_FLAG_DTIMEOUT) || \ + ((FLAG) == SDIO_FLAG_TXUNDERR) || \ + ((FLAG) == SDIO_FLAG_RXOVERR) || \ + ((FLAG) == SDIO_FLAG_CMDREND) || \ + ((FLAG) == SDIO_FLAG_CMDSENT) || \ + ((FLAG) == SDIO_FLAG_DATAEND) || \ + ((FLAG) == SDIO_FLAG_STBITERR) || \ + ((FLAG) == SDIO_FLAG_DBCKEND) || \ + ((FLAG) == SDIO_FLAG_CMDACT) || \ + ((FLAG) == SDIO_FLAG_TXACT) || \ + ((FLAG) == SDIO_FLAG_RXACT) || \ + ((FLAG) == SDIO_FLAG_TXFIFOHE) || \ + ((FLAG) == SDIO_FLAG_RXFIFOHF) || \ + ((FLAG) == SDIO_FLAG_TXFIFOF) || \ + ((FLAG) == SDIO_FLAG_RXFIFOF) || \ + ((FLAG) == SDIO_FLAG_TXFIFOE) || \ + ((FLAG) == SDIO_FLAG_RXFIFOE) || \ + ((FLAG) == SDIO_FLAG_TXDAVL) || \ + ((FLAG) == SDIO_FLAG_RXDAVL) || \ + ((FLAG) == SDIO_FLAG_SDIOIT) || \ + ((FLAG) == SDIO_FLAG_CEATAEND)) + +#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00)) + +#define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) || \ + ((IT) == SDIO_IT_DCRCFAIL) || \ + ((IT) == SDIO_IT_CTIMEOUT) || \ + ((IT) == SDIO_IT_DTIMEOUT) || \ + ((IT) == SDIO_IT_TXUNDERR) || \ + ((IT) == SDIO_IT_RXOVERR) || \ + ((IT) == SDIO_IT_CMDREND) || \ + ((IT) == SDIO_IT_CMDSENT) || \ + ((IT) == SDIO_IT_DATAEND) || \ + ((IT) == SDIO_IT_STBITERR) || \ + ((IT) == SDIO_IT_DBCKEND) || \ + ((IT) == SDIO_IT_CMDACT) || \ + ((IT) == SDIO_IT_TXACT) || \ + ((IT) == SDIO_IT_RXACT) || \ + ((IT) == SDIO_IT_TXFIFOHE) || \ + ((IT) == SDIO_IT_RXFIFOHF) || \ + ((IT) == SDIO_IT_TXFIFOF) || \ + ((IT) == SDIO_IT_RXFIFOF) || \ + ((IT) == SDIO_IT_TXFIFOE) || \ + ((IT) == SDIO_IT_RXFIFOE) || \ + ((IT) == SDIO_IT_TXDAVL) || \ + ((IT) == SDIO_IT_RXDAVL) || \ + ((IT) == SDIO_IT_SDIOIT) || \ + ((IT) == SDIO_IT_CEATAEND)) + +#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00)) + +/** + * @} + */ + +/** @defgroup SDIO_Read_Wait_Mode + * @{ + */ + +#define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000001) +#define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000000) +#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \ + ((MODE) == SDIO_ReadWaitMode_DATA2)) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup SDIO_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup SDIO_Exported_Functions + * @{ + */ + +void SDIO_DeInit(void); +void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct); +void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct); +void SDIO_ClockCmd(FunctionalState NewState); +void SDIO_SetPowerState(uint32_t SDIO_PowerState); +uint32_t SDIO_GetPowerState(void); +void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState); +void SDIO_DMACmd(FunctionalState NewState); +void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct); +void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct); +uint8_t SDIO_GetCommandResponse(void); +uint32_t SDIO_GetResponse(uint32_t SDIO_RESP); +void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct); +void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct); +uint32_t SDIO_GetDataCounter(void); +uint32_t SDIO_ReadData(void); +void SDIO_WriteData(uint32_t Data); +uint32_t SDIO_GetFIFOCount(void); +void SDIO_StartSDIOReadWait(FunctionalState NewState); +void SDIO_StopSDIOReadWait(FunctionalState NewState); +void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode); +void SDIO_SetSDIOOperation(FunctionalState NewState); +void SDIO_SendSDIOSuspendCmd(FunctionalState NewState); +void SDIO_CommandCompletionCmd(FunctionalState NewState); +void SDIO_CEATAITCmd(FunctionalState NewState); +void SDIO_SendCEATACmd(FunctionalState NewState); +FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG); +void SDIO_ClearFlag(uint32_t SDIO_FLAG); +ITStatus SDIO_GetITStatus(uint32_t SDIO_IT); +void SDIO_ClearITPendingBit(uint32_t SDIO_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_SDIO_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32f10x/stm32f10x_spi.h b/example/libs_stm/inc/stm32f10x/stm32f10x_spi.h new file mode 100644 index 0000000..920c826 --- /dev/null +++ b/example/libs_stm/inc/stm32f10x/stm32f10x_spi.h @@ -0,0 +1,490 @@ +/** + ****************************************************************************** + * @file stm32f10x_spi.h + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file contains all the functions prototypes for the SPI firmware + * library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_SPI_H +#define __STM32F10x_SPI_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup SPI + * @{ + */ + +/** @defgroup SPI_Exported_Types + * @{ + */ + +/** + * @brief SPI Init structure definition + */ + +typedef struct +{ + uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode. + This parameter can be a value of @ref SPI_data_direction */ + + uint16_t SPI_Mode; /*!< Specifies the SPI operating mode. + This parameter can be a value of @ref SPI_mode */ + + uint16_t SPI_DataSize; /*!< Specifies the SPI data size. + This parameter can be a value of @ref SPI_data_size */ + + uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state. + This parameter can be a value of @ref SPI_Clock_Polarity */ + + uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture. + This parameter can be a value of @ref SPI_Clock_Phase */ + + uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by + hardware (NSS pin) or by software using the SSI bit. + This parameter can be a value of @ref SPI_Slave_Select_management */ + + uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be + used to configure the transmit and receive SCK clock. + This parameter can be a value of @ref SPI_BaudRate_Prescaler. + @note The communication clock is derived from the master + clock. The slave clock does not need to be set. */ + + uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. + This parameter can be a value of @ref SPI_MSB_LSB_transmission */ + + uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */ +}SPI_InitTypeDef; + +/** + * @brief I2S Init structure definition + */ + +typedef struct +{ + + uint16_t I2S_Mode; /*!< Specifies the I2S operating mode. + This parameter can be a value of @ref I2S_Mode */ + + uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication. + This parameter can be a value of @ref I2S_Standard */ + + uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication. + This parameter can be a value of @ref I2S_Data_Format */ + + uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. + This parameter can be a value of @ref I2S_MCLK_Output */ + + uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication. + This parameter can be a value of @ref I2S_Audio_Frequency */ + + uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock. + This parameter can be a value of @ref I2S_Clock_Polarity */ +}I2S_InitTypeDef; + +/** + * @} + */ + +/** @defgroup SPI_Exported_Constants + * @{ + */ + +#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \ + ((PERIPH) == SPI2) || \ + ((PERIPH) == SPI3)) + +#define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \ + ((PERIPH) == SPI3)) + +/** @defgroup SPI_data_direction + * @{ + */ + +#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) +#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) +#define SPI_Direction_1Line_Rx ((uint16_t)0x8000) +#define SPI_Direction_1Line_Tx ((uint16_t)0xC000) +#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \ + ((MODE) == SPI_Direction_2Lines_RxOnly) || \ + ((MODE) == SPI_Direction_1Line_Rx) || \ + ((MODE) == SPI_Direction_1Line_Tx)) +/** + * @} + */ + +/** @defgroup SPI_mode + * @{ + */ + +#define SPI_Mode_Master ((uint16_t)0x0104) +#define SPI_Mode_Slave ((uint16_t)0x0000) +#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \ + ((MODE) == SPI_Mode_Slave)) +/** + * @} + */ + +/** @defgroup SPI_data_size + * @{ + */ + +#define SPI_DataSize_16b ((uint16_t)0x0800) +#define SPI_DataSize_8b ((uint16_t)0x0000) +#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \ + ((DATASIZE) == SPI_DataSize_8b)) +/** + * @} + */ + +/** @defgroup SPI_Clock_Polarity + * @{ + */ + +#define SPI_CPOL_Low ((uint16_t)0x0000) +#define SPI_CPOL_High ((uint16_t)0x0002) +#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \ + ((CPOL) == SPI_CPOL_High)) +/** + * @} + */ + +/** @defgroup SPI_Clock_Phase + * @{ + */ + +#define SPI_CPHA_1Edge ((uint16_t)0x0000) +#define SPI_CPHA_2Edge ((uint16_t)0x0001) +#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \ + ((CPHA) == SPI_CPHA_2Edge)) +/** + * @} + */ + +/** @defgroup SPI_Slave_Select_management + * @{ + */ + +#define SPI_NSS_Soft ((uint16_t)0x0200) +#define SPI_NSS_Hard ((uint16_t)0x0000) +#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \ + ((NSS) == SPI_NSS_Hard)) +/** + * @} + */ + +/** @defgroup SPI_BaudRate_Prescaler + * @{ + */ + +#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) +#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) +#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) +#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) +#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) +#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) +#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) +#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) +#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_4) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_8) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_16) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_32) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_64) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_128) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_256)) +/** + * @} + */ + +/** @defgroup SPI_MSB_LSB_transmission + * @{ + */ + +#define SPI_FirstBit_MSB ((uint16_t)0x0000) +#define SPI_FirstBit_LSB ((uint16_t)0x0080) +#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \ + ((BIT) == SPI_FirstBit_LSB)) +/** + * @} + */ + +/** @defgroup I2S_Mode + * @{ + */ + +#define I2S_Mode_SlaveTx ((uint16_t)0x0000) +#define I2S_Mode_SlaveRx ((uint16_t)0x0100) +#define I2S_Mode_MasterTx ((uint16_t)0x0200) +#define I2S_Mode_MasterRx ((uint16_t)0x0300) +#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \ + ((MODE) == I2S_Mode_SlaveRx) || \ + ((MODE) == I2S_Mode_MasterTx) || \ + ((MODE) == I2S_Mode_MasterRx) ) +/** + * @} + */ + +/** @defgroup I2S_Standard + * @{ + */ + +#define I2S_Standard_Phillips ((uint16_t)0x0000) +#define I2S_Standard_MSB ((uint16_t)0x0010) +#define I2S_Standard_LSB ((uint16_t)0x0020) +#define I2S_Standard_PCMShort ((uint16_t)0x0030) +#define I2S_Standard_PCMLong ((uint16_t)0x00B0) +#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \ + ((STANDARD) == I2S_Standard_MSB) || \ + ((STANDARD) == I2S_Standard_LSB) || \ + ((STANDARD) == I2S_Standard_PCMShort) || \ + ((STANDARD) == I2S_Standard_PCMLong)) +/** + * @} + */ + +/** @defgroup I2S_Data_Format + * @{ + */ + +#define I2S_DataFormat_16b ((uint16_t)0x0000) +#define I2S_DataFormat_16bextended ((uint16_t)0x0001) +#define I2S_DataFormat_24b ((uint16_t)0x0003) +#define I2S_DataFormat_32b ((uint16_t)0x0005) +#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \ + ((FORMAT) == I2S_DataFormat_16bextended) || \ + ((FORMAT) == I2S_DataFormat_24b) || \ + ((FORMAT) == I2S_DataFormat_32b)) +/** + * @} + */ + +/** @defgroup I2S_MCLK_Output + * @{ + */ + +#define I2S_MCLKOutput_Enable ((uint16_t)0x0200) +#define I2S_MCLKOutput_Disable ((uint16_t)0x0000) +#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \ + ((OUTPUT) == I2S_MCLKOutput_Disable)) +/** + * @} + */ + +/** @defgroup I2S_Audio_Frequency + * @{ + */ + +#define I2S_AudioFreq_96k ((uint32_t)96000) +#define I2S_AudioFreq_48k ((uint32_t)48000) +#define I2S_AudioFreq_44k ((uint32_t)44100) +#define I2S_AudioFreq_32k ((uint32_t)32000) +#define I2S_AudioFreq_22k ((uint32_t)22050) +#define I2S_AudioFreq_16k ((uint32_t)16000) +#define I2S_AudioFreq_11k ((uint32_t)11025) +#define I2S_AudioFreq_8k ((uint32_t)8000) +#define I2S_AudioFreq_Default ((uint32_t)2) +#define IS_I2S_AUDIO_FREQ(FREQ) (((FREQ) == I2S_AudioFreq_96k) || \ + ((FREQ) == I2S_AudioFreq_48k) || \ + ((FREQ) == I2S_AudioFreq_44k) || \ + ((FREQ) == I2S_AudioFreq_32k) || \ + ((FREQ) == I2S_AudioFreq_22k) || \ + ((FREQ) == I2S_AudioFreq_16k) || \ + ((FREQ) == I2S_AudioFreq_11k) || \ + ((FREQ) == I2S_AudioFreq_8k) || \ + ((FREQ) == I2S_AudioFreq_Default)) +/** + * @} + */ + +/** @defgroup I2S_Clock_Polarity + * @{ + */ + +#define I2S_CPOL_Low ((uint16_t)0x0000) +#define I2S_CPOL_High ((uint16_t)0x0008) +#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \ + ((CPOL) == I2S_CPOL_High)) +/** + * @} + */ + +/** @defgroup SPI_I2S_DMA_transfer_requests + * @{ + */ + +#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) +#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) +#define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00)) +/** + * @} + */ + +/** @defgroup SPI_NSS_internal_software_mangement + * @{ + */ + +#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) +#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) +#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \ + ((INTERNAL) == SPI_NSSInternalSoft_Reset)) +/** + * @} + */ + +/** @defgroup SPI_CRC_Transmit_Receive + * @{ + */ + +#define SPI_CRC_Tx ((uint8_t)0x00) +#define SPI_CRC_Rx ((uint8_t)0x01) +#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx)) +/** + * @} + */ + +/** @defgroup SPI_direction_transmit_receive + * @{ + */ + +#define SPI_Direction_Rx ((uint16_t)0xBFFF) +#define SPI_Direction_Tx ((uint16_t)0x4000) +#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \ + ((DIRECTION) == SPI_Direction_Tx)) +/** + * @} + */ + +/** @defgroup SPI_I2S_interrupts_definition + * @{ + */ + +#define SPI_I2S_IT_TXE ((uint8_t)0x71) +#define SPI_I2S_IT_RXNE ((uint8_t)0x60) +#define SPI_I2S_IT_ERR ((uint8_t)0x50) +#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \ + ((IT) == SPI_I2S_IT_RXNE) || \ + ((IT) == SPI_I2S_IT_ERR)) +#define SPI_I2S_IT_OVR ((uint8_t)0x56) +#define SPI_IT_MODF ((uint8_t)0x55) +#define SPI_IT_CRCERR ((uint8_t)0x54) +#define I2S_IT_UDR ((uint8_t)0x53) +#define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR)) +#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \ + ((IT) == I2S_IT_UDR) || ((IT) == SPI_IT_CRCERR) || \ + ((IT) == SPI_IT_MODF) || ((IT) == SPI_I2S_IT_OVR)) +/** + * @} + */ + +/** @defgroup SPI_I2S_flags_definition + * @{ + */ + +#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) +#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002) +#define I2S_FLAG_CHSIDE ((uint16_t)0x0004) +#define I2S_FLAG_UDR ((uint16_t)0x0008) +#define SPI_FLAG_CRCERR ((uint16_t)0x0010) +#define SPI_FLAG_MODF ((uint16_t)0x0020) +#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) +#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) +#define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR)) +#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \ + ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \ + ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \ + ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)) +/** + * @} + */ + +/** @defgroup SPI_CRC_polynomial + * @{ + */ + +#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup SPI_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup SPI_Exported_Functions + * @{ + */ + +void SPI_I2S_DeInit(SPI_TypeDef* SPIx); +void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct); +void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct); +void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct); +void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct); +void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); +void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); +void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); +void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); +void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data); +uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx); +void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft); +void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState); +void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize); +void SPI_TransmitCRC(SPI_TypeDef* SPIx); +void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState); +uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC); +uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx); +void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction); +FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); +void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); +ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); +void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F10x_SPI_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32f10x/stm32f10x_tim.h b/example/libs_stm/inc/stm32f10x/stm32f10x_tim.h new file mode 100644 index 0000000..500c195 --- /dev/null +++ b/example/libs_stm/inc/stm32f10x/stm32f10x_tim.h @@ -0,0 +1,1133 @@ +/** + ****************************************************************************** + * @file stm32f10x_tim.h + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file contains all the functions prototypes for the TIM firmware + * library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_TIM_H +#define __STM32F10x_TIM_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup TIM + * @{ + */ + +/** @defgroup TIM_Exported_Types + * @{ + */ + +/** + * @brief TIM Time Base Init structure definition + * @note This sturcture is used with all TIMx except for TIM6 and TIM7. + */ + +typedef struct +{ + uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. + This parameter can be a number between 0x0000 and 0xFFFF */ + + uint16_t TIM_CounterMode; /*!< Specifies the counter mode. + This parameter can be a value of @ref TIM_Counter_Mode */ + + uint16_t TIM_Period; /*!< Specifies the period value to be loaded into the active + Auto-Reload Register at the next update event. + This parameter must be a number between 0x0000 and 0xFFFF. */ + + uint16_t TIM_ClockDivision; /*!< Specifies the clock division. + This parameter can be a value of @ref TIM_Clock_Division_CKD */ + + uint8_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter + reaches zero, an update event is generated and counting restarts + from the RCR value (N). + This means in PWM mode that (N+1) corresponds to: + - the number of PWM periods in edge-aligned mode + - the number of half PWM period in center-aligned mode + This parameter must be a number between 0x00 and 0xFF. + @note This parameter is valid only for TIM1 and TIM8. */ +} TIM_TimeBaseInitTypeDef; + +/** + * @brief TIM Output Compare Init structure definition + */ + +typedef struct +{ + uint16_t TIM_OCMode; /*!< Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state. + This parameter can be a value of @ref TIM_Output_Compare_state */ + + uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state. + This parameter can be a value of @ref TIM_Output_Compare_N_state + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between 0x0000 and 0xFFFF */ + + uint16_t TIM_OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint16_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for TIM1 and TIM8. */ +} TIM_OCInitTypeDef; + +/** + * @brief TIM Input Capture Init structure definition + */ + +typedef struct +{ + + uint16_t TIM_Channel; /*!< Specifies the TIM channel. + This parameter can be a value of @ref TIM_Channel */ + + uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint16_t TIM_ICSelection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint16_t TIM_ICFilter; /*!< Specifies the input capture filter. + This parameter can be a number between 0x0 and 0xF */ +} TIM_ICInitTypeDef; + +/** + * @brief BDTR structure definition + * @note This sturcture is used only with TIM1 and TIM8. + */ + +typedef struct +{ + + uint16_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode. + This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */ + + uint16_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state. + This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */ + + uint16_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters. + This parameter can be a value of @ref Lock_level */ + + uint16_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and the + switching-on of the outputs. + This parameter can be a number between 0x00 and 0xFF */ + + uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not. + This parameter can be a value of @ref Break_Input_enable_disable */ + + uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. + This parameter can be a value of @ref Break_Polarity */ + + uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. + This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ +} TIM_BDTRInitTypeDef; + +/** @defgroup TIM_Exported_constants + * @{ + */ + +#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM4) || \ + ((PERIPH) == TIM5) || \ + ((PERIPH) == TIM6) || \ + ((PERIPH) == TIM7) || \ + ((PERIPH) == TIM8) || \ + ((PERIPH) == TIM9) || \ + ((PERIPH) == TIM10)|| \ + ((PERIPH) == TIM11)|| \ + ((PERIPH) == TIM12)|| \ + ((PERIPH) == TIM13)|| \ + ((PERIPH) == TIM14)|| \ + ((PERIPH) == TIM15)|| \ + ((PERIPH) == TIM16)|| \ + ((PERIPH) == TIM17)) + +/* LIST1: TIM 1 and 8 */ +#define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM8)) + +/* LIST2: TIM 1, 8, 15 16 and 17 */ +#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM8) || \ + ((PERIPH) == TIM15)|| \ + ((PERIPH) == TIM16)|| \ + ((PERIPH) == TIM17)) + +/* LIST3: TIM 1, 2, 3, 4, 5 and 8 */ +#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM4) || \ + ((PERIPH) == TIM5) || \ + ((PERIPH) == TIM8)) + +/* LIST4: TIM 1, 2, 3, 4, 5, 8, 15, 16 and 17 */ +#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM4) || \ + ((PERIPH) == TIM5) || \ + ((PERIPH) == TIM8) || \ + ((PERIPH) == TIM15)|| \ + ((PERIPH) == TIM16)|| \ + ((PERIPH) == TIM17)) + +/* LIST5: TIM 1, 2, 3, 4, 5, 8 and 15 */ +#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM4) || \ + ((PERIPH) == TIM5) || \ + ((PERIPH) == TIM8) || \ + ((PERIPH) == TIM15)) + +/* LIST6: TIM 1, 2, 3, 4, 5, 8, 9, 12 and 15 */ +#define IS_TIM_LIST6_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM4) || \ + ((PERIPH) == TIM5) || \ + ((PERIPH) == TIM8) || \ + ((PERIPH) == TIM9) || \ + ((PERIPH) == TIM12)|| \ + ((PERIPH) == TIM15)) + +/* LIST7: TIM 1, 2, 3, 4, 5, 6, 7, 8, 9, 12 and 15 */ +#define IS_TIM_LIST7_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM4) || \ + ((PERIPH) == TIM5) || \ + ((PERIPH) == TIM6) || \ + ((PERIPH) == TIM7) || \ + ((PERIPH) == TIM8) || \ + ((PERIPH) == TIM9) || \ + ((PERIPH) == TIM12)|| \ + ((PERIPH) == TIM15)) + +/* LIST8: TIM 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13, 14, 15, 16 and 17 */ +#define IS_TIM_LIST8_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM4) || \ + ((PERIPH) == TIM5) || \ + ((PERIPH) == TIM8) || \ + ((PERIPH) == TIM9) || \ + ((PERIPH) == TIM10)|| \ + ((PERIPH) == TIM11)|| \ + ((PERIPH) == TIM12)|| \ + ((PERIPH) == TIM13)|| \ + ((PERIPH) == TIM14)|| \ + ((PERIPH) == TIM15)|| \ + ((PERIPH) == TIM16)|| \ + ((PERIPH) == TIM17)) + +/* LIST9: TIM 1, 2, 3, 4, 5, 6, 7, 8, 15, 16, and 17 */ +#define IS_TIM_LIST9_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM4) || \ + ((PERIPH) == TIM5) || \ + ((PERIPH) == TIM6) || \ + ((PERIPH) == TIM7) || \ + ((PERIPH) == TIM8) || \ + ((PERIPH) == TIM15)|| \ + ((PERIPH) == TIM16)|| \ + ((PERIPH) == TIM17)) + +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_and_PWM_modes + * @{ + */ + +#define TIM_OCMode_Timing ((uint16_t)0x0000) +#define TIM_OCMode_Active ((uint16_t)0x0010) +#define TIM_OCMode_Inactive ((uint16_t)0x0020) +#define TIM_OCMode_Toggle ((uint16_t)0x0030) +#define TIM_OCMode_PWM1 ((uint16_t)0x0060) +#define TIM_OCMode_PWM2 ((uint16_t)0x0070) +#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \ + ((MODE) == TIM_OCMode_Active) || \ + ((MODE) == TIM_OCMode_Inactive) || \ + ((MODE) == TIM_OCMode_Toggle)|| \ + ((MODE) == TIM_OCMode_PWM1) || \ + ((MODE) == TIM_OCMode_PWM2)) +#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \ + ((MODE) == TIM_OCMode_Active) || \ + ((MODE) == TIM_OCMode_Inactive) || \ + ((MODE) == TIM_OCMode_Toggle)|| \ + ((MODE) == TIM_OCMode_PWM1) || \ + ((MODE) == TIM_OCMode_PWM2) || \ + ((MODE) == TIM_ForcedAction_Active) || \ + ((MODE) == TIM_ForcedAction_InActive)) +/** + * @} + */ + +/** @defgroup TIM_One_Pulse_Mode + * @{ + */ + +#define TIM_OPMode_Single ((uint16_t)0x0008) +#define TIM_OPMode_Repetitive ((uint16_t)0x0000) +#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \ + ((MODE) == TIM_OPMode_Repetitive)) +/** + * @} + */ + +/** @defgroup TIM_Channel + * @{ + */ + +#define TIM_Channel_1 ((uint16_t)0x0000) +#define TIM_Channel_2 ((uint16_t)0x0004) +#define TIM_Channel_3 ((uint16_t)0x0008) +#define TIM_Channel_4 ((uint16_t)0x000C) +#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ + ((CHANNEL) == TIM_Channel_2) || \ + ((CHANNEL) == TIM_Channel_3) || \ + ((CHANNEL) == TIM_Channel_4)) +#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ + ((CHANNEL) == TIM_Channel_2)) +#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ + ((CHANNEL) == TIM_Channel_2) || \ + ((CHANNEL) == TIM_Channel_3)) +/** + * @} + */ + +/** @defgroup TIM_Clock_Division_CKD + * @{ + */ + +#define TIM_CKD_DIV1 ((uint16_t)0x0000) +#define TIM_CKD_DIV2 ((uint16_t)0x0100) +#define TIM_CKD_DIV4 ((uint16_t)0x0200) +#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \ + ((DIV) == TIM_CKD_DIV2) || \ + ((DIV) == TIM_CKD_DIV4)) +/** + * @} + */ + +/** @defgroup TIM_Counter_Mode + * @{ + */ + +#define TIM_CounterMode_Up ((uint16_t)0x0000) +#define TIM_CounterMode_Down ((uint16_t)0x0010) +#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) +#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) +#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) +#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \ + ((MODE) == TIM_CounterMode_Down) || \ + ((MODE) == TIM_CounterMode_CenterAligned1) || \ + ((MODE) == TIM_CounterMode_CenterAligned2) || \ + ((MODE) == TIM_CounterMode_CenterAligned3)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Polarity + * @{ + */ + +#define TIM_OCPolarity_High ((uint16_t)0x0000) +#define TIM_OCPolarity_Low ((uint16_t)0x0002) +#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \ + ((POLARITY) == TIM_OCPolarity_Low)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_Polarity + * @{ + */ + +#define TIM_OCNPolarity_High ((uint16_t)0x0000) +#define TIM_OCNPolarity_Low ((uint16_t)0x0008) +#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \ + ((POLARITY) == TIM_OCNPolarity_Low)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_state + * @{ + */ + +#define TIM_OutputState_Disable ((uint16_t)0x0000) +#define TIM_OutputState_Enable ((uint16_t)0x0001) +#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \ + ((STATE) == TIM_OutputState_Enable)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_state + * @{ + */ + +#define TIM_OutputNState_Disable ((uint16_t)0x0000) +#define TIM_OutputNState_Enable ((uint16_t)0x0004) +#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \ + ((STATE) == TIM_OutputNState_Enable)) +/** + * @} + */ + +/** @defgroup TIM_Capture_Compare_state + * @{ + */ + +#define TIM_CCx_Enable ((uint16_t)0x0001) +#define TIM_CCx_Disable ((uint16_t)0x0000) +#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \ + ((CCX) == TIM_CCx_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Capture_Compare_N_state + * @{ + */ + +#define TIM_CCxN_Enable ((uint16_t)0x0004) +#define TIM_CCxN_Disable ((uint16_t)0x0000) +#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \ + ((CCXN) == TIM_CCxN_Disable)) +/** + * @} + */ + +/** @defgroup Break_Input_enable_disable + * @{ + */ + +#define TIM_Break_Enable ((uint16_t)0x1000) +#define TIM_Break_Disable ((uint16_t)0x0000) +#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \ + ((STATE) == TIM_Break_Disable)) +/** + * @} + */ + +/** @defgroup Break_Polarity + * @{ + */ + +#define TIM_BreakPolarity_Low ((uint16_t)0x0000) +#define TIM_BreakPolarity_High ((uint16_t)0x2000) +#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \ + ((POLARITY) == TIM_BreakPolarity_High)) +/** + * @} + */ + +/** @defgroup TIM_AOE_Bit_Set_Reset + * @{ + */ + +#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) +#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) +#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \ + ((STATE) == TIM_AutomaticOutput_Disable)) +/** + * @} + */ + +/** @defgroup Lock_level + * @{ + */ + +#define TIM_LOCKLevel_OFF ((uint16_t)0x0000) +#define TIM_LOCKLevel_1 ((uint16_t)0x0100) +#define TIM_LOCKLevel_2 ((uint16_t)0x0200) +#define TIM_LOCKLevel_3 ((uint16_t)0x0300) +#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \ + ((LEVEL) == TIM_LOCKLevel_1) || \ + ((LEVEL) == TIM_LOCKLevel_2) || \ + ((LEVEL) == TIM_LOCKLevel_3)) +/** + * @} + */ + +/** @defgroup OSSI_Off_State_Selection_for_Idle_mode_state + * @{ + */ + +#define TIM_OSSIState_Enable ((uint16_t)0x0400) +#define TIM_OSSIState_Disable ((uint16_t)0x0000) +#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \ + ((STATE) == TIM_OSSIState_Disable)) +/** + * @} + */ + +/** @defgroup OSSR_Off_State_Selection_for_Run_mode_state + * @{ + */ + +#define TIM_OSSRState_Enable ((uint16_t)0x0800) +#define TIM_OSSRState_Disable ((uint16_t)0x0000) +#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \ + ((STATE) == TIM_OSSRState_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Idle_State + * @{ + */ + +#define TIM_OCIdleState_Set ((uint16_t)0x0100) +#define TIM_OCIdleState_Reset ((uint16_t)0x0000) +#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \ + ((STATE) == TIM_OCIdleState_Reset)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_Idle_State + * @{ + */ + +#define TIM_OCNIdleState_Set ((uint16_t)0x0200) +#define TIM_OCNIdleState_Reset ((uint16_t)0x0000) +#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \ + ((STATE) == TIM_OCNIdleState_Reset)) +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Polarity + * @{ + */ + +#define TIM_ICPolarity_Rising ((uint16_t)0x0000) +#define TIM_ICPolarity_Falling ((uint16_t)0x0002) +#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \ + ((POLARITY) == TIM_ICPolarity_Falling)) +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Selection + * @{ + */ + +#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be + connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be + connected to IC2, IC1, IC4 or IC3, respectively. */ +#define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ +#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \ + ((SELECTION) == TIM_ICSelection_IndirectTI) || \ + ((SELECTION) == TIM_ICSelection_TRC)) +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Prescaler + * @{ + */ + +#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */ +#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */ +#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */ +#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */ +#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \ + ((PRESCALER) == TIM_ICPSC_DIV2) || \ + ((PRESCALER) == TIM_ICPSC_DIV4) || \ + ((PRESCALER) == TIM_ICPSC_DIV8)) +/** + * @} + */ + +/** @defgroup TIM_interrupt_sources + * @{ + */ + +#define TIM_IT_Update ((uint16_t)0x0001) +#define TIM_IT_CC1 ((uint16_t)0x0002) +#define TIM_IT_CC2 ((uint16_t)0x0004) +#define TIM_IT_CC3 ((uint16_t)0x0008) +#define TIM_IT_CC4 ((uint16_t)0x0010) +#define TIM_IT_COM ((uint16_t)0x0020) +#define TIM_IT_Trigger ((uint16_t)0x0040) +#define TIM_IT_Break ((uint16_t)0x0080) +#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000)) + +#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \ + ((IT) == TIM_IT_CC1) || \ + ((IT) == TIM_IT_CC2) || \ + ((IT) == TIM_IT_CC3) || \ + ((IT) == TIM_IT_CC4) || \ + ((IT) == TIM_IT_COM) || \ + ((IT) == TIM_IT_Trigger) || \ + ((IT) == TIM_IT_Break)) +/** + * @} + */ + +/** @defgroup TIM_DMA_Base_address + * @{ + */ + +#define TIM_DMABase_CR1 ((uint16_t)0x0000) +#define TIM_DMABase_CR2 ((uint16_t)0x0001) +#define TIM_DMABase_SMCR ((uint16_t)0x0002) +#define TIM_DMABase_DIER ((uint16_t)0x0003) +#define TIM_DMABase_SR ((uint16_t)0x0004) +#define TIM_DMABase_EGR ((uint16_t)0x0005) +#define TIM_DMABase_CCMR1 ((uint16_t)0x0006) +#define TIM_DMABase_CCMR2 ((uint16_t)0x0007) +#define TIM_DMABase_CCER ((uint16_t)0x0008) +#define TIM_DMABase_CNT ((uint16_t)0x0009) +#define TIM_DMABase_PSC ((uint16_t)0x000A) +#define TIM_DMABase_ARR ((uint16_t)0x000B) +#define TIM_DMABase_RCR ((uint16_t)0x000C) +#define TIM_DMABase_CCR1 ((uint16_t)0x000D) +#define TIM_DMABase_CCR2 ((uint16_t)0x000E) +#define TIM_DMABase_CCR3 ((uint16_t)0x000F) +#define TIM_DMABase_CCR4 ((uint16_t)0x0010) +#define TIM_DMABase_BDTR ((uint16_t)0x0011) +#define TIM_DMABase_DCR ((uint16_t)0x0012) +#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \ + ((BASE) == TIM_DMABase_CR2) || \ + ((BASE) == TIM_DMABase_SMCR) || \ + ((BASE) == TIM_DMABase_DIER) || \ + ((BASE) == TIM_DMABase_SR) || \ + ((BASE) == TIM_DMABase_EGR) || \ + ((BASE) == TIM_DMABase_CCMR1) || \ + ((BASE) == TIM_DMABase_CCMR2) || \ + ((BASE) == TIM_DMABase_CCER) || \ + ((BASE) == TIM_DMABase_CNT) || \ + ((BASE) == TIM_DMABase_PSC) || \ + ((BASE) == TIM_DMABase_ARR) || \ + ((BASE) == TIM_DMABase_RCR) || \ + ((BASE) == TIM_DMABase_CCR1) || \ + ((BASE) == TIM_DMABase_CCR2) || \ + ((BASE) == TIM_DMABase_CCR3) || \ + ((BASE) == TIM_DMABase_CCR4) || \ + ((BASE) == TIM_DMABase_BDTR) || \ + ((BASE) == TIM_DMABase_DCR)) +/** + * @} + */ + +/** @defgroup TIM_DMA_Burst_Length + * @{ + */ + +#define TIM_DMABurstLength_1Byte ((uint16_t)0x0000) +#define TIM_DMABurstLength_2Bytes ((uint16_t)0x0100) +#define TIM_DMABurstLength_3Bytes ((uint16_t)0x0200) +#define TIM_DMABurstLength_4Bytes ((uint16_t)0x0300) +#define TIM_DMABurstLength_5Bytes ((uint16_t)0x0400) +#define TIM_DMABurstLength_6Bytes ((uint16_t)0x0500) +#define TIM_DMABurstLength_7Bytes ((uint16_t)0x0600) +#define TIM_DMABurstLength_8Bytes ((uint16_t)0x0700) +#define TIM_DMABurstLength_9Bytes ((uint16_t)0x0800) +#define TIM_DMABurstLength_10Bytes ((uint16_t)0x0900) +#define TIM_DMABurstLength_11Bytes ((uint16_t)0x0A00) +#define TIM_DMABurstLength_12Bytes ((uint16_t)0x0B00) +#define TIM_DMABurstLength_13Bytes ((uint16_t)0x0C00) +#define TIM_DMABurstLength_14Bytes ((uint16_t)0x0D00) +#define TIM_DMABurstLength_15Bytes ((uint16_t)0x0E00) +#define TIM_DMABurstLength_16Bytes ((uint16_t)0x0F00) +#define TIM_DMABurstLength_17Bytes ((uint16_t)0x1000) +#define TIM_DMABurstLength_18Bytes ((uint16_t)0x1100) +#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Byte) || \ + ((LENGTH) == TIM_DMABurstLength_2Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_3Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_4Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_5Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_6Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_7Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_8Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_9Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_10Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_11Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_12Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_13Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_14Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_15Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_16Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_17Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_18Bytes)) +/** + * @} + */ + +/** @defgroup TIM_DMA_sources + * @{ + */ + +#define TIM_DMA_Update ((uint16_t)0x0100) +#define TIM_DMA_CC1 ((uint16_t)0x0200) +#define TIM_DMA_CC2 ((uint16_t)0x0400) +#define TIM_DMA_CC3 ((uint16_t)0x0800) +#define TIM_DMA_CC4 ((uint16_t)0x1000) +#define TIM_DMA_COM ((uint16_t)0x2000) +#define TIM_DMA_Trigger ((uint16_t)0x4000) +#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000)) + +/** + * @} + */ + +/** @defgroup TIM_External_Trigger_Prescaler + * @{ + */ + +#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) +#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) +#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) +#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) +#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \ + ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \ + ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \ + ((PRESCALER) == TIM_ExtTRGPSC_DIV8)) +/** + * @} + */ + +/** @defgroup TIM_Internal_Trigger_Selection + * @{ + */ + +#define TIM_TS_ITR0 ((uint16_t)0x0000) +#define TIM_TS_ITR1 ((uint16_t)0x0010) +#define TIM_TS_ITR2 ((uint16_t)0x0020) +#define TIM_TS_ITR3 ((uint16_t)0x0030) +#define TIM_TS_TI1F_ED ((uint16_t)0x0040) +#define TIM_TS_TI1FP1 ((uint16_t)0x0050) +#define TIM_TS_TI2FP2 ((uint16_t)0x0060) +#define TIM_TS_ETRF ((uint16_t)0x0070) +#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ + ((SELECTION) == TIM_TS_ITR1) || \ + ((SELECTION) == TIM_TS_ITR2) || \ + ((SELECTION) == TIM_TS_ITR3) || \ + ((SELECTION) == TIM_TS_TI1F_ED) || \ + ((SELECTION) == TIM_TS_TI1FP1) || \ + ((SELECTION) == TIM_TS_TI2FP2) || \ + ((SELECTION) == TIM_TS_ETRF)) +#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ + ((SELECTION) == TIM_TS_ITR1) || \ + ((SELECTION) == TIM_TS_ITR2) || \ + ((SELECTION) == TIM_TS_ITR3)) +/** + * @} + */ + +/** @defgroup TIM_TIx_External_Clock_Source + * @{ + */ + +#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) +#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) +#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) +#define IS_TIM_TIXCLK_SOURCE(SOURCE) (((SOURCE) == TIM_TIxExternalCLK1Source_TI1) || \ + ((SOURCE) == TIM_TIxExternalCLK1Source_TI2) || \ + ((SOURCE) == TIM_TIxExternalCLK1Source_TI1ED)) +/** + * @} + */ + +/** @defgroup TIM_External_Trigger_Polarity + * @{ + */ +#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) +#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) +#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \ + ((POLARITY) == TIM_ExtTRGPolarity_NonInverted)) +/** + * @} + */ + +/** @defgroup TIM_Prescaler_Reload_Mode + * @{ + */ + +#define TIM_PSCReloadMode_Update ((uint16_t)0x0000) +#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) +#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \ + ((RELOAD) == TIM_PSCReloadMode_Immediate)) +/** + * @} + */ + +/** @defgroup TIM_Forced_Action + * @{ + */ + +#define TIM_ForcedAction_Active ((uint16_t)0x0050) +#define TIM_ForcedAction_InActive ((uint16_t)0x0040) +#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \ + ((ACTION) == TIM_ForcedAction_InActive)) +/** + * @} + */ + +/** @defgroup TIM_Encoder_Mode + * @{ + */ + +#define TIM_EncoderMode_TI1 ((uint16_t)0x0001) +#define TIM_EncoderMode_TI2 ((uint16_t)0x0002) +#define TIM_EncoderMode_TI12 ((uint16_t)0x0003) +#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \ + ((MODE) == TIM_EncoderMode_TI2) || \ + ((MODE) == TIM_EncoderMode_TI12)) +/** + * @} + */ + + +/** @defgroup TIM_Event_Source + * @{ + */ + +#define TIM_EventSource_Update ((uint16_t)0x0001) +#define TIM_EventSource_CC1 ((uint16_t)0x0002) +#define TIM_EventSource_CC2 ((uint16_t)0x0004) +#define TIM_EventSource_CC3 ((uint16_t)0x0008) +#define TIM_EventSource_CC4 ((uint16_t)0x0010) +#define TIM_EventSource_COM ((uint16_t)0x0020) +#define TIM_EventSource_Trigger ((uint16_t)0x0040) +#define TIM_EventSource_Break ((uint16_t)0x0080) +#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000)) + +/** + * @} + */ + +/** @defgroup TIM_Update_Source + * @{ + */ + +#define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow + or the setting of UG bit, or an update generation + through the slave mode controller. */ +#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */ +#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \ + ((SOURCE) == TIM_UpdateSource_Regular)) +/** + * @} + */ + +/** @defgroup TIM_Ouput_Compare_Preload_State + * @{ + */ + +#define TIM_OCPreload_Enable ((uint16_t)0x0008) +#define TIM_OCPreload_Disable ((uint16_t)0x0000) +#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \ + ((STATE) == TIM_OCPreload_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Ouput_Compare_Fast_State + * @{ + */ + +#define TIM_OCFast_Enable ((uint16_t)0x0004) +#define TIM_OCFast_Disable ((uint16_t)0x0000) +#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \ + ((STATE) == TIM_OCFast_Disable)) + +/** + * @} + */ + +/** @defgroup TIM_Ouput_Compare_Clear_State + * @{ + */ + +#define TIM_OCClear_Enable ((uint16_t)0x0080) +#define TIM_OCClear_Disable ((uint16_t)0x0000) +#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \ + ((STATE) == TIM_OCClear_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Trigger_Output_Source + * @{ + */ + +#define TIM_TRGOSource_Reset ((uint16_t)0x0000) +#define TIM_TRGOSource_Enable ((uint16_t)0x0010) +#define TIM_TRGOSource_Update ((uint16_t)0x0020) +#define TIM_TRGOSource_OC1 ((uint16_t)0x0030) +#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) +#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) +#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) +#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) +#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \ + ((SOURCE) == TIM_TRGOSource_Enable) || \ + ((SOURCE) == TIM_TRGOSource_Update) || \ + ((SOURCE) == TIM_TRGOSource_OC1) || \ + ((SOURCE) == TIM_TRGOSource_OC1Ref) || \ + ((SOURCE) == TIM_TRGOSource_OC2Ref) || \ + ((SOURCE) == TIM_TRGOSource_OC3Ref) || \ + ((SOURCE) == TIM_TRGOSource_OC4Ref)) +/** + * @} + */ + +/** @defgroup TIM_Slave_Mode + * @{ + */ + +#define TIM_SlaveMode_Reset ((uint16_t)0x0004) +#define TIM_SlaveMode_Gated ((uint16_t)0x0005) +#define TIM_SlaveMode_Trigger ((uint16_t)0x0006) +#define TIM_SlaveMode_External1 ((uint16_t)0x0007) +#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \ + ((MODE) == TIM_SlaveMode_Gated) || \ + ((MODE) == TIM_SlaveMode_Trigger) || \ + ((MODE) == TIM_SlaveMode_External1)) +/** + * @} + */ + +/** @defgroup TIM_Master_Slave_Mode + * @{ + */ + +#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) +#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) +#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \ + ((STATE) == TIM_MasterSlaveMode_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Flags + * @{ + */ + +#define TIM_FLAG_Update ((uint16_t)0x0001) +#define TIM_FLAG_CC1 ((uint16_t)0x0002) +#define TIM_FLAG_CC2 ((uint16_t)0x0004) +#define TIM_FLAG_CC3 ((uint16_t)0x0008) +#define TIM_FLAG_CC4 ((uint16_t)0x0010) +#define TIM_FLAG_COM ((uint16_t)0x0020) +#define TIM_FLAG_Trigger ((uint16_t)0x0040) +#define TIM_FLAG_Break ((uint16_t)0x0080) +#define TIM_FLAG_CC1OF ((uint16_t)0x0200) +#define TIM_FLAG_CC2OF ((uint16_t)0x0400) +#define TIM_FLAG_CC3OF ((uint16_t)0x0800) +#define TIM_FLAG_CC4OF ((uint16_t)0x1000) +#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \ + ((FLAG) == TIM_FLAG_CC1) || \ + ((FLAG) == TIM_FLAG_CC2) || \ + ((FLAG) == TIM_FLAG_CC3) || \ + ((FLAG) == TIM_FLAG_CC4) || \ + ((FLAG) == TIM_FLAG_COM) || \ + ((FLAG) == TIM_FLAG_Trigger) || \ + ((FLAG) == TIM_FLAG_Break) || \ + ((FLAG) == TIM_FLAG_CC1OF) || \ + ((FLAG) == TIM_FLAG_CC2OF) || \ + ((FLAG) == TIM_FLAG_CC3OF) || \ + ((FLAG) == TIM_FLAG_CC4OF)) + + +#define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000)) +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Filer_Value + * @{ + */ + +#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) +/** + * @} + */ + +/** @defgroup TIM_External_Trigger_Filter + * @{ + */ + +#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup TIM_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions + * @{ + */ + +void TIM_DeInit(TIM_TypeDef* TIMx); +void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); +void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); +void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); +void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); +void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); +void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct); +void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct); +void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState); +void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource); +void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength); +void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState); +void TIM_InternalClockConfig(TIM_TypeDef* TIMx); +void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); +void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, + uint16_t TIM_ICPolarity, uint16_t ICFilter); +void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); +void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); +void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); +void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode); +void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode); +void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); +void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, + uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity); +void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx); +void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN); +void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode); +void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource); +void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode); +void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); +void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); +void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode); +void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter); +void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload); +void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1); +void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2); +void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3); +void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4); +void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); +void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD); +uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx); +uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx); +uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx); +uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx); +uint16_t TIM_GetCounter(TIM_TypeDef* TIMx); +uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx); +FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); +void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); +ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT); +void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F10x_TIM_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32f10x/stm32f10x_usart.h b/example/libs_stm/inc/stm32f10x/stm32f10x_usart.h new file mode 100644 index 0000000..b79855a --- /dev/null +++ b/example/libs_stm/inc/stm32f10x/stm32f10x_usart.h @@ -0,0 +1,411 @@ +/** + ****************************************************************************** + * @file stm32f10x_usart.h + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file contains all the functions prototypes for the USART + * firmware library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_USART_H +#define __STM32F10x_USART_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup USART + * @{ + */ + +/** @defgroup USART_Exported_Types + * @{ + */ + +/** + * @brief USART Init Structure definition + */ + +typedef struct +{ + uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate. + The baud rate is computed using the following formula: + - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate))) + - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */ + + uint16_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref USART_Word_Length */ + + uint16_t USART_StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref USART_Stop_Bits */ + + uint16_t USART_Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref USART_Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ + + uint16_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref USART_Mode */ + + uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled + or disabled. + This parameter can be a value of @ref USART_Hardware_Flow_Control */ +} USART_InitTypeDef; + +/** + * @brief USART Clock Init Structure definition + */ + +typedef struct +{ + + uint16_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled. + This parameter can be a value of @ref USART_Clock */ + + uint16_t USART_CPOL; /*!< Specifies the steady state value of the serial clock. + This parameter can be a value of @ref USART_Clock_Polarity */ + + uint16_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref USART_Clock_Phase */ + + uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted + data bit (MSB) has to be output on the SCLK pin in synchronous mode. + This parameter can be a value of @ref USART_Last_Bit */ +} USART_ClockInitTypeDef; + +/** + * @} + */ + +/** @defgroup USART_Exported_Constants + * @{ + */ + +#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \ + ((PERIPH) == USART2) || \ + ((PERIPH) == USART3) || \ + ((PERIPH) == UART4) || \ + ((PERIPH) == UART5)) + +#define IS_USART_123_PERIPH(PERIPH) (((PERIPH) == USART1) || \ + ((PERIPH) == USART2) || \ + ((PERIPH) == USART3)) + +#define IS_USART_1234_PERIPH(PERIPH) (((PERIPH) == USART1) || \ + ((PERIPH) == USART2) || \ + ((PERIPH) == USART3) || \ + ((PERIPH) == UART4)) +/** @defgroup USART_Word_Length + * @{ + */ + +#define USART_WordLength_8b ((uint16_t)0x0000) +#define USART_WordLength_9b ((uint16_t)0x1000) + +#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \ + ((LENGTH) == USART_WordLength_9b)) +/** + * @} + */ + +/** @defgroup USART_Stop_Bits + * @{ + */ + +#define USART_StopBits_1 ((uint16_t)0x0000) +#define USART_StopBits_0_5 ((uint16_t)0x1000) +#define USART_StopBits_2 ((uint16_t)0x2000) +#define USART_StopBits_1_5 ((uint16_t)0x3000) +#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \ + ((STOPBITS) == USART_StopBits_0_5) || \ + ((STOPBITS) == USART_StopBits_2) || \ + ((STOPBITS) == USART_StopBits_1_5)) +/** + * @} + */ + +/** @defgroup USART_Parity + * @{ + */ + +#define USART_Parity_No ((uint16_t)0x0000) +#define USART_Parity_Even ((uint16_t)0x0400) +#define USART_Parity_Odd ((uint16_t)0x0600) +#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \ + ((PARITY) == USART_Parity_Even) || \ + ((PARITY) == USART_Parity_Odd)) +/** + * @} + */ + +/** @defgroup USART_Mode + * @{ + */ + +#define USART_Mode_Rx ((uint16_t)0x0004) +#define USART_Mode_Tx ((uint16_t)0x0008) +#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00)) +/** + * @} + */ + +/** @defgroup USART_Hardware_Flow_Control + * @{ + */ +#define USART_HardwareFlowControl_None ((uint16_t)0x0000) +#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100) +#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200) +#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300) +#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\ + (((CONTROL) == USART_HardwareFlowControl_None) || \ + ((CONTROL) == USART_HardwareFlowControl_RTS) || \ + ((CONTROL) == USART_HardwareFlowControl_CTS) || \ + ((CONTROL) == USART_HardwareFlowControl_RTS_CTS)) +/** + * @} + */ + +/** @defgroup USART_Clock + * @{ + */ +#define USART_Clock_Disable ((uint16_t)0x0000) +#define USART_Clock_Enable ((uint16_t)0x0800) +#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \ + ((CLOCK) == USART_Clock_Enable)) +/** + * @} + */ + +/** @defgroup USART_Clock_Polarity + * @{ + */ + +#define USART_CPOL_Low ((uint16_t)0x0000) +#define USART_CPOL_High ((uint16_t)0x0400) +#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High)) + +/** + * @} + */ + +/** @defgroup USART_Clock_Phase + * @{ + */ + +#define USART_CPHA_1Edge ((uint16_t)0x0000) +#define USART_CPHA_2Edge ((uint16_t)0x0200) +#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge)) + +/** + * @} + */ + +/** @defgroup USART_Last_Bit + * @{ + */ + +#define USART_LastBit_Disable ((uint16_t)0x0000) +#define USART_LastBit_Enable ((uint16_t)0x0100) +#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \ + ((LASTBIT) == USART_LastBit_Enable)) +/** + * @} + */ + +/** @defgroup USART_Interrupt_definition + * @{ + */ + +#define USART_IT_PE ((uint16_t)0x0028) +#define USART_IT_TXE ((uint16_t)0x0727) +#define USART_IT_TC ((uint16_t)0x0626) +#define USART_IT_RXNE ((uint16_t)0x0525) +#define USART_IT_IDLE ((uint16_t)0x0424) +#define USART_IT_LBD ((uint16_t)0x0846) +#define USART_IT_CTS ((uint16_t)0x096A) +#define USART_IT_ERR ((uint16_t)0x0060) +#define USART_IT_ORE ((uint16_t)0x0360) +#define USART_IT_NE ((uint16_t)0x0260) +#define USART_IT_FE ((uint16_t)0x0160) +#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ + ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ + ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ + ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR)) +#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ + ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ + ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ + ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \ + ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE)) +#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ + ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS)) +/** + * @} + */ + +/** @defgroup USART_DMA_Requests + * @{ + */ + +#define USART_DMAReq_Tx ((uint16_t)0x0080) +#define USART_DMAReq_Rx ((uint16_t)0x0040) +#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00)) + +/** + * @} + */ + +/** @defgroup USART_WakeUp_methods + * @{ + */ + +#define USART_WakeUp_IdleLine ((uint16_t)0x0000) +#define USART_WakeUp_AddressMark ((uint16_t)0x0800) +#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \ + ((WAKEUP) == USART_WakeUp_AddressMark)) +/** + * @} + */ + +/** @defgroup USART_LIN_Break_Detection_Length + * @{ + */ + +#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000) +#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020) +#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \ + (((LENGTH) == USART_LINBreakDetectLength_10b) || \ + ((LENGTH) == USART_LINBreakDetectLength_11b)) +/** + * @} + */ + +/** @defgroup USART_IrDA_Low_Power + * @{ + */ + +#define USART_IrDAMode_LowPower ((uint16_t)0x0004) +#define USART_IrDAMode_Normal ((uint16_t)0x0000) +#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \ + ((MODE) == USART_IrDAMode_Normal)) +/** + * @} + */ + +/** @defgroup USART_Flags + * @{ + */ + +#define USART_FLAG_CTS ((uint16_t)0x0200) +#define USART_FLAG_LBD ((uint16_t)0x0100) +#define USART_FLAG_TXE ((uint16_t)0x0080) +#define USART_FLAG_TC ((uint16_t)0x0040) +#define USART_FLAG_RXNE ((uint16_t)0x0020) +#define USART_FLAG_IDLE ((uint16_t)0x0010) +#define USART_FLAG_ORE ((uint16_t)0x0008) +#define USART_FLAG_NE ((uint16_t)0x0004) +#define USART_FLAG_FE ((uint16_t)0x0002) +#define USART_FLAG_PE ((uint16_t)0x0001) +#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \ + ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \ + ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \ + ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \ + ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE)) + +#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00)) +#define IS_USART_PERIPH_FLAG(PERIPH, USART_FLAG) ((((*(uint32_t*)&(PERIPH)) != UART4_BASE) &&\ + ((*(uint32_t*)&(PERIPH)) != UART5_BASE)) \ + || ((USART_FLAG) != USART_FLAG_CTS)) +#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x0044AA21)) +#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF) +#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF) + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup USART_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup USART_Exported_Functions + * @{ + */ + +void USART_DeInit(USART_TypeDef* USARTx); +void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct); +void USART_StructInit(USART_InitTypeDef* USART_InitStruct); +void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct); +void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct); +void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState); +void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState); +void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address); +void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp); +void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength); +void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_SendData(USART_TypeDef* USARTx, uint16_t Data); +uint16_t USART_ReceiveData(USART_TypeDef* USARTx); +void USART_SendBreak(USART_TypeDef* USARTx); +void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime); +void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler); +void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode); +void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState); +FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG); +void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG); +ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT); +void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_USART_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32f10x/stm32f10x_wwdg.h b/example/libs_stm/inc/stm32f10x/stm32f10x_wwdg.h new file mode 100644 index 0000000..fe238cd --- /dev/null +++ b/example/libs_stm/inc/stm32f10x/stm32f10x_wwdg.h @@ -0,0 +1,114 @@ +/** + ****************************************************************************** + * @file stm32f10x_wwdg.h + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file contains all the functions prototypes for the WWDG firmware + * library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_WWDG_H +#define __STM32F10x_WWDG_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup WWDG + * @{ + */ + +/** @defgroup WWDG_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @defgroup WWDG_Exported_Constants + * @{ + */ + +/** @defgroup WWDG_Prescaler + * @{ + */ + +#define WWDG_Prescaler_1 ((uint32_t)0x00000000) +#define WWDG_Prescaler_2 ((uint32_t)0x00000080) +#define WWDG_Prescaler_4 ((uint32_t)0x00000100) +#define WWDG_Prescaler_8 ((uint32_t)0x00000180) +#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \ + ((PRESCALER) == WWDG_Prescaler_2) || \ + ((PRESCALER) == WWDG_Prescaler_4) || \ + ((PRESCALER) == WWDG_Prescaler_8)) +#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F) +#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F)) + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup WWDG_Exported_Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup WWDG_Exported_Functions + * @{ + */ + +void WWDG_DeInit(void); +void WWDG_SetPrescaler(uint32_t WWDG_Prescaler); +void WWDG_SetWindowValue(uint8_t WindowValue); +void WWDG_EnableIT(void); +void WWDG_SetCounter(uint8_t Counter); +void WWDG_Enable(uint8_t Counter); +FlagStatus WWDG_GetFlagStatus(void); +void WWDG_ClearFlag(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_WWDG_H */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32f10x/Release_Notes_for_STM32F10x_StdPeriph_Driver.html b/example/libs_stm/src/stm32f10x/Release_Notes_for_STM32F10x_StdPeriph_Driver.html new file mode 100644 index 0000000..018141b --- /dev/null +++ b/example/libs_stm/src/stm32f10x/Release_Notes_for_STM32F10x_StdPeriph_Driver.html @@ -0,0 +1,203 @@ + + + + + + +Release Notes for STM32F10x Standard Peripherals Library Drivers + + + + + +
+


+

+
+ + + + + + +
+ + + + + + + + + +
Back to Release page
+

Release +Notes for STM32F10x Standard Peripherals Library Drivers +(StdPeriph_Driver)

+

Copyright 2010 STMicroelectronics

+

+
+

 

+ + + + + + +
+

Contents

+
    +
  1. STM32F10x Standard Peripherals Library +Drivers update History
    2. +
  2. License
    3. +
+ + +

STM32F10x Standard +Peripherals Library Drivers  update History

3.3.0 +- 04/16/2010

+
  1. General
+
  • Add support for STM32F10x XL-density devices.
  • I2C driver: events description and management enhancement.
+
  1. STM32F10x_StdPeriph_Driver
+
  • stm32f10x_dbgmcu.h/.c
    • DBGMCU_Config() function: add new values DBGMCU_TIMx_STOP (x: 9..14) for DBGMCU_Periph parameter.
  • stm32f10x_flash.h/.c: +updated to support Bank2 of XL-density devices (up to 1MByte of Flash +memory). For more details, refer to the description provided within +stm32f10x_flash.c file.
  • stm32f10x_gpio.h/.c
    • GPIO_PinRemapConfig() function: add new values for GPIO_Remap parameter, to support new remap for FSMC_NADV pin and TIM9..11,13,14.
  • stm32f10x_i2c.h/.c: I2C events description and management enhancement.
    • I2C_CheckEvent() +function: updated to check whether the last event contains the +I2C_EVENT  (instead of check whether the last event is equal to +I2C_EVENT)
    • Add +detailed description of I2C events and how to manage them using the +functions provided by this driver. For more information, refer to +stm32f10x_i2c.h and stm32f10x_i2c.c files.
  • stm32f10x_rcc.h/.c: updated to support TIM9..TIM14 APB clock and reset configuration
  • stm32f10x_tim.h/.c: updated to support new Timers TIM9..TIM14.
  • stm32f10x_sdio.h: 
    • SDIO_SetSDIOReadWaitMode() function: correct values of SDIO_ReadWaitMode parameter
      change
        +#define +SDIO_ReadWaitMode_CLK               +  ((uint32_t)0x00000000)
        #define +SDIO_ReadWaitMode_DATA2             +((uint32_t)0x00000001)
      by
        #define +SDIO_ReadWaitMode_CLK               +  ((uint32_t)0x00000001)
        #define +SDIO_ReadWaitMode_DATA2             +((uint32_t)0x00000000)
+

3.2.0 +- 03/01/2010

+
    +
  1. General
    2. +
+
    + +
  • Add support +for STM32 Low-density Value line (STM32F100x4/6) and +Medium-density Value line (STM32F100x8/B) devices.
    • +
  • Almost +peripherals drivers were updated to support Value +line devices features
    • +
  • Drivers limitations fix and enhancements.
    • + +
+
    +
  1. STM32F10x_StdPeriph_Driver
    2. +
+
    +
  • Add new +firmware driver for CEC peripheral: stm32f10x_cec.h and stm32f10x_cec.c
    • +
  • Timers drivers stm32f10x_tim.h/.c: add support for new General Purpose Timers: TIM15, TIM16 and TIM17.
    • +
  • RCC driver: add support for new Value peripherals: HDMI-CEC, TIM15, TIM16 and TIM17.
    • +
  • GPIO driver: add new remap parameters for TIM1, TIM15, TIM16, TIM17 and HDMI-CEC: GPIO_Remap_TIM1_DMA, GPIO_Remap_TIM15, GPIO_Remap_TIM16, GPIO_Remap_TIM17, GPIO_Remap_CEC.
    • +
  • USART +driver: add support for Oversampling by 8 mode and onebit method. 2 +functions has been added: USART_OverSampling8Cmd() and +USART_OneBitMethodCmd().
    +
    • +
  • DAC +driver: add new functions handling the DAC under run feature: +DAC_ITConfig(), DAC_GetFlagStatus(), DAC_ClearFlag(), DAC_GetITStatus() +and DAC_ClearITPendingBit().
    • +
  • DBGMCU driver: add new parameters for TIM15, TIM16 and TIM17: DBGMCU_TIM15_STOP, DBGMCU_TIM16_STOP, DBGMCU_TIM17_STOP.
    +
    • +
  • FLASH +driver: the FLASH_EraseOptionBytes() function updated. This is now just +erasing the option bytes without modifying the RDP status either +enabled or disabled.
    • +
  • PWR +driver: the PWR_EnterSTOPMode() function updated. When woken up from +STOP mode, this function resets again the SLEEPDEEP bit in the +Cortex-M3 System Control register to allow Sleep mode entering.
    • + + +
+

License

+

The +enclosed firmware and all the related documentation are not covered by +a License Agreement, if you need such License you can contact your +local STMicroelectronics office.

+

THE +PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO +SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR +ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY +CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY +CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH +THEIR PRODUCTS.

+

 

+
+
+

For +complete documentation on STM32(CORTEX M3) 32-Bit Microcontrollers +visit www.st.com/STM32

+
+

+
+
+

 

+
+ \ No newline at end of file diff --git a/example/libs_stm/src/stm32f10x/misc.c b/example/libs_stm/src/stm32f10x/misc.c new file mode 100644 index 0000000..b8349fa --- /dev/null +++ b/example/libs_stm/src/stm32f10x/misc.c @@ -0,0 +1,223 @@ +/** + ****************************************************************************** + * @file misc.c + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file provides all the miscellaneous firmware functions (add-on + * to CMSIS functions). + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "misc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup MISC + * @brief MISC driver modules + * @{ + */ + +/** @defgroup MISC_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup MISC_Private_Defines + * @{ + */ + +#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) +/** + * @} + */ + +/** @defgroup MISC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup MISC_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup MISC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup MISC_Private_Functions + * @{ + */ + +/** + * @brief Configures the priority grouping: pre-emption priority and subpriority. + * @param NVIC_PriorityGroup: specifies the priority grouping bits length. + * This parameter can be one of the following values: + * @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority + * 4 bits for subpriority + * @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority + * 3 bits for subpriority + * @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority + * 2 bits for subpriority + * @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority + * 1 bits for subpriority + * @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority + * 0 bits for subpriority + * @retval None + */ +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) +{ + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup)); + + /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */ + SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup; +} + +/** + * @brief Initializes the NVIC peripheral according to the specified + * parameters in the NVIC_InitStruct. + * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains + * the configuration information for the specified NVIC peripheral. + * @retval None + */ +void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct) +{ + uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F; + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd)); + assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority)); + assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority)); + + if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) + { + /* Compute the Corresponding IRQ Priority --------------------------------*/ + tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08; + tmppre = (0x4 - tmppriority); + tmpsub = tmpsub >> tmppriority; + + tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre; + tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub; + tmppriority = tmppriority << 0x04; + + NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority; + + /* Enable the Selected IRQ Channels --------------------------------------*/ + NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = + (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); + } + else + { + /* Disable the Selected IRQ Channels -------------------------------------*/ + NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = + (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); + } +} + +/** + * @brief Sets the vector table location and Offset. + * @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory. + * This parameter can be one of the following values: + * @arg NVIC_VectTab_RAM + * @arg NVIC_VectTab_FLASH + * @param Offset: Vector Table base offset field. This value must be a multiple of 0x100. + * @retval None + */ +void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset) +{ + /* Check the parameters */ + assert_param(IS_NVIC_VECTTAB(NVIC_VectTab)); + assert_param(IS_NVIC_OFFSET(Offset)); + + SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80); +} + +/** + * @brief Selects the condition for the system to enter low power mode. + * @param LowPowerMode: Specifies the new mode for the system to enter low power mode. + * This parameter can be one of the following values: + * @arg NVIC_LP_SEVONPEND + * @arg NVIC_LP_SLEEPDEEP + * @arg NVIC_LP_SLEEPONEXIT + * @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_NVIC_LP(LowPowerMode)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + SCB->SCR |= LowPowerMode; + } + else + { + SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode); + } +} + +/** + * @brief Configures the SysTick clock source. + * @param SysTick_CLKSource: specifies the SysTick clock source. + * This parameter can be one of the following values: + * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source. + * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source. + * @retval None + */ +void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource) +{ + /* Check the parameters */ + assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource)); + if (SysTick_CLKSource == SysTick_CLKSource_HCLK) + { + SysTick->CTRL |= SysTick_CLKSource_HCLK; + } + else + { + SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32f10x/stm32f10x_adc.c b/example/libs_stm/src/stm32f10x/stm32f10x_adc.c new file mode 100644 index 0000000..a027f33 --- /dev/null +++ b/example/libs_stm/src/stm32f10x/stm32f10x_adc.c @@ -0,0 +1,1306 @@ +/** + ****************************************************************************** + * @file stm32f10x_adc.c + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file provides all the ADC firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_adc.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup ADC + * @brief ADC driver modules + * @{ + */ + +/** @defgroup ADC_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup ADC_Private_Defines + * @{ + */ + +/* ADC DISCNUM mask */ +#define CR1_DISCNUM_Reset ((uint32_t)0xFFFF1FFF) + +/* ADC DISCEN mask */ +#define CR1_DISCEN_Set ((uint32_t)0x00000800) +#define CR1_DISCEN_Reset ((uint32_t)0xFFFFF7FF) + +/* ADC JAUTO mask */ +#define CR1_JAUTO_Set ((uint32_t)0x00000400) +#define CR1_JAUTO_Reset ((uint32_t)0xFFFFFBFF) + +/* ADC JDISCEN mask */ +#define CR1_JDISCEN_Set ((uint32_t)0x00001000) +#define CR1_JDISCEN_Reset ((uint32_t)0xFFFFEFFF) + +/* ADC AWDCH mask */ +#define CR1_AWDCH_Reset ((uint32_t)0xFFFFFFE0) + +/* ADC Analog watchdog enable mode mask */ +#define CR1_AWDMode_Reset ((uint32_t)0xFF3FFDFF) + +/* CR1 register Mask */ +#define CR1_CLEAR_Mask ((uint32_t)0xFFF0FEFF) + +/* ADC ADON mask */ +#define CR2_ADON_Set ((uint32_t)0x00000001) +#define CR2_ADON_Reset ((uint32_t)0xFFFFFFFE) + +/* ADC DMA mask */ +#define CR2_DMA_Set ((uint32_t)0x00000100) +#define CR2_DMA_Reset ((uint32_t)0xFFFFFEFF) + +/* ADC RSTCAL mask */ +#define CR2_RSTCAL_Set ((uint32_t)0x00000008) + +/* ADC CAL mask */ +#define CR2_CAL_Set ((uint32_t)0x00000004) + +/* ADC SWSTART mask */ +#define CR2_SWSTART_Set ((uint32_t)0x00400000) + +/* ADC EXTTRIG mask */ +#define CR2_EXTTRIG_Set ((uint32_t)0x00100000) +#define CR2_EXTTRIG_Reset ((uint32_t)0xFFEFFFFF) + +/* ADC Software start mask */ +#define CR2_EXTTRIG_SWSTART_Set ((uint32_t)0x00500000) +#define CR2_EXTTRIG_SWSTART_Reset ((uint32_t)0xFFAFFFFF) + +/* ADC JEXTSEL mask */ +#define CR2_JEXTSEL_Reset ((uint32_t)0xFFFF8FFF) + +/* ADC JEXTTRIG mask */ +#define CR2_JEXTTRIG_Set ((uint32_t)0x00008000) +#define CR2_JEXTTRIG_Reset ((uint32_t)0xFFFF7FFF) + +/* ADC JSWSTART mask */ +#define CR2_JSWSTART_Set ((uint32_t)0x00200000) + +/* ADC injected software start mask */ +#define CR2_JEXTTRIG_JSWSTART_Set ((uint32_t)0x00208000) +#define CR2_JEXTTRIG_JSWSTART_Reset ((uint32_t)0xFFDF7FFF) + +/* ADC TSPD mask */ +#define CR2_TSVREFE_Set ((uint32_t)0x00800000) +#define CR2_TSVREFE_Reset ((uint32_t)0xFF7FFFFF) + +/* CR2 register Mask */ +#define CR2_CLEAR_Mask ((uint32_t)0xFFF1F7FD) + +/* ADC SQx mask */ +#define SQR3_SQ_Set ((uint32_t)0x0000001F) +#define SQR2_SQ_Set ((uint32_t)0x0000001F) +#define SQR1_SQ_Set ((uint32_t)0x0000001F) + +/* SQR1 register Mask */ +#define SQR1_CLEAR_Mask ((uint32_t)0xFF0FFFFF) + +/* ADC JSQx mask */ +#define JSQR_JSQ_Set ((uint32_t)0x0000001F) + +/* ADC JL mask */ +#define JSQR_JL_Set ((uint32_t)0x00300000) +#define JSQR_JL_Reset ((uint32_t)0xFFCFFFFF) + +/* ADC SMPx mask */ +#define SMPR1_SMP_Set ((uint32_t)0x00000007) +#define SMPR2_SMP_Set ((uint32_t)0x00000007) + +/* ADC JDRx registers offset */ +#define JDR_Offset ((uint8_t)0x28) + +/* ADC1 DR register base address */ +#define DR_ADDRESS ((uint32_t)0x4001244C) + +/** + * @} + */ + +/** @defgroup ADC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup ADC_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup ADC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup ADC_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the ADCx peripheral registers to their default reset values. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval None + */ +void ADC_DeInit(ADC_TypeDef* ADCx) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + + if (ADCx == ADC1) + { + /* Enable ADC1 reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE); + /* Release ADC1 from reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE); + } + else if (ADCx == ADC2) + { + /* Enable ADC2 reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, ENABLE); + /* Release ADC2 from reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, DISABLE); + } + else + { + if (ADCx == ADC3) + { + /* Enable ADC3 reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, ENABLE); + /* Release ADC3 from reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, DISABLE); + } + } +} + +/** + * @brief Initializes the ADCx peripheral according to the specified parameters + * in the ADC_InitStruct. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains + * the configuration information for the specified ADC peripheral. + * @retval None + */ +void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct) +{ + uint32_t tmpreg1 = 0; + uint8_t tmpreg2 = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_MODE(ADC_InitStruct->ADC_Mode)); + assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode)); + assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode)); + assert_param(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv)); + assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign)); + assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfChannel)); + + /*---------------------------- ADCx CR1 Configuration -----------------*/ + /* Get the ADCx CR1 value */ + tmpreg1 = ADCx->CR1; + /* Clear DUALMOD and SCAN bits */ + tmpreg1 &= CR1_CLEAR_Mask; + /* Configure ADCx: Dual mode and scan conversion mode */ + /* Set DUALMOD bits according to ADC_Mode value */ + /* Set SCAN bit according to ADC_ScanConvMode value */ + tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_Mode | ((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8)); + /* Write to ADCx CR1 */ + ADCx->CR1 = tmpreg1; + + /*---------------------------- ADCx CR2 Configuration -----------------*/ + /* Get the ADCx CR2 value */ + tmpreg1 = ADCx->CR2; + /* Clear CONT, ALIGN and EXTSEL bits */ + tmpreg1 &= CR2_CLEAR_Mask; + /* Configure ADCx: external trigger event and continuous conversion mode */ + /* Set ALIGN bit according to ADC_DataAlign value */ + /* Set EXTSEL bits according to ADC_ExternalTrigConv value */ + /* Set CONT bit according to ADC_ContinuousConvMode value */ + tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv | + ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1)); + /* Write to ADCx CR2 */ + ADCx->CR2 = tmpreg1; + + /*---------------------------- ADCx SQR1 Configuration -----------------*/ + /* Get the ADCx SQR1 value */ + tmpreg1 = ADCx->SQR1; + /* Clear L bits */ + tmpreg1 &= SQR1_CLEAR_Mask; + /* Configure ADCx: regular channel sequence length */ + /* Set L bits according to ADC_NbrOfChannel value */ + tmpreg2 |= (uint8_t) (ADC_InitStruct->ADC_NbrOfChannel - (uint8_t)1); + tmpreg1 |= (uint32_t)tmpreg2 << 20; + /* Write to ADCx SQR1 */ + ADCx->SQR1 = tmpreg1; +} + +/** + * @brief Fills each ADC_InitStruct member with its default value. + * @param ADC_InitStruct : pointer to an ADC_InitTypeDef structure which will be initialized. + * @retval None + */ +void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct) +{ + /* Reset ADC init structure parameters values */ + /* Initialize the ADC_Mode member */ + ADC_InitStruct->ADC_Mode = ADC_Mode_Independent; + /* initialize the ADC_ScanConvMode member */ + ADC_InitStruct->ADC_ScanConvMode = DISABLE; + /* Initialize the ADC_ContinuousConvMode member */ + ADC_InitStruct->ADC_ContinuousConvMode = DISABLE; + /* Initialize the ADC_ExternalTrigConv member */ + ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1; + /* Initialize the ADC_DataAlign member */ + ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right; + /* Initialize the ADC_NbrOfChannel member */ + ADC_InitStruct->ADC_NbrOfChannel = 1; +} + +/** + * @brief Enables or disables the specified ADC peripheral. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the ADCx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Set the ADON bit to wake up the ADC from power down mode */ + ADCx->CR2 |= CR2_ADON_Set; + } + else + { + /* Disable the selected ADC peripheral */ + ADCx->CR2 &= CR2_ADON_Reset; + } +} + +/** + * @brief Enables or disables the specified ADC DMA request. + * @param ADCx: where x can be 1 or 3 to select the ADC peripheral. + * Note: ADC2 hasn't a DMA capability. + * @param NewState: new state of the selected ADC DMA transfer. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_DMA_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC DMA request */ + ADCx->CR2 |= CR2_DMA_Set; + } + else + { + /* Disable the selected ADC DMA request */ + ADCx->CR2 &= CR2_DMA_Reset; + } +} + +/** + * @brief Enables or disables the specified ADC interrupts. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_IT: specifies the ADC interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg ADC_IT_EOC: End of conversion interrupt mask + * @arg ADC_IT_AWD: Analog watchdog interrupt mask + * @arg ADC_IT_JEOC: End of injected conversion interrupt mask + * @param NewState: new state of the specified ADC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState) +{ + uint8_t itmask = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_ADC_IT(ADC_IT)); + /* Get the ADC IT index */ + itmask = (uint8_t)ADC_IT; + if (NewState != DISABLE) + { + /* Enable the selected ADC interrupts */ + ADCx->CR1 |= itmask; + } + else + { + /* Disable the selected ADC interrupts */ + ADCx->CR1 &= (~(uint32_t)itmask); + } +} + +/** + * @brief Resets the selected ADC calibration registers. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval None + */ +void ADC_ResetCalibration(ADC_TypeDef* ADCx) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + /* Resets the selected ADC calibartion registers */ + ADCx->CR2 |= CR2_RSTCAL_Set; +} + +/** + * @brief Gets the selected ADC reset calibration registers status. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval The new state of ADC reset calibration registers (SET or RESET). + */ +FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + /* Check the status of RSTCAL bit */ + if ((ADCx->CR2 & CR2_RSTCAL_Set) != (uint32_t)RESET) + { + /* RSTCAL bit is set */ + bitstatus = SET; + } + else + { + /* RSTCAL bit is reset */ + bitstatus = RESET; + } + /* Return the RSTCAL bit status */ + return bitstatus; +} + +/** + * @brief Starts the selected ADC calibration process. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval None + */ +void ADC_StartCalibration(ADC_TypeDef* ADCx) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + /* Enable the selected ADC calibration process */ + ADCx->CR2 |= CR2_CAL_Set; +} + +/** + * @brief Gets the selected ADC calibration status. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval The new state of ADC calibration (SET or RESET). + */ +FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + /* Check the status of CAL bit */ + if ((ADCx->CR2 & CR2_CAL_Set) != (uint32_t)RESET) + { + /* CAL bit is set: calibration on going */ + bitstatus = SET; + } + else + { + /* CAL bit is reset: end of calibration */ + bitstatus = RESET; + } + /* Return the CAL bit status */ + return bitstatus; +} + +/** + * @brief Enables or disables the selected ADC software start conversion . + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC software start conversion. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC conversion on external event and start the selected + ADC conversion */ + ADCx->CR2 |= CR2_EXTTRIG_SWSTART_Set; + } + else + { + /* Disable the selected ADC conversion on external event and stop the selected + ADC conversion */ + ADCx->CR2 &= CR2_EXTTRIG_SWSTART_Reset; + } +} + +/** + * @brief Gets the selected ADC Software start conversion Status. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval The new state of ADC software start conversion (SET or RESET). + */ +FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + /* Check the status of SWSTART bit */ + if ((ADCx->CR2 & CR2_SWSTART_Set) != (uint32_t)RESET) + { + /* SWSTART bit is set */ + bitstatus = SET; + } + else + { + /* SWSTART bit is reset */ + bitstatus = RESET; + } + /* Return the SWSTART bit status */ + return bitstatus; +} + +/** + * @brief Configures the discontinuous mode for the selected ADC regular + * group channel. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param Number: specifies the discontinuous mode regular channel + * count value. This number must be between 1 and 8. + * @retval None + */ +void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number) +{ + uint32_t tmpreg1 = 0; + uint32_t tmpreg2 = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_REGULAR_DISC_NUMBER(Number)); + /* Get the old register value */ + tmpreg1 = ADCx->CR1; + /* Clear the old discontinuous mode channel count */ + tmpreg1 &= CR1_DISCNUM_Reset; + /* Set the discontinuous mode channel count */ + tmpreg2 = Number - 1; + tmpreg1 |= tmpreg2 << 13; + /* Store the new register value */ + ADCx->CR1 = tmpreg1; +} + +/** + * @brief Enables or disables the discontinuous mode on regular group + * channel for the specified ADC + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC discontinuous mode + * on regular group channel. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC regular discontinuous mode */ + ADCx->CR1 |= CR1_DISCEN_Set; + } + else + { + /* Disable the selected ADC regular discontinuous mode */ + ADCx->CR1 &= CR1_DISCEN_Reset; + } +} + +/** + * @brief Configures for the selected ADC regular channel its corresponding + * rank in the sequencer and its sample time. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_Channel: the ADC channel to configure. + * This parameter can be one of the following values: + * @arg ADC_Channel_0: ADC Channel0 selected + * @arg ADC_Channel_1: ADC Channel1 selected + * @arg ADC_Channel_2: ADC Channel2 selected + * @arg ADC_Channel_3: ADC Channel3 selected + * @arg ADC_Channel_4: ADC Channel4 selected + * @arg ADC_Channel_5: ADC Channel5 selected + * @arg ADC_Channel_6: ADC Channel6 selected + * @arg ADC_Channel_7: ADC Channel7 selected + * @arg ADC_Channel_8: ADC Channel8 selected + * @arg ADC_Channel_9: ADC Channel9 selected + * @arg ADC_Channel_10: ADC Channel10 selected + * @arg ADC_Channel_11: ADC Channel11 selected + * @arg ADC_Channel_12: ADC Channel12 selected + * @arg ADC_Channel_13: ADC Channel13 selected + * @arg ADC_Channel_14: ADC Channel14 selected + * @arg ADC_Channel_15: ADC Channel15 selected + * @arg ADC_Channel_16: ADC Channel16 selected + * @arg ADC_Channel_17: ADC Channel17 selected + * @param Rank: The rank in the regular group sequencer. This parameter must be between 1 to 16. + * @param ADC_SampleTime: The sample time value to be set for the selected channel. + * This parameter can be one of the following values: + * @arg ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles + * @arg ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles + * @arg ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles + * @arg ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles + * @arg ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles + * @arg ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles + * @arg ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles + * @arg ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles + * @retval None + */ +void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_CHANNEL(ADC_Channel)); + assert_param(IS_ADC_REGULAR_RANK(Rank)); + assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime)); + /* if ADC_Channel_10 ... ADC_Channel_17 is selected */ + if (ADC_Channel > ADC_Channel_9) + { + /* Get the old register value */ + tmpreg1 = ADCx->SMPR1; + /* Calculate the mask to clear */ + tmpreg2 = SMPR1_SMP_Set << (3 * (ADC_Channel - 10)); + /* Clear the old channel sample time */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); + /* Set the new channel sample time */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SMPR1 = tmpreg1; + } + else /* ADC_Channel include in ADC_Channel_[0..9] */ + { + /* Get the old register value */ + tmpreg1 = ADCx->SMPR2; + /* Calculate the mask to clear */ + tmpreg2 = SMPR2_SMP_Set << (3 * ADC_Channel); + /* Clear the old channel sample time */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); + /* Set the new channel sample time */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SMPR2 = tmpreg1; + } + /* For Rank 1 to 6 */ + if (Rank < 7) + { + /* Get the old register value */ + tmpreg1 = ADCx->SQR3; + /* Calculate the mask to clear */ + tmpreg2 = SQR3_SQ_Set << (5 * (Rank - 1)); + /* Clear the old SQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1)); + /* Set the SQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SQR3 = tmpreg1; + } + /* For Rank 7 to 12 */ + else if (Rank < 13) + { + /* Get the old register value */ + tmpreg1 = ADCx->SQR2; + /* Calculate the mask to clear */ + tmpreg2 = SQR2_SQ_Set << (5 * (Rank - 7)); + /* Clear the old SQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7)); + /* Set the SQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SQR2 = tmpreg1; + } + /* For Rank 13 to 16 */ + else + { + /* Get the old register value */ + tmpreg1 = ADCx->SQR1; + /* Calculate the mask to clear */ + tmpreg2 = SQR1_SQ_Set << (5 * (Rank - 13)); + /* Clear the old SQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13)); + /* Set the SQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SQR1 = tmpreg1; + } +} + +/** + * @brief Enables or disables the ADCx conversion through external trigger. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC external trigger start of conversion. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC conversion on external event */ + ADCx->CR2 |= CR2_EXTTRIG_Set; + } + else + { + /* Disable the selected ADC conversion on external event */ + ADCx->CR2 &= CR2_EXTTRIG_Reset; + } +} + +/** + * @brief Returns the last ADCx conversion result data for regular channel. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval The Data conversion value. + */ +uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + /* Return the selected ADC conversion value */ + return (uint16_t) ADCx->DR; +} + +/** + * @brief Returns the last ADC1 and ADC2 conversion result data in dual mode. + * @retval The Data conversion value. + */ +uint32_t ADC_GetDualModeConversionValue(void) +{ + /* Return the dual mode conversion value */ + return (*(__IO uint32_t *) DR_ADDRESS); +} + +/** + * @brief Enables or disables the selected ADC automatic injected group + * conversion after regular one. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC auto injected conversion + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC automatic injected group conversion */ + ADCx->CR1 |= CR1_JAUTO_Set; + } + else + { + /* Disable the selected ADC automatic injected group conversion */ + ADCx->CR1 &= CR1_JAUTO_Reset; + } +} + +/** + * @brief Enables or disables the discontinuous mode for injected group + * channel for the specified ADC + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC discontinuous mode + * on injected group channel. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC injected discontinuous mode */ + ADCx->CR1 |= CR1_JDISCEN_Set; + } + else + { + /* Disable the selected ADC injected discontinuous mode */ + ADCx->CR1 &= CR1_JDISCEN_Reset; + } +} + +/** + * @brief Configures the ADCx external trigger for injected channels conversion. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_ExternalTrigInjecConv: specifies the ADC trigger to start injected conversion. + * This parameter can be one of the following values: + * @arg ADC_ExternalTrigInjecConv_T1_TRGO: Timer1 TRGO event selected (for ADC1, ADC2 and ADC3) + * @arg ADC_ExternalTrigInjecConv_T1_CC4: Timer1 capture compare4 selected (for ADC1, ADC2 and ADC3) + * @arg ADC_ExternalTrigInjecConv_T2_TRGO: Timer2 TRGO event selected (for ADC1 and ADC2) + * @arg ADC_ExternalTrigInjecConv_T2_CC1: Timer2 capture compare1 selected (for ADC1 and ADC2) + * @arg ADC_ExternalTrigInjecConv_T3_CC4: Timer3 capture compare4 selected (for ADC1 and ADC2) + * @arg ADC_ExternalTrigInjecConv_T4_TRGO: Timer4 TRGO event selected (for ADC1 and ADC2) + * @arg ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4: External interrupt line 15 or Timer8 + * capture compare4 event selected (for ADC1 and ADC2) + * @arg ADC_ExternalTrigInjecConv_T4_CC3: Timer4 capture compare3 selected (for ADC3 only) + * @arg ADC_ExternalTrigInjecConv_T8_CC2: Timer8 capture compare2 selected (for ADC3 only) + * @arg ADC_ExternalTrigInjecConv_T8_CC4: Timer8 capture compare4 selected (for ADC3 only) + * @arg ADC_ExternalTrigInjecConv_T5_TRGO: Timer5 TRGO event selected (for ADC3 only) + * @arg ADC_ExternalTrigInjecConv_T5_CC4: Timer5 capture compare4 selected (for ADC3 only) + * @arg ADC_ExternalTrigInjecConv_None: Injected conversion started by software and not + * by external trigger (for ADC1, ADC2 and ADC3) + * @retval None + */ +void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv)); + /* Get the old register value */ + tmpreg = ADCx->CR2; + /* Clear the old external event selection for injected group */ + tmpreg &= CR2_JEXTSEL_Reset; + /* Set the external event selection for injected group */ + tmpreg |= ADC_ExternalTrigInjecConv; + /* Store the new register value */ + ADCx->CR2 = tmpreg; +} + +/** + * @brief Enables or disables the ADCx injected channels conversion through + * external trigger + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC external trigger start of + * injected conversion. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC external event selection for injected group */ + ADCx->CR2 |= CR2_JEXTTRIG_Set; + } + else + { + /* Disable the selected ADC external event selection for injected group */ + ADCx->CR2 &= CR2_JEXTTRIG_Reset; + } +} + +/** + * @brief Enables or disables the selected ADC start of the injected + * channels conversion. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC software start injected conversion. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC conversion for injected group on external event and start the selected + ADC injected conversion */ + ADCx->CR2 |= CR2_JEXTTRIG_JSWSTART_Set; + } + else + { + /* Disable the selected ADC conversion on external event for injected group and stop the selected + ADC injected conversion */ + ADCx->CR2 &= CR2_JEXTTRIG_JSWSTART_Reset; + } +} + +/** + * @brief Gets the selected ADC Software start injected conversion Status. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval The new state of ADC software start injected conversion (SET or RESET). + */ +FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + /* Check the status of JSWSTART bit */ + if ((ADCx->CR2 & CR2_JSWSTART_Set) != (uint32_t)RESET) + { + /* JSWSTART bit is set */ + bitstatus = SET; + } + else + { + /* JSWSTART bit is reset */ + bitstatus = RESET; + } + /* Return the JSWSTART bit status */ + return bitstatus; +} + +/** + * @brief Configures for the selected ADC injected channel its corresponding + * rank in the sequencer and its sample time. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_Channel: the ADC channel to configure. + * This parameter can be one of the following values: + * @arg ADC_Channel_0: ADC Channel0 selected + * @arg ADC_Channel_1: ADC Channel1 selected + * @arg ADC_Channel_2: ADC Channel2 selected + * @arg ADC_Channel_3: ADC Channel3 selected + * @arg ADC_Channel_4: ADC Channel4 selected + * @arg ADC_Channel_5: ADC Channel5 selected + * @arg ADC_Channel_6: ADC Channel6 selected + * @arg ADC_Channel_7: ADC Channel7 selected + * @arg ADC_Channel_8: ADC Channel8 selected + * @arg ADC_Channel_9: ADC Channel9 selected + * @arg ADC_Channel_10: ADC Channel10 selected + * @arg ADC_Channel_11: ADC Channel11 selected + * @arg ADC_Channel_12: ADC Channel12 selected + * @arg ADC_Channel_13: ADC Channel13 selected + * @arg ADC_Channel_14: ADC Channel14 selected + * @arg ADC_Channel_15: ADC Channel15 selected + * @arg ADC_Channel_16: ADC Channel16 selected + * @arg ADC_Channel_17: ADC Channel17 selected + * @param Rank: The rank in the injected group sequencer. This parameter must be between 1 and 4. + * @param ADC_SampleTime: The sample time value to be set for the selected channel. + * This parameter can be one of the following values: + * @arg ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles + * @arg ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles + * @arg ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles + * @arg ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles + * @arg ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles + * @arg ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles + * @arg ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles + * @arg ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles + * @retval None + */ +void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_CHANNEL(ADC_Channel)); + assert_param(IS_ADC_INJECTED_RANK(Rank)); + assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime)); + /* if ADC_Channel_10 ... ADC_Channel_17 is selected */ + if (ADC_Channel > ADC_Channel_9) + { + /* Get the old register value */ + tmpreg1 = ADCx->SMPR1; + /* Calculate the mask to clear */ + tmpreg2 = SMPR1_SMP_Set << (3*(ADC_Channel - 10)); + /* Clear the old channel sample time */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_SampleTime << (3*(ADC_Channel - 10)); + /* Set the new channel sample time */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SMPR1 = tmpreg1; + } + else /* ADC_Channel include in ADC_Channel_[0..9] */ + { + /* Get the old register value */ + tmpreg1 = ADCx->SMPR2; + /* Calculate the mask to clear */ + tmpreg2 = SMPR2_SMP_Set << (3 * ADC_Channel); + /* Clear the old channel sample time */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); + /* Set the new channel sample time */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SMPR2 = tmpreg1; + } + /* Rank configuration */ + /* Get the old register value */ + tmpreg1 = ADCx->JSQR; + /* Get JL value: Number = JL+1 */ + tmpreg3 = (tmpreg1 & JSQR_JL_Set)>> 20; + /* Calculate the mask to clear: ((Rank-1)+(4-JL-1)) */ + tmpreg2 = JSQR_JSQ_Set << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); + /* Clear the old JSQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set: ((Rank-1)+(4-JL-1)) */ + tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); + /* Set the JSQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->JSQR = tmpreg1; +} + +/** + * @brief Configures the sequencer length for injected channels + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param Length: The sequencer length. + * This parameter must be a number between 1 to 4. + * @retval None + */ +void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length) +{ + uint32_t tmpreg1 = 0; + uint32_t tmpreg2 = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_INJECTED_LENGTH(Length)); + + /* Get the old register value */ + tmpreg1 = ADCx->JSQR; + /* Clear the old injected sequnence lenght JL bits */ + tmpreg1 &= JSQR_JL_Reset; + /* Set the injected sequnence lenght JL bits */ + tmpreg2 = Length - 1; + tmpreg1 |= tmpreg2 << 20; + /* Store the new register value */ + ADCx->JSQR = tmpreg1; +} + +/** + * @brief Set the injected channels conversion value offset + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_InjectedChannel: the ADC injected channel to set its offset. + * This parameter can be one of the following values: + * @arg ADC_InjectedChannel_1: Injected Channel1 selected + * @arg ADC_InjectedChannel_2: Injected Channel2 selected + * @arg ADC_InjectedChannel_3: Injected Channel3 selected + * @arg ADC_InjectedChannel_4: Injected Channel4 selected + * @param Offset: the offset value for the selected ADC injected channel + * This parameter must be a 12bit value. + * @retval None + */ +void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel)); + assert_param(IS_ADC_OFFSET(Offset)); + + tmp = (uint32_t)ADCx; + tmp += ADC_InjectedChannel; + + /* Set the selected injected channel data offset */ + *(__IO uint32_t *) tmp = (uint32_t)Offset; +} + +/** + * @brief Returns the ADC injected channel conversion result + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_InjectedChannel: the converted ADC injected channel. + * This parameter can be one of the following values: + * @arg ADC_InjectedChannel_1: Injected Channel1 selected + * @arg ADC_InjectedChannel_2: Injected Channel2 selected + * @arg ADC_InjectedChannel_3: Injected Channel3 selected + * @arg ADC_InjectedChannel_4: Injected Channel4 selected + * @retval The Data conversion value. + */ +uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel)); + + tmp = (uint32_t)ADCx; + tmp += ADC_InjectedChannel + JDR_Offset; + + /* Returns the selected injected channel conversion data value */ + return (uint16_t) (*(__IO uint32_t*) tmp); +} + +/** + * @brief Enables or disables the analog watchdog on single/all regular + * or injected channels + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_AnalogWatchdog: the ADC analog watchdog configuration. + * This parameter can be one of the following values: + * @arg ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on a single regular channel + * @arg ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on a single injected channel + * @arg ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog watchdog on a single regular or injected channel + * @arg ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on all regular channel + * @arg ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on all injected channel + * @arg ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog on all regular and injected channels + * @arg ADC_AnalogWatchdog_None: No channel guarded by the analog watchdog + * @retval None + */ +void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog)); + /* Get the old register value */ + tmpreg = ADCx->CR1; + /* Clear AWDEN, AWDENJ and AWDSGL bits */ + tmpreg &= CR1_AWDMode_Reset; + /* Set the analog watchdog enable mode */ + tmpreg |= ADC_AnalogWatchdog; + /* Store the new register value */ + ADCx->CR1 = tmpreg; +} + +/** + * @brief Configures the high and low thresholds of the analog watchdog. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param HighThreshold: the ADC analog watchdog High threshold value. + * This parameter must be a 12bit value. + * @param LowThreshold: the ADC analog watchdog Low threshold value. + * This parameter must be a 12bit value. + * @retval None + */ +void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, + uint16_t LowThreshold) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_THRESHOLD(HighThreshold)); + assert_param(IS_ADC_THRESHOLD(LowThreshold)); + /* Set the ADCx high threshold */ + ADCx->HTR = HighThreshold; + /* Set the ADCx low threshold */ + ADCx->LTR = LowThreshold; +} + +/** + * @brief Configures the analog watchdog guarded single channel + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_Channel: the ADC channel to configure for the analog watchdog. + * This parameter can be one of the following values: + * @arg ADC_Channel_0: ADC Channel0 selected + * @arg ADC_Channel_1: ADC Channel1 selected + * @arg ADC_Channel_2: ADC Channel2 selected + * @arg ADC_Channel_3: ADC Channel3 selected + * @arg ADC_Channel_4: ADC Channel4 selected + * @arg ADC_Channel_5: ADC Channel5 selected + * @arg ADC_Channel_6: ADC Channel6 selected + * @arg ADC_Channel_7: ADC Channel7 selected + * @arg ADC_Channel_8: ADC Channel8 selected + * @arg ADC_Channel_9: ADC Channel9 selected + * @arg ADC_Channel_10: ADC Channel10 selected + * @arg ADC_Channel_11: ADC Channel11 selected + * @arg ADC_Channel_12: ADC Channel12 selected + * @arg ADC_Channel_13: ADC Channel13 selected + * @arg ADC_Channel_14: ADC Channel14 selected + * @arg ADC_Channel_15: ADC Channel15 selected + * @arg ADC_Channel_16: ADC Channel16 selected + * @arg ADC_Channel_17: ADC Channel17 selected + * @retval None + */ +void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_CHANNEL(ADC_Channel)); + /* Get the old register value */ + tmpreg = ADCx->CR1; + /* Clear the Analog watchdog channel select bits */ + tmpreg &= CR1_AWDCH_Reset; + /* Set the Analog watchdog channel */ + tmpreg |= ADC_Channel; + /* Store the new register value */ + ADCx->CR1 = tmpreg; +} + +/** + * @brief Enables or disables the temperature sensor and Vrefint channel. + * @param NewState: new state of the temperature sensor. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_TempSensorVrefintCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the temperature sensor and Vrefint channel*/ + ADC1->CR2 |= CR2_TSVREFE_Set; + } + else + { + /* Disable the temperature sensor and Vrefint channel*/ + ADC1->CR2 &= CR2_TSVREFE_Reset; + } +} + +/** + * @brief Checks whether the specified ADC flag is set or not. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg ADC_FLAG_AWD: Analog watchdog flag + * @arg ADC_FLAG_EOC: End of conversion flag + * @arg ADC_FLAG_JEOC: End of injected group conversion flag + * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag + * @arg ADC_FLAG_STRT: Start of regular group conversion flag + * @retval The new state of ADC_FLAG (SET or RESET). + */ +FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_GET_FLAG(ADC_FLAG)); + /* Check the status of the specified ADC flag */ + if ((ADCx->SR & ADC_FLAG) != (uint8_t)RESET) + { + /* ADC_FLAG is set */ + bitstatus = SET; + } + else + { + /* ADC_FLAG is reset */ + bitstatus = RESET; + } + /* Return the ADC_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the ADCx's pending flags. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg ADC_FLAG_AWD: Analog watchdog flag + * @arg ADC_FLAG_EOC: End of conversion flag + * @arg ADC_FLAG_JEOC: End of injected group conversion flag + * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag + * @arg ADC_FLAG_STRT: Start of regular group conversion flag + * @retval None + */ +void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG)); + /* Clear the selected ADC flags */ + ADCx->SR = ~(uint32_t)ADC_FLAG; +} + +/** + * @brief Checks whether the specified ADC interrupt has occurred or not. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_IT: specifies the ADC interrupt source to check. + * This parameter can be one of the following values: + * @arg ADC_IT_EOC: End of conversion interrupt mask + * @arg ADC_IT_AWD: Analog watchdog interrupt mask + * @arg ADC_IT_JEOC: End of injected conversion interrupt mask + * @retval The new state of ADC_IT (SET or RESET). + */ +ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT) +{ + ITStatus bitstatus = RESET; + uint32_t itmask = 0, enablestatus = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_GET_IT(ADC_IT)); + /* Get the ADC IT index */ + itmask = ADC_IT >> 8; + /* Get the ADC_IT enable bit status */ + enablestatus = (ADCx->CR1 & (uint8_t)ADC_IT) ; + /* Check the status of the specified ADC interrupt */ + if (((ADCx->SR & itmask) != (uint32_t)RESET) && enablestatus) + { + /* ADC_IT is set */ + bitstatus = SET; + } + else + { + /* ADC_IT is reset */ + bitstatus = RESET; + } + /* Return the ADC_IT status */ + return bitstatus; +} + +/** + * @brief Clears the ADCx’s interrupt pending bits. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_IT: specifies the ADC interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg ADC_IT_EOC: End of conversion interrupt mask + * @arg ADC_IT_AWD: Analog watchdog interrupt mask + * @arg ADC_IT_JEOC: End of injected conversion interrupt mask + * @retval None + */ +void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT) +{ + uint8_t itmask = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_IT(ADC_IT)); + /* Get the ADC IT index */ + itmask = (uint8_t)(ADC_IT >> 8); + /* Clear the selected ADC interrupt pending bits */ + ADCx->SR = ~(uint32_t)itmask; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32f10x/stm32f10x_bkp.c b/example/libs_stm/src/stm32f10x/stm32f10x_bkp.c new file mode 100644 index 0000000..de06564 --- /dev/null +++ b/example/libs_stm/src/stm32f10x/stm32f10x_bkp.c @@ -0,0 +1,311 @@ +/** + ****************************************************************************** + * @file stm32f10x_bkp.c + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file provides all the BKP firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_bkp.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup BKP + * @brief BKP driver modules + * @{ + */ + +/** @defgroup BKP_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup BKP_Private_Defines + * @{ + */ + +/* ------------ BKP registers bit address in the alias region --------------- */ +#define BKP_OFFSET (BKP_BASE - PERIPH_BASE) + +/* --- CR Register ----*/ + +/* Alias word address of TPAL bit */ +#define CR_OFFSET (BKP_OFFSET + 0x30) +#define TPAL_BitNumber 0x01 +#define CR_TPAL_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPAL_BitNumber * 4)) + +/* Alias word address of TPE bit */ +#define TPE_BitNumber 0x00 +#define CR_TPE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPE_BitNumber * 4)) + +/* --- CSR Register ---*/ + +/* Alias word address of TPIE bit */ +#define CSR_OFFSET (BKP_OFFSET + 0x34) +#define TPIE_BitNumber 0x02 +#define CSR_TPIE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TPIE_BitNumber * 4)) + +/* Alias word address of TIF bit */ +#define TIF_BitNumber 0x09 +#define CSR_TIF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TIF_BitNumber * 4)) + +/* Alias word address of TEF bit */ +#define TEF_BitNumber 0x08 +#define CSR_TEF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEF_BitNumber * 4)) + +/* ---------------------- BKP registers bit mask ------------------------ */ + +/* RTCCR register bit mask */ +#define RTCCR_CAL_Mask ((uint16_t)0xFF80) +#define RTCCR_Mask ((uint16_t)0xFC7F) + +/* CSR register bit mask */ +#define CSR_CTE_Set ((uint16_t)0x0001) +#define CSR_CTI_Set ((uint16_t)0x0002) + +/** + * @} + */ + + +/** @defgroup BKP_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup BKP_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup BKP_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup BKP_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the BKP peripheral registers to their default reset values. + * @param None + * @retval None + */ +void BKP_DeInit(void) +{ + RCC_BackupResetCmd(ENABLE); + RCC_BackupResetCmd(DISABLE); +} + +/** + * @brief Configures the Tamper Pin active level. + * @param BKP_TamperPinLevel: specifies the Tamper Pin active level. + * This parameter can be one of the following values: + * @arg BKP_TamperPinLevel_High: Tamper pin active on high level + * @arg BKP_TamperPinLevel_Low: Tamper pin active on low level + * @retval None + */ +void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel) +{ + /* Check the parameters */ + assert_param(IS_BKP_TAMPER_PIN_LEVEL(BKP_TamperPinLevel)); + *(__IO uint32_t *) CR_TPAL_BB = BKP_TamperPinLevel; +} + +/** + * @brief Enables or disables the Tamper Pin activation. + * @param NewState: new state of the Tamper Pin activation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void BKP_TamperPinCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CR_TPE_BB = (uint32_t)NewState; +} + +/** + * @brief Enables or disables the Tamper Pin Interrupt. + * @param NewState: new state of the Tamper Pin Interrupt. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void BKP_ITConfig(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CSR_TPIE_BB = (uint32_t)NewState; +} + +/** + * @brief Select the RTC output source to output on the Tamper pin. + * @param BKP_RTCOutputSource: specifies the RTC output source. + * This parameter can be one of the following values: + * @arg BKP_RTCOutputSource_None: no RTC output on the Tamper pin. + * @arg BKP_RTCOutputSource_CalibClock: output the RTC clock with frequency + * divided by 64 on the Tamper pin. + * @arg BKP_RTCOutputSource_Alarm: output the RTC Alarm pulse signal on + * the Tamper pin. + * @arg BKP_RTCOutputSource_Second: output the RTC Second pulse signal on + * the Tamper pin. + * @retval None + */ +void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource) +{ + uint16_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_BKP_RTC_OUTPUT_SOURCE(BKP_RTCOutputSource)); + tmpreg = BKP->RTCCR; + /* Clear CCO, ASOE and ASOS bits */ + tmpreg &= RTCCR_Mask; + + /* Set CCO, ASOE and ASOS bits according to BKP_RTCOutputSource value */ + tmpreg |= BKP_RTCOutputSource; + /* Store the new value */ + BKP->RTCCR = tmpreg; +} + +/** + * @brief Sets RTC Clock Calibration value. + * @param CalibrationValue: specifies the RTC Clock Calibration value. + * This parameter must be a number between 0 and 0x7F. + * @retval None + */ +void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue) +{ + uint16_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_BKP_CALIBRATION_VALUE(CalibrationValue)); + tmpreg = BKP->RTCCR; + /* Clear CAL[6:0] bits */ + tmpreg &= RTCCR_CAL_Mask; + /* Set CAL[6:0] bits according to CalibrationValue value */ + tmpreg |= CalibrationValue; + /* Store the new value */ + BKP->RTCCR = tmpreg; +} + +/** + * @brief Writes user data to the specified Data Backup Register. + * @param BKP_DR: specifies the Data Backup Register. + * This parameter can be BKP_DRx where x:[1, 42] + * @param Data: data to write + * @retval None + */ +void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_BKP_DR(BKP_DR)); + + tmp = (uint32_t)BKP_BASE; + tmp += BKP_DR; + + *(__IO uint32_t *) tmp = Data; +} + +/** + * @brief Reads data from the specified Data Backup Register. + * @param BKP_DR: specifies the Data Backup Register. + * This parameter can be BKP_DRx where x:[1, 42] + * @retval The content of the specified Data Backup Register + */ +uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_BKP_DR(BKP_DR)); + + tmp = (uint32_t)BKP_BASE; + tmp += BKP_DR; + + return (*(__IO uint16_t *) tmp); +} + +/** + * @brief Checks whether the Tamper Pin Event flag is set or not. + * @param None + * @retval The new state of the Tamper Pin Event flag (SET or RESET). + */ +FlagStatus BKP_GetFlagStatus(void) +{ + return (FlagStatus)(*(__IO uint32_t *) CSR_TEF_BB); +} + +/** + * @brief Clears Tamper Pin Event pending flag. + * @param None + * @retval None + */ +void BKP_ClearFlag(void) +{ + /* Set CTE bit to clear Tamper Pin Event flag */ + BKP->CSR |= CSR_CTE_Set; +} + +/** + * @brief Checks whether the Tamper Pin Interrupt has occurred or not. + * @param None + * @retval The new state of the Tamper Pin Interrupt (SET or RESET). + */ +ITStatus BKP_GetITStatus(void) +{ + return (ITStatus)(*(__IO uint32_t *) CSR_TIF_BB); +} + +/** + * @brief Clears Tamper Pin Interrupt pending bit. + * @param None + * @retval None + */ +void BKP_ClearITPendingBit(void) +{ + /* Set CTI bit to clear Tamper Pin Interrupt pending bit */ + BKP->CSR |= CSR_CTI_Set; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32f10x/stm32f10x_can.c b/example/libs_stm/src/stm32f10x/stm32f10x_can.c new file mode 100644 index 0000000..537f333 --- /dev/null +++ b/example/libs_stm/src/stm32f10x/stm32f10x_can.c @@ -0,0 +1,990 @@ +/** + ****************************************************************************** + * @file stm32f10x_can.c + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file provides all the CAN firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_can.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup CAN + * @brief CAN driver modules + * @{ + */ + +/** @defgroup CAN_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup CAN_Private_Defines + * @{ + */ + +/* CAN Master Control Register bits */ +#define MCR_INRQ ((uint32_t)0x00000001) /* Initialization request */ +#define MCR_SLEEP ((uint32_t)0x00000002) /* Sleep mode request */ +#define MCR_TXFP ((uint32_t)0x00000004) /* Transmit FIFO priority */ +#define MCR_RFLM ((uint32_t)0x00000008) /* Receive FIFO locked mode */ +#define MCR_NART ((uint32_t)0x00000010) /* No automatic retransmission */ +#define MCR_AWUM ((uint32_t)0x00000020) /* Automatic wake up mode */ +#define MCR_ABOM ((uint32_t)0x00000040) /* Automatic bus-off management */ +#define MCR_TTCM ((uint32_t)0x00000080) /* time triggered communication */ +#define MCR_RESET ((uint32_t)0x00008000) /* time triggered communication */ +#define MCR_DBF ((uint32_t)0x00010000) /* software master reset */ + +/* CAN Master Status Register bits */ +#define MSR_INAK ((uint32_t)0x00000001) /* Initialization acknowledge */ +#define MSR_WKUI ((uint32_t)0x00000008) /* Wake-up interrupt */ +#define MSR_SLAKI ((uint32_t)0x00000010) /* Sleep acknowledge interrupt */ + +/* CAN Transmit Status Register bits */ +#define TSR_RQCP0 ((uint32_t)0x00000001) /* Request completed mailbox0 */ +#define TSR_TXOK0 ((uint32_t)0x00000002) /* Transmission OK of mailbox0 */ +#define TSR_ABRQ0 ((uint32_t)0x00000080) /* Abort request for mailbox0 */ +#define TSR_RQCP1 ((uint32_t)0x00000100) /* Request completed mailbox1 */ +#define TSR_TXOK1 ((uint32_t)0x00000200) /* Transmission OK of mailbox1 */ +#define TSR_ABRQ1 ((uint32_t)0x00008000) /* Abort request for mailbox1 */ +#define TSR_RQCP2 ((uint32_t)0x00010000) /* Request completed mailbox2 */ +#define TSR_TXOK2 ((uint32_t)0x00020000) /* Transmission OK of mailbox2 */ +#define TSR_ABRQ2 ((uint32_t)0x00800000) /* Abort request for mailbox2 */ +#define TSR_TME0 ((uint32_t)0x04000000) /* Transmit mailbox 0 empty */ +#define TSR_TME1 ((uint32_t)0x08000000) /* Transmit mailbox 1 empty */ +#define TSR_TME2 ((uint32_t)0x10000000) /* Transmit mailbox 2 empty */ + +/* CAN Receive FIFO 0 Register bits */ +#define RF0R_FULL0 ((uint32_t)0x00000008) /* FIFO 0 full */ +#define RF0R_FOVR0 ((uint32_t)0x00000010) /* FIFO 0 overrun */ +#define RF0R_RFOM0 ((uint32_t)0x00000020) /* Release FIFO 0 output mailbox */ + +/* CAN Receive FIFO 1 Register bits */ +#define RF1R_FULL1 ((uint32_t)0x00000008) /* FIFO 1 full */ +#define RF1R_FOVR1 ((uint32_t)0x00000010) /* FIFO 1 overrun */ +#define RF1R_RFOM1 ((uint32_t)0x00000020) /* Release FIFO 1 output mailbox */ + +/* CAN Error Status Register bits */ +#define ESR_EWGF ((uint32_t)0x00000001) /* Error warning flag */ +#define ESR_EPVF ((uint32_t)0x00000002) /* Error passive flag */ +#define ESR_BOFF ((uint32_t)0x00000004) /* Bus-off flag */ + +/* CAN Mailbox Transmit Request */ +#define TMIDxR_TXRQ ((uint32_t)0x00000001) /* Transmit mailbox request */ + +/* CAN Filter Master Register bits */ +#define FMR_FINIT ((uint32_t)0x00000001) /* Filter init mode */ + +/* Time out for INAK bit */ +#define INAK_TimeOut ((uint32_t)0x0000FFFF) + +/* Time out for SLAK bit */ +#define SLAK_TimeOut ((uint32_t)0x0000FFFF) + +/** + * @} + */ + +/** @defgroup CAN_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup CAN_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup CAN_Private_FunctionPrototypes + * @{ + */ + +static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit); + +/** + * @} + */ + +/** @defgroup CAN_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the CAN peripheral registers to their default reset values. + * @param CANx: where x can be 1 or 2 to select the CAN peripheral. + * @retval None. + */ +void CAN_DeInit(CAN_TypeDef* CANx) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + if (CANx == CAN1) + { + /* Enable CAN1 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, ENABLE); + /* Release CAN1 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, DISABLE); + } + else + { + /* Enable CAN2 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, ENABLE); + /* Release CAN2 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, DISABLE); + } +} + +/** + * @brief Initializes the CAN peripheral according to the specified + * parameters in the CAN_InitStruct. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure that + * contains the configuration information for the CAN peripheral. + * @retval Constant indicates initialization succeed which will be + * CANINITFAILED or CANINITOK. + */ +uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct) +{ + uint8_t InitStatus = CANINITFAILED; + uint32_t wait_ack = 0x00000000; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TTCM)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_ABOM)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_AWUM)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_NART)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_RFLM)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TXFP)); + assert_param(IS_CAN_MODE(CAN_InitStruct->CAN_Mode)); + assert_param(IS_CAN_SJW(CAN_InitStruct->CAN_SJW)); + assert_param(IS_CAN_BS1(CAN_InitStruct->CAN_BS1)); + assert_param(IS_CAN_BS2(CAN_InitStruct->CAN_BS2)); + assert_param(IS_CAN_PRESCALER(CAN_InitStruct->CAN_Prescaler)); + + /* exit from sleep mode */ + CANx->MCR &= ~MCR_SLEEP; + + /* Request initialisation */ + CANx->MCR |= MCR_INRQ ; + + /* Wait the acknowledge */ + while (((CANx->MSR & MSR_INAK) != MSR_INAK) && (wait_ack != INAK_TimeOut)) + { + wait_ack++; + } + + /* ...and check acknowledged */ + if ((CANx->MSR & MSR_INAK) != MSR_INAK) + { + InitStatus = CANINITFAILED; + } + else + { + /* Set the time triggered communication mode */ + if (CAN_InitStruct->CAN_TTCM == ENABLE) + { + CANx->MCR |= MCR_TTCM; + } + else + { + CANx->MCR &= ~MCR_TTCM; + } + + /* Set the automatic bus-off management */ + if (CAN_InitStruct->CAN_ABOM == ENABLE) + { + CANx->MCR |= MCR_ABOM; + } + else + { + CANx->MCR &= ~MCR_ABOM; + } + + /* Set the automatic wake-up mode */ + if (CAN_InitStruct->CAN_AWUM == ENABLE) + { + CANx->MCR |= MCR_AWUM; + } + else + { + CANx->MCR &= ~MCR_AWUM; + } + + /* Set the no automatic retransmission */ + if (CAN_InitStruct->CAN_NART == ENABLE) + { + CANx->MCR |= MCR_NART; + } + else + { + CANx->MCR &= ~MCR_NART; + } + + /* Set the receive FIFO locked mode */ + if (CAN_InitStruct->CAN_RFLM == ENABLE) + { + CANx->MCR |= MCR_RFLM; + } + else + { + CANx->MCR &= ~MCR_RFLM; + } + + /* Set the transmit FIFO priority */ + if (CAN_InitStruct->CAN_TXFP == ENABLE) + { + CANx->MCR |= MCR_TXFP; + } + else + { + CANx->MCR &= ~MCR_TXFP; + } + + /* Set the bit timing register */ + CANx->BTR = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) | ((uint32_t)CAN_InitStruct->CAN_SJW << 24) | + ((uint32_t)CAN_InitStruct->CAN_BS1 << 16) | ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) | + ((uint32_t)CAN_InitStruct->CAN_Prescaler - 1); + + /* Request leave initialisation */ + CANx->MCR &= ~MCR_INRQ; + + /* Wait the acknowledge */ + wait_ack = 0x00; + + while (((CANx->MSR & MSR_INAK) == MSR_INAK) && (wait_ack != INAK_TimeOut)) + { + wait_ack++; + } + + /* ...and check acknowledged */ + if ((CANx->MSR & MSR_INAK) == MSR_INAK) + { + InitStatus = CANINITFAILED; + } + else + { + InitStatus = CANINITOK ; + } + } + + /* At this step, return the status of initialization */ + return InitStatus; +} + +/** + * @brief Initializes the CAN peripheral according to the specified + * parameters in the CAN_FilterInitStruct. + * @param CAN_FilterInitStruct: pointer to a CAN_FilterInitTypeDef + * structure that contains the configuration information. + * @retval None. + */ +void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct) +{ + uint32_t filter_number_bit_pos = 0; + /* Check the parameters */ + assert_param(IS_CAN_FILTER_NUMBER(CAN_FilterInitStruct->CAN_FilterNumber)); + assert_param(IS_CAN_FILTER_MODE(CAN_FilterInitStruct->CAN_FilterMode)); + assert_param(IS_CAN_FILTER_SCALE(CAN_FilterInitStruct->CAN_FilterScale)); + assert_param(IS_CAN_FILTER_FIFO(CAN_FilterInitStruct->CAN_FilterFIFOAssignment)); + assert_param(IS_FUNCTIONAL_STATE(CAN_FilterInitStruct->CAN_FilterActivation)); + + filter_number_bit_pos = ((uint32_t)0x00000001) << CAN_FilterInitStruct->CAN_FilterNumber; + + /* Initialisation mode for the filter */ + CAN1->FMR |= FMR_FINIT; + + /* Filter Deactivation */ + CAN1->FA1R &= ~(uint32_t)filter_number_bit_pos; + + /* Filter Scale */ + if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit) + { + /* 16-bit scale for the filter */ + CAN1->FS1R &= ~(uint32_t)filter_number_bit_pos; + + /* First 16-bit identifier and First 16-bit mask */ + /* Or First 16-bit identifier and Second 16-bit identifier */ + CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); + + /* Second 16-bit identifier and Second 16-bit mask */ + /* Or Third 16-bit identifier and Fourth 16-bit identifier */ + CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh); + } + + if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit) + { + /* 32-bit scale for the filter */ + CAN1->FS1R |= filter_number_bit_pos; + /* 32-bit identifier or First 32-bit identifier */ + CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); + /* 32-bit mask or Second 32-bit identifier */ + CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow); + } + + /* Filter Mode */ + if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask) + { + /*Id/Mask mode for the filter*/ + CAN1->FM1R &= ~(uint32_t)filter_number_bit_pos; + } + else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ + { + /*Identifier list mode for the filter*/ + CAN1->FM1R |= (uint32_t)filter_number_bit_pos; + } + + /* Filter FIFO assignment */ + if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_FilterFIFO0) + { + /* FIFO 0 assignation for the filter */ + CAN1->FFA1R &= ~(uint32_t)filter_number_bit_pos; + } + + if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_FilterFIFO1) + { + /* FIFO 1 assignation for the filter */ + CAN1->FFA1R |= (uint32_t)filter_number_bit_pos; + } + + /* Filter activation */ + if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE) + { + CAN1->FA1R |= filter_number_bit_pos; + } + + /* Leave the initialisation mode for the filter */ + CAN1->FMR &= ~FMR_FINIT; +} + +/** + * @brief Fills each CAN_InitStruct member with its default value. + * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure which + * will be initialized. + * @retval None. + */ +void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct) +{ + /* Reset CAN init structure parameters values */ + /* Initialize the time triggered communication mode */ + CAN_InitStruct->CAN_TTCM = DISABLE; + /* Initialize the automatic bus-off management */ + CAN_InitStruct->CAN_ABOM = DISABLE; + /* Initialize the automatic wake-up mode */ + CAN_InitStruct->CAN_AWUM = DISABLE; + /* Initialize the no automatic retransmission */ + CAN_InitStruct->CAN_NART = DISABLE; + /* Initialize the receive FIFO locked mode */ + CAN_InitStruct->CAN_RFLM = DISABLE; + /* Initialize the transmit FIFO priority */ + CAN_InitStruct->CAN_TXFP = DISABLE; + /* Initialize the CAN_Mode member */ + CAN_InitStruct->CAN_Mode = CAN_Mode_Normal; + /* Initialize the CAN_SJW member */ + CAN_InitStruct->CAN_SJW = CAN_SJW_1tq; + /* Initialize the CAN_BS1 member */ + CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq; + /* Initialize the CAN_BS2 member */ + CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq; + /* Initialize the CAN_Prescaler member */ + CAN_InitStruct->CAN_Prescaler = 1; +} + +/** + * @brief Select the start bank filter for slave CAN. + * @note This function applies only to STM32 Connectivity line devices. + * @param CAN_BankNumber: Select the start slave bank filter from 1..27. + * @retval None. + */ +void CAN_SlaveStartBank(uint8_t CAN_BankNumber) +{ + /* Check the parameters */ + assert_param(IS_CAN_BANKNUMBER(CAN_BankNumber)); + /* enter Initialisation mode for the filter */ + CAN1->FMR |= FMR_FINIT; + /* Select the start slave bank */ + CAN1->FMR &= (uint32_t)0xFFFFC0F1 ; + CAN1->FMR |= (uint32_t)(CAN_BankNumber)<<8; + /* Leave Initialisation mode for the filter */ + CAN1->FMR &= ~FMR_FINIT; +} + +/** + * @brief Enables or disables the specified CAN interrupts. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param CAN_IT: specifies the CAN interrupt sources to be enabled or disabled. + * This parameter can be: CAN_IT_TME, CAN_IT_FMP0, CAN_IT_FF0, + * CAN_IT_FOV0, CAN_IT_FMP1, CAN_IT_FF1, + * CAN_IT_FOV1, CAN_IT_EWG, CAN_IT_EPV, + * CAN_IT_LEC, CAN_IT_ERR, CAN_IT_WKU or + * CAN_IT_SLK. + * @param NewState: new state of the CAN interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None. + */ +void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_ITConfig(CAN_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected CAN interrupt */ + CANx->IER |= CAN_IT; + } + else + { + /* Disable the selected CAN interrupt */ + CANx->IER &= ~CAN_IT; + } +} + +/** + * @brief Initiates the transmission of a message. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param TxMessage: pointer to a structure which contains CAN Id, CAN + * DLC and CAN datas. + * @retval The number of the mailbox that is used for transmission + * or CAN_NO_MB if there is no empty mailbox. + */ +uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage) +{ + uint8_t transmit_mailbox = 0; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_IDTYPE(TxMessage->IDE)); + assert_param(IS_CAN_RTR(TxMessage->RTR)); + assert_param(IS_CAN_DLC(TxMessage->DLC)); + + /* Select one empty transmit mailbox */ + if ((CANx->TSR&TSR_TME0) == TSR_TME0) + { + transmit_mailbox = 0; + } + else if ((CANx->TSR&TSR_TME1) == TSR_TME1) + { + transmit_mailbox = 1; + } + else if ((CANx->TSR&TSR_TME2) == TSR_TME2) + { + transmit_mailbox = 2; + } + else + { + transmit_mailbox = CAN_NO_MB; + } + + if (transmit_mailbox != CAN_NO_MB) + { + /* Set up the Id */ + CANx->sTxMailBox[transmit_mailbox].TIR &= TMIDxR_TXRQ; + if (TxMessage->IDE == CAN_ID_STD) + { + assert_param(IS_CAN_STDID(TxMessage->StdId)); + CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->StdId << 21) | TxMessage->RTR); + } + else + { + assert_param(IS_CAN_EXTID(TxMessage->ExtId)); + CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->ExtId<<3) | TxMessage->IDE | + TxMessage->RTR); + } + + + /* Set up the DLC */ + TxMessage->DLC &= (uint8_t)0x0000000F; + CANx->sTxMailBox[transmit_mailbox].TDTR &= (uint32_t)0xFFFFFFF0; + CANx->sTxMailBox[transmit_mailbox].TDTR |= TxMessage->DLC; + + /* Set up the data field */ + CANx->sTxMailBox[transmit_mailbox].TDLR = (((uint32_t)TxMessage->Data[3] << 24) | + ((uint32_t)TxMessage->Data[2] << 16) | + ((uint32_t)TxMessage->Data[1] << 8) | + ((uint32_t)TxMessage->Data[0])); + CANx->sTxMailBox[transmit_mailbox].TDHR = (((uint32_t)TxMessage->Data[7] << 24) | + ((uint32_t)TxMessage->Data[6] << 16) | + ((uint32_t)TxMessage->Data[5] << 8) | + ((uint32_t)TxMessage->Data[4])); + /* Request transmission */ + CANx->sTxMailBox[transmit_mailbox].TIR |= TMIDxR_TXRQ; + } + return transmit_mailbox; +} + +/** + * @brief Checks the transmission of a message. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param TransmitMailbox: the number of the mailbox that is used for transmission. + * @retval CANTXOK if the CAN driver transmits the message, CANTXFAILED in an other case. + */ +uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox) +{ + /* RQCP, TXOK and TME bits */ + uint8_t state = 0; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_TRANSMITMAILBOX(TransmitMailbox)); + switch (TransmitMailbox) + { + case (0): state |= (uint8_t)((CANx->TSR & TSR_RQCP0) << 2); + state |= (uint8_t)((CANx->TSR & TSR_TXOK0) >> 0); + state |= (uint8_t)((CANx->TSR & TSR_TME0) >> 26); + break; + case (1): state |= (uint8_t)((CANx->TSR & TSR_RQCP1) >> 6); + state |= (uint8_t)((CANx->TSR & TSR_TXOK1) >> 8); + state |= (uint8_t)((CANx->TSR & TSR_TME1) >> 27); + break; + case (2): state |= (uint8_t)((CANx->TSR & TSR_RQCP2) >> 14); + state |= (uint8_t)((CANx->TSR & TSR_TXOK2) >> 16); + state |= (uint8_t)((CANx->TSR & TSR_TME2) >> 28); + break; + default: + state = CANTXFAILED; + break; + } + switch (state) + { + /* transmit pending */ + case (0x0): state = CANTXPENDING; + break; + /* transmit failed */ + case (0x5): state = CANTXFAILED; + break; + /* transmit succedeed */ + case (0x7): state = CANTXOK; + break; + default: + state = CANTXFAILED; + break; + } + return state; +} + +/** + * @brief Cancels a transmit request. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param Mailbox: Mailbox number. + * @retval None. + */ +void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_TRANSMITMAILBOX(Mailbox)); + /* abort transmission */ + switch (Mailbox) + { + case (0): CANx->TSR |= TSR_ABRQ0; + break; + case (1): CANx->TSR |= TSR_ABRQ1; + break; + case (2): CANx->TSR |= TSR_ABRQ2; + break; + default: + break; + } +} + +/** + * @brief Releases a FIFO. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param FIFONumber: FIFO to release, CAN_FIFO0 or CAN_FIFO1. + * @retval None. + */ +void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_FIFO(FIFONumber)); + /* Release FIFO0 */ + if (FIFONumber == CAN_FIFO0) + { + CANx->RF0R = RF0R_RFOM0; + } + /* Release FIFO1 */ + else /* FIFONumber == CAN_FIFO1 */ + { + CANx->RF1R = RF1R_RFOM1; + } +} + +/** + * @brief Returns the number of pending messages. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. + * @retval NbMessage which is the number of pending message. + */ +uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber) +{ + uint8_t message_pending=0; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_FIFO(FIFONumber)); + if (FIFONumber == CAN_FIFO0) + { + message_pending = (uint8_t)(CANx->RF0R&(uint32_t)0x03); + } + else if (FIFONumber == CAN_FIFO1) + { + message_pending = (uint8_t)(CANx->RF1R&(uint32_t)0x03); + } + else + { + message_pending = 0; + } + return message_pending; +} + +/** + * @brief Receives a message. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. + * @param RxMessage: pointer to a structure receive message which + * contains CAN Id, CAN DLC, CAN datas and FMI number. + * @retval None. + */ +void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_FIFO(FIFONumber)); + /* Get the Id */ + RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RIR; + if (RxMessage->IDE == CAN_ID_STD) + { + RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 21); + } + else + { + RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 3); + } + + RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RIR; + /* Get the DLC */ + RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RDTR; + /* Get the FMI */ + RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDTR >> 8); + /* Get the data field */ + RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDLR; + RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 8); + RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 16); + RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 24); + RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDHR; + RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 8); + RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 16); + RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 24); + /* Release the FIFO */ + CAN_FIFORelease(CANx, FIFONumber); +} + +/** + * @brief Enables or disables the DBG Freeze for CAN. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param NewState: new state of the CAN peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None. + */ +void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable Debug Freeze */ + CANx->MCR |= MCR_DBF; + } + else + { + /* Disable Debug Freeze */ + CANx->MCR &= ~MCR_DBF; + } +} + +/** + * @brief Enters the low power mode. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @retval CANSLEEPOK if sleep entered, CANSLEEPFAILED in an other case. + */ +uint8_t CAN_Sleep(CAN_TypeDef* CANx) +{ + uint8_t sleepstatus = CANSLEEPFAILED; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Request Sleep mode */ + CANx->MCR = (((CANx->MCR) & (uint32_t)(~MCR_INRQ)) | MCR_SLEEP); + + /* Sleep mode status */ + if ((CANx->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) == CAN_MSR_SLAK) + { + /* Sleep mode not entered */ + sleepstatus = CANSLEEPOK; + } + /* At this step, sleep mode status */ + return (uint8_t)sleepstatus; +} + +/** + * @brief Wakes the CAN up. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @retval CANWAKEUPOK if sleep mode left, CANWAKEUPFAILED in an other case. + */ +uint8_t CAN_WakeUp(CAN_TypeDef* CANx) +{ + uint32_t wait_slak = SLAK_TimeOut ; + uint8_t wakeupstatus = CANWAKEUPFAILED; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Wake up request */ + CANx->MCR &= ~MCR_SLEEP; + + /* Sleep mode status */ + while(((CANx->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)&&(wait_slak!=0x00)) + { + wait_slak--; + } + if((CANx->MSR & CAN_MSR_SLAK) != CAN_MSR_SLAK) + { + /* Sleep mode exited */ + wakeupstatus = CANWAKEUPOK; + } + /* At this step, sleep mode status */ + return (uint8_t)wakeupstatus; +} + +/** + * @brief Checks whether the specified CAN flag is set or not. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param CAN_FLAG: specifies the flag to check. + * This parameter can be: CAN_FLAG_EWG, CAN_FLAG_EPV or CAN_FLAG_BOF. + * @retval The new state of CAN_FLAG (SET or RESET). + */ +FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_FLAG(CAN_FLAG)); + /* Check the status of the specified CAN flag */ + if ((CANx->ESR & CAN_FLAG) != (uint32_t)RESET) + { + /* CAN_FLAG is set */ + bitstatus = SET; + } + else + { + /* CAN_FLAG is reset */ + bitstatus = RESET; + } + /* Return the CAN_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the CAN's pending flags. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param CAN_FLAG: specifies the flag to clear. + * @retval None. + */ +void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_FLAG(CAN_FLAG)); + /* Clear the selected CAN flags */ + CANx->ESR &= ~CAN_FLAG; +} + +/** + * @brief Checks whether the specified CAN interrupt has occurred or not. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param CAN_IT: specifies the CAN interrupt source to check. + * This parameter can be: CAN_IT_RQCP0, CAN_IT_RQCP1, CAN_IT_RQCP2, + * CAN_IT_FF0, CAN_IT_FOV0, CAN_IT_FF1, + * CAN_IT_FOV1, CAN_IT_EWG, CAN_IT_EPV, + * CAN_IT_BOF, CAN_IT_WKU or CAN_IT_SLK. + * @retval The new state of CAN_IT (SET or RESET). + */ +ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT) +{ + ITStatus pendingbitstatus = RESET; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_ITStatus(CAN_IT)); + switch (CAN_IT) + { + case CAN_IT_RQCP0: + pendingbitstatus = CheckITStatus(CANx->TSR, TSR_RQCP0); + break; + case CAN_IT_RQCP1: + pendingbitstatus = CheckITStatus(CANx->TSR, TSR_RQCP1); + break; + case CAN_IT_RQCP2: + pendingbitstatus = CheckITStatus(CANx->TSR, TSR_RQCP2); + break; + case CAN_IT_FF0: + pendingbitstatus = CheckITStatus(CANx->RF0R, RF0R_FULL0); + break; + case CAN_IT_FOV0: + pendingbitstatus = CheckITStatus(CANx->RF0R, RF0R_FOVR0); + break; + case CAN_IT_FF1: + pendingbitstatus = CheckITStatus(CANx->RF1R, RF1R_FULL1); + break; + case CAN_IT_FOV1: + pendingbitstatus = CheckITStatus(CANx->RF1R, RF1R_FOVR1); + break; + case CAN_IT_EWG: + pendingbitstatus = CheckITStatus(CANx->ESR, ESR_EWGF); + break; + case CAN_IT_EPV: + pendingbitstatus = CheckITStatus(CANx->ESR, ESR_EPVF); + break; + case CAN_IT_BOF: + pendingbitstatus = CheckITStatus(CANx->ESR, ESR_BOFF); + break; + case CAN_IT_SLK: + pendingbitstatus = CheckITStatus(CANx->MSR, MSR_SLAKI); + break; + case CAN_IT_WKU: + pendingbitstatus = CheckITStatus(CANx->MSR, MSR_WKUI); + break; + default : + pendingbitstatus = RESET; + break; + } + /* Return the CAN_IT status */ + return pendingbitstatus; +} + +/** + * @brief Clears the CAN’s interrupt pending bits. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param CAN_IT: specifies the interrupt pending bit to clear. + * @retval None. + */ +void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_ITStatus(CAN_IT)); + switch (CAN_IT) + { + case CAN_IT_RQCP0: + CANx->TSR = TSR_RQCP0; /* rc_w1*/ + break; + case CAN_IT_RQCP1: + CANx->TSR = TSR_RQCP1; /* rc_w1*/ + break; + case CAN_IT_RQCP2: + CANx->TSR = TSR_RQCP2; /* rc_w1*/ + break; + case CAN_IT_FF0: + CANx->RF0R = RF0R_FULL0; /* rc_w1*/ + break; + case CAN_IT_FOV0: + CANx->RF0R = RF0R_FOVR0; /* rc_w1*/ + break; + case CAN_IT_FF1: + CANx->RF1R = RF1R_FULL1; /* rc_w1*/ + break; + case CAN_IT_FOV1: + CANx->RF1R = RF1R_FOVR1; /* rc_w1*/ + break; + case CAN_IT_EWG: + CANx->ESR &= ~ ESR_EWGF; /* rw */ + break; + case CAN_IT_EPV: + CANx->ESR &= ~ ESR_EPVF; /* rw */ + break; + case CAN_IT_BOF: + CANx->ESR &= ~ ESR_BOFF; /* rw */ + break; + case CAN_IT_WKU: + CANx->MSR = MSR_WKUI; /* rc_w1*/ + break; + case CAN_IT_SLK: + CANx->MSR = MSR_SLAKI; /* rc_w1*/ + break; + default : + break; + } +} + +/** + * @brief Checks whether the CAN interrupt has occurred or not. + * @param CAN_Reg: specifies the CAN interrupt register to check. + * @param It_Bit: specifies the interrupt source bit to check. + * @retval The new state of the CAN Interrupt (SET or RESET). + */ +static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit) +{ + ITStatus pendingbitstatus = RESET; + + if ((CAN_Reg & It_Bit) != (uint32_t)RESET) + { + /* CAN_IT is set */ + pendingbitstatus = SET; + } + else + { + /* CAN_IT is reset */ + pendingbitstatus = RESET; + } + return pendingbitstatus; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32f10x/stm32f10x_cec.c b/example/libs_stm/src/stm32f10x/stm32f10x_cec.c new file mode 100644 index 0000000..4ae2445 --- /dev/null +++ b/example/libs_stm/src/stm32f10x/stm32f10x_cec.c @@ -0,0 +1,432 @@ +/** + ****************************************************************************** + * @file stm32f10x_cec.c + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file provides all the CEC firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_cec.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup CEC + * @brief CEC driver modules + * @{ + */ + +/** @defgroup CEC_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + + +/** @defgroup CEC_Private_Defines + * @{ + */ + +/* ------------ CEC registers bit address in the alias region ----------- */ +#define CEC_OFFSET (CEC_BASE - PERIPH_BASE) + +/* --- CFGR Register ---*/ + +/* Alias word address of PE bit */ +#define CFGR_OFFSET (CEC_OFFSET + 0x00) +#define PE_BitNumber 0x00 +#define CFGR_PE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (PE_BitNumber * 4)) + +/* Alias word address of IE bit */ +#define IE_BitNumber 0x01 +#define CFGR_IE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (IE_BitNumber * 4)) + +/* --- CSR Register ---*/ + +/* Alias word address of TSOM bit */ +#define CSR_OFFSET (CEC_OFFSET + 0x10) +#define TSOM_BitNumber 0x00 +#define CSR_TSOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TSOM_BitNumber * 4)) + +/* Alias word address of TEOM bit */ +#define TEOM_BitNumber 0x01 +#define CSR_TEOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEOM_BitNumber * 4)) + +#define CFGR_CLEAR_Mask (uint8_t)(0xF3) /* CFGR register Mask */ +#define FLAG_Mask ((uint32_t)0x00FFFFFF) /* CEC FLAG mask */ + +/** + * @} + */ + + +/** @defgroup CEC_Private_Macros + * @{ + */ + +/** + * @} + */ + + +/** @defgroup CEC_Private_Variables + * @{ + */ + +/** + * @} + */ + + +/** @defgroup CEC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + + +/** @defgroup CEC_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the CEC peripheral registers to their default reset + * values. + * @param None + * @retval None + */ +void CEC_DeInit(void) +{ + /* Enable CEC reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, ENABLE); + /* Release CEC from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, DISABLE); +} + + +/** + * @brief Initializes the CEC peripheral according to the specified + * parameters in the CEC_InitStruct. + * @param CEC_InitStruct: pointer to an CEC_InitTypeDef structure that + * contains the configuration information for the specified + * CEC peripheral. + * @retval None + */ +void CEC_Init(CEC_InitTypeDef* CEC_InitStruct) +{ + uint16_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_CEC_BIT_TIMING_ERROR_MODE(CEC_InitStruct->CEC_BitTimingMode)); + assert_param(IS_CEC_BIT_PERIOD_ERROR_MODE(CEC_InitStruct->CEC_BitPeriodMode)); + + /*---------------------------- CEC CFGR Configuration -----------------*/ + /* Get the CEC CFGR value */ + tmpreg = CEC->CFGR; + + /* Clear BTEM and BPEM bits */ + tmpreg &= CFGR_CLEAR_Mask; + + /* Configure CEC: Bit Timing Error and Bit Period Error */ + tmpreg |= (uint16_t)(CEC_InitStruct->CEC_BitTimingMode | CEC_InitStruct->CEC_BitPeriodMode); + + /* Write to CEC CFGR register*/ + CEC->CFGR = tmpreg; + +} + +/** + * @brief Enables or disables the specified CEC peripheral. + * @param NewState: new state of the CEC peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void CEC_Cmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CFGR_PE_BB = (uint32_t)NewState; + + if(NewState == DISABLE) + { + /* Wait until the PE bit is cleared by hardware (Idle Line detected) */ + while((CEC->CFGR & CEC_CFGR_PE) != (uint32_t)RESET) + { + } + } +} + +/** + * @brief Enables or disables the CEC interrupt. + * @param NewState: new state of the CEC interrupt. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void CEC_ITConfig(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CFGR_IE_BB = (uint32_t)NewState; +} + +/** + * @brief Defines the Own Address of the CEC device. + * @param CEC_OwnAddress: The CEC own address + * @retval None + */ +void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress) +{ + /* Check the parameters */ + assert_param(IS_CEC_ADDRESS(CEC_OwnAddress)); + + /* Set the CEC own address */ + CEC->OAR = CEC_OwnAddress; +} + +/** + * @brief Sets the CEC prescaler value. + * @param CEC_Prescaler: CEC prescaler new value + * @retval None + */ +void CEC_SetPrescaler(uint16_t CEC_Prescaler) +{ + /* Check the parameters */ + assert_param(IS_CEC_PRESCALER(CEC_Prescaler)); + + /* Set the Prescaler value*/ + CEC->PRES = CEC_Prescaler; +} + +/** + * @brief Transmits single data through the CEC peripheral. + * @param Data: the data to transmit. + * @retval None + */ +void CEC_SendDataByte(uint8_t Data) +{ + /* Transmit Data */ + CEC->TXD = Data ; +} + + +/** + * @brief Returns the most recent received data by the CEC peripheral. + * @param None + * @retval The received data. + */ +uint8_t CEC_ReceiveDataByte(void) +{ + /* Receive Data */ + return (uint8_t)(CEC->RXD); +} + +/** + * @brief Starts a new message. + * @param None + * @retval None + */ +void CEC_StartOfMessage(void) +{ + /* Starts of new message */ + *(__IO uint32_t *) CSR_TSOM_BB = (uint32_t)0x1; +} + +/** + * @brief Transmits message with or without an EOM bit. + * @param NewState: new state of the CEC Tx End Of Message. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void CEC_EndOfMessageCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + /* The data byte will be transmitted with or without an EOM bit*/ + *(__IO uint32_t *) CSR_TEOM_BB = (uint32_t)NewState; +} + +/** + * @brief Gets the CEC flag status + * @param CEC_FLAG: specifies the CEC flag to check. + * This parameter can be one of the following values: + * @arg CEC_FLAG_BTE: Bit Timing Error + * @arg CEC_FLAG_BPE: Bit Period Error + * @arg CEC_FLAG_RBTFE: Rx Block Transfer Finished Error + * @arg CEC_FLAG_SBE: Start Bit Error + * @arg CEC_FLAG_ACKE: Block Acknowledge Error + * @arg CEC_FLAG_LINE: Line Error + * @arg CEC_FLAG_TBTFE: Tx Block Transfer Finsihed Error + * @arg CEC_FLAG_TEOM: Tx End Of Message + * @arg CEC_FLAG_TERR: Tx Error + * @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished + * @arg CEC_FLAG_RSOM: Rx Start Of Message + * @arg CEC_FLAG_REOM: Rx End Of Message + * @arg CEC_FLAG_RERR: Rx Error + * @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished + * @retval The new state of CEC_FLAG (SET or RESET) + */ +FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG) +{ + FlagStatus bitstatus = RESET; + uint32_t cecreg = 0, cecbase = 0; + + /* Check the parameters */ + assert_param(IS_CEC_GET_FLAG(CEC_FLAG)); + + /* Get the CEC peripheral base address */ + cecbase = (uint32_t)(CEC_BASE); + + /* Read flag register index */ + cecreg = CEC_FLAG >> 28; + + /* Get bit[23:0] of the flag */ + CEC_FLAG &= FLAG_Mask; + + if(cecreg != 0) + { + /* Flag in CEC ESR Register */ + CEC_FLAG = (uint32_t)(CEC_FLAG >> 16); + + /* Get the CEC ESR register address */ + cecbase += 0xC; + } + else + { + /* Get the CEC CSR register address */ + cecbase += 0x10; + } + + if(((*(__IO uint32_t *)cecbase) & CEC_FLAG) != (uint32_t)RESET) + { + /* CEC_FLAG is set */ + bitstatus = SET; + } + else + { + /* CEC_FLAG is reset */ + bitstatus = RESET; + } + + /* Return the CEC_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the CEC's pending flags. + * @param CEC_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg CEC_FLAG_TERR: Tx Error + * @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished + * @arg CEC_FLAG_RSOM: Rx Start Of Message + * @arg CEC_FLAG_REOM: Rx End Of Message + * @arg CEC_FLAG_RERR: Rx Error + * @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished + * @retval None + */ +void CEC_ClearFlag(uint32_t CEC_FLAG) +{ + uint32_t tmp = 0x0; + + /* Check the parameters */ + assert_param(IS_CEC_CLEAR_FLAG(CEC_FLAG)); + + tmp = CEC->CSR & 0x2; + + /* Clear the selected CEC flags */ + CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_FLAG) & 0xFFFFFFFC) | tmp); +} + +/** + * @brief Checks whether the specified CEC interrupt has occurred or not. + * @param CEC_IT: specifies the CEC interrupt source to check. + * This parameter can be one of the following values: + * @arg CEC_IT_TERR: Tx Error + * @arg CEC_IT_TBTF: Tx Block Transfer Finished + * @arg CEC_IT_RERR: Rx Error + * @arg CEC_IT_RBTF: Rx Block Transfer Finished + * @retval The new state of CEC_IT (SET or RESET). + */ +ITStatus CEC_GetITStatus(uint8_t CEC_IT) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_CEC_GET_IT(CEC_IT)); + + /* Get the CEC IT enable bit status */ + enablestatus = (CEC->CFGR & (uint8_t)CEC_CFGR_IE) ; + + /* Check the status of the specified CEC interrupt */ + if (((CEC->CSR & CEC_IT) != (uint32_t)RESET) && enablestatus) + { + /* CEC_IT is set */ + bitstatus = SET; + } + else + { + /* CEC_IT is reset */ + bitstatus = RESET; + } + /* Return the CEC_IT status */ + return bitstatus; +} + +/** + * @brief Clears the CEC's interrupt pending bits. + * @param CEC_IT: specifies the CEC interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg CEC_IT_TERR: Tx Error + * @arg CEC_IT_TBTF: Tx Block Transfer Finished + * @arg CEC_IT_RERR: Rx Error + * @arg CEC_IT_RBTF: Rx Block Transfer Finished + * @retval None + */ +void CEC_ClearITPendingBit(uint16_t CEC_IT) +{ + uint32_t tmp = 0x0; + + /* Check the parameters */ + assert_param(IS_CEC_GET_IT(CEC_IT)); + + tmp = CEC->CSR & 0x2; + + /* Clear the selected CEC interrupt pending bits */ + CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_IT) & 0xFFFFFFFC) | tmp); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32f10x/stm32f10x_crc.c b/example/libs_stm/src/stm32f10x/stm32f10x_crc.c new file mode 100644 index 0000000..c9291f4 --- /dev/null +++ b/example/libs_stm/src/stm32f10x/stm32f10x_crc.c @@ -0,0 +1,163 @@ +/** + ****************************************************************************** + * @file stm32f10x_crc.c + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file provides all the CRC firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_crc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup CRC + * @brief CRC driver modules + * @{ + */ + +/** @defgroup CRC_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup CRC_Private_Defines + * @{ + */ + +/* CR register bit mask */ + +#define CR_RESET_Set ((uint32_t)0x00000001) + +/** + * @} + */ + +/** @defgroup CRC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup CRC_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup CRC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup CRC_Private_Functions + * @{ + */ + +/** + * @brief Resets the CRC Data register (DR). + * @param None + * @retval None + */ +void CRC_ResetDR(void) +{ + /* Reset CRC generator */ + CRC->CR = CR_RESET_Set; +} + +/** + * @brief Computes the 32-bit CRC of a given data word(32-bit). + * @param Data: data word(32-bit) to compute its CRC + * @retval 32-bit CRC + */ +uint32_t CRC_CalcCRC(uint32_t Data) +{ + CRC->DR = Data; + + return (CRC->DR); +} + +/** + * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit). + * @param pBuffer: pointer to the buffer containing the data to be computed + * @param BufferLength: length of the buffer to be computed + * @retval 32-bit CRC + */ +uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength) +{ + uint32_t index = 0; + + for(index = 0; index < BufferLength; index++) + { + CRC->DR = pBuffer[index]; + } + return (CRC->DR); +} + +/** + * @brief Returns the current CRC value. + * @param None + * @retval 32-bit CRC + */ +uint32_t CRC_GetCRC(void) +{ + return (CRC->DR); +} + +/** + * @brief Stores a 8-bit data in the Independent Data(ID) register. + * @param IDValue: 8-bit value to be stored in the ID register + * @retval None + */ +void CRC_SetIDRegister(uint8_t IDValue) +{ + CRC->IDR = IDValue; +} + +/** + * @brief Returns the 8-bit data stored in the Independent Data(ID) register + * @param None + * @retval 8-bit value of the ID register + */ +uint8_t CRC_GetIDRegister(void) +{ + return (CRC->IDR); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32f10x/stm32f10x_dac.c b/example/libs_stm/src/stm32f10x/stm32f10x_dac.c new file mode 100644 index 0000000..e20b4a9 --- /dev/null +++ b/example/libs_stm/src/stm32f10x/stm32f10x_dac.c @@ -0,0 +1,579 @@ +/** + ****************************************************************************** + * @file stm32f10x_dac.c + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file provides all the DAC firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_dac.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup DAC + * @brief DAC driver modules + * @{ + */ + +/** @defgroup DAC_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup DAC_Private_Defines + * @{ + */ + +/* DAC EN mask */ +#define CR_EN_Set ((uint32_t)0x00000001) + +/* DAC DMAEN mask */ +#define CR_DMAEN_Set ((uint32_t)0x00001000) + +/* CR register Mask */ +#define CR_CLEAR_Mask ((uint32_t)0x00000FFE) + +/* DAC SWTRIG mask */ +#define SWTRIGR_SWTRIG_Set ((uint32_t)0x00000001) + +/* DAC Dual Channels SWTRIG masks */ +#define DUAL_SWTRIG_Set ((uint32_t)0x00000003) +#define DUAL_SWTRIG_Reset ((uint32_t)0xFFFFFFFC) + +/* DHR registers offsets */ +#define DHR12R1_Offset ((uint32_t)0x00000008) +#define DHR12R2_Offset ((uint32_t)0x00000014) +#define DHR12RD_Offset ((uint32_t)0x00000020) + +/* DOR register offset */ +#define DOR_Offset ((uint32_t)0x0000002C) +/** + * @} + */ + +/** @defgroup DAC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup DAC_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup DAC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup DAC_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the DAC peripheral registers to their default reset values. + * @param None + * @retval None + */ +void DAC_DeInit(void) +{ + /* Enable DAC reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE); + /* Release DAC from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE); +} + +/** + * @brief Initializes the DAC peripheral according to the specified + * parameters in the DAC_InitStruct. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that + * contains the configuration information for the specified DAC channel. + * @retval None + */ +void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0; + /* Check the DAC parameters */ + assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger)); + assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration)); + assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude)); + assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer)); +/*---------------------------- DAC CR Configuration --------------------------*/ + /* Get the DAC CR value */ + tmpreg1 = DAC->CR; + /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */ + tmpreg1 &= ~(CR_CLEAR_Mask << DAC_Channel); + /* Configure for the selected DAC channel: buffer output, trigger, wave genration, + mask/amplitude for wave genration */ + /* Set TSELx and TENx bits according to DAC_Trigger value */ + /* Set WAVEx bits according to DAC_WaveGeneration value */ + /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */ + /* Set BOFFx bit according to DAC_OutputBuffer value */ + tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration | + DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer); + /* Calculate CR register value depending on DAC_Channel */ + tmpreg1 |= tmpreg2 << DAC_Channel; + /* Write to DAC CR */ + DAC->CR = tmpreg1; +} + +/** + * @brief Fills each DAC_InitStruct member with its default value. + * @param DAC_InitStruct : pointer to a DAC_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct) +{ +/*--------------- Reset DAC init structure parameters values -----------------*/ + /* Initialize the DAC_Trigger member */ + DAC_InitStruct->DAC_Trigger = DAC_Trigger_None; + /* Initialize the DAC_WaveGeneration member */ + DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None; + /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */ + DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0; + /* Initialize the DAC_OutputBuffer member */ + DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable; +} + +/** + * @brief Enables or disables the specified DAC channel. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param NewState: new state of the DAC channel. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected DAC channel */ + DAC->CR |= CR_EN_Set << DAC_Channel; + } + else + { + /* Disable the selected DAC channel */ + DAC->CR &= ~(CR_EN_Set << DAC_Channel); + } +} +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) +/** + * @brief Enables or disables the specified DAC interrupts. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_IT: specifies the DAC interrupt sources to be enabled or disabled. + * This parameter can be the following values: + * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask + * @param NewState: new state of the specified DAC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_DAC_IT(DAC_IT)); + + if (NewState != DISABLE) + { + /* Enable the selected DAC interrupts */ + DAC->CR |= (DAC_IT << DAC_Channel); + } + else + { + /* Disable the selected DAC interrupts */ + DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel)); + } +} +#endif + +/** + * @brief Enables or disables the specified DAC channel DMA request. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param NewState: new state of the selected DAC channel DMA request. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected DAC channel DMA request */ + DAC->CR |= CR_DMAEN_Set << DAC_Channel; + } + else + { + /* Disable the selected DAC channel DMA request */ + DAC->CR &= ~(CR_DMAEN_Set << DAC_Channel); + } +} + +/** + * @brief Enables or disables the selected DAC channel software trigger. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param NewState: new state of the selected DAC channel software trigger. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable software trigger for the selected DAC channel */ + DAC->SWTRIGR |= SWTRIGR_SWTRIG_Set << (DAC_Channel >> 4); + } + else + { + /* Disable software trigger for the selected DAC channel */ + DAC->SWTRIGR &= ~(SWTRIGR_SWTRIG_Set << (DAC_Channel >> 4)); + } +} + +/** + * @brief Enables or disables simultaneously the two DAC channels software + * triggers. + * @param NewState: new state of the DAC channels software triggers. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DAC_DualSoftwareTriggerCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable software trigger for both DAC channels */ + DAC->SWTRIGR |= DUAL_SWTRIG_Set ; + } + else + { + /* Disable software trigger for both DAC channels */ + DAC->SWTRIGR &= DUAL_SWTRIG_Reset; + } +} + +/** + * @brief Enables or disables the selected DAC channel wave generation. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_Wave: Specifies the wave type to enable or disable. + * This parameter can be one of the following values: + * @arg DAC_Wave_Noise: noise wave generation + * @arg DAC_Wave_Triangle: triangle wave generation + * @param NewState: new state of the selected DAC channel wave generation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_DAC_WAVE(DAC_Wave)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected wave generation for the selected DAC channel */ + DAC->CR |= DAC_Wave << DAC_Channel; + } + else + { + /* Disable the selected wave generation for the selected DAC channel */ + DAC->CR &= ~(DAC_Wave << DAC_Channel); + } +} + +/** + * @brief Set the specified data holding register value for DAC channel1. + * @param DAC_Align: Specifies the data alignement for DAC channel1. + * This parameter can be one of the following values: + * @arg DAC_Align_8b_R: 8bit right data alignement selected + * @arg DAC_Align_12b_L: 12bit left data alignement selected + * @arg DAC_Align_12b_R: 12bit right data alignement selected + * @param Data : Data to be loaded in the selected data holding register. + * @retval None + */ +void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_DAC_ALIGN(DAC_Align)); + assert_param(IS_DAC_DATA(Data)); + + tmp = (uint32_t)DAC_BASE; + tmp += DHR12R1_Offset + DAC_Align; + + /* Set the DAC channel1 selected data holding register */ + *(__IO uint32_t *) tmp = Data; +} + +/** + * @brief Set the specified data holding register value for DAC channel2. + * @param DAC_Align: Specifies the data alignement for DAC channel2. + * This parameter can be one of the following values: + * @arg DAC_Align_8b_R: 8bit right data alignement selected + * @arg DAC_Align_12b_L: 12bit left data alignement selected + * @arg DAC_Align_12b_R: 12bit right data alignement selected + * @param Data : Data to be loaded in the selected data holding register. + * @retval None + */ +void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_DAC_ALIGN(DAC_Align)); + assert_param(IS_DAC_DATA(Data)); + + tmp = (uint32_t)DAC_BASE; + tmp += DHR12R2_Offset + DAC_Align; + + /* Set the DAC channel2 selected data holding register */ + *(__IO uint32_t *)tmp = Data; +} + +/** + * @brief Set the specified data holding register value for dual channel + * DAC. + * @param DAC_Align: Specifies the data alignement for dual channel DAC. + * This parameter can be one of the following values: + * @arg DAC_Align_8b_R: 8bit right data alignement selected + * @arg DAC_Align_12b_L: 12bit left data alignement selected + * @arg DAC_Align_12b_R: 12bit right data alignement selected + * @param Data2: Data for DAC Channel2 to be loaded in the selected data + * holding register. + * @param Data1: Data for DAC Channel1 to be loaded in the selected data + * holding register. + * @retval None + */ +void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1) +{ + uint32_t data = 0, tmp = 0; + + /* Check the parameters */ + assert_param(IS_DAC_ALIGN(DAC_Align)); + assert_param(IS_DAC_DATA(Data1)); + assert_param(IS_DAC_DATA(Data2)); + + /* Calculate and set dual DAC data holding register value */ + if (DAC_Align == DAC_Align_8b_R) + { + data = ((uint32_t)Data2 << 8) | Data1; + } + else + { + data = ((uint32_t)Data2 << 16) | Data1; + } + + tmp = (uint32_t)DAC_BASE; + tmp += DHR12RD_Offset + DAC_Align; + + /* Set the dual DAC selected data holding register */ + *(__IO uint32_t *)tmp = data; +} + +/** + * @brief Returns the last data output value of the selected DAC cahnnel. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @retval The selected DAC channel data output value. + */ +uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + + tmp = (uint32_t) DAC_BASE ; + tmp += DOR_Offset + ((uint32_t)DAC_Channel >> 2); + + /* Returns the DAC channel data output register value */ + return (uint16_t) (*(__IO uint32_t*) tmp); +} + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) +/** + * @brief Checks whether the specified DAC flag is set or not. + * @param DAC_Channel: thee selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_FLAG: specifies the flag to check. + * This parameter can be only of the following value: + * @arg DAC_FLAG_DMAUDR: DMA underrun flag + * @retval The new state of DAC_FLAG (SET or RESET). + */ +FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_DAC_FLAG(DAC_FLAG)); + + /* Check the status of the specified DAC flag */ + if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET) + { + /* DAC_FLAG is set */ + bitstatus = SET; + } + else + { + /* DAC_FLAG is reset */ + bitstatus = RESET; + } + /* Return the DAC_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the DAC channelx's pending flags. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_FLAG: specifies the flag to clear. + * This parameter can be of the following value: + * @arg DAC_FLAG_DMAUDR: DMA underrun flag + * @retval None + */ +void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_DAC_FLAG(DAC_FLAG)); + + /* Clear the selected DAC flags */ + DAC->SR = (DAC_FLAG << DAC_Channel); +} + +/** + * @brief Checks whether the specified DAC interrupt has occurred or not. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_IT: specifies the DAC interrupt source to check. + * This parameter can be the following values: + * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask + * @retval The new state of DAC_IT (SET or RESET). + */ +ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_DAC_IT(DAC_IT)); + + /* Get the DAC_IT enable bit status */ + enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ; + + /* Check the status of the specified DAC interrupt */ + if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus) + { + /* DAC_IT is set */ + bitstatus = SET; + } + else + { + /* DAC_IT is reset */ + bitstatus = RESET; + } + /* Return the DAC_IT status */ + return bitstatus; +} + +/** + * @brief Clears the DAC channelx’s interrupt pending bits. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_IT: specifies the DAC interrupt pending bit to clear. + * This parameter can be the following values: + * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask + * @retval None + */ +void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_DAC_IT(DAC_IT)); + + /* Clear the selected DAC interrupt pending bits */ + DAC->SR = (DAC_IT << DAC_Channel); +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32f10x/stm32f10x_dbgmcu.c b/example/libs_stm/src/stm32f10x/stm32f10x_dbgmcu.c new file mode 100644 index 0000000..6cfceba --- /dev/null +++ b/example/libs_stm/src/stm32f10x/stm32f10x_dbgmcu.c @@ -0,0 +1,161 @@ +/** + ****************************************************************************** + * @file stm32f10x_dbgmcu.c + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file provides all the DBGMCU firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_dbgmcu.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup DBGMCU + * @brief DBGMCU driver modules + * @{ + */ + +/** @defgroup DBGMCU_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup DBGMCU_Private_Defines + * @{ + */ + +#define IDCODE_DEVID_Mask ((uint32_t)0x00000FFF) +/** + * @} + */ + +/** @defgroup DBGMCU_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup DBGMCU_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup DBGMCU_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup DBGMCU_Private_Functions + * @{ + */ + +/** + * @brief Returns the device revision identifier. + * @param None + * @retval Device revision identifier + */ +uint32_t DBGMCU_GetREVID(void) +{ + return(DBGMCU->IDCODE >> 16); +} + +/** + * @brief Returns the device identifier. + * @param None + * @retval Device identifier + */ +uint32_t DBGMCU_GetDEVID(void) +{ + return(DBGMCU->IDCODE & IDCODE_DEVID_Mask); +} + +/** + * @brief Configures the specified peripheral and low power mode behavior + * when the MCU under Debug mode. + * @param DBGMCU_Periph: specifies the peripheral and low power mode. + * This parameter can be any combination of the following values: + * @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode + * @arg DBGMCU_STOP: Keep debugger connection during STOP mode + * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode + * @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted + * @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted + * @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted + * @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted + * @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted + * @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted + * @arg DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted + * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted + * @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted + * @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted + * @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted + * @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted + * @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted + * @arg DBGMCU_CAN2_STOP: Debug CAN2 stopped when Core is halted + * @arg DBGMCU_TIM15_STOP: TIM15 counter stopped when Core is halted + * @arg DBGMCU_TIM16_STOP: TIM16 counter stopped when Core is halted + * @arg DBGMCU_TIM17_STOP: TIM17 counter stopped when Core is halted + * @arg DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted + * @arg DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted + * @arg DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted + * @arg DBGMCU_TIM12_STOP: TIM12 counter stopped when Core is halted + * @arg DBGMCU_TIM13_STOP: TIM13 counter stopped when Core is halted + * @arg DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted + * @param NewState: new state of the specified peripheral in Debug mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + DBGMCU->CR |= DBGMCU_Periph; + } + else + { + DBGMCU->CR &= ~DBGMCU_Periph; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32f10x/stm32f10x_dma.c b/example/libs_stm/src/stm32f10x/stm32f10x_dma.c new file mode 100644 index 0000000..aa890c6 --- /dev/null +++ b/example/libs_stm/src/stm32f10x/stm32f10x_dma.c @@ -0,0 +1,693 @@ +/** + ****************************************************************************** + * @file stm32f10x_dma.c + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file provides all the DMA firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_dma.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup DMA + * @brief DMA driver modules + * @{ + */ + +/** @defgroup DMA_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + +/** @defgroup DMA_Private_Defines + * @{ + */ + +/* DMA ENABLE mask */ +#define CCR_ENABLE_Set ((uint32_t)0x00000001) +#define CCR_ENABLE_Reset ((uint32_t)0xFFFFFFFE) + +/* DMA1 Channelx interrupt pending bit masks */ +#define DMA1_Channel1_IT_Mask ((uint32_t)0x0000000F) +#define DMA1_Channel2_IT_Mask ((uint32_t)0x000000F0) +#define DMA1_Channel3_IT_Mask ((uint32_t)0x00000F00) +#define DMA1_Channel4_IT_Mask ((uint32_t)0x0000F000) +#define DMA1_Channel5_IT_Mask ((uint32_t)0x000F0000) +#define DMA1_Channel6_IT_Mask ((uint32_t)0x00F00000) +#define DMA1_Channel7_IT_Mask ((uint32_t)0x0F000000) + +/* DMA2 Channelx interrupt pending bit masks */ +#define DMA2_Channel1_IT_Mask ((uint32_t)0x0000000F) +#define DMA2_Channel2_IT_Mask ((uint32_t)0x000000F0) +#define DMA2_Channel3_IT_Mask ((uint32_t)0x00000F00) +#define DMA2_Channel4_IT_Mask ((uint32_t)0x0000F000) +#define DMA2_Channel5_IT_Mask ((uint32_t)0x000F0000) + +/* DMA2 FLAG mask */ +#define FLAG_Mask ((uint32_t)0x10000000) + +/* DMA registers Masks */ +#define CCR_CLEAR_Mask ((uint32_t)0xFFFF800F) + +/** + * @} + */ + +/** @defgroup DMA_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup DMA_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup DMA_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup DMA_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the DMAy Channelx registers to their default reset + * values. + * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and + * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. + * @retval None + */ +void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + /* Disable the selected DMAy Channelx */ + DMAy_Channelx->CCR &= CCR_ENABLE_Reset; + /* Reset DMAy Channelx control register */ + DMAy_Channelx->CCR = 0; + + /* Reset DMAy Channelx remaining bytes register */ + DMAy_Channelx->CNDTR = 0; + + /* Reset DMAy Channelx peripheral address register */ + DMAy_Channelx->CPAR = 0; + + /* Reset DMAy Channelx memory address register */ + DMAy_Channelx->CMAR = 0; + + if (DMAy_Channelx == DMA1_Channel1) + { + /* Reset interrupt pending bits for DMA1 Channel1 */ + DMA1->IFCR |= DMA1_Channel1_IT_Mask; + } + else if (DMAy_Channelx == DMA1_Channel2) + { + /* Reset interrupt pending bits for DMA1 Channel2 */ + DMA1->IFCR |= DMA1_Channel2_IT_Mask; + } + else if (DMAy_Channelx == DMA1_Channel3) + { + /* Reset interrupt pending bits for DMA1 Channel3 */ + DMA1->IFCR |= DMA1_Channel3_IT_Mask; + } + else if (DMAy_Channelx == DMA1_Channel4) + { + /* Reset interrupt pending bits for DMA1 Channel4 */ + DMA1->IFCR |= DMA1_Channel4_IT_Mask; + } + else if (DMAy_Channelx == DMA1_Channel5) + { + /* Reset interrupt pending bits for DMA1 Channel5 */ + DMA1->IFCR |= DMA1_Channel5_IT_Mask; + } + else if (DMAy_Channelx == DMA1_Channel6) + { + /* Reset interrupt pending bits for DMA1 Channel6 */ + DMA1->IFCR |= DMA1_Channel6_IT_Mask; + } + else if (DMAy_Channelx == DMA1_Channel7) + { + /* Reset interrupt pending bits for DMA1 Channel7 */ + DMA1->IFCR |= DMA1_Channel7_IT_Mask; + } + else if (DMAy_Channelx == DMA2_Channel1) + { + /* Reset interrupt pending bits for DMA2 Channel1 */ + DMA2->IFCR |= DMA2_Channel1_IT_Mask; + } + else if (DMAy_Channelx == DMA2_Channel2) + { + /* Reset interrupt pending bits for DMA2 Channel2 */ + DMA2->IFCR |= DMA2_Channel2_IT_Mask; + } + else if (DMAy_Channelx == DMA2_Channel3) + { + /* Reset interrupt pending bits for DMA2 Channel3 */ + DMA2->IFCR |= DMA2_Channel3_IT_Mask; + } + else if (DMAy_Channelx == DMA2_Channel4) + { + /* Reset interrupt pending bits for DMA2 Channel4 */ + DMA2->IFCR |= DMA2_Channel4_IT_Mask; + } + else + { + if (DMAy_Channelx == DMA2_Channel5) + { + /* Reset interrupt pending bits for DMA2 Channel5 */ + DMA2->IFCR |= DMA2_Channel5_IT_Mask; + } + } +} + +/** + * @brief Initializes the DMAy Channelx according to the specified + * parameters in the DMA_InitStruct. + * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and + * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. + * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that + * contains the configuration information for the specified DMA Channel. + * @retval None + */ +void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR)); + assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize)); + assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc)); + assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc)); + assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize)); + assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize)); + assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode)); + assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority)); + assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M)); + +/*--------------------------- DMAy Channelx CCR Configuration -----------------*/ + /* Get the DMAy_Channelx CCR value */ + tmpreg = DMAy_Channelx->CCR; + /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */ + tmpreg &= CCR_CLEAR_Mask; + /* Configure DMAy Channelx: data transfer, data size, priority level and mode */ + /* Set DIR bit according to DMA_DIR value */ + /* Set CIRC bit according to DMA_Mode value */ + /* Set PINC bit according to DMA_PeripheralInc value */ + /* Set MINC bit according to DMA_MemoryInc value */ + /* Set PSIZE bits according to DMA_PeripheralDataSize value */ + /* Set MSIZE bits according to DMA_MemoryDataSize value */ + /* Set PL bits according to DMA_Priority value */ + /* Set the MEM2MEM bit according to DMA_M2M value */ + tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode | + DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc | + DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize | + DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M; + + /* Write to DMAy Channelx CCR */ + DMAy_Channelx->CCR = tmpreg; + +/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/ + /* Write to DMAy Channelx CNDTR */ + DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize; + +/*--------------------------- DMAy Channelx CPAR Configuration ----------------*/ + /* Write to DMAy Channelx CPAR */ + DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr; + +/*--------------------------- DMAy Channelx CMAR Configuration ----------------*/ + /* Write to DMAy Channelx CMAR */ + DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr; +} + +/** + * @brief Fills each DMA_InitStruct member with its default value. + * @param DMA_InitStruct : pointer to a DMA_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct) +{ +/*-------------- Reset DMA init structure parameters values ------------------*/ + /* Initialize the DMA_PeripheralBaseAddr member */ + DMA_InitStruct->DMA_PeripheralBaseAddr = 0; + /* Initialize the DMA_MemoryBaseAddr member */ + DMA_InitStruct->DMA_MemoryBaseAddr = 0; + /* Initialize the DMA_DIR member */ + DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC; + /* Initialize the DMA_BufferSize member */ + DMA_InitStruct->DMA_BufferSize = 0; + /* Initialize the DMA_PeripheralInc member */ + DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable; + /* Initialize the DMA_MemoryInc member */ + DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable; + /* Initialize the DMA_PeripheralDataSize member */ + DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; + /* Initialize the DMA_MemoryDataSize member */ + DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; + /* Initialize the DMA_Mode member */ + DMA_InitStruct->DMA_Mode = DMA_Mode_Normal; + /* Initialize the DMA_Priority member */ + DMA_InitStruct->DMA_Priority = DMA_Priority_Low; + /* Initialize the DMA_M2M member */ + DMA_InitStruct->DMA_M2M = DMA_M2M_Disable; +} + +/** + * @brief Enables or disables the specified DMAy Channelx. + * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and + * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. + * @param NewState: new state of the DMAy Channelx. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DMAy Channelx */ + DMAy_Channelx->CCR |= CCR_ENABLE_Set; + } + else + { + /* Disable the selected DMAy Channelx */ + DMAy_Channelx->CCR &= CCR_ENABLE_Reset; + } +} + +/** + * @brief Enables or disables the specified DMAy Channelx interrupts. + * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and + * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. + * @param DMA_IT: specifies the DMA interrupts sources to be enabled + * or disabled. + * This parameter can be any combination of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask + * @arg DMA_IT_HT: Half transfer interrupt mask + * @arg DMA_IT_TE: Transfer error interrupt mask + * @param NewState: new state of the specified DMA interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + assert_param(IS_DMA_CONFIG_IT(DMA_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected DMA interrupts */ + DMAy_Channelx->CCR |= DMA_IT; + } + else + { + /* Disable the selected DMA interrupts */ + DMAy_Channelx->CCR &= ~DMA_IT; + } +} + +/** + * @brief Returns the number of remaining data units in the current + * DMAy Channelx transfer. + * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and + * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. + * @retval The number of remaining data units in the current DMAy Channelx + * transfer. + */ +uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + /* Return the number of remaining data units for DMAy Channelx */ + return ((uint16_t)(DMAy_Channelx->CNDTR)); +} + +/** + * @brief Checks whether the specified DMAy Channelx flag is set or not. + * @param DMA_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag. + * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag. + * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag. + * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag. + * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag. + * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag. + * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag. + * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag. + * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag. + * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag. + * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag. + * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag. + * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag. + * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag. + * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag. + * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag. + * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag. + * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag. + * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag. + * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag. + * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag. + * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag. + * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag. + * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag. + * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag. + * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag. + * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag. + * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag. + * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag. + * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag. + * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag. + * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag. + * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag. + * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag. + * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag. + * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag. + * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag. + * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag. + * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag. + * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag. + * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag. + * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag. + * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag. + * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag. + * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag. + * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag. + * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag. + * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag. + * @retval The new state of DMA_FLAG (SET or RESET). + */ +FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG) +{ + FlagStatus bitstatus = RESET; + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_DMA_GET_FLAG(DMA_FLAG)); + + /* Calculate the used DMA */ + if ((DMA_FLAG & FLAG_Mask) != (uint32_t)RESET) + { + /* Get DMA2 ISR register value */ + tmpreg = DMA2->ISR ; + } + else + { + /* Get DMA1 ISR register value */ + tmpreg = DMA1->ISR ; + } + + /* Check the status of the specified DMA flag */ + if ((tmpreg & DMA_FLAG) != (uint32_t)RESET) + { + /* DMA_FLAG is set */ + bitstatus = SET; + } + else + { + /* DMA_FLAG is reset */ + bitstatus = RESET; + } + + /* Return the DMA_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the DMAy Channelx's pending flags. + * @param DMA_FLAG: specifies the flag to clear. + * This parameter can be any combination (for the same DMA) of the following values: + * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag. + * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag. + * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag. + * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag. + * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag. + * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag. + * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag. + * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag. + * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag. + * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag. + * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag. + * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag. + * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag. + * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag. + * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag. + * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag. + * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag. + * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag. + * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag. + * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag. + * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag. + * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag. + * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag. + * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag. + * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag. + * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag. + * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag. + * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag. + * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag. + * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag. + * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag. + * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag. + * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag. + * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag. + * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag. + * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag. + * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag. + * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag. + * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag. + * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag. + * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag. + * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag. + * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag. + * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag. + * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag. + * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag. + * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag. + * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag. + * @retval None + */ +void DMA_ClearFlag(uint32_t DMA_FLAG) +{ + /* Check the parameters */ + assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG)); + /* Calculate the used DMA */ + + if ((DMA_FLAG & FLAG_Mask) != (uint32_t)RESET) + { + /* Clear the selected DMA flags */ + DMA2->IFCR = DMA_FLAG; + } + else + { + /* Clear the selected DMA flags */ + DMA1->IFCR = DMA_FLAG; + } +} + +/** + * @brief Checks whether the specified DMAy Channelx interrupt has occurred or not. + * @param DMA_IT: specifies the DMA interrupt source to check. + * This parameter can be one of the following values: + * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt. + * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt. + * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt. + * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt. + * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt. + * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt. + * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt. + * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt. + * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt. + * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt. + * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt. + * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt. + * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt. + * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt. + * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt. + * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt. + * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt. + * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt. + * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt. + * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt. + * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt. + * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt. + * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt. + * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt. + * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt. + * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt. + * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt. + * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt. + * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt. + * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt. + * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt. + * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt. + * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt. + * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt. + * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt. + * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt. + * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt. + * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt. + * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt. + * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt. + * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt. + * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt. + * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt. + * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt. + * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt. + * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt. + * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt. + * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt. + * @retval The new state of DMA_IT (SET or RESET). + */ +ITStatus DMA_GetITStatus(uint32_t DMA_IT) +{ + ITStatus bitstatus = RESET; + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_DMA_GET_IT(DMA_IT)); + + /* Calculate the used DMA */ + if ((DMA_IT & FLAG_Mask) != (uint32_t)RESET) + { + /* Get DMA2 ISR register value */ + tmpreg = DMA2->ISR ; + } + else + { + /* Get DMA1 ISR register value */ + tmpreg = DMA1->ISR ; + } + + /* Check the status of the specified DMA interrupt */ + if ((tmpreg & DMA_IT) != (uint32_t)RESET) + { + /* DMA_IT is set */ + bitstatus = SET; + } + else + { + /* DMA_IT is reset */ + bitstatus = RESET; + } + /* Return the DMA_IT status */ + return bitstatus; +} + +/** + * @brief Clears the DMAy Channelx’s interrupt pending bits. + * @param DMA_IT: specifies the DMA interrupt pending bit to clear. + * This parameter can be any combination (for the same DMA) of the following values: + * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt. + * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt. + * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt. + * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt. + * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt. + * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt. + * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt. + * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt. + * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt. + * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt. + * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt. + * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt. + * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt. + * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt. + * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt. + * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt. + * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt. + * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt. + * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt. + * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt. + * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt. + * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt. + * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt. + * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt. + * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt. + * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt. + * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt. + * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt. + * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt. + * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt. + * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt. + * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt. + * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt. + * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt. + * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt. + * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt. + * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt. + * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt. + * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt. + * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt. + * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt. + * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt. + * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt. + * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt. + * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt. + * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt. + * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt. + * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt. + * @retval None + */ +void DMA_ClearITPendingBit(uint32_t DMA_IT) +{ + /* Check the parameters */ + assert_param(IS_DMA_CLEAR_IT(DMA_IT)); + + /* Calculate the used DMA */ + if ((DMA_IT & FLAG_Mask) != (uint32_t)RESET) + { + /* Clear the selected DMA interrupt pending bits */ + DMA2->IFCR = DMA_IT; + } + else + { + /* Clear the selected DMA interrupt pending bits */ + DMA1->IFCR = DMA_IT; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32f10x/stm32f10x_exti.c b/example/libs_stm/src/stm32f10x/stm32f10x_exti.c new file mode 100644 index 0000000..eae3253 --- /dev/null +++ b/example/libs_stm/src/stm32f10x/stm32f10x_exti.c @@ -0,0 +1,268 @@ +/** + ****************************************************************************** + * @file stm32f10x_exti.c + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file provides all the EXTI firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_exti.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup EXTI + * @brief EXTI driver modules + * @{ + */ + +/** @defgroup EXTI_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup EXTI_Private_Defines + * @{ + */ + +#define EXTI_LineNone ((uint32_t)0x00000) /* No interrupt selected */ + +/** + * @} + */ + +/** @defgroup EXTI_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup EXTI_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup EXTI_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup EXTI_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the EXTI peripheral registers to their default reset values. + * @param None + * @retval None + */ +void EXTI_DeInit(void) +{ + EXTI->IMR = 0x00000000; + EXTI->EMR = 0x00000000; + EXTI->RTSR = 0x00000000; + EXTI->FTSR = 0x00000000; + EXTI->PR = 0x000FFFFF; +} + +/** + * @brief Initializes the EXTI peripheral according to the specified + * parameters in the EXTI_InitStruct. + * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure + * that contains the configuration information for the EXTI peripheral. + * @retval None + */ +void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct) +{ + uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode)); + assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger)); + assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line)); + assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd)); + + tmp = (uint32_t)EXTI_BASE; + + if (EXTI_InitStruct->EXTI_LineCmd != DISABLE) + { + /* Clear EXTI line configuration */ + EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line; + EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line; + + tmp += EXTI_InitStruct->EXTI_Mode; + + *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; + + /* Clear Rising Falling edge configuration */ + EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line; + EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line; + + /* Select the trigger for the selected external interrupts */ + if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) + { + /* Rising Falling edge */ + EXTI->RTSR |= EXTI_InitStruct->EXTI_Line; + EXTI->FTSR |= EXTI_InitStruct->EXTI_Line; + } + else + { + tmp = (uint32_t)EXTI_BASE; + tmp += EXTI_InitStruct->EXTI_Trigger; + + *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; + } + } + else + { + tmp += EXTI_InitStruct->EXTI_Mode; + + /* Disable the selected external lines */ + *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line; + } +} + +/** + * @brief Fills each EXTI_InitStruct member with its reset value. + * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct) +{ + EXTI_InitStruct->EXTI_Line = EXTI_LineNone; + EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; + EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; + EXTI_InitStruct->EXTI_LineCmd = DISABLE; +} + +/** + * @brief Generates a Software interrupt. + * @param EXTI_Line: specifies the EXTI lines to be enabled or disabled. + * This parameter can be any combination of EXTI_Linex where x can be (0..19). + * @retval None + */ +void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(EXTI_Line)); + + EXTI->SWIER |= EXTI_Line; +} + +/** + * @brief Checks whether the specified EXTI line flag is set or not. + * @param EXTI_Line: specifies the EXTI line flag to check. + * This parameter can be: + * @arg EXTI_Linex: External interrupt line x where x(0..19) + * @retval The new state of EXTI_Line (SET or RESET). + */ +FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_GET_EXTI_LINE(EXTI_Line)); + + if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the EXTI’s line pending flags. + * @param EXTI_Line: specifies the EXTI lines flags to clear. + * This parameter can be any combination of EXTI_Linex where x can be (0..19). + * @retval None + */ +void EXTI_ClearFlag(uint32_t EXTI_Line) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(EXTI_Line)); + + EXTI->PR = EXTI_Line; +} + +/** + * @brief Checks whether the specified EXTI line is asserted or not. + * @param EXTI_Line: specifies the EXTI line to check. + * This parameter can be: + * @arg EXTI_Linex: External interrupt line x where x(0..19) + * @retval The new state of EXTI_Line (SET or RESET). + */ +ITStatus EXTI_GetITStatus(uint32_t EXTI_Line) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + /* Check the parameters */ + assert_param(IS_GET_EXTI_LINE(EXTI_Line)); + + enablestatus = EXTI->IMR & EXTI_Line; + if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the EXTI’s line pending bits. + * @param EXTI_Line: specifies the EXTI lines to clear. + * This parameter can be any combination of EXTI_Linex where x can be (0..19). + * @retval None + */ +void EXTI_ClearITPendingBit(uint32_t EXTI_Line) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(EXTI_Line)); + + EXTI->PR = EXTI_Line; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32f10x/stm32f10x_flash.c b/example/libs_stm/src/stm32f10x/stm32f10x_flash.c new file mode 100644 index 0000000..3475e6a --- /dev/null +++ b/example/libs_stm/src/stm32f10x/stm32f10x_flash.c @@ -0,0 +1,1735 @@ +/** + ****************************************************************************** + * @file stm32f10x_flash.c + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file provides all the FLASH firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_flash.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup FLASH + * @brief FLASH driver modules + * @{ + */ + +/** @defgroup FLASH_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup FLASH_Private_Defines + * @{ + */ + +/* Flash Access Control Register bits */ +#define ACR_LATENCY_Mask ((uint32_t)0x00000038) +#define ACR_HLFCYA_Mask ((uint32_t)0xFFFFFFF7) +#define ACR_PRFTBE_Mask ((uint32_t)0xFFFFFFEF) + +/* Flash Access Control Register bits */ +#define ACR_PRFTBS_Mask ((uint32_t)0x00000020) + +/* Flash Control Register bits */ +#define CR_PG_Set ((uint32_t)0x00000001) +#define CR_PG_Reset ((uint32_t)0x00001FFE) +#define CR_PER_Set ((uint32_t)0x00000002) +#define CR_PER_Reset ((uint32_t)0x00001FFD) +#define CR_MER_Set ((uint32_t)0x00000004) +#define CR_MER_Reset ((uint32_t)0x00001FFB) +#define CR_OPTPG_Set ((uint32_t)0x00000010) +#define CR_OPTPG_Reset ((uint32_t)0x00001FEF) +#define CR_OPTER_Set ((uint32_t)0x00000020) +#define CR_OPTER_Reset ((uint32_t)0x00001FDF) +#define CR_STRT_Set ((uint32_t)0x00000040) +#define CR_LOCK_Set ((uint32_t)0x00000080) + +/* FLASH Mask */ +#define RDPRT_Mask ((uint32_t)0x00000002) +#define WRP0_Mask ((uint32_t)0x000000FF) +#define WRP1_Mask ((uint32_t)0x0000FF00) +#define WRP2_Mask ((uint32_t)0x00FF0000) +#define WRP3_Mask ((uint32_t)0xFF000000) +#define OB_USER_BFB2 ((uint16_t)0x0008) + +/* FLASH Keys */ +#define RDP_Key ((uint16_t)0x00A5) +#define FLASH_KEY1 ((uint32_t)0x45670123) +#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) + +/* FLASH BANK address */ +#define FLASH_BANK1_END_ADDRESS ((uint32_t)0x807FFFF) + +/* Delay definition */ +#define EraseTimeout ((uint32_t)0x000B0000) +#define ProgramTimeout ((uint32_t)0x00002000) +/** + * @} + */ + +/** @defgroup FLASH_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup FLASH_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup FLASH_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup FLASH_Private_Functions + * @{ + */ + +/** +@code + + This driver provides functions to configure and program the Flash memory of all STM32F10x devices, + including the latest STM32F10x_XL density devices. + + STM32F10x_XL devices feature up to 1 Mbyte with dual bank architecture for read-while-write (RWW) capability: + - bank1: fixed size of 512 Kbytes (256 pages of 2Kbytes each) + - bank2: up to 512 Kbytes (up to 256 pages of 2Kbytes each) + While other STM32F10x devices features only one bank with memory up to 512 Kbytes. + + In version V3.3.0, some functions were updated and new ones were added to support + STM32F10x_XL devices. Thus some functions manages all devices, while other are + dedicated for XL devices only. + + The table below presents the list of available functions depending on the used STM32F10x devices. + + *************************************************** + * Legacy functions used for all STM32F10x devices * + *************************************************** + +----------------------------------------------------------------------------------------------------------------------------------+ + | Functions prototypes |STM32F10x_XL|Other STM32F10x| Comments | + | | devices | devices | | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_SetLatency | Yes | Yes | No change | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_HalfCycleAccessCmd | Yes | Yes | No change | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_PrefetchBufferCmd | Yes | Yes | No change | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_Unlock | Yes | Yes | - For STM32F10X_XL devices: unlock Bank1 and Bank2. | + | | | | - For other devices: unlock Bank1 and it is equivalent | + | | | | to FLASH_UnlockBank1 function. | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_Lock | Yes | Yes | - For STM32F10X_XL devices: lock Bank1 and Bank2. | + | | | | - For other devices: lock Bank1 and it is equivalent | + | | | | to FLASH_LockBank1 function. | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_ErasePage | Yes | Yes | - For STM32F10x_XL devices: erase a page in Bank1 and Bank2 | + | | | | - For other devices: erase a page in Bank1 | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_EraseAllPages | Yes | Yes | - For STM32F10x_XL devices: erase all pages in Bank1 and Bank2 | + | | | | - For other devices: erase all pages in Bank1 | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_EraseOptionBytes | Yes | Yes | No change | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_ProgramWord | Yes | Yes | Updated to program up to 1MByte (depending on the used device) | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_ProgramHalfWord | Yes | Yes | Updated to program up to 1MByte (depending on the used device) | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_ProgramOptionByteData | Yes | Yes | No change | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_EnableWriteProtection | Yes | Yes | No change | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_ReadOutProtection | Yes | Yes | No change | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_UserOptionByteConfig | Yes | Yes | No change | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_GetUserOptionByte | Yes | Yes | No change | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_GetWriteProtectionOptionByte | Yes | Yes | No change | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_GetReadOutProtectionStatus | Yes | Yes | No change | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_GetPrefetchBufferStatus | Yes | Yes | No change | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_ITConfig | Yes | Yes | - For STM32F10x_XL devices: enable Bank1 and Bank2's interrupts| + | | | | - For other devices: enable Bank1's interrupts | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_GetFlagStatus | Yes | Yes | - For STM32F10x_XL devices: return Bank1 and Bank2's flag status| + | | | | - For other devices: return Bank1's flag status | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_ClearFlag | Yes | Yes | - For STM32F10x_XL devices: clear Bank1 and Bank2's flag | + | | | | - For other devices: clear Bank1's flag | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_GetStatus | Yes | Yes | - Return the status of Bank1 (for all devices) | + | | | | equivalent to FLASH_GetBank1Status function | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_WaitForLastOperation | Yes | Yes | - Wait for Bank1 last operation (for all devices) | + | | | | equivalent to: FLASH_WaitForLastBank1Operation function | + +----------------------------------------------------------------------------------------------------------------------------------+ + + ************************************************************************************************************************ + * New functions used for all STM32F10x devices to manage Bank1: * + * - These functions are mainly useful for STM32F10x_XL density devices, to have separate control for Bank1 and bank2 * + * - For other devices, these functions are optional (covered by functions listed above) * + ************************************************************************************************************************ + +----------------------------------------------------------------------------------------------------------------------------------+ + | Functions prototypes |STM32F10x_XL|Other STM32F10x| Comments | + | | devices | devices | | + |----------------------------------------------------------------------------------------------------------------------------------| + | FLASH_UnlockBank1 | Yes | Yes | - Unlock Bank1 | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_LockBank1 | Yes | Yes | - Lock Bank1 | + |----------------------------------------------------------------------------------------------------------------------------------| + | FLASH_EraseAllBank1Pages | Yes | Yes | - Erase all pages in Bank1 | + |----------------------------------------------------------------------------------------------------------------------------------| + | FLASH_GetBank1Status | Yes | Yes | - Return the status of Bank1 | + |----------------------------------------------------------------------------------------------------------------------------------| + | FLASH_WaitForLastBank1Operation | Yes | Yes | - Wait for Bank1 last operation | + +----------------------------------------------------------------------------------------------------------------------------------+ + + ***************************************************************************** + * New Functions used only with STM32F10x_XL density devices to manage Bank2 * + ***************************************************************************** + +----------------------------------------------------------------------------------------------------------------------------------+ + | Functions prototypes |STM32F10x_XL|Other STM32F10x| Comments | + | | devices | devices | | + |----------------------------------------------------------------------------------------------------------------------------------| + | FLASH_UnlockBank2 | Yes | No | - Unlock Bank2 | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_LockBank2 | Yes | No | - Lock Bank2 | + |----------------------------------------------------------------------------------------------------------------------------------| + | FLASH_EraseAllBank2Pages | Yes | No | - Erase all pages in Bank2 | + |----------------------------------------------------------------------------------------------------------------------------------| + | FLASH_GetBank2Status | Yes | No | - Return the status of Bank2 | + |----------------------------------------------------------------------------------------------------------------------------------| + | FLASH_WaitForLastBank2Operation | Yes | No | - Wait for Bank2 last operation | + |----------------------------------------------------------------------------------------------------------------------------------| + | FLASH_BootConfig | Yes | No | - Configure to boot from Bank1 or Bank2 | + +----------------------------------------------------------------------------------------------------------------------------------+ +@endcode +*/ + + +/** + * @brief Sets the code latency value. + * @note This function can be used for all STM32F10x devices. + * @param FLASH_Latency: specifies the FLASH Latency value. + * This parameter can be one of the following values: + * @arg FLASH_Latency_0: FLASH Zero Latency cycle + * @arg FLASH_Latency_1: FLASH One Latency cycle + * @arg FLASH_Latency_2: FLASH Two Latency cycles + * @retval None + */ +void FLASH_SetLatency(uint32_t FLASH_Latency) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_FLASH_LATENCY(FLASH_Latency)); + + /* Read the ACR register */ + tmpreg = FLASH->ACR; + + /* Sets the Latency value */ + tmpreg &= ACR_LATENCY_Mask; + tmpreg |= FLASH_Latency; + + /* Write the ACR register */ + FLASH->ACR = tmpreg; +} + +/** + * @brief Enables or disables the Half cycle flash access. + * @note This function can be used for all STM32F10x devices. + * @param FLASH_HalfCycleAccess: specifies the FLASH Half cycle Access mode. + * This parameter can be one of the following values: + * @arg FLASH_HalfCycleAccess_Enable: FLASH Half Cycle Enable + * @arg FLASH_HalfCycleAccess_Disable: FLASH Half Cycle Disable + * @retval None + */ +void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess) +{ + /* Check the parameters */ + assert_param(IS_FLASH_HALFCYCLEACCESS_STATE(FLASH_HalfCycleAccess)); + + /* Enable or disable the Half cycle access */ + FLASH->ACR &= ACR_HLFCYA_Mask; + FLASH->ACR |= FLASH_HalfCycleAccess; +} + +/** + * @brief Enables or disables the Prefetch Buffer. + * @note This function can be used for all STM32F10x devices. + * @param FLASH_PrefetchBuffer: specifies the Prefetch buffer status. + * This parameter can be one of the following values: + * @arg FLASH_PrefetchBuffer_Enable: FLASH Prefetch Buffer Enable + * @arg FLASH_PrefetchBuffer_Disable: FLASH Prefetch Buffer Disable + * @retval None + */ +void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer) +{ + /* Check the parameters */ + assert_param(IS_FLASH_PREFETCHBUFFER_STATE(FLASH_PrefetchBuffer)); + + /* Enable or disable the Prefetch Buffer */ + FLASH->ACR &= ACR_PRFTBE_Mask; + FLASH->ACR |= FLASH_PrefetchBuffer; +} + +/** + * @brief Unlocks the FLASH Program Erase Controller. + * @note This function can be used for all STM32F10x devices. + * - For STM32F10X_XL devices this function unlocks Bank1 and Bank2. + * - For all other devices it unlocks Bank1 and it is equivalent + * to FLASH_UnlockBank1 function.. + * @param None + * @retval None + */ +void FLASH_Unlock(void) +{ + /* Authorize the FPEC of Bank1 Access */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; + +#ifdef STM32F10X_XL + /* Authorize the FPEC of Bank2 Access */ + FLASH->KEYR2 = FLASH_KEY1; + FLASH->KEYR2 = FLASH_KEY2; +#endif /* STM32F10X_XL */ +} +/** + * @brief Unlocks the FLASH Bank1 Program Erase Controller. + * @note This function can be used for all STM32F10x devices. + * - For STM32F10X_XL devices this function unlocks Bank1. + * - For all other devices it unlocks Bank1 and it is + * equivalent to FLASH_Unlock function. + * @param None + * @retval None + */ +void FLASH_UnlockBank1(void) +{ + /* Authorize the FPEC of Bank1 Access */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; +} + +#ifdef STM32F10X_XL +/** + * @brief Unlocks the FLASH Bank2 Program Erase Controller. + * @note This function can be used only for STM32F10X_XL density devices. + * @param None + * @retval None + */ +void FLASH_UnlockBank2(void) +{ + /* Authorize the FPEC of Bank2 Access */ + FLASH->KEYR2 = FLASH_KEY1; + FLASH->KEYR2 = FLASH_KEY2; + +} +#endif /* STM32F10X_XL */ + +/** + * @brief Locks the FLASH Program Erase Controller. + * @note This function can be used for all STM32F10x devices. + * - For STM32F10X_XL devices this function Locks Bank1 and Bank2. + * - For all other devices it Locks Bank1 and it is equivalent + * to FLASH_LockBank1 function. + * @param None + * @retval None + */ +void FLASH_Lock(void) +{ + /* Set the Lock Bit to lock the FPEC and the CR of Bank1 */ + FLASH->CR |= CR_LOCK_Set; + +#ifdef STM32F10X_XL + /* Set the Lock Bit to lock the FPEC and the CR of Bank2 */ + FLASH->CR2 |= CR_LOCK_Set; +#endif /* STM32F10X_XL */ +} + +/** + * @brief Locks the FLASH Bank1 Program Erase Controller. + * @note this function can be used for all STM32F10x devices. + * - For STM32F10X_XL devices this function Locks Bank1. + * - For all other devices it Locks Bank1 and it is equivalent + * to FLASH_Lock function. + * @param None + * @retval None + */ +void FLASH_LockBank1(void) +{ + /* Set the Lock Bit to lock the FPEC and the CR of Bank1 */ + FLASH->CR |= CR_LOCK_Set; +} + +#ifdef STM32F10X_XL +/** + * @brief Locks the FLASH Bank2 Program Erase Controller. + * @note This function can be used only for STM32F10X_XL density devices. + * @param None + * @retval None + */ +void FLASH_LockBank2(void) +{ + /* Set the Lock Bit to lock the FPEC and the CR of Bank2 */ + FLASH->CR2 |= CR_LOCK_Set; +} +#endif /* STM32F10X_XL */ + +/** + * @brief Erases a specified FLASH page. + * @note This function can be used for all STM32F10x devices. + * @param Page_Address: The page address to be erased. + * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ErasePage(uint32_t Page_Address) +{ + FLASH_Status status = FLASH_COMPLETE; + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(Page_Address)); + +#ifdef STM32F10X_XL + if(Page_Address < FLASH_BANK1_END_ADDRESS) + { + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank1Operation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to erase the page */ + FLASH->CR|= CR_PER_Set; + FLASH->AR = Page_Address; + FLASH->CR|= CR_STRT_Set; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank1Operation(EraseTimeout); + if(status != FLASH_TIMEOUT) + { + /* if the erase operation is completed, disable the PER Bit */ + FLASH->CR &= CR_PER_Reset; + } + } + } + else + { + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank2Operation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to erase the page */ + FLASH->CR2|= CR_PER_Set; + FLASH->AR2 = Page_Address; + FLASH->CR2|= CR_STRT_Set; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank2Operation(EraseTimeout); + if(status != FLASH_TIMEOUT) + { + /* if the erase operation is completed, disable the PER Bit */ + FLASH->CR2 &= CR_PER_Reset; + } + } + } +#else + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to erase the page */ + FLASH->CR|= CR_PER_Set; + FLASH->AR = Page_Address; + FLASH->CR|= CR_STRT_Set; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status != FLASH_TIMEOUT) + { + /* if the erase operation is completed, disable the PER Bit */ + FLASH->CR &= CR_PER_Reset; + } + } +#endif /* STM32F10X_XL */ + + /* Return the Erase Status */ + return status; +} + +/** + * @brief Erases all FLASH pages. + * @note This function can be used for all STM32F10x devices. + * @param None + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EraseAllPages(void) +{ + FLASH_Status status = FLASH_COMPLETE; + +#ifdef STM32F10X_XL + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank1Operation(EraseTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to erase all pages */ + FLASH->CR |= CR_MER_Set; + FLASH->CR |= CR_STRT_Set; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank1Operation(EraseTimeout); + if(status != FLASH_TIMEOUT) + { + /* if the erase operation is completed, disable the MER Bit */ + FLASH->CR &= CR_MER_Reset; + } + } + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to erase all pages */ + FLASH->CR2 |= CR_MER_Set; + FLASH->CR2 |= CR_STRT_Set; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank2Operation(EraseTimeout); + if(status != FLASH_TIMEOUT) + { + /* if the erase operation is completed, disable the MER Bit */ + FLASH->CR2 &= CR_MER_Reset; + } + } +#else + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to erase all pages */ + FLASH->CR |= CR_MER_Set; + FLASH->CR |= CR_STRT_Set; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status != FLASH_TIMEOUT) + { + /* if the erase operation is completed, disable the MER Bit */ + FLASH->CR &= CR_MER_Reset; + } + } +#endif /* STM32F10X_XL */ + + /* Return the Erase Status */ + return status; +} + +/** + * @brief Erases all Bank1 FLASH pages. + * @note This function can be used for all STM32F10x devices. + * - For STM32F10X_XL devices this function erases all Bank1 pages. + * - For all other devices it erases all Bank1 pages and it is equivalent + * to FLASH_EraseAllPages function. + * @param None + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EraseAllBank1Pages(void) +{ + FLASH_Status status = FLASH_COMPLETE; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank1Operation(EraseTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to erase all pages */ + FLASH->CR |= CR_MER_Set; + FLASH->CR |= CR_STRT_Set; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank1Operation(EraseTimeout); + if(status != FLASH_TIMEOUT) + { + /* if the erase operation is completed, disable the MER Bit */ + FLASH->CR &= CR_MER_Reset; + } + } + /* Return the Erase Status */ + return status; +} + +#ifdef STM32F10X_XL +/** + * @brief Erases all Bank2 FLASH pages. + * @note This function can be used only for STM32F10x_XL density devices. + * @param None + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EraseAllBank2Pages(void) +{ + FLASH_Status status = FLASH_COMPLETE; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank2Operation(EraseTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to erase all pages */ + FLASH->CR2 |= CR_MER_Set; + FLASH->CR2 |= CR_STRT_Set; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank2Operation(EraseTimeout); + if(status != FLASH_TIMEOUT) + { + /* if the erase operation is completed, disable the MER Bit */ + FLASH->CR2 &= CR_MER_Reset; + } + } + /* Return the Erase Status */ + return status; +} +#endif /* STM32F10X_XL */ + +/** + * @brief Erases the FLASH option bytes. + * @note This functions erases all option bytes except the Read protection (RDP). + * @note This function can be used for all STM32F10x devices. + * @param None + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EraseOptionBytes(void) +{ + uint16_t rdptmp = RDP_Key; + + FLASH_Status status = FLASH_COMPLETE; + + /* Get the actual read protection Option Byte value */ + if(FLASH_GetReadOutProtectionStatus() != RESET) + { + rdptmp = 0x00; + } + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + /* Authorize the small information block programming */ + FLASH->OPTKEYR = FLASH_KEY1; + FLASH->OPTKEYR = FLASH_KEY2; + + /* if the previous operation is completed, proceed to erase the option bytes */ + FLASH->CR |= CR_OPTER_Set; + FLASH->CR |= CR_STRT_Set; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the erase operation is completed, disable the OPTER Bit */ + FLASH->CR &= CR_OPTER_Reset; + + /* Enable the Option Bytes Programming operation */ + FLASH->CR |= CR_OPTPG_Set; + /* Restore the last read protection Option Byte value */ + OB->RDP = (uint16_t)rdptmp; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= CR_OPTPG_Reset; + } + } + else + { + if (status != FLASH_TIMEOUT) + { + /* Disable the OPTPG Bit */ + FLASH->CR &= CR_OPTPG_Reset; + } + } + } + /* Return the erase status */ + return status; +} + +/** + * @brief Programs a word at a specified address. + * @note This function can be used for all STM32F10x devices. + * @param Address: specifies the address to be programmed. + * @param Data: specifies the data to be programmed. + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data) +{ + FLASH_Status status = FLASH_COMPLETE; + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(Address)); + +#ifdef STM32F10X_XL + if(Address < FLASH_BANK1_END_ADDRESS - 2) + { + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank1Operation(ProgramTimeout); + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new first + half word */ + FLASH->CR |= CR_PG_Set; + + *(__IO uint16_t*)Address = (uint16_t)Data; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new second + half word */ + tmp = Address + 2; + + *(__IO uint16_t*) tmp = Data >> 16; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status != FLASH_TIMEOUT) + { + /* Disable the PG Bit */ + FLASH->CR &= CR_PG_Reset; + } + } + else + { + if (status != FLASH_TIMEOUT) + { + /* Disable the PG Bit */ + FLASH->CR &= CR_PG_Reset; + } + } + } + } + else if(Address == (FLASH_BANK1_END_ADDRESS - 1)) + { + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank1Operation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new first + half word */ + FLASH->CR |= CR_PG_Set; + + *(__IO uint16_t*)Address = (uint16_t)Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank1Operation(ProgramTimeout); + + if(status != FLASH_TIMEOUT) + { + /* Disable the PG Bit */ + FLASH->CR &= CR_PG_Reset; + } + } + else + { + if (status != FLASH_TIMEOUT) + { + /* Disable the PG Bit */ + FLASH->CR &= CR_PG_Reset; + } + } + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank2Operation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new second + half word */ + FLASH->CR2 |= CR_PG_Set; + tmp = Address + 2; + + *(__IO uint16_t*) tmp = Data >> 16; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank2Operation(ProgramTimeout); + + if(status != FLASH_TIMEOUT) + { + /* Disable the PG Bit */ + FLASH->CR2 &= CR_PG_Reset; + } + } + else + { + if (status != FLASH_TIMEOUT) + { + /* Disable the PG Bit */ + FLASH->CR2 &= CR_PG_Reset; + } + } + } + else + { + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank2Operation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new first + half word */ + FLASH->CR2 |= CR_PG_Set; + + *(__IO uint16_t*)Address = (uint16_t)Data; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank2Operation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new second + half word */ + tmp = Address + 2; + + *(__IO uint16_t*) tmp = Data >> 16; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank2Operation(ProgramTimeout); + + if(status != FLASH_TIMEOUT) + { + /* Disable the PG Bit */ + FLASH->CR2 &= CR_PG_Reset; + } + } + else + { + if (status != FLASH_TIMEOUT) + { + /* Disable the PG Bit */ + FLASH->CR2 &= CR_PG_Reset; + } + } + } + } +#else + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new first + half word */ + FLASH->CR |= CR_PG_Set; + + *(__IO uint16_t*)Address = (uint16_t)Data; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new second + half word */ + tmp = Address + 2; + + *(__IO uint16_t*) tmp = Data >> 16; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status != FLASH_TIMEOUT) + { + /* Disable the PG Bit */ + FLASH->CR &= CR_PG_Reset; + } + } + else + { + if (status != FLASH_TIMEOUT) + { + /* Disable the PG Bit */ + FLASH->CR &= CR_PG_Reset; + } + } + } +#endif /* STM32F10X_XL */ + + /* Return the Program Status */ + return status; +} + +/** + * @brief Programs a half word at a specified address. + * @note This function can be used for all STM32F10x devices. + * @param Address: specifies the address to be programmed. + * @param Data: specifies the data to be programmed. + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data) +{ + FLASH_Status status = FLASH_COMPLETE; + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(Address)); + +#ifdef STM32F10X_XL + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(Address < FLASH_BANK1_END_ADDRESS) + { + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new data */ + FLASH->CR |= CR_PG_Set; + + *(__IO uint16_t*)Address = Data; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank1Operation(ProgramTimeout); + if(status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the PG Bit */ + FLASH->CR &= CR_PG_Reset; + } + } + } + else + { + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new data */ + FLASH->CR2 |= CR_PG_Set; + + *(__IO uint16_t*)Address = Data; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank2Operation(ProgramTimeout); + if(status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the PG Bit */ + FLASH->CR2 &= CR_PG_Reset; + } + } + } +#else + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new data */ + FLASH->CR |= CR_PG_Set; + + *(__IO uint16_t*)Address = Data; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + if(status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the PG Bit */ + FLASH->CR &= CR_PG_Reset; + } + } +#endif /* STM32F10X_XL */ + + /* Return the Program Status */ + return status; +} + +/** + * @brief Programs a half word at a specified Option Byte Data address. + * @note This function can be used for all STM32F10x devices. + * @param Address: specifies the address to be programmed. + * This parameter can be 0x1FFFF804 or 0x1FFFF806. + * @param Data: specifies the data to be programmed. + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data) +{ + FLASH_Status status = FLASH_COMPLETE; + /* Check the parameters */ + assert_param(IS_OB_DATA_ADDRESS(Address)); + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* Authorize the small information block programming */ + FLASH->OPTKEYR = FLASH_KEY1; + FLASH->OPTKEYR = FLASH_KEY2; + /* Enables the Option Bytes Programming operation */ + FLASH->CR |= CR_OPTPG_Set; + *(__IO uint16_t*)Address = Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + if(status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= CR_OPTPG_Reset; + } + } + /* Return the Option Byte Data Program Status */ + return status; +} + +/** + * @brief Write protects the desired pages + * @note This function can be used for all STM32F10x devices. + * @param FLASH_Pages: specifies the address of the pages to be write protected. + * This parameter can be: + * @arg For @b STM32_Low-density_devices: value between FLASH_WRProt_Pages0to3 and FLASH_WRProt_Pages28to31 + * @arg For @b STM32_Medium-density_devices: value between FLASH_WRProt_Pages0to3 + * and FLASH_WRProt_Pages124to127 + * @arg For @b STM32_High-density_devices: value between FLASH_WRProt_Pages0to1 and + * FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to255 + * @arg For @b STM32_Connectivity_line_devices: value between FLASH_WRProt_Pages0to1 and + * FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to127 + * @arg For @b STM32_XL-density_devices: value between FLASH_WRProt_Pages0to1 and + * FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to511 + * @arg FLASH_WRProt_AllPages + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages) +{ + uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF; + + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_FLASH_WRPROT_PAGE(FLASH_Pages)); + + FLASH_Pages = (uint32_t)(~FLASH_Pages); + WRP0_Data = (uint16_t)(FLASH_Pages & WRP0_Mask); + WRP1_Data = (uint16_t)((FLASH_Pages & WRP1_Mask) >> 8); + WRP2_Data = (uint16_t)((FLASH_Pages & WRP2_Mask) >> 16); + WRP3_Data = (uint16_t)((FLASH_Pages & WRP3_Mask) >> 24); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* Authorizes the small information block programming */ + FLASH->OPTKEYR = FLASH_KEY1; + FLASH->OPTKEYR = FLASH_KEY2; + FLASH->CR |= CR_OPTPG_Set; + if(WRP0_Data != 0xFF) + { + OB->WRP0 = WRP0_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + } + if((status == FLASH_COMPLETE) && (WRP1_Data != 0xFF)) + { + OB->WRP1 = WRP1_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + } + if((status == FLASH_COMPLETE) && (WRP2_Data != 0xFF)) + { + OB->WRP2 = WRP2_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + } + + if((status == FLASH_COMPLETE)&& (WRP3_Data != 0xFF)) + { + OB->WRP3 = WRP3_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + } + + if(status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= CR_OPTPG_Reset; + } + } + /* Return the write protection operation Status */ + return status; +} + +/** + * @brief Enables or disables the read out protection. + * @note If the user has already programmed the other option bytes before calling + * this function, he must re-program them since this function erases all option bytes. + * @note This function can be used for all STM32F10x devices. + * @param Newstate: new state of the ReadOut Protection. + * This parameter can be: ENABLE or DISABLE. + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState) +{ + FLASH_Status status = FLASH_COMPLETE; + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + /* Authorizes the small information block programming */ + FLASH->OPTKEYR = FLASH_KEY1; + FLASH->OPTKEYR = FLASH_KEY2; + FLASH->CR |= CR_OPTER_Set; + FLASH->CR |= CR_STRT_Set; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + /* if the erase operation is completed, disable the OPTER Bit */ + FLASH->CR &= CR_OPTER_Reset; + /* Enable the Option Bytes Programming operation */ + FLASH->CR |= CR_OPTPG_Set; + if(NewState != DISABLE) + { + OB->RDP = 0x00; + } + else + { + OB->RDP = RDP_Key; + } + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + + if(status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= CR_OPTPG_Reset; + } + } + else + { + if(status != FLASH_TIMEOUT) + { + /* Disable the OPTER Bit */ + FLASH->CR &= CR_OPTER_Reset; + } + } + } + /* Return the protection operation Status */ + return status; +} + +/** + * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. + * @note This function can be used for all STM32F10x devices. + * @param OB_IWDG: Selects the IWDG mode + * This parameter can be one of the following values: + * @arg OB_IWDG_SW: Software IWDG selected + * @arg OB_IWDG_HW: Hardware IWDG selected + * @param OB_STOP: Reset event when entering STOP mode. + * This parameter can be one of the following values: + * @arg OB_STOP_NoRST: No reset generated when entering in STOP + * @arg OB_STOP_RST: Reset generated when entering in STOP + * @param OB_STDBY: Reset event when entering Standby mode. + * This parameter can be one of the following values: + * @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY + * @arg OB_STDBY_RST: Reset generated when entering in STANDBY + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_OB_IWDG_SOURCE(OB_IWDG)); + assert_param(IS_OB_STOP_SOURCE(OB_STOP)); + assert_param(IS_OB_STDBY_SOURCE(OB_STDBY)); + + /* Authorize the small information block programming */ + FLASH->OPTKEYR = FLASH_KEY1; + FLASH->OPTKEYR = FLASH_KEY2; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* Enable the Option Bytes Programming operation */ + FLASH->CR |= CR_OPTPG_Set; + + OB->USER = OB_IWDG | (uint16_t)(OB_STOP | (uint16_t)(OB_STDBY | ((uint16_t)0xF8))); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + if(status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= CR_OPTPG_Reset; + } + } + /* Return the Option Byte program Status */ + return status; +} + +#ifdef STM32F10X_XL +/** + * @brief Configures to boot from Bank1 or Bank2. + * @note This function can be used only for STM32F10x_XL density devices. + * @param FLASH_BOOT: select the FLASH Bank to boot from. + * This parameter can be one of the following values: + * @arg FLASH_BOOT_Bank1: At startup, if boot pins are set in boot from user Flash + * position and this parameter is selected the device will boot from Bank1(Default). + * @arg FLASH_BOOT_Bank2: At startup, if boot pins are set in boot from user Flash + * position and this parameter is selected the device will boot from Bank2 or Bank1, + * depending on the activation of the bank. The active banks are checked in + * the following order: Bank2, followed by Bank1. + * The active bank is recognized by the value programmed at the base address + * of the respective bank (corresponding to the initial stack pointer value + * in the interrupt vector table). + * For more information, please refer to AN2606 from www.st.com. + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_BootConfig(uint16_t FLASH_BOOT) +{ + FLASH_Status status = FLASH_COMPLETE; + assert_param(IS_FLASH_BOOT(FLASH_BOOT)); + /* Authorize the small information block programming */ + FLASH->OPTKEYR = FLASH_KEY1; + FLASH->OPTKEYR = FLASH_KEY2; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* Enable the Option Bytes Programming operation */ + FLASH->CR |= CR_OPTPG_Set; + + if(FLASH_BOOT == FLASH_BOOT_Bank1) + { + OB->USER |= OB_USER_BFB2; + } + else + { + OB->USER &= (uint16_t)(~(uint16_t)(OB_USER_BFB2)); + } + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + if(status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= CR_OPTPG_Reset; + } + } + /* Return the Option Byte program Status */ + return status; +} +#endif /* STM32F10X_XL */ + +/** + * @brief Returns the FLASH User Option Bytes values. + * @note This function can be used for all STM32F10x devices. + * @param None + * @retval The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1) + * and RST_STDBY(Bit2). + */ +uint32_t FLASH_GetUserOptionByte(void) +{ + /* Return the User Option Byte */ + return (uint32_t)(FLASH->OBR >> 2); +} + +/** + * @brief Returns the FLASH Write Protection Option Bytes Register value. + * @note This function can be used for all STM32F10x devices. + * @param None + * @retval The FLASH Write Protection Option Bytes Register value + */ +uint32_t FLASH_GetWriteProtectionOptionByte(void) +{ + /* Return the Falsh write protection Register value */ + return (uint32_t)(FLASH->WRPR); +} + +/** + * @brief Checks whether the FLASH Read Out Protection Status is set or not. + * @note This function can be used for all STM32F10x devices. + * @param None + * @retval FLASH ReadOut Protection Status(SET or RESET) + */ +FlagStatus FLASH_GetReadOutProtectionStatus(void) +{ + FlagStatus readoutstatus = RESET; + if ((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET) + { + readoutstatus = SET; + } + else + { + readoutstatus = RESET; + } + return readoutstatus; +} + +/** + * @brief Checks whether the FLASH Prefetch Buffer status is set or not. + * @note This function can be used for all STM32F10x devices. + * @param None + * @retval FLASH Prefetch Buffer Status (SET or RESET). + */ +FlagStatus FLASH_GetPrefetchBufferStatus(void) +{ + FlagStatus bitstatus = RESET; + + if ((FLASH->ACR & ACR_PRFTBS_Mask) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the new state of FLASH Prefetch Buffer Status (SET or RESET) */ + return bitstatus; +} + +/** + * @brief Enables or disables the specified FLASH interrupts. + * @note This function can be used for all STM32F10x devices. + * - For STM32F10X_XL devices, enables or disables the specified FLASH interrupts + for Bank1 and Bank2. + * - For other devices it enables or disables the specified FLASH interrupts for Bank1. + * @param FLASH_IT: specifies the FLASH interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg FLASH_IT_ERROR: FLASH Error Interrupt + * @arg FLASH_IT_EOP: FLASH end of operation Interrupt + * @param NewState: new state of the specified Flash interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState) +{ +#ifdef STM32F10X_XL + /* Check the parameters */ + assert_param(IS_FLASH_IT(FLASH_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if((FLASH_IT & 0x80000000) != 0x0) + { + if(NewState != DISABLE) + { + /* Enable the interrupt sources */ + FLASH->CR2 |= (FLASH_IT & 0x7FFFFFFF); + } + else + { + /* Disable the interrupt sources */ + FLASH->CR2 &= ~(uint32_t)(FLASH_IT & 0x7FFFFFFF); + } + } + else + { + if(NewState != DISABLE) + { + /* Enable the interrupt sources */ + FLASH->CR |= FLASH_IT; + } + else + { + /* Disable the interrupt sources */ + FLASH->CR &= ~(uint32_t)FLASH_IT; + } + } +#else + /* Check the parameters */ + assert_param(IS_FLASH_IT(FLASH_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if(NewState != DISABLE) + { + /* Enable the interrupt sources */ + FLASH->CR |= FLASH_IT; + } + else + { + /* Disable the interrupt sources */ + FLASH->CR &= ~(uint32_t)FLASH_IT; + } +#endif /* STM32F10X_XL */ +} + +/** + * @brief Checks whether the specified FLASH flag is set or not. + * @note This function can be used for all STM32F10x devices. + * - For STM32F10X_XL devices, this function checks whether the specified + * Bank1 or Bank2 flag is set or not. + * - For other devices, it checks whether the specified Bank1 flag is + * set or not. + * @param FLASH_FLAG: specifies the FLASH flag to check. + * This parameter can be one of the following values: + * @arg FLASH_FLAG_BSY: FLASH Busy flag + * @arg FLASH_FLAG_PGERR: FLASH Program error flag + * @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag + * @arg FLASH_FLAG_EOP: FLASH End of Operation flag + * @arg FLASH_FLAG_OPTERR: FLASH Option Byte error flag + * @retval The new state of FLASH_FLAG (SET or RESET). + */ +FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG) +{ + FlagStatus bitstatus = RESET; + +#ifdef STM32F10X_XL + /* Check the parameters */ + assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)) ; + if(FLASH_FLAG == FLASH_FLAG_OPTERR) + { + if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if((FLASH_FLAG & 0x80000000) != 0x0) + { + if((FLASH->SR2 & FLASH_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + } +#else + /* Check the parameters */ + assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)) ; + if(FLASH_FLAG == FLASH_FLAG_OPTERR) + { + if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } +#endif /* STM32F10X_XL */ + + /* Return the new state of FLASH_FLAG (SET or RESET) */ + return bitstatus; +} + +/** + * @brief Clears the FLASH’s pending flags. + * @note This function can be used for all STM32F10x devices. + * - For STM32F10X_XL devices, this function clears Bank1 or Bank2’s pending flags + * - For other devices, it clears Bank1’s pending flags. + * @param FLASH_FLAG: specifies the FLASH flags to clear. + * This parameter can be any combination of the following values: + * @arg FLASH_FLAG_PGERR: FLASH Program error flag + * @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag + * @arg FLASH_FLAG_EOP: FLASH End of Operation flag + * @retval None + */ +void FLASH_ClearFlag(uint32_t FLASH_FLAG) +{ +#ifdef STM32F10X_XL + /* Check the parameters */ + assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)) ; + + if((FLASH_FLAG & 0x80000000) != 0x0) + { + /* Clear the flags */ + FLASH->SR2 = FLASH_FLAG; + } + else + { + /* Clear the flags */ + FLASH->SR = FLASH_FLAG; + } + +#else + /* Check the parameters */ + assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)) ; + + /* Clear the flags */ + FLASH->SR = FLASH_FLAG; +#endif /* STM32F10X_XL */ +} + +/** + * @brief Returns the FLASH Status. + * @note This function can be used for all STM32F10x devices, it is equivalent + * to FLASH_GetBank1Status function. + * @param None + * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE + */ +FLASH_Status FLASH_GetStatus(void) +{ + FLASH_Status flashstatus = FLASH_COMPLETE; + + if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) + { + flashstatus = FLASH_BUSY; + } + else + { + if((FLASH->SR & FLASH_FLAG_PGERR) != 0) + { + flashstatus = FLASH_ERROR_PG; + } + else + { + if((FLASH->SR & FLASH_FLAG_WRPRTERR) != 0 ) + { + flashstatus = FLASH_ERROR_WRP; + } + else + { + flashstatus = FLASH_COMPLETE; + } + } + } + /* Return the Flash Status */ + return flashstatus; +} + +/** + * @brief Returns the FLASH Bank1 Status. + * @note This function can be used for all STM32F10x devices, it is equivalent + * to FLASH_GetStatus function. + * @param None + * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE + */ +FLASH_Status FLASH_GetBank1Status(void) +{ + FLASH_Status flashstatus = FLASH_COMPLETE; + + if((FLASH->SR & FLASH_FLAG_BANK1_BSY) == FLASH_FLAG_BSY) + { + flashstatus = FLASH_BUSY; + } + else + { + if((FLASH->SR & FLASH_FLAG_BANK1_PGERR) != 0) + { + flashstatus = FLASH_ERROR_PG; + } + else + { + if((FLASH->SR & FLASH_FLAG_BANK1_WRPRTERR) != 0 ) + { + flashstatus = FLASH_ERROR_WRP; + } + else + { + flashstatus = FLASH_COMPLETE; + } + } + } + /* Return the Flash Status */ + return flashstatus; +} + +#ifdef STM32F10X_XL +/** + * @brief Returns the FLASH Bank2 Status. + * @note This function can be used for STM32F10x_XL density devices. + * @param None + * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE + */ +FLASH_Status FLASH_GetBank2Status(void) +{ + FLASH_Status flashstatus = FLASH_COMPLETE; + + if((FLASH->SR2 & (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF)) == (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF)) + { + flashstatus = FLASH_BUSY; + } + else + { + if((FLASH->SR2 & (FLASH_FLAG_BANK2_PGERR & 0x7FFFFFFF)) != 0) + { + flashstatus = FLASH_ERROR_PG; + } + else + { + if((FLASH->SR2 & (FLASH_FLAG_BANK2_WRPRTERR & 0x7FFFFFFF)) != 0 ) + { + flashstatus = FLASH_ERROR_WRP; + } + else + { + flashstatus = FLASH_COMPLETE; + } + } + } + /* Return the Flash Status */ + return flashstatus; +} +#endif /* STM32F10X_XL */ +/** + * @brief Waits for a Flash operation to complete or a TIMEOUT to occur. + * @note This function can be used for all STM32F10x devices, + * it is equivalent to FLASH_WaitForLastBank1Operation. + * - For STM32F10X_XL devices this function waits for a Bank1 Flash operation + * to complete or a TIMEOUT to occur. + * - For all other devices it waits for a Flash operation to complete + * or a TIMEOUT to occur. + * @param Timeout: FLASH progamming Timeout + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check for the Flash Status */ + status = FLASH_GetBank1Status(); + /* Wait for a Flash operation to complete or a TIMEOUT to occur */ + while((status == FLASH_BUSY) && (Timeout != 0x00)) + { + status = FLASH_GetBank1Status(); + Timeout--; + } + if(Timeout == 0x00 ) + { + status = FLASH_TIMEOUT; + } + /* Return the operation status */ + return status; +} + +/** + * @brief Waits for a Flash operation on Bank1 to complete or a TIMEOUT to occur. + * @note This function can be used for all STM32F10x devices, + * it is equivalent to FLASH_WaitForLastOperation. + * @param Timeout: FLASH progamming Timeout + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check for the Flash Status */ + status = FLASH_GetBank1Status(); + /* Wait for a Flash operation to complete or a TIMEOUT to occur */ + while((status == FLASH_FLAG_BANK1_BSY) && (Timeout != 0x00)) + { + status = FLASH_GetBank1Status(); + Timeout--; + } + if(Timeout == 0x00 ) + { + status = FLASH_TIMEOUT; + } + /* Return the operation status */ + return status; +} + +#ifdef STM32F10X_XL +/** + * @brief Waits for a Flash operation on Bank2 to complete or a TIMEOUT to occur. + * @note This function can be used only for STM32F10x_XL density devices. + * @param Timeout: FLASH progamming Timeout + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_WaitForLastBank2Operation(uint32_t Timeout) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check for the Flash Status */ + status = FLASH_GetBank2Status(); + /* Wait for a Flash operation to complete or a TIMEOUT to occur */ + while((status == (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF)) && (Timeout != 0x00)) + { + status = FLASH_GetBank2Status(); + Timeout--; + } + if(Timeout == 0x00 ) + { + status = FLASH_TIMEOUT; + } + /* Return the operation status */ + return status; +} +#endif /* STM32F10X_XL */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32f10x/stm32f10x_fsmc.c b/example/libs_stm/src/stm32f10x/stm32f10x_fsmc.c new file mode 100644 index 0000000..d042219 --- /dev/null +++ b/example/libs_stm/src/stm32f10x/stm32f10x_fsmc.c @@ -0,0 +1,858 @@ +/** + ****************************************************************************** + * @file stm32f10x_fsmc.c + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file provides all the FSMC firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_fsmc.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup FSMC + * @brief FSMC driver modules + * @{ + */ + +/** @defgroup FSMC_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + +/** @defgroup FSMC_Private_Defines + * @{ + */ + +/* --------------------- FSMC registers bit mask ---------------------------- */ + +/* FSMC BCRx Mask */ +#define BCR_MBKEN_Set ((uint32_t)0x00000001) +#define BCR_MBKEN_Reset ((uint32_t)0x000FFFFE) +#define BCR_FACCEN_Set ((uint32_t)0x00000040) + +/* FSMC PCRx Mask */ +#define PCR_PBKEN_Set ((uint32_t)0x00000004) +#define PCR_PBKEN_Reset ((uint32_t)0x000FFFFB) +#define PCR_ECCEN_Set ((uint32_t)0x00000040) +#define PCR_ECCEN_Reset ((uint32_t)0x000FFFBF) +#define PCR_MemoryType_NAND ((uint32_t)0x00000008) +/** + * @} + */ + +/** @defgroup FSMC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup FSMC_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup FSMC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup FSMC_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the FSMC NOR/SRAM Banks registers to their default + * reset values. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1 + * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 + * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 + * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 + * @retval None + */ +void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank) +{ + /* Check the parameter */ + assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank)); + + /* FSMC_Bank1_NORSRAM1 */ + if(FSMC_Bank == FSMC_Bank1_NORSRAM1) + { + FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB; + } + /* FSMC_Bank1_NORSRAM2, FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */ + else + { + FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2; + } + FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF; + FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF; +} + +/** + * @brief Deinitializes the FSMC NAND Banks registers to their default reset values. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @retval None + */ +void FSMC_NANDDeInit(uint32_t FSMC_Bank) +{ + /* Check the parameter */ + assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + /* Set the FSMC_Bank2 registers to their reset values */ + FSMC_Bank2->PCR2 = 0x00000018; + FSMC_Bank2->SR2 = 0x00000040; + FSMC_Bank2->PMEM2 = 0xFCFCFCFC; + FSMC_Bank2->PATT2 = 0xFCFCFCFC; + } + /* FSMC_Bank3_NAND */ + else + { + /* Set the FSMC_Bank3 registers to their reset values */ + FSMC_Bank3->PCR3 = 0x00000018; + FSMC_Bank3->SR3 = 0x00000040; + FSMC_Bank3->PMEM3 = 0xFCFCFCFC; + FSMC_Bank3->PATT3 = 0xFCFCFCFC; + } +} + +/** + * @brief Deinitializes the FSMC PCCARD Bank registers to their default reset values. + * @param None + * @retval None + */ +void FSMC_PCCARDDeInit(void) +{ + /* Set the FSMC_Bank4 registers to their reset values */ + FSMC_Bank4->PCR4 = 0x00000018; + FSMC_Bank4->SR4 = 0x00000000; + FSMC_Bank4->PMEM4 = 0xFCFCFCFC; + FSMC_Bank4->PATT4 = 0xFCFCFCFC; + FSMC_Bank4->PIO4 = 0xFCFCFCFC; +} + +/** + * @brief Initializes the FSMC NOR/SRAM Banks according to the specified + * parameters in the FSMC_NORSRAMInitStruct. + * @param FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef + * structure that contains the configuration information for + * the FSMC NOR/SRAM specified Banks. + * @retval None + */ +void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct) +{ + /* Check the parameters */ + assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank)); + assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux)); + assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType)); + assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth)); + assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode)); + assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity)); + assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode)); + assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive)); + assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation)); + assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal)); + assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode)); + assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst)); + assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime)); + assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime)); + assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime)); + assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration)); + assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision)); + assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency)); + assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode)); + + /* Bank1 NOR/SRAM control register configuration */ + FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] = + (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux | + FSMC_NORSRAMInitStruct->FSMC_MemoryType | + FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth | + FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode | + FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity | + FSMC_NORSRAMInitStruct->FSMC_WrapMode | + FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive | + FSMC_NORSRAMInitStruct->FSMC_WriteOperation | + FSMC_NORSRAMInitStruct->FSMC_WaitSignal | + FSMC_NORSRAMInitStruct->FSMC_ExtendedMode | + FSMC_NORSRAMInitStruct->FSMC_WriteBurst; + if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR) + { + FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_Set; + } + /* Bank1 NOR/SRAM timing register configuration */ + FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] = + (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) | + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode; + + + /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */ + if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable) + { + assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime)); + assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime)); + assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime)); + assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision)); + assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency)); + assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode)); + FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = + (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime | + (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )| + (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) | + (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) | + (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) | + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode; + } + else + { + FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF; + } +} + +/** + * @brief Initializes the FSMC NAND Banks according to the specified + * parameters in the FSMC_NANDInitStruct. + * @param FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef + * structure that contains the configuration information for the FSMC NAND specified Banks. + * @retval None + */ +void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct) +{ + uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000; + + /* Check the parameters */ + assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank)); + assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature)); + assert_param( IS_FSMC_MEMORY_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth)); + assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC)); + assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize)); + assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime)); + assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime)); + assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime)); + assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime)); + assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime)); + assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime)); + assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime)); + assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime)); + assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime)); + assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime)); + + /* Set the tmppcr value according to FSMC_NANDInitStruct parameters */ + tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature | + PCR_MemoryType_NAND | + FSMC_NANDInitStruct->FSMC_MemoryDataWidth | + FSMC_NANDInitStruct->FSMC_ECC | + FSMC_NANDInitStruct->FSMC_ECCPageSize | + (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )| + (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13); + + /* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */ + tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime | + (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) | + (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)| + (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); + + /* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */ + tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime | + (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) | + (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)| + (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24); + + if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND) + { + /* FSMC_Bank2_NAND registers configuration */ + FSMC_Bank2->PCR2 = tmppcr; + FSMC_Bank2->PMEM2 = tmppmem; + FSMC_Bank2->PATT2 = tmppatt; + } + else + { + /* FSMC_Bank3_NAND registers configuration */ + FSMC_Bank3->PCR3 = tmppcr; + FSMC_Bank3->PMEM3 = tmppmem; + FSMC_Bank3->PATT3 = tmppatt; + } +} + +/** + * @brief Initializes the FSMC PCCARD Bank according to the specified + * parameters in the FSMC_PCCARDInitStruct. + * @param FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef + * structure that contains the configuration information for the FSMC PCCARD Bank. + * @retval None + */ +void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct) +{ + /* Check the parameters */ + assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature)); + assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime)); + assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime)); + + assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime)); + assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime)); + assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime)); + assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime)); + + assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime)); + assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime)); + assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime)); + assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime)); + assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime)); + assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime)); + assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime)); + assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime)); + + /* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */ + FSMC_Bank4->PCR4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature | + FSMC_MemoryDataWidth_16b | + (FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) | + (FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13); + + /* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */ + FSMC_Bank4->PMEM4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime | + (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) | + (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)| + (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); + + /* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */ + FSMC_Bank4->PATT4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime | + (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) | + (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)| + (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24); + + /* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */ + FSMC_Bank4->PIO4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime | + (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) | + (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)| + (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24); +} + +/** + * @brief Fills each FSMC_NORSRAMInitStruct member with its default value. + * @param FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef + * structure which will be initialized. + * @retval None + */ +void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct) +{ + /* Reset NOR/SRAM Init structure parameters values */ + FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1; + FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable; + FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM; + FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; + FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable; + FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; +} + +/** + * @brief Fills each FSMC_NANDInitStruct member with its default value. + * @param FSMC_NANDInitStruct: pointer to a FSMC_NANDInitTypeDef + * structure which will be initialized. + * @retval None + */ +void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct) +{ + /* Reset NAND Init structure parameters values */ + FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND; + FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable; + FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; + FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable; + FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes; + FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0; + FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0; + FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; +} + +/** + * @brief Fills each FSMC_PCCARDInitStruct member with its default value. + * @param FSMC_PCCARDInitStruct: pointer to a FSMC_PCCARDInitTypeDef + * structure which will be initialized. + * @retval None + */ +void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct) +{ + /* Reset PCCARD Init structure parameters values */ + FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable; + FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0; + FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0; + FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; +} + +/** + * @brief Enables or disables the specified NOR/SRAM Memory Bank. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1 + * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 + * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 + * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 + * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState) +{ + assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */ + FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_Set; + } + else + { + /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */ + FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_Reset; + } +} + +/** + * @brief Enables or disables the specified NAND Memory Bank. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState) +{ + assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->PCR2 |= PCR_PBKEN_Set; + } + else + { + FSMC_Bank3->PCR3 |= PCR_PBKEN_Set; + } + } + else + { + /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->PCR2 &= PCR_PBKEN_Reset; + } + else + { + FSMC_Bank3->PCR3 &= PCR_PBKEN_Reset; + } + } +} + +/** + * @brief Enables or disables the PCCARD Memory Bank. + * @param NewState: new state of the PCCARD Memory Bank. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FSMC_PCCARDCmd(FunctionalState NewState) +{ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */ + FSMC_Bank4->PCR4 |= PCR_PBKEN_Set; + } + else + { + /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */ + FSMC_Bank4->PCR4 &= PCR_PBKEN_Reset; + } +} + +/** + * @brief Enables or disables the FSMC NAND ECC feature. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @param NewState: new state of the FSMC NAND ECC feature. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState) +{ + assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->PCR2 |= PCR_ECCEN_Set; + } + else + { + FSMC_Bank3->PCR3 |= PCR_ECCEN_Set; + } + } + else + { + /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->PCR2 &= PCR_ECCEN_Reset; + } + else + { + FSMC_Bank3->PCR3 &= PCR_ECCEN_Reset; + } + } +} + +/** + * @brief Returns the error correction code register value. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @retval The Error Correction Code (ECC) value. + */ +uint32_t FSMC_GetECC(uint32_t FSMC_Bank) +{ + uint32_t eccval = 0x00000000; + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + /* Get the ECCR2 register value */ + eccval = FSMC_Bank2->ECCR2; + } + else + { + /* Get the ECCR3 register value */ + eccval = FSMC_Bank3->ECCR3; + } + /* Return the error correction code value */ + return(eccval); +} + +/** + * @brief Enables or disables the specified FSMC interrupts. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD + * @param FSMC_IT: specifies the FSMC interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. + * @arg FSMC_IT_Level: Level edge detection interrupt. + * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. + * @param NewState: new state of the specified FSMC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState) +{ + assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); + assert_param(IS_FSMC_IT(FSMC_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected FSMC_Bank2 interrupts */ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->SR2 |= FSMC_IT; + } + /* Enable the selected FSMC_Bank3 interrupts */ + else if (FSMC_Bank == FSMC_Bank3_NAND) + { + FSMC_Bank3->SR3 |= FSMC_IT; + } + /* Enable the selected FSMC_Bank4 interrupts */ + else + { + FSMC_Bank4->SR4 |= FSMC_IT; + } + } + else + { + /* Disable the selected FSMC_Bank2 interrupts */ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + + FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT; + } + /* Disable the selected FSMC_Bank3 interrupts */ + else if (FSMC_Bank == FSMC_Bank3_NAND) + { + FSMC_Bank3->SR3 &= (uint32_t)~FSMC_IT; + } + /* Disable the selected FSMC_Bank4 interrupts */ + else + { + FSMC_Bank4->SR4 &= (uint32_t)~FSMC_IT; + } + } +} + +/** + * @brief Checks whether the specified FSMC flag is set or not. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD + * @param FSMC_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag. + * @arg FSMC_FLAG_Level: Level detection Flag. + * @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag. + * @arg FSMC_FLAG_FEMPT: Fifo empty Flag. + * @retval The new state of FSMC_FLAG (SET or RESET). + */ +FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG) +{ + FlagStatus bitstatus = RESET; + uint32_t tmpsr = 0x00000000; + + /* Check the parameters */ + assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank)); + assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG)); + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + tmpsr = FSMC_Bank2->SR2; + } + else if(FSMC_Bank == FSMC_Bank3_NAND) + { + tmpsr = FSMC_Bank3->SR3; + } + /* FSMC_Bank4_PCCARD*/ + else + { + tmpsr = FSMC_Bank4->SR4; + } + + /* Get the flag status */ + if ((tmpsr & FSMC_FLAG) != (uint16_t)RESET ) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the flag status */ + return bitstatus; +} + +/** + * @brief Clears the FSMC’s pending flags. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD + * @param FSMC_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag. + * @arg FSMC_FLAG_Level: Level detection Flag. + * @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag. + * @retval None + */ +void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG) +{ + /* Check the parameters */ + assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank)); + assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ; + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->SR2 &= ~FSMC_FLAG; + } + else if(FSMC_Bank == FSMC_Bank3_NAND) + { + FSMC_Bank3->SR3 &= ~FSMC_FLAG; + } + /* FSMC_Bank4_PCCARD*/ + else + { + FSMC_Bank4->SR4 &= ~FSMC_FLAG; + } +} + +/** + * @brief Checks whether the specified FSMC interrupt has occurred or not. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD + * @param FSMC_IT: specifies the FSMC interrupt source to check. + * This parameter can be one of the following values: + * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. + * @arg FSMC_IT_Level: Level edge detection interrupt. + * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. + * @retval The new state of FSMC_IT (SET or RESET). + */ +ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT) +{ + ITStatus bitstatus = RESET; + uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0; + + /* Check the parameters */ + assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); + assert_param(IS_FSMC_GET_IT(FSMC_IT)); + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + tmpsr = FSMC_Bank2->SR2; + } + else if(FSMC_Bank == FSMC_Bank3_NAND) + { + tmpsr = FSMC_Bank3->SR3; + } + /* FSMC_Bank4_PCCARD*/ + else + { + tmpsr = FSMC_Bank4->SR4; + } + + itstatus = tmpsr & FSMC_IT; + + itenable = tmpsr & (FSMC_IT >> 3); + if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the FSMC’s interrupt pending bits. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD + * @param FSMC_IT: specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. + * @arg FSMC_IT_Level: Level edge detection interrupt. + * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. + * @retval None + */ +void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT) +{ + /* Check the parameters */ + assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); + assert_param(IS_FSMC_IT(FSMC_IT)); + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3); + } + else if(FSMC_Bank == FSMC_Bank3_NAND) + { + FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3); + } + /* FSMC_Bank4_PCCARD*/ + else + { + FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3); + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32f10x/stm32f10x_gpio.c b/example/libs_stm/src/stm32f10x/stm32f10x_gpio.c new file mode 100644 index 0000000..0978e98 --- /dev/null +++ b/example/libs_stm/src/stm32f10x/stm32f10x_gpio.c @@ -0,0 +1,642 @@ +/** + ****************************************************************************** + * @file stm32f10x_gpio.c + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file provides all the GPIO firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_gpio.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup GPIO + * @brief GPIO driver modules + * @{ + */ + +/** @defgroup GPIO_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup GPIO_Private_Defines + * @{ + */ + +/* ------------ RCC registers bit address in the alias region ----------------*/ +#define AFIO_OFFSET (AFIO_BASE - PERIPH_BASE) + +/* --- EVENTCR Register -----*/ + +/* Alias word address of EVOE bit */ +#define EVCR_OFFSET (AFIO_OFFSET + 0x00) +#define EVOE_BitNumber ((uint8_t)0x07) +#define EVCR_EVOE_BB (PERIPH_BB_BASE + (EVCR_OFFSET * 32) + (EVOE_BitNumber * 4)) + + +/* --- MAPR Register ---*/ +/* Alias word address of MII_RMII_SEL bit */ +#define MAPR_OFFSET (AFIO_OFFSET + 0x04) +#define MII_RMII_SEL_BitNumber ((u8)0x17) +#define MAPR_MII_RMII_SEL_BB (PERIPH_BB_BASE + (MAPR_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4)) + + +#define EVCR_PORTPINCONFIG_MASK ((uint16_t)0xFF80) +#define LSB_MASK ((uint16_t)0xFFFF) +#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000) +#define DBGAFR_SWJCFG_MASK ((uint32_t)0xF0FFFFFF) +#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000) +#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000) +/** + * @} + */ + +/** @defgroup GPIO_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup GPIO_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup GPIO_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup GPIO_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the GPIOx peripheral registers to their default reset values. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @retval None + */ +void GPIO_DeInit(GPIO_TypeDef* GPIOx) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + if (GPIOx == GPIOA) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE); + } + else if (GPIOx == GPIOB) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE); + } + else if (GPIOx == GPIOC) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE); + } + else if (GPIOx == GPIOD) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE); + } + else if (GPIOx == GPIOE) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE); + } + else if (GPIOx == GPIOF) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, DISABLE); + } + else + { + if (GPIOx == GPIOG) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, DISABLE); + } + } +} + +/** + * @brief Deinitializes the Alternate Functions (remap, event control + * and EXTI configuration) registers to their default reset values. + * @param None + * @retval None + */ +void GPIO_AFIODeInit(void) +{ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE); +} + +/** + * @brief Initializes the GPIOx peripheral according to the specified + * parameters in the GPIO_InitStruct. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that + * contains the configuration information for the specified GPIO peripheral. + * @retval None + */ +void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct) +{ + uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00; + uint32_t tmpreg = 0x00, pinmask = 0x00; + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode)); + assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin)); + +/*---------------------------- GPIO Mode Configuration -----------------------*/ + currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F); + if ((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00) + { + /* Check the parameters */ + assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed)); + /* Output mode */ + currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed; + } +/*---------------------------- GPIO CRL Configuration ------------------------*/ + /* Configure the eight low port pins */ + if (((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00) + { + tmpreg = GPIOx->CRL; + for (pinpos = 0x00; pinpos < 0x08; pinpos++) + { + pos = ((uint32_t)0x01) << pinpos; + /* Get the port pins position */ + currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; + if (currentpin == pos) + { + pos = pinpos << 2; + /* Clear the corresponding low control register bits */ + pinmask = ((uint32_t)0x0F) << pos; + tmpreg &= ~pinmask; + /* Write the mode configuration in the corresponding bits */ + tmpreg |= (currentmode << pos); + /* Reset the corresponding ODR bit */ + if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) + { + GPIOx->BRR = (((uint32_t)0x01) << pinpos); + } + else + { + /* Set the corresponding ODR bit */ + if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) + { + GPIOx->BSRR = (((uint32_t)0x01) << pinpos); + } + } + } + } + GPIOx->CRL = tmpreg; + } +/*---------------------------- GPIO CRH Configuration ------------------------*/ + /* Configure the eight high port pins */ + if (GPIO_InitStruct->GPIO_Pin > 0x00FF) + { + tmpreg = GPIOx->CRH; + for (pinpos = 0x00; pinpos < 0x08; pinpos++) + { + pos = (((uint32_t)0x01) << (pinpos + 0x08)); + /* Get the port pins position */ + currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos); + if (currentpin == pos) + { + pos = pinpos << 2; + /* Clear the corresponding high control register bits */ + pinmask = ((uint32_t)0x0F) << pos; + tmpreg &= ~pinmask; + /* Write the mode configuration in the corresponding bits */ + tmpreg |= (currentmode << pos); + /* Reset the corresponding ODR bit */ + if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) + { + GPIOx->BRR = (((uint32_t)0x01) << (pinpos + 0x08)); + } + /* Set the corresponding ODR bit */ + if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) + { + GPIOx->BSRR = (((uint32_t)0x01) << (pinpos + 0x08)); + } + } + } + GPIOx->CRH = tmpreg; + } +} + +/** + * @brief Fills each GPIO_InitStruct member with its default value. + * @param GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct) +{ + /* Reset GPIO init structure parameters values */ + GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; + GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING; +} + +/** + * @brief Reads the specified input port pin. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bit to read. + * This parameter can be GPIO_Pin_x where x can be (0..15). + * @retval The input port pin value. + */ +uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + uint8_t bitstatus = 0x00; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); + + if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + return bitstatus; +} + +/** + * @brief Reads the specified GPIO input data port. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @retval GPIO input data port value. + */ +uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + return ((uint16_t)GPIOx->IDR); +} + +/** + * @brief Reads the specified output data port bit. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bit to read. + * This parameter can be GPIO_Pin_x where x can be (0..15). + * @retval The output port pin value. + */ +uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + uint8_t bitstatus = 0x00; + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); + + if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + return bitstatus; +} + +/** + * @brief Reads the specified GPIO output data port. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @retval GPIO output data port value. + */ +uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + return ((uint16_t)GPIOx->ODR); +} + +/** + * @brief Sets the selected data port bits. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bits to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval None + */ +void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + GPIOx->BSRR = GPIO_Pin; +} + +/** + * @brief Clears the selected data port bits. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bits to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval None + */ +void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + GPIOx->BRR = GPIO_Pin; +} + +/** + * @brief Sets or clears the selected data port bit. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bit to be written. + * This parameter can be one of GPIO_Pin_x where x can be (0..15). + * @param BitVal: specifies the value to be written to the selected bit. + * This parameter can be one of the BitAction enum values: + * @arg Bit_RESET: to clear the port pin + * @arg Bit_SET: to set the port pin + * @retval None + */ +void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_BIT_ACTION(BitVal)); + + if (BitVal != Bit_RESET) + { + GPIOx->BSRR = GPIO_Pin; + } + else + { + GPIOx->BRR = GPIO_Pin; + } +} + +/** + * @brief Writes data to the specified GPIO data port. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @param PortVal: specifies the value to be written to the port output data register. + * @retval None + */ +void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + GPIOx->ODR = PortVal; +} + +/** + * @brief Locks GPIO Pins configuration registers. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bit to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval None + */ +void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + uint32_t tmp = 0x00010000; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + tmp |= GPIO_Pin; + /* Set LCKK bit */ + GPIOx->LCKR = tmp; + /* Reset LCKK bit */ + GPIOx->LCKR = GPIO_Pin; + /* Set LCKK bit */ + GPIOx->LCKR = tmp; + /* Read LCKK bit*/ + tmp = GPIOx->LCKR; + /* Read LCKK bit*/ + tmp = GPIOx->LCKR; +} + +/** + * @brief Selects the GPIO pin used as Event output. + * @param GPIO_PortSource: selects the GPIO port to be used as source + * for Event output. + * This parameter can be GPIO_PortSourceGPIOx where x can be (A..E). + * @param GPIO_PinSource: specifies the pin for the Event output. + * This parameter can be GPIO_PinSourcex where x can be (0..15). + * @retval None + */ +void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource) +{ + uint32_t tmpreg = 0x00; + /* Check the parameters */ + assert_param(IS_GPIO_EVENTOUT_PORT_SOURCE(GPIO_PortSource)); + assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource)); + + tmpreg = AFIO->EVCR; + /* Clear the PORT[6:4] and PIN[3:0] bits */ + tmpreg &= EVCR_PORTPINCONFIG_MASK; + tmpreg |= (uint32_t)GPIO_PortSource << 0x04; + tmpreg |= GPIO_PinSource; + AFIO->EVCR = tmpreg; +} + +/** + * @brief Enables or disables the Event Output. + * @param NewState: new state of the Event output. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void GPIO_EventOutputCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) EVCR_EVOE_BB = (uint32_t)NewState; +} + +/** + * @brief Changes the mapping of the specified pin. + * @param GPIO_Remap: selects the pin to remap. + * This parameter can be one of the following values: + * @arg GPIO_Remap_SPI1 + * @arg GPIO_Remap_I2C1 + * @arg GPIO_Remap_USART1 + * @arg GPIO_Remap_USART2 + * @arg GPIO_PartialRemap_USART3 + * @arg GPIO_FullRemap_USART3 + * @arg GPIO_PartialRemap_TIM1 + * @arg GPIO_FullRemap_TIM1 + * @arg GPIO_PartialRemap1_TIM2 + * @arg GPIO_PartialRemap2_TIM2 + * @arg GPIO_FullRemap_TIM2 + * @arg GPIO_PartialRemap_TIM3 + * @arg GPIO_FullRemap_TIM3 + * @arg GPIO_Remap_TIM4 + * @arg GPIO_Remap1_CAN1 + * @arg GPIO_Remap2_CAN1 + * @arg GPIO_Remap_PD01 + * @arg GPIO_Remap_TIM5CH4_LSI + * @arg GPIO_Remap_ADC1_ETRGINJ + * @arg GPIO_Remap_ADC1_ETRGREG + * @arg GPIO_Remap_ADC2_ETRGINJ + * @arg GPIO_Remap_ADC2_ETRGREG + * @arg GPIO_Remap_ETH + * @arg GPIO_Remap_CAN2 + * @arg GPIO_Remap_SWJ_NoJTRST + * @arg GPIO_Remap_SWJ_JTAGDisable + * @arg GPIO_Remap_SWJ_Disable + * @arg GPIO_Remap_SPI3 + * @arg GPIO_Remap_TIM2ITR1_PTP_SOF + * @arg GPIO_Remap_PTP_PPS + * @arg GPIO_Remap_TIM15 + * @arg GPIO_Remap_TIM16 + * @arg GPIO_Remap_TIM17 + * @arg GPIO_Remap_CEC + * @arg GPIO_Remap_TIM1_DMA + * @arg GPIO_Remap_TIM9 + * @arg GPIO_Remap_TIM10 + * @arg GPIO_Remap_TIM11 + * @arg GPIO_Remap_TIM13 + * @arg GPIO_Remap_TIM14 + * @arg GPIO_Remap_FSMC_NADV + * @note If the GPIO_Remap_TIM2ITR1_PTP_SOF is enabled the TIM2 ITR1 is connected + * to Ethernet PTP output. When Reset TIM2 ITR1 is connected to USB OTG SOF output. + * @param NewState: new state of the port pin remapping. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState) +{ + uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00; + + /* Check the parameters */ + assert_param(IS_GPIO_REMAP(GPIO_Remap)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if((GPIO_Remap & 0x80000000) == 0x80000000) + { + tmpreg = AFIO->MAPR2; + } + else + { + tmpreg = AFIO->MAPR; + } + + tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10; + tmp = GPIO_Remap & LSB_MASK; + + if ((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) + { + tmpreg &= DBGAFR_SWJCFG_MASK; + AFIO->MAPR &= DBGAFR_SWJCFG_MASK; + } + else if ((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK) + { + tmp1 = ((uint32_t)0x03) << tmpmask; + tmpreg &= ~tmp1; + tmpreg |= ~DBGAFR_SWJCFG_MASK; + } + else + { + tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15)*0x10)); + tmpreg |= ~DBGAFR_SWJCFG_MASK; + } + + if (NewState != DISABLE) + { + tmpreg |= (tmp << ((GPIO_Remap >> 0x15)*0x10)); + } + + if((GPIO_Remap & 0x80000000) == 0x80000000) + { + AFIO->MAPR2 = tmpreg; + } + else + { + AFIO->MAPR = tmpreg; + } +} + +/** + * @brief Selects the GPIO pin used as EXTI Line. + * @param GPIO_PortSource: selects the GPIO port to be used as source for EXTI lines. + * This parameter can be GPIO_PortSourceGPIOx where x can be (A..G). + * @param GPIO_PinSource: specifies the EXTI line to be configured. + * This parameter can be GPIO_PinSourcex where x can be (0..15). + * @retval None + */ +void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource) +{ + uint32_t tmp = 0x00; + /* Check the parameters */ + assert_param(IS_GPIO_EXTI_PORT_SOURCE(GPIO_PortSource)); + assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource)); + + tmp = ((uint32_t)0x0F) << (0x04 * (GPIO_PinSource & (uint8_t)0x03)); + AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp; + AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((uint32_t)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (uint8_t)0x03))); +} + +/** + * @brief Selects the Ethernet media interface. + * @note This function applies only to STM32 Connectivity line devices. + * @param GPIO_ETH_MediaInterface: specifies the Media Interface mode. + * This parameter can be one of the following values: + * @arg GPIO_ETH_MediaInterface_MII: MII mode + * @arg GPIO_ETH_MediaInterface_RMII: RMII mode + * @retval None + */ +void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface) +{ + assert_param(IS_GPIO_ETH_MEDIA_INTERFACE(GPIO_ETH_MediaInterface)); + + /* Configure MII_RMII selection bit */ + *(__IO uint32_t *) MAPR_MII_RMII_SEL_BB = GPIO_ETH_MediaInterface; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32f10x/stm32f10x_i2c.c b/example/libs_stm/src/stm32f10x/stm32f10x_i2c.c new file mode 100644 index 0000000..32545f5 --- /dev/null +++ b/example/libs_stm/src/stm32f10x/stm32f10x_i2c.c @@ -0,0 +1,1285 @@ +/** + ****************************************************************************** + * @file stm32f10x_i2c.c + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file provides all the I2C firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_i2c.h" +#include "stm32f10x_rcc.h" + + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup I2C + * @brief I2C driver modules + * @{ + */ + +/** @defgroup I2C_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup I2C_Private_Defines + * @{ + */ + +/* I2C SPE mask */ +#define CR1_PE_Set ((uint16_t)0x0001) +#define CR1_PE_Reset ((uint16_t)0xFFFE) + +/* I2C START mask */ +#define CR1_START_Set ((uint16_t)0x0100) +#define CR1_START_Reset ((uint16_t)0xFEFF) + +/* I2C STOP mask */ +#define CR1_STOP_Set ((uint16_t)0x0200) +#define CR1_STOP_Reset ((uint16_t)0xFDFF) + +/* I2C ACK mask */ +#define CR1_ACK_Set ((uint16_t)0x0400) +#define CR1_ACK_Reset ((uint16_t)0xFBFF) + +/* I2C ENGC mask */ +#define CR1_ENGC_Set ((uint16_t)0x0040) +#define CR1_ENGC_Reset ((uint16_t)0xFFBF) + +/* I2C SWRST mask */ +#define CR1_SWRST_Set ((uint16_t)0x8000) +#define CR1_SWRST_Reset ((uint16_t)0x7FFF) + +/* I2C PEC mask */ +#define CR1_PEC_Set ((uint16_t)0x1000) +#define CR1_PEC_Reset ((uint16_t)0xEFFF) + +/* I2C ENPEC mask */ +#define CR1_ENPEC_Set ((uint16_t)0x0020) +#define CR1_ENPEC_Reset ((uint16_t)0xFFDF) + +/* I2C ENARP mask */ +#define CR1_ENARP_Set ((uint16_t)0x0010) +#define CR1_ENARP_Reset ((uint16_t)0xFFEF) + +/* I2C NOSTRETCH mask */ +#define CR1_NOSTRETCH_Set ((uint16_t)0x0080) +#define CR1_NOSTRETCH_Reset ((uint16_t)0xFF7F) + +/* I2C registers Masks */ +#define CR1_CLEAR_Mask ((uint16_t)0xFBF5) + +/* I2C DMAEN mask */ +#define CR2_DMAEN_Set ((uint16_t)0x0800) +#define CR2_DMAEN_Reset ((uint16_t)0xF7FF) + +/* I2C LAST mask */ +#define CR2_LAST_Set ((uint16_t)0x1000) +#define CR2_LAST_Reset ((uint16_t)0xEFFF) + +/* I2C FREQ mask */ +#define CR2_FREQ_Reset ((uint16_t)0xFFC0) + +/* I2C ADD0 mask */ +#define OAR1_ADD0_Set ((uint16_t)0x0001) +#define OAR1_ADD0_Reset ((uint16_t)0xFFFE) + +/* I2C ENDUAL mask */ +#define OAR2_ENDUAL_Set ((uint16_t)0x0001) +#define OAR2_ENDUAL_Reset ((uint16_t)0xFFFE) + +/* I2C ADD2 mask */ +#define OAR2_ADD2_Reset ((uint16_t)0xFF01) + +/* I2C F/S mask */ +#define CCR_FS_Set ((uint16_t)0x8000) + +/* I2C CCR mask */ +#define CCR_CCR_Set ((uint16_t)0x0FFF) + +/* I2C FLAG mask */ +#define FLAG_Mask ((uint32_t)0x00FFFFFF) + +/* I2C Interrupt Enable mask */ +#define ITEN_Mask ((uint32_t)0x07000000) + +/** + * @} + */ + +/** @defgroup I2C_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup I2C_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup I2C_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup I2C_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the I2Cx peripheral registers to their default reset values. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @retval None + */ +void I2C_DeInit(I2C_TypeDef* I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + + if (I2Cx == I2C1) + { + /* Enable I2C1 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE); + /* Release I2C1 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE); + } + else + { + /* Enable I2C2 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE); + /* Release I2C2 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE); + } +} + +/** + * @brief Initializes the I2Cx peripheral according to the specified + * parameters in the I2C_InitStruct. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_InitStruct: pointer to a I2C_InitTypeDef structure that + * contains the configuration information for the specified I2C peripheral. + * @retval None + */ +void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct) +{ + uint16_t tmpreg = 0, freqrange = 0; + uint16_t result = 0x04; + uint32_t pclk1 = 8000000; + RCC_ClocksTypeDef rcc_clocks; + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_CLOCK_SPEED(I2C_InitStruct->I2C_ClockSpeed)); + assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode)); + assert_param(IS_I2C_DUTY_CYCLE(I2C_InitStruct->I2C_DutyCycle)); + assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1)); + assert_param(IS_I2C_ACK_STATE(I2C_InitStruct->I2C_Ack)); + assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress)); + +/*---------------------------- I2Cx CR2 Configuration ------------------------*/ + /* Get the I2Cx CR2 value */ + tmpreg = I2Cx->CR2; + /* Clear frequency FREQ[5:0] bits */ + tmpreg &= CR2_FREQ_Reset; + /* Get pclk1 frequency value */ + RCC_GetClocksFreq(&rcc_clocks); + pclk1 = rcc_clocks.PCLK1_Frequency; + /* Set frequency bits depending on pclk1 value */ + freqrange = (uint16_t)(pclk1 / 1000000); + tmpreg |= freqrange; + /* Write to I2Cx CR2 */ + I2Cx->CR2 = tmpreg; + +/*---------------------------- I2Cx CCR Configuration ------------------------*/ + /* Disable the selected I2C peripheral to configure TRISE */ + I2Cx->CR1 &= CR1_PE_Reset; + /* Reset tmpreg value */ + /* Clear F/S, DUTY and CCR[11:0] bits */ + tmpreg = 0; + + /* Configure speed in standard mode */ + if (I2C_InitStruct->I2C_ClockSpeed <= 100000) + { + /* Standard mode speed calculate */ + result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1)); + /* Test if CCR value is under 0x4*/ + if (result < 0x04) + { + /* Set minimum allowed value */ + result = 0x04; + } + /* Set speed value for standard mode */ + tmpreg |= result; + /* Set Maximum Rise Time for standard mode */ + I2Cx->TRISE = freqrange + 1; + } + /* Configure speed in fast mode */ + else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/ + { + if (I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2) + { + /* Fast mode speed calculate: Tlow/Thigh = 2 */ + result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3)); + } + else /*I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_16_9*/ + { + /* Fast mode speed calculate: Tlow/Thigh = 16/9 */ + result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25)); + /* Set DUTY bit */ + result |= I2C_DutyCycle_16_9; + } + + /* Test if CCR value is under 0x1*/ + if ((result & CCR_CCR_Set) == 0) + { + /* Set minimum allowed value */ + result |= (uint16_t)0x0001; + } + /* Set speed value and set F/S bit for fast mode */ + tmpreg |= (uint16_t)(result | CCR_FS_Set); + /* Set Maximum Rise Time for fast mode */ + I2Cx->TRISE = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1); + } + + /* Write to I2Cx CCR */ + I2Cx->CCR = tmpreg; + /* Enable the selected I2C peripheral */ + I2Cx->CR1 |= CR1_PE_Set; + +/*---------------------------- I2Cx CR1 Configuration ------------------------*/ + /* Get the I2Cx CR1 value */ + tmpreg = I2Cx->CR1; + /* Clear ACK, SMBTYPE and SMBUS bits */ + tmpreg &= CR1_CLEAR_Mask; + /* Configure I2Cx: mode and acknowledgement */ + /* Set SMBTYPE and SMBUS bits according to I2C_Mode value */ + /* Set ACK bit according to I2C_Ack value */ + tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack); + /* Write to I2Cx CR1 */ + I2Cx->CR1 = tmpreg; + +/*---------------------------- I2Cx OAR1 Configuration -----------------------*/ + /* Set I2Cx Own Address1 and acknowledged address */ + I2Cx->OAR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1); +} + +/** + * @brief Fills each I2C_InitStruct member with its default value. + * @param I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized. + * @retval None + */ +void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct) +{ +/*---------------- Reset I2C init structure parameters values ----------------*/ + /* initialize the I2C_ClockSpeed member */ + I2C_InitStruct->I2C_ClockSpeed = 5000; + /* Initialize the I2C_Mode member */ + I2C_InitStruct->I2C_Mode = I2C_Mode_I2C; + /* Initialize the I2C_DutyCycle member */ + I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2; + /* Initialize the I2C_OwnAddress1 member */ + I2C_InitStruct->I2C_OwnAddress1 = 0; + /* Initialize the I2C_Ack member */ + I2C_InitStruct->I2C_Ack = I2C_Ack_Disable; + /* Initialize the I2C_AcknowledgedAddress member */ + I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; +} + +/** + * @brief Enables or disables the specified I2C peripheral. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2Cx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected I2C peripheral */ + I2Cx->CR1 |= CR1_PE_Set; + } + else + { + /* Disable the selected I2C peripheral */ + I2Cx->CR1 &= CR1_PE_Reset; + } +} + +/** + * @brief Enables or disables the specified I2C DMA requests. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C DMA transfer. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected I2C DMA requests */ + I2Cx->CR2 |= CR2_DMAEN_Set; + } + else + { + /* Disable the selected I2C DMA requests */ + I2Cx->CR2 &= CR2_DMAEN_Reset; + } +} + +/** + * @brief Specifies if the next DMA transfer will be the last one. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C DMA last transfer. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Next DMA transfer is the last transfer */ + I2Cx->CR2 |= CR2_LAST_Set; + } + else + { + /* Next DMA transfer is not the last transfer */ + I2Cx->CR2 &= CR2_LAST_Reset; + } +} + +/** + * @brief Generates I2Cx communication START condition. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C START condition generation. + * This parameter can be: ENABLE or DISABLE. + * @retval None. + */ +void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Generate a START condition */ + I2Cx->CR1 |= CR1_START_Set; + } + else + { + /* Disable the START condition generation */ + I2Cx->CR1 &= CR1_START_Reset; + } +} + +/** + * @brief Generates I2Cx communication STOP condition. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C STOP condition generation. + * This parameter can be: ENABLE or DISABLE. + * @retval None. + */ +void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Generate a STOP condition */ + I2Cx->CR1 |= CR1_STOP_Set; + } + else + { + /* Disable the STOP condition generation */ + I2Cx->CR1 &= CR1_STOP_Reset; + } +} + +/** + * @brief Enables or disables the specified I2C acknowledge feature. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C Acknowledgement. + * This parameter can be: ENABLE or DISABLE. + * @retval None. + */ +void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the acknowledgement */ + I2Cx->CR1 |= CR1_ACK_Set; + } + else + { + /* Disable the acknowledgement */ + I2Cx->CR1 &= CR1_ACK_Reset; + } +} + +/** + * @brief Configures the specified I2C own address2. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param Address: specifies the 7bit I2C own address2. + * @retval None. + */ +void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address) +{ + uint16_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + + /* Get the old register value */ + tmpreg = I2Cx->OAR2; + + /* Reset I2Cx Own address2 bit [7:1] */ + tmpreg &= OAR2_ADD2_Reset; + + /* Set I2Cx Own address2 */ + tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE); + + /* Store the new register value */ + I2Cx->OAR2 = tmpreg; +} + +/** + * @brief Enables or disables the specified I2C dual addressing mode. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C dual addressing mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable dual addressing mode */ + I2Cx->OAR2 |= OAR2_ENDUAL_Set; + } + else + { + /* Disable dual addressing mode */ + I2Cx->OAR2 &= OAR2_ENDUAL_Reset; + } +} + +/** + * @brief Enables or disables the specified I2C general call feature. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C General call. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable generall call */ + I2Cx->CR1 |= CR1_ENGC_Set; + } + else + { + /* Disable generall call */ + I2Cx->CR1 &= CR1_ENGC_Reset; + } +} + +/** + * @brief Enables or disables the specified I2C interrupts. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_IT: specifies the I2C interrupts sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg I2C_IT_BUF: Buffer interrupt mask + * @arg I2C_IT_EVT: Event interrupt mask + * @arg I2C_IT_ERR: Error interrupt mask + * @param NewState: new state of the specified I2C interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_I2C_CONFIG_IT(I2C_IT)); + + if (NewState != DISABLE) + { + /* Enable the selected I2C interrupts */ + I2Cx->CR2 |= I2C_IT; + } + else + { + /* Disable the selected I2C interrupts */ + I2Cx->CR2 &= (uint16_t)~I2C_IT; + } +} + +/** + * @brief Sends a data byte through the I2Cx peripheral. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param Data: Byte to be transmitted.. + * @retval None + */ +void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + /* Write in the DR register the data to be sent */ + I2Cx->DR = Data; +} + +/** + * @brief Returns the most recent received data by the I2Cx peripheral. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @retval The value of the received data. + */ +uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + /* Return the data in the DR register */ + return (uint8_t)I2Cx->DR; +} + +/** + * @brief Transmits the address byte to select the slave device. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param Address: specifies the slave address which will be transmitted + * @param I2C_Direction: specifies whether the I2C device will be a + * Transmitter or a Receiver. This parameter can be one of the following values + * @arg I2C_Direction_Transmitter: Transmitter mode + * @arg I2C_Direction_Receiver: Receiver mode + * @retval None. + */ +void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_DIRECTION(I2C_Direction)); + /* Test on the direction to set/reset the read/write bit */ + if (I2C_Direction != I2C_Direction_Transmitter) + { + /* Set the address bit0 for read */ + Address |= OAR1_ADD0_Set; + } + else + { + /* Reset the address bit0 for write */ + Address &= OAR1_ADD0_Reset; + } + /* Send the address */ + I2Cx->DR = Address; +} + +/** + * @brief Reads the specified I2C register and returns its value. + * @param I2C_Register: specifies the register to read. + * This parameter can be one of the following values: + * @arg I2C_Register_CR1: CR1 register. + * @arg I2C_Register_CR2: CR2 register. + * @arg I2C_Register_OAR1: OAR1 register. + * @arg I2C_Register_OAR2: OAR2 register. + * @arg I2C_Register_DR: DR register. + * @arg I2C_Register_SR1: SR1 register. + * @arg I2C_Register_SR2: SR2 register. + * @arg I2C_Register_CCR: CCR register. + * @arg I2C_Register_TRISE: TRISE register. + * @retval The value of the read register. + */ +uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_REGISTER(I2C_Register)); + + tmp = (uint32_t) I2Cx; + tmp += I2C_Register; + + /* Return the selected register value */ + return (*(__IO uint16_t *) tmp); +} + +/** + * @brief Enables or disables the specified I2C software reset. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C software reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Peripheral under reset */ + I2Cx->CR1 |= CR1_SWRST_Set; + } + else + { + /* Peripheral not under reset */ + I2Cx->CR1 &= CR1_SWRST_Reset; + } +} + +/** + * @brief Drives the SMBusAlert pin high or low for the specified I2C. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_SMBusAlert: specifies SMBAlert pin level. + * This parameter can be one of the following values: + * @arg I2C_SMBusAlert_Low: SMBAlert pin driven low + * @arg I2C_SMBusAlert_High: SMBAlert pin driven high + * @retval None + */ +void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_SMBUS_ALERT(I2C_SMBusAlert)); + if (I2C_SMBusAlert == I2C_SMBusAlert_Low) + { + /* Drive the SMBusAlert pin Low */ + I2Cx->CR1 |= I2C_SMBusAlert_Low; + } + else + { + /* Drive the SMBusAlert pin High */ + I2Cx->CR1 &= I2C_SMBusAlert_High; + } +} + +/** + * @brief Enables or disables the specified I2C PEC transfer. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C PEC transmission. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected I2C PEC transmission */ + I2Cx->CR1 |= CR1_PEC_Set; + } + else + { + /* Disable the selected I2C PEC transmission */ + I2Cx->CR1 &= CR1_PEC_Reset; + } +} + +/** + * @brief Selects the specified I2C PEC position. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_PECPosition: specifies the PEC position. + * This parameter can be one of the following values: + * @arg I2C_PECPosition_Next: indicates that the next byte is PEC + * @arg I2C_PECPosition_Current: indicates that current byte is PEC + * @retval None + */ +void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_PEC_POSITION(I2C_PECPosition)); + if (I2C_PECPosition == I2C_PECPosition_Next) + { + /* Next byte in shift register is PEC */ + I2Cx->CR1 |= I2C_PECPosition_Next; + } + else + { + /* Current byte in shift register is PEC */ + I2Cx->CR1 &= I2C_PECPosition_Current; + } +} + +/** + * @brief Enables or disables the PEC value calculation of the transfered bytes. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2Cx PEC value calculation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected I2C PEC calculation */ + I2Cx->CR1 |= CR1_ENPEC_Set; + } + else + { + /* Disable the selected I2C PEC calculation */ + I2Cx->CR1 &= CR1_ENPEC_Reset; + } +} + +/** + * @brief Returns the PEC value for the specified I2C. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @retval The PEC value. + */ +uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + /* Return the selected I2C PEC value */ + return ((I2Cx->SR2) >> 8); +} + +/** + * @brief Enables or disables the specified I2C ARP. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2Cx ARP. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected I2C ARP */ + I2Cx->CR1 |= CR1_ENARP_Set; + } + else + { + /* Disable the selected I2C ARP */ + I2Cx->CR1 &= CR1_ENARP_Reset; + } +} + +/** + * @brief Enables or disables the specified I2C Clock stretching. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2Cx Clock stretching. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState == DISABLE) + { + /* Enable the selected I2C Clock stretching */ + I2Cx->CR1 |= CR1_NOSTRETCH_Set; + } + else + { + /* Disable the selected I2C Clock stretching */ + I2Cx->CR1 &= CR1_NOSTRETCH_Reset; + } +} + +/** + * @brief Selects the specified I2C fast mode duty cycle. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_DutyCycle: specifies the fast mode duty cycle. + * This parameter can be one of the following values: + * @arg I2C_DutyCycle_2: I2C fast mode Tlow/Thigh = 2 + * @arg I2C_DutyCycle_16_9: I2C fast mode Tlow/Thigh = 16/9 + * @retval None + */ +void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_DUTY_CYCLE(I2C_DutyCycle)); + if (I2C_DutyCycle != I2C_DutyCycle_16_9) + { + /* I2C fast mode Tlow/Thigh=2 */ + I2Cx->CCR &= I2C_DutyCycle_2; + } + else + { + /* I2C fast mode Tlow/Thigh=16/9 */ + I2Cx->CCR |= I2C_DutyCycle_16_9; + } +} + + + +/** + * @brief + **************************************************************************************** + * + * I2C State Monitoring Functions + * + **************************************************************************************** + * This I2C driver provides three different ways for I2C state monitoring + * depending on the application requirements and constraints: + * + * + * 1) Basic state monitoring: + * Using I2C_CheckEvent() function: + * It compares the status registers (SR1 and SR2) content to a given event + * (can be the combination of one or more flags). + * It returns SUCCESS if the current status includes the given flags + * and returns ERROR if one or more flags are missing in the current status. + * - When to use: + * - This function is suitable for most applciations as well as for startup + * activity since the events are fully described in the product reference manual + * (RM0008). + * - It is also suitable for users who need to define their own events. + * - Limitations: + * - If an error occurs (ie. error flags are set besides to the monitored flags), + * the I2C_CheckEvent() function may return SUCCESS despite the communication + * hold or corrupted real state. + * In this case, it is advised to use error interrupts to monitor the error + * events and handle them in the interrupt IRQ handler. + * + * @note + * For error management, it is advised to use the following functions: + * - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR). + * - I2Cx_ER_IRQHandler() which is called when the error interurpt occurs. + * Where x is the peripheral instance (I2C1, I2C2 ...) + * - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into I2Cx_ER_IRQHandler() + * in order to determine which error occured. + * - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() + * and/or I2C_GenerateStop() in order to clear the error flag and source, + * and return to correct communication status. + * + * + * 2) Advanced state monitoring: + * Using the function I2C_GetLastEvent() which returns the image of both status + * registers in a single word (uint32_t) (Status Register 2 value is shifted left + * by 16 bits and concatenated to Status Register 1). + * - When to use: + * - This function is suitable for the same applications above but it allows to + * overcome the mentionned limitation of I2C_GetFlagStatus() function. + * The returned value could be compared to events already defined in the + * library (stm32f10x_i2c.h) or to custom values defiend by user. + * - This function is suitable when multiple flags are monitored at the same time. + * - At the opposite of I2C_CheckEvent() function, this function allows user to + * choose when an event is accepted (when all events flags are set and no + * other flags are set or just when the needed flags are set like + * I2C_CheckEvent() function). + * - Limitations: + * - User may need to define his own events. + * - Same remark concerning the error management is applicable for this + * function if user decides to check only regular communication flags (and + * ignores error flags). + * + * + * 3) Flag-based state monitoring: + * Using the function I2C_GetFlagStatus() which simply returns the status of + * one single flag (ie. I2C_FLAG_RXNE ...). + * - When to use: + * - This function could be used for specific applications or in debug phase. + * - It is suitable when only one flag checking is needed (most I2C events + * are monitored through multiple flags). + * - Limitations: + * - When calling this function, the Status register is accessed. Some flags are + * cleared when the status register is accessed. So checking the status + * of one Flag, may clear other ones. + * - Function may need to be called twice or more in order to monitor one + * single event. + * + * For detailed description of Events, please refer to section I2C_Events in + * stm32f10x_i2c.h file. + * + */ + +/** + * + * 1) Basic state monitoring + ******************************************************************************* + */ + +/** + * @brief Checks whether the last I2Cx Event is equal to the one passed + * as parameter. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_EVENT: specifies the event to be checked. + * This parameter can be one of the following values: + * @arg I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED : EV1 + * @arg I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED : EV1 + * @arg I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED : EV1 + * @arg I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED : EV1 + * @arg I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED : EV1 + * @arg I2C_EVENT_SLAVE_BYTE_RECEIVED : EV2 + * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF) : EV2 + * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL) : EV2 + * @arg I2C_EVENT_SLAVE_BYTE_TRANSMITTED : EV3 + * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF) : EV3 + * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL) : EV3 + * @arg I2C_EVENT_SLAVE_ACK_FAILURE : EV3_2 + * @arg I2C_EVENT_SLAVE_STOP_DETECTED : EV4 + * @arg I2C_EVENT_MASTER_MODE_SELECT : EV5 + * @arg I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED : EV6 + * @arg I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED : EV6 + * @arg I2C_EVENT_MASTER_BYTE_RECEIVED : EV7 + * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTING : EV8 + * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTED : EV8_2 + * @arg I2C_EVENT_MASTER_MODE_ADDRESS10 : EV9 + * + * @note: For detailed description of Events, please refer to section + * I2C_Events in stm32f10x_i2c.h file. + * + * @retval An ErrorStatus enumuration value: + * - SUCCESS: Last event is equal to the I2C_EVENT + * - ERROR: Last event is different from the I2C_EVENT + */ +ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT) +{ + uint32_t lastevent = 0; + uint32_t flag1 = 0, flag2 = 0; + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_EVENT(I2C_EVENT)); + + /* Read the I2Cx status register */ + flag1 = I2Cx->SR1; + flag2 = I2Cx->SR2; + flag2 = flag2 << 16; + + /* Get the last event value from I2C status register */ + lastevent = (flag1 | flag2) & FLAG_Mask; + + /* Check whether the last event contains the I2C_EVENT */ + if ((lastevent & I2C_EVENT) == I2C_EVENT) + { + /* SUCCESS: last event is equal to I2C_EVENT */ + status = SUCCESS; + } + else + { + /* ERROR: last event is different from I2C_EVENT */ + status = ERROR; + } + /* Return status */ + return status; +} + +/** + * + * 2) Advanced state monitoring + ******************************************************************************* + */ + +/** + * @brief Returns the last I2Cx Event. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * + * @note: For detailed description of Events, please refer to section + * I2C_Events in stm32f10x_i2c.h file. + * + * @retval The last event + */ +uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx) +{ + uint32_t lastevent = 0; + uint32_t flag1 = 0, flag2 = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + + /* Read the I2Cx status register */ + flag1 = I2Cx->SR1; + flag2 = I2Cx->SR2; + flag2 = flag2 << 16; + + /* Get the last event value from I2C status register */ + lastevent = (flag1 | flag2) & FLAG_Mask; + + /* Return status */ + return lastevent; +} + +/** + * + * 3) Flag-based state monitoring + ******************************************************************************* + */ + +/** + * @brief Checks whether the specified I2C flag is set or not. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg I2C_FLAG_DUALF: Dual flag (Slave mode) + * @arg I2C_FLAG_SMBHOST: SMBus host header (Slave mode) + * @arg I2C_FLAG_SMBDEFAULT: SMBus default header (Slave mode) + * @arg I2C_FLAG_GENCALL: General call header flag (Slave mode) + * @arg I2C_FLAG_TRA: Transmitter/Receiver flag + * @arg I2C_FLAG_BUSY: Bus busy flag + * @arg I2C_FLAG_MSL: Master/Slave flag + * @arg I2C_FLAG_SMBALERT: SMBus Alert flag + * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag + * @arg I2C_FLAG_PECERR: PEC error in reception flag + * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode) + * @arg I2C_FLAG_AF: Acknowledge failure flag + * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode) + * @arg I2C_FLAG_BERR: Bus error flag + * @arg I2C_FLAG_TXE: Data register empty flag (Transmitter) + * @arg I2C_FLAG_RXNE: Data register not empty (Receiver) flag + * @arg I2C_FLAG_STOPF: Stop detection flag (Slave mode) + * @arg I2C_FLAG_ADD10: 10-bit header sent flag (Master mode) + * @arg I2C_FLAG_BTF: Byte transfer finished flag + * @arg I2C_FLAG_ADDR: Address sent flag (Master mode) “ADSL” + * Address matched flag (Slave mode)”ENDAD” + * @arg I2C_FLAG_SB: Start bit flag (Master mode) + * @retval The new state of I2C_FLAG (SET or RESET). + */ +FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG) +{ + FlagStatus bitstatus = RESET; + __IO uint32_t i2creg = 0, i2cxbase = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_GET_FLAG(I2C_FLAG)); + + /* Get the I2Cx peripheral base address */ + i2cxbase = (uint32_t)I2Cx; + + /* Read flag register index */ + i2creg = I2C_FLAG >> 28; + + /* Get bit[23:0] of the flag */ + I2C_FLAG &= FLAG_Mask; + + if(i2creg != 0) + { + /* Get the I2Cx SR1 register address */ + i2cxbase += 0x14; + } + else + { + /* Flag in I2Cx SR2 Register */ + I2C_FLAG = (uint32_t)(I2C_FLAG >> 16); + /* Get the I2Cx SR2 register address */ + i2cxbase += 0x18; + } + + if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET) + { + /* I2C_FLAG is set */ + bitstatus = SET; + } + else + { + /* I2C_FLAG is reset */ + bitstatus = RESET; + } + + /* Return the I2C_FLAG status */ + return bitstatus; +} + + + +/** + * @brief Clears the I2Cx's pending flags. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg I2C_FLAG_SMBALERT: SMBus Alert flag + * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag + * @arg I2C_FLAG_PECERR: PEC error in reception flag + * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode) + * @arg I2C_FLAG_AF: Acknowledge failure flag + * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode) + * @arg I2C_FLAG_BERR: Bus error flag + * + * @note + * - STOPF (STOP detection) is cleared by software sequence: a read operation + * to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation + * to I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral). + * - ADD10 (10-bit header sent) is cleared by software sequence: a read + * operation to I2C_SR1 (I2C_GetFlagStatus()) followed by writing the + * second byte of the address in DR register. + * - BTF (Byte Transfer Finished) is cleared by software sequence: a read + * operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a + * read/write to I2C_DR register (I2C_SendData()). + * - ADDR (Address sent) is cleared by software sequence: a read operation to + * I2C_SR1 register (I2C_GetFlagStatus()) followed by a read operation to + * I2C_SR2 register ((void)(I2Cx->SR2)). + * - SB (Start Bit) is cleared software sequence: a read operation to I2C_SR1 + * register (I2C_GetFlagStatus()) followed by a write operation to I2C_DR + * register (I2C_SendData()). + * @retval None + */ +void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG) +{ + uint32_t flagpos = 0; + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG)); + /* Get the I2C flag position */ + flagpos = I2C_FLAG & FLAG_Mask; + /* Clear the selected I2C flag */ + I2Cx->SR1 = (uint16_t)~flagpos; +} + +/** + * @brief Checks whether the specified I2C interrupt has occurred or not. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_IT: specifies the interrupt source to check. + * This parameter can be one of the following values: + * @arg I2C_IT_SMBALERT: SMBus Alert flag + * @arg I2C_IT_TIMEOUT: Timeout or Tlow error flag + * @arg I2C_IT_PECERR: PEC error in reception flag + * @arg I2C_IT_OVR: Overrun/Underrun flag (Slave mode) + * @arg I2C_IT_AF: Acknowledge failure flag + * @arg I2C_IT_ARLO: Arbitration lost flag (Master mode) + * @arg I2C_IT_BERR: Bus error flag + * @arg I2C_IT_TXE: Data register empty flag (Transmitter) + * @arg I2C_IT_RXNE: Data register not empty (Receiver) flag + * @arg I2C_IT_STOPF: Stop detection flag (Slave mode) + * @arg I2C_IT_ADD10: 10-bit header sent flag (Master mode) + * @arg I2C_IT_BTF: Byte transfer finished flag + * @arg I2C_IT_ADDR: Address sent flag (Master mode) “ADSL” + * Address matched flag (Slave mode)”ENDAD” + * @arg I2C_IT_SB: Start bit flag (Master mode) + * @retval The new state of I2C_IT (SET or RESET). + */ +ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_GET_IT(I2C_IT)); + + /* Check if the interrupt source is enabled or not */ + enablestatus = (uint32_t)(((I2C_IT & ITEN_Mask) >> 16) & (I2Cx->CR2)) ; + + /* Get bit[23:0] of the flag */ + I2C_IT &= FLAG_Mask; + + /* Check the status of the specified I2C flag */ + if (((I2Cx->SR1 & I2C_IT) != (uint32_t)RESET) && enablestatus) + { + /* I2C_IT is set */ + bitstatus = SET; + } + else + { + /* I2C_IT is reset */ + bitstatus = RESET; + } + /* Return the I2C_IT status */ + return bitstatus; +} + +/** + * @brief Clears the I2Cx’s interrupt pending bits. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_IT: specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg I2C_IT_SMBALERT: SMBus Alert interrupt + * @arg I2C_IT_TIMEOUT: Timeout or Tlow error interrupt + * @arg I2C_IT_PECERR: PEC error in reception interrupt + * @arg I2C_IT_OVR: Overrun/Underrun interrupt (Slave mode) + * @arg I2C_IT_AF: Acknowledge failure interrupt + * @arg I2C_IT_ARLO: Arbitration lost interrupt (Master mode) + * @arg I2C_IT_BERR: Bus error interrupt + * + * @note + * - STOPF (STOP detection) is cleared by software sequence: a read operation + * to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to + * I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral). + * - ADD10 (10-bit header sent) is cleared by software sequence: a read + * operation to I2C_SR1 (I2C_GetITStatus()) followed by writing the second + * byte of the address in I2C_DR register. + * - BTF (Byte Transfer Finished) is cleared by software sequence: a read + * operation to I2C_SR1 register (I2C_GetITStatus()) followed by a + * read/write to I2C_DR register (I2C_SendData()). + * - ADDR (Address sent) is cleared by software sequence: a read operation to + * I2C_SR1 register (I2C_GetITStatus()) followed by a read operation to + * I2C_SR2 register ((void)(I2Cx->SR2)). + * - SB (Start Bit) is cleared by software sequence: a read operation to + * I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to + * I2C_DR register (I2C_SendData()). + * @retval None + */ +void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT) +{ + uint32_t flagpos = 0; + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_CLEAR_IT(I2C_IT)); + /* Get the I2C flag position */ + flagpos = I2C_IT & FLAG_Mask; + /* Clear the selected I2C flag */ + I2Cx->SR1 = (uint16_t)~flagpos; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32f10x/stm32f10x_iwdg.c b/example/libs_stm/src/stm32f10x/stm32f10x_iwdg.c new file mode 100644 index 0000000..58ab061 --- /dev/null +++ b/example/libs_stm/src/stm32f10x/stm32f10x_iwdg.c @@ -0,0 +1,189 @@ +/** + ****************************************************************************** + * @file stm32f10x_iwdg.c + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file provides all the IWDG firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_iwdg.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup IWDG + * @brief IWDG driver modules + * @{ + */ + +/** @defgroup IWDG_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup IWDG_Private_Defines + * @{ + */ + +/* ---------------------- IWDG registers bit mask ----------------------------*/ + +/* KR register bit mask */ +#define KR_KEY_Reload ((uint16_t)0xAAAA) +#define KR_KEY_Enable ((uint16_t)0xCCCC) + +/** + * @} + */ + +/** @defgroup IWDG_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup IWDG_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup IWDG_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup IWDG_Private_Functions + * @{ + */ + +/** + * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers. + * @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers. + * This parameter can be one of the following values: + * @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers + * @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers + * @retval None + */ +void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess) +{ + /* Check the parameters */ + assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess)); + IWDG->KR = IWDG_WriteAccess; +} + +/** + * @brief Sets IWDG Prescaler value. + * @param IWDG_Prescaler: specifies the IWDG Prescaler value. + * This parameter can be one of the following values: + * @arg IWDG_Prescaler_4: IWDG prescaler set to 4 + * @arg IWDG_Prescaler_8: IWDG prescaler set to 8 + * @arg IWDG_Prescaler_16: IWDG prescaler set to 16 + * @arg IWDG_Prescaler_32: IWDG prescaler set to 32 + * @arg IWDG_Prescaler_64: IWDG prescaler set to 64 + * @arg IWDG_Prescaler_128: IWDG prescaler set to 128 + * @arg IWDG_Prescaler_256: IWDG prescaler set to 256 + * @retval None + */ +void IWDG_SetPrescaler(uint8_t IWDG_Prescaler) +{ + /* Check the parameters */ + assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler)); + IWDG->PR = IWDG_Prescaler; +} + +/** + * @brief Sets IWDG Reload value. + * @param Reload: specifies the IWDG Reload value. + * This parameter must be a number between 0 and 0x0FFF. + * @retval None + */ +void IWDG_SetReload(uint16_t Reload) +{ + /* Check the parameters */ + assert_param(IS_IWDG_RELOAD(Reload)); + IWDG->RLR = Reload; +} + +/** + * @brief Reloads IWDG counter with value defined in the reload register + * (write access to IWDG_PR and IWDG_RLR registers disabled). + * @param None + * @retval None + */ +void IWDG_ReloadCounter(void) +{ + IWDG->KR = KR_KEY_Reload; +} + +/** + * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled). + * @param None + * @retval None + */ +void IWDG_Enable(void) +{ + IWDG->KR = KR_KEY_Enable; +} + +/** + * @brief Checks whether the specified IWDG flag is set or not. + * @param IWDG_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg IWDG_FLAG_PVU: Prescaler Value Update on going + * @arg IWDG_FLAG_RVU: Reload Value Update on going + * @retval The new state of IWDG_FLAG (SET or RESET). + */ +FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_IWDG_FLAG(IWDG_FLAG)); + if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the flag status */ + return bitstatus; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32f10x/stm32f10x_pwr.c b/example/libs_stm/src/stm32f10x/stm32f10x_pwr.c new file mode 100644 index 0000000..a017ac6 --- /dev/null +++ b/example/libs_stm/src/stm32f10x/stm32f10x_pwr.c @@ -0,0 +1,316 @@ +/** + ****************************************************************************** + * @file stm32f10x_pwr.c + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file provides all the PWR firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_pwr.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup PWR + * @brief PWR driver modules + * @{ + */ + +/** @defgroup PWR_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup PWR_Private_Defines + * @{ + */ + +/* --------- PWR registers bit address in the alias region ---------- */ +#define PWR_OFFSET (PWR_BASE - PERIPH_BASE) + +/* --- CR Register ---*/ + +/* Alias word address of DBP bit */ +#define CR_OFFSET (PWR_OFFSET + 0x00) +#define DBP_BitNumber 0x08 +#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4)) + +/* Alias word address of PVDE bit */ +#define PVDE_BitNumber 0x04 +#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4)) + +/* --- CSR Register ---*/ + +/* Alias word address of EWUP bit */ +#define CSR_OFFSET (PWR_OFFSET + 0x04) +#define EWUP_BitNumber 0x08 +#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4)) + +/* ------------------ PWR registers bit mask ------------------------ */ + +/* CR register bit mask */ +#define CR_PDDS_Set ((uint32_t)0x00000002) +#define CR_DS_Mask ((uint32_t)0xFFFFFFFC) +#define CR_CWUF_Set ((uint32_t)0x00000004) +#define CR_PLS_Mask ((uint32_t)0xFFFFFF1F) + +/* --------- Cortex System Control register bit mask ---------------- */ + +/* Cortex System Control register address */ +#define SCB_SysCtrl ((uint32_t)0xE000ED10) + +/* SLEEPDEEP bit mask */ +#define SysCtrl_SLEEPDEEP_Set ((uint32_t)0x00000004) +#define SysCtrl_SLEEPDEEP_Reset ((uint32_t)0xFFFFFFFB) + +/** + * @} + */ + +/** @defgroup PWR_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup PWR_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup PWR_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup PWR_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the PWR peripheral registers to their default reset values. + * @param None + * @retval None + */ +void PWR_DeInit(void) +{ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE); +} + +/** + * @brief Enables or disables access to the RTC and backup registers. + * @param NewState: new state of the access to the RTC and backup registers. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void PWR_BackupAccessCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState; +} + +/** + * @brief Enables or disables the Power Voltage Detector(PVD). + * @param NewState: new state of the PVD. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void PWR_PVDCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState; +} + +/** + * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). + * @param PWR_PVDLevel: specifies the PVD detection level + * This parameter can be one of the following values: + * @arg PWR_PVDLevel_2V2: PVD detection level set to 2.2V + * @arg PWR_PVDLevel_2V3: PVD detection level set to 2.3V + * @arg PWR_PVDLevel_2V4: PVD detection level set to 2.4V + * @arg PWR_PVDLevel_2V5: PVD detection level set to 2.5V + * @arg PWR_PVDLevel_2V6: PVD detection level set to 2.6V + * @arg PWR_PVDLevel_2V7: PVD detection level set to 2.7V + * @arg PWR_PVDLevel_2V8: PVD detection level set to 2.8V + * @arg PWR_PVDLevel_2V9: PVD detection level set to 2.9V + * @retval None + */ +void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel)); + tmpreg = PWR->CR; + /* Clear PLS[7:5] bits */ + tmpreg &= CR_PLS_Mask; + /* Set PLS[7:5] bits according to PWR_PVDLevel value */ + tmpreg |= PWR_PVDLevel; + /* Store the new value */ + PWR->CR = tmpreg; +} + +/** + * @brief Enables or disables the WakeUp Pin functionality. + * @param NewState: new state of the WakeUp Pin functionality. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void PWR_WakeUpPinCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState; +} + +/** + * @brief Enters STOP mode. + * @param PWR_Regulator: specifies the regulator state in STOP mode. + * This parameter can be one of the following values: + * @arg PWR_Regulator_ON: STOP mode with regulator ON + * @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode + * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction. + * This parameter can be one of the following values: + * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction + * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction + * @retval None + */ +void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_PWR_REGULATOR(PWR_Regulator)); + assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry)); + + /* Select the regulator state in STOP mode ---------------------------------*/ + tmpreg = PWR->CR; + /* Clear PDDS and LPDS bits */ + tmpreg &= CR_DS_Mask; + /* Set LPDS bit according to PWR_Regulator value */ + tmpreg |= PWR_Regulator; + /* Store the new value */ + PWR->CR = tmpreg; + /* Set SLEEPDEEP bit of Cortex System Control Register */ + *(__IO uint32_t *) SCB_SysCtrl |= SysCtrl_SLEEPDEEP_Set; + + /* Select STOP mode entry --------------------------------------------------*/ + if(PWR_STOPEntry == PWR_STOPEntry_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __WFE(); + } + + /* Reset SLEEPDEEP bit of Cortex System Control Register */ + *(__IO uint32_t *) SCB_SysCtrl &= SysCtrl_SLEEPDEEP_Reset; +} + +/** + * @brief Enters STANDBY mode. + * @param None + * @retval None + */ +void PWR_EnterSTANDBYMode(void) +{ + /* Clear Wake-up flag */ + PWR->CR |= CR_CWUF_Set; + /* Select STANDBY mode */ + PWR->CR |= CR_PDDS_Set; + /* Set SLEEPDEEP bit of Cortex System Control Register */ + *(__IO uint32_t *) SCB_SysCtrl |= SysCtrl_SLEEPDEEP_Set; +/* This option is used to ensure that store operations are completed */ +#if defined ( __CC_ARM ) + __force_stores(); +#endif + /* Request Wait For Interrupt */ + __WFI(); +} + +/** + * @brief Checks whether the specified PWR flag is set or not. + * @param PWR_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg PWR_FLAG_WU: Wake Up flag + * @arg PWR_FLAG_SB: StandBy flag + * @arg PWR_FLAG_PVDO: PVD Output + * @retval The new state of PWR_FLAG (SET or RESET). + */ +FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_PWR_GET_FLAG(PWR_FLAG)); + + if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the flag status */ + return bitstatus; +} + +/** + * @brief Clears the PWR's pending flags. + * @param PWR_FLAG: specifies the flag to clear. + * This parameter can be one of the following values: + * @arg PWR_FLAG_WU: Wake Up flag + * @arg PWR_FLAG_SB: StandBy flag + * @retval None + */ +void PWR_ClearFlag(uint32_t PWR_FLAG) +{ + /* Check the parameters */ + assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG)); + + PWR->CR |= PWR_FLAG << 2; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32f10x/stm32f10x_rcc.c b/example/libs_stm/src/stm32f10x/stm32f10x_rcc.c new file mode 100644 index 0000000..0fb0d58 --- /dev/null +++ b/example/libs_stm/src/stm32f10x/stm32f10x_rcc.c @@ -0,0 +1,1477 @@ +/** + ****************************************************************************** + * @file stm32f10x_rcc.c + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file provides all the RCC firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup RCC + * @brief RCC driver modules + * @{ + */ + +/** @defgroup RCC_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup RCC_Private_Defines + * @{ + */ + +/* ------------ RCC registers bit address in the alias region ----------- */ +#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) + +/* --- CR Register ---*/ + +/* Alias word address of HSION bit */ +#define CR_OFFSET (RCC_OFFSET + 0x00) +#define HSION_BitNumber 0x00 +#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4)) + +/* Alias word address of PLLON bit */ +#define PLLON_BitNumber 0x18 +#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4)) + +#ifdef STM32F10X_CL + /* Alias word address of PLL2ON bit */ + #define PLL2ON_BitNumber 0x1A + #define CR_PLL2ON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL2ON_BitNumber * 4)) + + /* Alias word address of PLL3ON bit */ + #define PLL3ON_BitNumber 0x1C + #define CR_PLL3ON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL3ON_BitNumber * 4)) +#endif /* STM32F10X_CL */ + +/* Alias word address of CSSON bit */ +#define CSSON_BitNumber 0x13 +#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4)) + +/* --- CFGR Register ---*/ + +/* Alias word address of USBPRE bit */ +#define CFGR_OFFSET (RCC_OFFSET + 0x04) + +#ifndef STM32F10X_CL + #define USBPRE_BitNumber 0x16 + #define CFGR_USBPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4)) +#else + #define OTGFSPRE_BitNumber 0x16 + #define CFGR_OTGFSPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (OTGFSPRE_BitNumber * 4)) +#endif /* STM32F10X_CL */ + +/* --- BDCR Register ---*/ + +/* Alias word address of RTCEN bit */ +#define BDCR_OFFSET (RCC_OFFSET + 0x20) +#define RTCEN_BitNumber 0x0F +#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4)) + +/* Alias word address of BDRST bit */ +#define BDRST_BitNumber 0x10 +#define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4)) + +/* --- CSR Register ---*/ + +/* Alias word address of LSION bit */ +#define CSR_OFFSET (RCC_OFFSET + 0x24) +#define LSION_BitNumber 0x00 +#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4)) + +#ifdef STM32F10X_CL +/* --- CFGR2 Register ---*/ + + /* Alias word address of I2S2SRC bit */ + #define CFGR2_OFFSET (RCC_OFFSET + 0x2C) + #define I2S2SRC_BitNumber 0x11 + #define CFGR2_I2S2SRC_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S2SRC_BitNumber * 4)) + + /* Alias word address of I2S3SRC bit */ + #define I2S3SRC_BitNumber 0x12 + #define CFGR2_I2S3SRC_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S3SRC_BitNumber * 4)) +#endif /* STM32F10X_CL */ + +/* ---------------------- RCC registers bit mask ------------------------ */ + +/* CR register bit mask */ +#define CR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF) +#define CR_HSEBYP_Set ((uint32_t)0x00040000) +#define CR_HSEON_Reset ((uint32_t)0xFFFEFFFF) +#define CR_HSEON_Set ((uint32_t)0x00010000) +#define CR_HSITRIM_Mask ((uint32_t)0xFFFFFF07) + +/* CFGR register bit mask */ +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_CL) + #define CFGR_PLL_Mask ((uint32_t)0xFFC2FFFF) +#else + #define CFGR_PLL_Mask ((uint32_t)0xFFC0FFFF) +#endif /* STM32F10X_CL */ + +#define CFGR_PLLMull_Mask ((uint32_t)0x003C0000) +#define CFGR_PLLSRC_Mask ((uint32_t)0x00010000) +#define CFGR_PLLXTPRE_Mask ((uint32_t)0x00020000) +#define CFGR_SWS_Mask ((uint32_t)0x0000000C) +#define CFGR_SW_Mask ((uint32_t)0xFFFFFFFC) +#define CFGR_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F) +#define CFGR_HPRE_Set_Mask ((uint32_t)0x000000F0) +#define CFGR_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF) +#define CFGR_PPRE1_Set_Mask ((uint32_t)0x00000700) +#define CFGR_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF) +#define CFGR_PPRE2_Set_Mask ((uint32_t)0x00003800) +#define CFGR_ADCPRE_Reset_Mask ((uint32_t)0xFFFF3FFF) +#define CFGR_ADCPRE_Set_Mask ((uint32_t)0x0000C000) + +/* CSR register bit mask */ +#define CSR_RMVF_Set ((uint32_t)0x01000000) + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_CL) +/* CFGR2 register bit mask */ + #define CFGR2_PREDIV1SRC ((uint32_t)0x00010000) + #define CFGR2_PREDIV1 ((uint32_t)0x0000000F) +#endif +#ifdef STM32F10X_CL + #define CFGR2_PREDIV2 ((uint32_t)0x000000F0) + #define CFGR2_PLL2MUL ((uint32_t)0x00000F00) + #define CFGR2_PLL3MUL ((uint32_t)0x0000F000) +#endif /* STM32F10X_CL */ + +/* RCC Flag Mask */ +#define FLAG_Mask ((uint8_t)0x1F) + +#ifndef HSI_Value +/* Typical Value of the HSI in Hz */ + #define HSI_Value ((uint32_t)8000000) +#endif /* HSI_Value */ + +/* CIR register byte 2 (Bits[15:8]) base address */ +#define CIR_BYTE2_ADDRESS ((uint32_t)0x40021009) + +/* CIR register byte 3 (Bits[23:16]) base address */ +#define CIR_BYTE3_ADDRESS ((uint32_t)0x4002100A) + +/* CFGR register byte 4 (Bits[31:24]) base address */ +#define CFGR_BYTE4_ADDRESS ((uint32_t)0x40021007) + +/* BDCR register base address */ +#define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET) + +#ifndef HSEStartUp_TimeOut +/* Time out for HSE start up */ + #define HSEStartUp_TimeOut ((uint16_t)0x0500) +#endif /* HSEStartUp_TimeOut */ + +/** + * @} + */ + +/** @defgroup RCC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup RCC_Private_Variables + * @{ + */ + +static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; +static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8}; + +/** + * @} + */ + +/** @defgroup RCC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup RCC_Private_Functions + * @{ + */ + +/** + * @brief Resets the RCC clock configuration to the default reset state. + * @param None + * @retval None + */ +void RCC_DeInit(void) +{ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ +#ifndef STM32F10X_CL + RCC->CFGR &= (uint32_t)0xF8FF0000; +#else + RCC->CFGR &= (uint32_t)0xF0FF0000; +#endif /* STM32F10X_CL */ + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ + RCC->CFGR &= (uint32_t)0xFF80FFFF; + +#ifdef STM32F10X_CL + /* Reset PLL2ON and PLL3ON bits */ + RCC->CR &= (uint32_t)0xEBFFFFFF; + + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x00FF0000; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000; +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000; +#else + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; +#endif /* STM32F10X_CL */ + +} + +/** + * @brief Configures the External High Speed oscillator (HSE). + * @note HSE can not be stopped if it is used directly or through the PLL as system clock. + * @param RCC_HSE: specifies the new state of the HSE. + * This parameter can be one of the following values: + * @arg RCC_HSE_OFF: HSE oscillator OFF + * @arg RCC_HSE_ON: HSE oscillator ON + * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock + * @retval None + */ +void RCC_HSEConfig(uint32_t RCC_HSE) +{ + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_HSE)); + /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/ + /* Reset HSEON bit */ + RCC->CR &= CR_HSEON_Reset; + /* Reset HSEBYP bit */ + RCC->CR &= CR_HSEBYP_Reset; + /* Configure HSE (RCC_HSE_OFF is already covered by the code section above) */ + switch(RCC_HSE) + { + case RCC_HSE_ON: + /* Set HSEON bit */ + RCC->CR |= CR_HSEON_Set; + break; + + case RCC_HSE_Bypass: + /* Set HSEBYP and HSEON bits */ + RCC->CR |= CR_HSEBYP_Set | CR_HSEON_Set; + break; + + default: + break; + } +} + +/** + * @brief Waits for HSE start-up. + * @param None + * @retval An ErrorStatus enumuration value: + * - SUCCESS: HSE oscillator is stable and ready to use + * - ERROR: HSE oscillator not yet ready + */ +ErrorStatus RCC_WaitForHSEStartUp(void) +{ + __IO uint32_t StartUpCounter = 0; + ErrorStatus status = ERROR; + FlagStatus HSEStatus = RESET; + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY); + StartUpCounter++; + } while((StartUpCounter != HSEStartUp_TimeOut) && (HSEStatus == RESET)); + + if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET) + { + status = SUCCESS; + } + else + { + status = ERROR; + } + return (status); +} + +/** + * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value. + * @param HSICalibrationValue: specifies the calibration trimming value. + * This parameter must be a number between 0 and 0x1F. + * @retval None + */ +void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue)); + tmpreg = RCC->CR; + /* Clear HSITRIM[4:0] bits */ + tmpreg &= CR_HSITRIM_Mask; + /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */ + tmpreg |= (uint32_t)HSICalibrationValue << 3; + /* Store the new value */ + RCC->CR = tmpreg; +} + +/** + * @brief Enables or disables the Internal High Speed oscillator (HSI). + * @note HSI can not be stopped if it is used directly or through the PLL as system clock. + * @param NewState: new state of the HSI. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_HSICmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState; +} + +/** + * @brief Configures the PLL clock source and multiplication factor. + * @note This function must be used only when the PLL is disabled. + * @param RCC_PLLSource: specifies the PLL entry clock source. + * For @b STM32_Connectivity_line_devices or @b STM32_Value_line_devices, + * this parameter can be one of the following values: + * @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry + * @arg RCC_PLLSource_PREDIV1: PREDIV1 clock selected as PLL clock entry + * For @b other_STM32_devices, this parameter can be one of the following values: + * @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry + * @arg RCC_PLLSource_HSE_Div1: HSE oscillator clock selected as PLL clock entry + * @arg RCC_PLLSource_HSE_Div2: HSE oscillator clock divided by 2 selected as PLL clock entry + * @param RCC_PLLMul: specifies the PLL multiplication factor. + * For @b STM32_Connectivity_line_devices, this parameter can be RCC_PLLMul_x where x:{[4,9], 6_5} + * For @b other_STM32_devices, this parameter can be RCC_PLLMul_x where x:[2,16] + * @retval None + */ +void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource)); + assert_param(IS_RCC_PLL_MUL(RCC_PLLMul)); + + tmpreg = RCC->CFGR; + /* Clear PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */ + tmpreg &= CFGR_PLL_Mask; + /* Set the PLL configuration bits */ + tmpreg |= RCC_PLLSource | RCC_PLLMul; + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** + * @brief Enables or disables the PLL. + * @note The PLL can not be disabled if it is used as system clock. + * @param NewState: new state of the PLL. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_PLLCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState; +} + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_CL) +/** + * @brief Configures the PREDIV1 division factor. + * @note + * - This function must be used only when the PLL is disabled. + * - This function applies only to STM32 Connectivity line and Value line + * devices. + * @param RCC_PREDIV1_Source: specifies the PREDIV1 clock source. + * This parameter can be one of the following values: + * @arg RCC_PREDIV1_Source_HSE: HSE selected as PREDIV1 clock + * @arg RCC_PREDIV1_Source_PLL2: PLL2 selected as PREDIV1 clock + * @note + * For @b STM32_Value_line_devices this parameter is always RCC_PREDIV1_Source_HSE + * @param RCC_PREDIV1_Div: specifies the PREDIV1 clock division factor. + * This parameter can be RCC_PREDIV1_Divx where x:[1,16] + * @retval None + */ +void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PREDIV1_SOURCE(RCC_PREDIV1_Source)); + assert_param(IS_RCC_PREDIV1(RCC_PREDIV1_Div)); + + tmpreg = RCC->CFGR2; + /* Clear PREDIV1[3:0] and PREDIV1SRC bits */ + tmpreg &= ~(CFGR2_PREDIV1 | CFGR2_PREDIV1SRC); + /* Set the PREDIV1 clock source and division factor */ + tmpreg |= RCC_PREDIV1_Source | RCC_PREDIV1_Div ; + /* Store the new value */ + RCC->CFGR2 = tmpreg; +} +#endif + +#ifdef STM32F10X_CL +/** + * @brief Configures the PREDIV2 division factor. + * @note + * - This function must be used only when both PLL2 and PLL3 are disabled. + * - This function applies only to STM32 Connectivity line devices. + * @param RCC_PREDIV2_Div: specifies the PREDIV2 clock division factor. + * This parameter can be RCC_PREDIV2_Divx where x:[1,16] + * @retval None + */ +void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PREDIV2(RCC_PREDIV2_Div)); + + tmpreg = RCC->CFGR2; + /* Clear PREDIV2[3:0] bits */ + tmpreg &= ~CFGR2_PREDIV2; + /* Set the PREDIV2 division factor */ + tmpreg |= RCC_PREDIV2_Div; + /* Store the new value */ + RCC->CFGR2 = tmpreg; +} + +/** + * @brief Configures the PLL2 multiplication factor. + * @note + * - This function must be used only when the PLL2 is disabled. + * - This function applies only to STM32 Connectivity line devices. + * @param RCC_PLL2Mul: specifies the PLL2 multiplication factor. + * This parameter can be RCC_PLL2Mul_x where x:{[8,14], 16, 20} + * @retval None + */ +void RCC_PLL2Config(uint32_t RCC_PLL2Mul) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PLL2_MUL(RCC_PLL2Mul)); + + tmpreg = RCC->CFGR2; + /* Clear PLL2Mul[3:0] bits */ + tmpreg &= ~CFGR2_PLL2MUL; + /* Set the PLL2 configuration bits */ + tmpreg |= RCC_PLL2Mul; + /* Store the new value */ + RCC->CFGR2 = tmpreg; +} + + +/** + * @brief Enables or disables the PLL2. + * @note + * - The PLL2 can not be disabled if it is used indirectly as system clock + * (i.e. it is used as PLL clock entry that is used as System clock). + * - This function applies only to STM32 Connectivity line devices. + * @param NewState: new state of the PLL2. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_PLL2Cmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CR_PLL2ON_BB = (uint32_t)NewState; +} + + +/** + * @brief Configures the PLL3 multiplication factor. + * @note + * - This function must be used only when the PLL3 is disabled. + * - This function applies only to STM32 Connectivity line devices. + * @param RCC_PLL3Mul: specifies the PLL3 multiplication factor. + * This parameter can be RCC_PLL3Mul_x where x:{[8,14], 16, 20} + * @retval None + */ +void RCC_PLL3Config(uint32_t RCC_PLL3Mul) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PLL3_MUL(RCC_PLL3Mul)); + + tmpreg = RCC->CFGR2; + /* Clear PLL3Mul[3:0] bits */ + tmpreg &= ~CFGR2_PLL3MUL; + /* Set the PLL3 configuration bits */ + tmpreg |= RCC_PLL3Mul; + /* Store the new value */ + RCC->CFGR2 = tmpreg; +} + + +/** + * @brief Enables or disables the PLL3. + * @note This function applies only to STM32 Connectivity line devices. + * @param NewState: new state of the PLL3. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_PLL3Cmd(FunctionalState NewState) +{ + /* Check the parameters */ + + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CR_PLL3ON_BB = (uint32_t)NewState; +} +#endif /* STM32F10X_CL */ + +/** + * @brief Configures the system clock (SYSCLK). + * @param RCC_SYSCLKSource: specifies the clock source used as system clock. + * This parameter can be one of the following values: + * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock + * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock + * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock + * @retval None + */ +void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource)); + tmpreg = RCC->CFGR; + /* Clear SW[1:0] bits */ + tmpreg &= CFGR_SW_Mask; + /* Set SW[1:0] bits according to RCC_SYSCLKSource value */ + tmpreg |= RCC_SYSCLKSource; + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** + * @brief Returns the clock source used as system clock. + * @param None + * @retval The clock source used as system clock. The returned value can + * be one of the following: + * - 0x00: HSI used as system clock + * - 0x04: HSE used as system clock + * - 0x08: PLL used as system clock + */ +uint8_t RCC_GetSYSCLKSource(void) +{ + return ((uint8_t)(RCC->CFGR & CFGR_SWS_Mask)); +} + +/** + * @brief Configures the AHB clock (HCLK). + * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from + * the system clock (SYSCLK). + * This parameter can be one of the following values: + * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK + * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2 + * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4 + * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8 + * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16 + * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64 + * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128 + * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256 + * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512 + * @retval None + */ +void RCC_HCLKConfig(uint32_t RCC_SYSCLK) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_RCC_HCLK(RCC_SYSCLK)); + tmpreg = RCC->CFGR; + /* Clear HPRE[3:0] bits */ + tmpreg &= CFGR_HPRE_Reset_Mask; + /* Set HPRE[3:0] bits according to RCC_SYSCLK value */ + tmpreg |= RCC_SYSCLK; + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** + * @brief Configures the Low Speed APB clock (PCLK1). + * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from + * the AHB clock (HCLK). + * This parameter can be one of the following values: + * @arg RCC_HCLK_Div1: APB1 clock = HCLK + * @arg RCC_HCLK_Div2: APB1 clock = HCLK/2 + * @arg RCC_HCLK_Div4: APB1 clock = HCLK/4 + * @arg RCC_HCLK_Div8: APB1 clock = HCLK/8 + * @arg RCC_HCLK_Div16: APB1 clock = HCLK/16 + * @retval None + */ +void RCC_PCLK1Config(uint32_t RCC_HCLK) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_RCC_PCLK(RCC_HCLK)); + tmpreg = RCC->CFGR; + /* Clear PPRE1[2:0] bits */ + tmpreg &= CFGR_PPRE1_Reset_Mask; + /* Set PPRE1[2:0] bits according to RCC_HCLK value */ + tmpreg |= RCC_HCLK; + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** + * @brief Configures the High Speed APB clock (PCLK2). + * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from + * the AHB clock (HCLK). + * This parameter can be one of the following values: + * @arg RCC_HCLK_Div1: APB2 clock = HCLK + * @arg RCC_HCLK_Div2: APB2 clock = HCLK/2 + * @arg RCC_HCLK_Div4: APB2 clock = HCLK/4 + * @arg RCC_HCLK_Div8: APB2 clock = HCLK/8 + * @arg RCC_HCLK_Div16: APB2 clock = HCLK/16 + * @retval None + */ +void RCC_PCLK2Config(uint32_t RCC_HCLK) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_RCC_PCLK(RCC_HCLK)); + tmpreg = RCC->CFGR; + /* Clear PPRE2[2:0] bits */ + tmpreg &= CFGR_PPRE2_Reset_Mask; + /* Set PPRE2[2:0] bits according to RCC_HCLK value */ + tmpreg |= RCC_HCLK << 3; + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** + * @brief Enables or disables the specified RCC interrupts. + * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled. + * + * For @b STM32_Connectivity_line_devices, this parameter can be any combination + * of the following values + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_PLLRDY: PLL ready interrupt + * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt + * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt + * + * For @b other_STM32_devices, this parameter can be any combination of the + * following values + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_PLLRDY: PLL ready interrupt + * + * @param NewState: new state of the specified RCC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_IT(RCC_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Perform Byte access to RCC_CIR bits to enable the selected interrupts */ + *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT; + } + else + { + /* Perform Byte access to RCC_CIR bits to disable the selected interrupts */ + *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT; + } +} + +#ifndef STM32F10X_CL +/** + * @brief Configures the USB clock (USBCLK). + * @param RCC_USBCLKSource: specifies the USB clock source. This clock is + * derived from the PLL output. + * This parameter can be one of the following values: + * @arg RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5 selected as USB + * clock source + * @arg RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB clock source + * @retval None + */ +void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource)); + + *(__IO uint32_t *) CFGR_USBPRE_BB = RCC_USBCLKSource; +} +#else +/** + * @brief Configures the USB OTG FS clock (OTGFSCLK). + * This function applies only to STM32 Connectivity line devices. + * @param RCC_OTGFSCLKSource: specifies the USB OTG FS clock source. + * This clock is derived from the PLL output. + * This parameter can be one of the following values: + * @arg RCC_OTGFSCLKSource_PLLVCO_Div3: PLL VCO clock divided by 2 selected as USB OTG FS clock source + * @arg RCC_OTGFSCLKSource_PLLVCO_Div2: PLL VCO clock divided by 2 selected as USB OTG FS clock source + * @retval None + */ +void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_OTGFSCLK_SOURCE(RCC_OTGFSCLKSource)); + + *(__IO uint32_t *) CFGR_OTGFSPRE_BB = RCC_OTGFSCLKSource; +} +#endif /* STM32F10X_CL */ + +/** + * @brief Configures the ADC clock (ADCCLK). + * @param RCC_PCLK2: defines the ADC clock divider. This clock is derived from + * the APB2 clock (PCLK2). + * This parameter can be one of the following values: + * @arg RCC_PCLK2_Div2: ADC clock = PCLK2/2 + * @arg RCC_PCLK2_Div4: ADC clock = PCLK2/4 + * @arg RCC_PCLK2_Div6: ADC clock = PCLK2/6 + * @arg RCC_PCLK2_Div8: ADC clock = PCLK2/8 + * @retval None + */ +void RCC_ADCCLKConfig(uint32_t RCC_PCLK2) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_RCC_ADCCLK(RCC_PCLK2)); + tmpreg = RCC->CFGR; + /* Clear ADCPRE[1:0] bits */ + tmpreg &= CFGR_ADCPRE_Reset_Mask; + /* Set ADCPRE[1:0] bits according to RCC_PCLK2 value */ + tmpreg |= RCC_PCLK2; + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +#ifdef STM32F10X_CL +/** + * @brief Configures the I2S2 clock source(I2S2CLK). + * @note + * - This function must be called before enabling I2S2 APB clock. + * - This function applies only to STM32 Connectivity line devices. + * @param RCC_I2S2CLKSource: specifies the I2S2 clock source. + * This parameter can be one of the following values: + * @arg RCC_I2S2CLKSource_SYSCLK: system clock selected as I2S2 clock entry + * @arg RCC_I2S2CLKSource_PLL3_VCO: PLL3 VCO clock selected as I2S2 clock entry + * @retval None + */ +void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_I2S2CLK_SOURCE(RCC_I2S2CLKSource)); + + *(__IO uint32_t *) CFGR2_I2S2SRC_BB = RCC_I2S2CLKSource; +} + +/** + * @brief Configures the I2S3 clock source(I2S2CLK). + * @note + * - This function must be called before enabling I2S3 APB clock. + * - This function applies only to STM32 Connectivity line devices. + * @param RCC_I2S3CLKSource: specifies the I2S3 clock source. + * This parameter can be one of the following values: + * @arg RCC_I2S3CLKSource_SYSCLK: system clock selected as I2S3 clock entry + * @arg RCC_I2S3CLKSource_PLL3_VCO: PLL3 VCO clock selected as I2S3 clock entry + * @retval None + */ +void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_I2S3CLK_SOURCE(RCC_I2S3CLKSource)); + + *(__IO uint32_t *) CFGR2_I2S3SRC_BB = RCC_I2S3CLKSource; +} +#endif /* STM32F10X_CL */ + +/** + * @brief Configures the External Low Speed oscillator (LSE). + * @param RCC_LSE: specifies the new state of the LSE. + * This parameter can be one of the following values: + * @arg RCC_LSE_OFF: LSE oscillator OFF + * @arg RCC_LSE_ON: LSE oscillator ON + * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock + * @retval None + */ +void RCC_LSEConfig(uint8_t RCC_LSE) +{ + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_LSE)); + /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/ + /* Reset LSEON bit */ + *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF; + /* Reset LSEBYP bit */ + *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF; + /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */ + switch(RCC_LSE) + { + case RCC_LSE_ON: + /* Set LSEON bit */ + *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON; + break; + + case RCC_LSE_Bypass: + /* Set LSEBYP and LSEON bits */ + *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON; + break; + + default: + break; + } +} + +/** + * @brief Enables or disables the Internal Low Speed oscillator (LSI). + * @note LSI can not be disabled if the IWDG is running. + * @param NewState: new state of the LSI. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_LSICmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState; +} + +/** + * @brief Configures the RTC clock (RTCCLK). + * @note Once the RTC clock is selected it can’t be changed unless the Backup domain is reset. + * @param RCC_RTCCLKSource: specifies the RTC clock source. + * This parameter can be one of the following values: + * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock + * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock + * @arg RCC_RTCCLKSource_HSE_Div128: HSE clock divided by 128 selected as RTC clock + * @retval None + */ +void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource)); + /* Select the RTC clock source */ + RCC->BDCR |= RCC_RTCCLKSource; +} + +/** + * @brief Enables or disables the RTC clock. + * @note This function must be used only after the RTC clock was selected using the RCC_RTCCLKConfig function. + * @param NewState: new state of the RTC clock. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_RTCCLKCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState; +} + +/** + * @brief Returns the frequencies of different on chip clocks. + * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold + * the clocks frequencies. + * @retval None + */ +void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0; + +#ifdef STM32F10X_CL + uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0; +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) + uint32_t prediv1factor = 0; +#endif + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & CFGR_SWS_Mask; + + switch (tmp) + { + case 0x00: /* HSI used as system clock */ + RCC_Clocks->SYSCLK_Frequency = HSI_Value; + break; + case 0x04: /* HSE used as system clock */ + RCC_Clocks->SYSCLK_Frequency = HSE_Value; + break; + case 0x08: /* PLL used as system clock */ + + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmull = RCC->CFGR & CFGR_PLLMull_Mask; + pllsource = RCC->CFGR & CFGR_PLLSRC_Mask; + +#ifndef STM32F10X_CL + pllmull = ( pllmull >> 18) + 2; + + if (pllsource == 0x00) + {/* HSI oscillator clock divided by 2 selected as PLL clock entry */ + RCC_Clocks->SYSCLK_Frequency = (HSI_Value >> 1) * pllmull; + } + else + { + #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) + prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1; + /* HSE oscillator clock selected as PREDIV1 clock entry */ + RCC_Clocks->SYSCLK_Frequency = (HSE_Value / prediv1factor) * pllmull; + #else + /* HSE selected as PLL clock entry */ + if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (uint32_t)RESET) + {/* HSE oscillator clock divided by 2 */ + RCC_Clocks->SYSCLK_Frequency = (HSE_Value >> 1) * pllmull; + } + else + { + RCC_Clocks->SYSCLK_Frequency = HSE_Value * pllmull; + } + #endif + } +#else + pllmull = pllmull >> 18; + + if (pllmull != 0x0D) + { + pllmull += 2; + } + else + { /* PLL multiplication factor = PLL input clock * 6.5 */ + pllmull = 13 / 2; + } + + if (pllsource == 0x00) + {/* HSI oscillator clock divided by 2 selected as PLL clock entry */ + RCC_Clocks->SYSCLK_Frequency = (HSI_Value >> 1) * pllmull; + } + else + {/* PREDIV1 selected as PLL clock entry */ + + /* Get PREDIV1 clock source and division factor */ + prediv1source = RCC->CFGR2 & CFGR2_PREDIV1SRC; + prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1; + + if (prediv1source == 0) + { /* HSE oscillator clock selected as PREDIV1 clock entry */ + RCC_Clocks->SYSCLK_Frequency = (HSE_Value / prediv1factor) * pllmull; + } + else + {/* PLL2 clock selected as PREDIV1 clock entry */ + + /* Get PREDIV2 division factor and PLL2 multiplication factor */ + prediv2factor = ((RCC->CFGR2 & CFGR2_PREDIV2) >> 4) + 1; + pll2mull = ((RCC->CFGR2 & CFGR2_PLL2MUL) >> 8 ) + 2; + RCC_Clocks->SYSCLK_Frequency = (((HSE_Value / prediv2factor) * pll2mull) / prediv1factor) * pllmull; + } + } +#endif /* STM32F10X_CL */ + break; + + default: + RCC_Clocks->SYSCLK_Frequency = HSI_Value; + break; + } + + /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/ + /* Get HCLK prescaler */ + tmp = RCC->CFGR & CFGR_HPRE_Set_Mask; + tmp = tmp >> 4; + presc = APBAHBPrescTable[tmp]; + /* HCLK clock frequency */ + RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc; + /* Get PCLK1 prescaler */ + tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask; + tmp = tmp >> 8; + presc = APBAHBPrescTable[tmp]; + /* PCLK1 clock frequency */ + RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc; + /* Get PCLK2 prescaler */ + tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask; + tmp = tmp >> 11; + presc = APBAHBPrescTable[tmp]; + /* PCLK2 clock frequency */ + RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc; + /* Get ADCCLK prescaler */ + tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask; + tmp = tmp >> 14; + presc = ADCPrescTable[tmp]; + /* ADCCLK clock frequency */ + RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc; +} + +/** + * @brief Enables or disables the AHB peripheral clock. + * @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock. + * + * For @b STM32_Connectivity_line_devices, this parameter can be any combination + * of the following values: + * @arg RCC_AHBPeriph_DMA1 + * @arg RCC_AHBPeriph_DMA2 + * @arg RCC_AHBPeriph_SRAM + * @arg RCC_AHBPeriph_FLITF + * @arg RCC_AHBPeriph_CRC + * @arg RCC_AHBPeriph_OTG_FS + * @arg RCC_AHBPeriph_ETH_MAC + * @arg RCC_AHBPeriph_ETH_MAC_Tx + * @arg RCC_AHBPeriph_ETH_MAC_Rx + * + * For @b other_STM32_devices, this parameter can be any combination of the + * following values: + * @arg RCC_AHBPeriph_DMA1 + * @arg RCC_AHBPeriph_DMA2 + * @arg RCC_AHBPeriph_SRAM + * @arg RCC_AHBPeriph_FLITF + * @arg RCC_AHBPeriph_CRC + * @arg RCC_AHBPeriph_FSMC + * @arg RCC_AHBPeriph_SDIO + * + * @note SRAM and FLITF clock can be disabled only during sleep mode. + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->AHBENR |= RCC_AHBPeriph; + } + else + { + RCC->AHBENR &= ~RCC_AHBPeriph; + } +} + +/** + * @brief Enables or disables the High Speed APB (APB2) peripheral clock. + * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB, + * RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE, + * RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1, + * RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1, + * RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3, + * RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17, + * RCC_APB2Periph_TIM9, RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11 + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->APB2ENR |= RCC_APB2Periph; + } + else + { + RCC->APB2ENR &= ~RCC_APB2Periph; + } +} + +/** + * @brief Enables or disables the Low Speed APB (APB1) peripheral clock. + * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4, + * RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7, + * RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3, + * RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4, + * RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2, + * RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP, + * RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_CEC, + * RCC_APB1Periph_TIM12, RCC_APB1Periph_TIM13, RCC_APB1Periph_TIM14 + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->APB1ENR |= RCC_APB1Periph; + } + else + { + RCC->APB1ENR &= ~RCC_APB1Periph; + } +} + +#ifdef STM32F10X_CL +/** + * @brief Forces or releases AHB peripheral reset. + * @note This function applies only to STM32 Connectivity line devices. + * @param RCC_AHBPeriph: specifies the AHB peripheral to reset. + * This parameter can be any combination of the following values: + * @arg RCC_AHBPeriph_OTG_FS + * @arg RCC_AHBPeriph_ETH_MAC + * @param NewState: new state of the specified peripheral reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB_PERIPH_RESET(RCC_AHBPeriph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->AHBRSTR |= RCC_AHBPeriph; + } + else + { + RCC->AHBRSTR &= ~RCC_AHBPeriph; + } +} +#endif /* STM32F10X_CL */ + +/** + * @brief Forces or releases High Speed APB (APB2) peripheral reset. + * @param RCC_APB2Periph: specifies the APB2 peripheral to reset. + * This parameter can be any combination of the following values: + * @arg RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB, + * RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE, + * RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1, + * RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1, + * RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3, + * RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17, + * RCC_APB2Periph_TIM9, RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11 + * @param NewState: new state of the specified peripheral reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->APB2RSTR |= RCC_APB2Periph; + } + else + { + RCC->APB2RSTR &= ~RCC_APB2Periph; + } +} + +/** + * @brief Forces or releases Low Speed APB (APB1) peripheral reset. + * @param RCC_APB1Periph: specifies the APB1 peripheral to reset. + * This parameter can be any combination of the following values: + * @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4, + * RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7, + * RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3, + * RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4, + * RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2, + * RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP, + * RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_CEC, + * RCC_APB1Periph_TIM12, RCC_APB1Periph_TIM13, RCC_APB1Periph_TIM14 + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->APB1RSTR |= RCC_APB1Periph; + } + else + { + RCC->APB1RSTR &= ~RCC_APB1Periph; + } +} + +/** + * @brief Forces or releases the Backup domain reset. + * @param NewState: new state of the Backup domain reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_BackupResetCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState; +} + +/** + * @brief Enables or disables the Clock Security System. + * @param NewState: new state of the Clock Security System.. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_ClockSecuritySystemCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState; +} + +/** + * @brief Selects the clock source to output on MCO pin. + * @param RCC_MCO: specifies the clock source to output. + * + * For @b STM32_Connectivity_line_devices, this parameter can be one of the + * following values: + * @arg RCC_MCO_NoClock: No clock selected + * @arg RCC_MCO_SYSCLK: System clock selected + * @arg RCC_MCO_HSI: HSI oscillator clock selected + * @arg RCC_MCO_HSE: HSE oscillator clock selected + * @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected + * @arg RCC_MCO_PLL2CLK: PLL2 clock selected + * @arg RCC_MCO_PLL3CLK_Div2: PLL3 clock divided by 2 selected + * @arg RCC_MCO_XT1: External 3-25 MHz oscillator clock selected + * @arg RCC_MCO_PLL3CLK: PLL3 clock selected + * + * For @b other_STM32_devices, this parameter can be one of the following values: + * @arg RCC_MCO_NoClock: No clock selected + * @arg RCC_MCO_SYSCLK: System clock selected + * @arg RCC_MCO_HSI: HSI oscillator clock selected + * @arg RCC_MCO_HSE: HSE oscillator clock selected + * @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected + * + * @retval None + */ +void RCC_MCOConfig(uint8_t RCC_MCO) +{ + /* Check the parameters */ + assert_param(IS_RCC_MCO(RCC_MCO)); + + /* Perform Byte access to MCO bits to select the MCO source */ + *(__IO uint8_t *) CFGR_BYTE4_ADDRESS = RCC_MCO; +} + +/** + * @brief Checks whether the specified RCC flag is set or not. + * @param RCC_FLAG: specifies the flag to check. + * + * For @b STM32_Connectivity_line_devices, this parameter can be one of the + * following values: + * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready + * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready + * @arg RCC_FLAG_PLLRDY: PLL clock ready + * @arg RCC_FLAG_PLL2RDY: PLL2 clock ready + * @arg RCC_FLAG_PLL3RDY: PLL3 clock ready + * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready + * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready + * @arg RCC_FLAG_PINRST: Pin reset + * @arg RCC_FLAG_PORRST: POR/PDR reset + * @arg RCC_FLAG_SFTRST: Software reset + * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset + * @arg RCC_FLAG_WWDGRST: Window Watchdog reset + * @arg RCC_FLAG_LPWRRST: Low Power reset + * + * For @b other_STM32_devices, this parameter can be one of the following values: + * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready + * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready + * @arg RCC_FLAG_PLLRDY: PLL clock ready + * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready + * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready + * @arg RCC_FLAG_PINRST: Pin reset + * @arg RCC_FLAG_PORRST: POR/PDR reset + * @arg RCC_FLAG_SFTRST: Software reset + * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset + * @arg RCC_FLAG_WWDGRST: Window Watchdog reset + * @arg RCC_FLAG_LPWRRST: Low Power reset + * + * @retval The new state of RCC_FLAG (SET or RESET). + */ +FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG) +{ + uint32_t tmp = 0; + uint32_t statusreg = 0; + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_RCC_FLAG(RCC_FLAG)); + + /* Get the RCC register index */ + tmp = RCC_FLAG >> 5; + if (tmp == 1) /* The flag to check is in CR register */ + { + statusreg = RCC->CR; + } + else if (tmp == 2) /* The flag to check is in BDCR register */ + { + statusreg = RCC->BDCR; + } + else /* The flag to check is in CSR register */ + { + statusreg = RCC->CSR; + } + + /* Get the flag position */ + tmp = RCC_FLAG & FLAG_Mask; + if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + /* Return the flag status */ + return bitstatus; +} + +/** + * @brief Clears the RCC reset flags. + * @note The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, + * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST + * @param None + * @retval None + */ +void RCC_ClearFlag(void) +{ + /* Set RMVF bit to clear the reset flags */ + RCC->CSR |= CSR_RMVF_Set; +} + +/** + * @brief Checks whether the specified RCC interrupt has occurred or not. + * @param RCC_IT: specifies the RCC interrupt source to check. + * + * For @b STM32_Connectivity_line_devices, this parameter can be one of the + * following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_PLLRDY: PLL ready interrupt + * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt + * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt + * @arg RCC_IT_CSS: Clock Security System interrupt + * + * For @b other_STM32_devices, this parameter can be one of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_PLLRDY: PLL ready interrupt + * @arg RCC_IT_CSS: Clock Security System interrupt + * + * @retval The new state of RCC_IT (SET or RESET). + */ +ITStatus RCC_GetITStatus(uint8_t RCC_IT) +{ + ITStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_RCC_GET_IT(RCC_IT)); + + /* Check the status of the specified RCC interrupt */ + if ((RCC->CIR & RCC_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + /* Return the RCC_IT status */ + return bitstatus; +} + +/** + * @brief Clears the RCC’s interrupt pending bits. + * @param RCC_IT: specifies the interrupt pending bit to clear. + * + * For @b STM32_Connectivity_line_devices, this parameter can be any combination + * of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_PLLRDY: PLL ready interrupt + * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt + * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt + * @arg RCC_IT_CSS: Clock Security System interrupt + * + * For @b other_STM32_devices, this parameter can be any combination of the + * following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_PLLRDY: PLL ready interrupt + * + * @arg RCC_IT_CSS: Clock Security System interrupt + * @retval None + */ +void RCC_ClearITPendingBit(uint8_t RCC_IT) +{ + /* Check the parameters */ + assert_param(IS_RCC_CLEAR_IT(RCC_IT)); + + /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt + pending bits */ + *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32f10x/stm32f10x_rtc.c b/example/libs_stm/src/stm32f10x/stm32f10x_rtc.c new file mode 100644 index 0000000..2720124 --- /dev/null +++ b/example/libs_stm/src/stm32f10x/stm32f10x_rtc.c @@ -0,0 +1,341 @@ +/** + ****************************************************************************** + * @file stm32f10x_rtc.c + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file provides all the RTC firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_rtc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup RTC + * @brief RTC driver modules + * @{ + */ + +/** @defgroup RTC_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + +/** @defgroup RTC_Private_Defines + * @{ + */ + +#define CRL_CNF_Set ((uint16_t)0x0010) /*!< Configuration Flag Enable Mask */ +#define CRL_CNF_Reset ((uint16_t)0xFFEF) /*!< Configuration Flag Disable Mask */ +#define RTC_LSB_Mask ((uint32_t)0x0000FFFF) /*!< RTC LSB Mask */ +#define PRLH_MSB_Mask ((uint32_t)0x000F0000) /*!< RTC Prescaler MSB Mask */ + +/** + * @} + */ + +/** @defgroup RTC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup RTC_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup RTC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup RTC_Private_Functions + * @{ + */ + +/** + * @brief Enables or disables the specified RTC interrupts. + * @param RTC_IT: specifies the RTC interrupts sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg RTC_IT_OW: Overflow interrupt + * @arg RTC_IT_ALR: Alarm interrupt + * @arg RTC_IT_SEC: Second interrupt + * @param NewState: new state of the specified RTC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RTC_IT(RTC_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RTC->CRH |= RTC_IT; + } + else + { + RTC->CRH &= (uint16_t)~RTC_IT; + } +} + +/** + * @brief Enters the RTC configuration mode. + * @param None + * @retval None + */ +void RTC_EnterConfigMode(void) +{ + /* Set the CNF flag to enter in the Configuration Mode */ + RTC->CRL |= CRL_CNF_Set; +} + +/** + * @brief Exits from the RTC configuration mode. + * @param None + * @retval None + */ +void RTC_ExitConfigMode(void) +{ + /* Reset the CNF flag to exit from the Configuration Mode */ + RTC->CRL &= CRL_CNF_Reset; +} + +/** + * @brief Gets the RTC counter value. + * @param None + * @retval RTC counter value. + */ +uint32_t RTC_GetCounter(void) +{ + uint16_t tmp = 0; + tmp = RTC->CNTL; + return (((uint32_t)RTC->CNTH << 16 ) | tmp) ; +} + +/** + * @brief Sets the RTC counter value. + * @param CounterValue: RTC counter new value. + * @retval None + */ +void RTC_SetCounter(uint32_t CounterValue) +{ + RTC_EnterConfigMode(); + /* Set RTC COUNTER MSB word */ + RTC->CNTH = CounterValue >> 16; + /* Set RTC COUNTER LSB word */ + RTC->CNTL = (CounterValue & RTC_LSB_Mask); + RTC_ExitConfigMode(); +} + +/** + * @brief Sets the RTC prescaler value. + * @param PrescalerValue: RTC prescaler new value. + * @retval None + */ +void RTC_SetPrescaler(uint32_t PrescalerValue) +{ + /* Check the parameters */ + assert_param(IS_RTC_PRESCALER(PrescalerValue)); + + RTC_EnterConfigMode(); + /* Set RTC PRESCALER MSB word */ + RTC->PRLH = (PrescalerValue & PRLH_MSB_Mask) >> 16; + /* Set RTC PRESCALER LSB word */ + RTC->PRLL = (PrescalerValue & RTC_LSB_Mask); + RTC_ExitConfigMode(); +} + +/** + * @brief Sets the RTC alarm value. + * @param AlarmValue: RTC alarm new value. + * @retval None + */ +void RTC_SetAlarm(uint32_t AlarmValue) +{ + RTC_EnterConfigMode(); + /* Set the ALARM MSB word */ + RTC->ALRH = AlarmValue >> 16; + /* Set the ALARM LSB word */ + RTC->ALRL = (AlarmValue & RTC_LSB_Mask); + RTC_ExitConfigMode(); +} + +/** + * @brief Gets the RTC divider value. + * @param None + * @retval RTC Divider value. + */ +uint32_t RTC_GetDivider(void) +{ + uint32_t tmp = 0x00; + tmp = ((uint32_t)RTC->DIVH & (uint32_t)0x000F) << 16; + tmp |= RTC->DIVL; + return tmp; +} + +/** + * @brief Waits until last write operation on RTC registers has finished. + * @note This function must be called before any write to RTC registers. + * @param None + * @retval None + */ +void RTC_WaitForLastTask(void) +{ + /* Loop until RTOFF flag is set */ + while ((RTC->CRL & RTC_FLAG_RTOFF) == (uint16_t)RESET) + { + } +} + +/** + * @brief Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL) + * are synchronized with RTC APB clock. + * @note This function must be called before any read operation after an APB reset + * or an APB clock stop. + * @param None + * @retval None + */ +void RTC_WaitForSynchro(void) +{ + /* Clear RSF flag */ + RTC->CRL &= (uint16_t)~RTC_FLAG_RSF; + /* Loop until RSF flag is set */ + while ((RTC->CRL & RTC_FLAG_RSF) == (uint16_t)RESET) + { + } +} + +/** + * @brief Checks whether the specified RTC flag is set or not. + * @param RTC_FLAG: specifies the flag to check. + * This parameter can be one the following values: + * @arg RTC_FLAG_RTOFF: RTC Operation OFF flag + * @arg RTC_FLAG_RSF: Registers Synchronized flag + * @arg RTC_FLAG_OW: Overflow flag + * @arg RTC_FLAG_ALR: Alarm flag + * @arg RTC_FLAG_SEC: Second flag + * @retval The new state of RTC_FLAG (SET or RESET). + */ +FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_RTC_GET_FLAG(RTC_FLAG)); + + if ((RTC->CRL & RTC_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the RTC’s pending flags. + * @param RTC_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg RTC_FLAG_RSF: Registers Synchronized flag. This flag is cleared only after + * an APB reset or an APB Clock stop. + * @arg RTC_FLAG_OW: Overflow flag + * @arg RTC_FLAG_ALR: Alarm flag + * @arg RTC_FLAG_SEC: Second flag + * @retval None + */ +void RTC_ClearFlag(uint16_t RTC_FLAG) +{ + /* Check the parameters */ + assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG)); + + /* Clear the coressponding RTC flag */ + RTC->CRL &= (uint16_t)~RTC_FLAG; +} + +/** + * @brief Checks whether the specified RTC interrupt has occured or not. + * @param RTC_IT: specifies the RTC interrupts sources to check. + * This parameter can be one of the following values: + * @arg RTC_IT_OW: Overflow interrupt + * @arg RTC_IT_ALR: Alarm interrupt + * @arg RTC_IT_SEC: Second interrupt + * @retval The new state of the RTC_IT (SET or RESET). + */ +ITStatus RTC_GetITStatus(uint16_t RTC_IT) +{ + ITStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_RTC_GET_IT(RTC_IT)); + + bitstatus = (ITStatus)(RTC->CRL & RTC_IT); + if (((RTC->CRH & RTC_IT) != (uint16_t)RESET) && (bitstatus != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the RTC’s interrupt pending bits. + * @param RTC_IT: specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg RTC_IT_OW: Overflow interrupt + * @arg RTC_IT_ALR: Alarm interrupt + * @arg RTC_IT_SEC: Second interrupt + * @retval None + */ +void RTC_ClearITPendingBit(uint16_t RTC_IT) +{ + /* Check the parameters */ + assert_param(IS_RTC_IT(RTC_IT)); + + /* Clear the coressponding RTC pending bit */ + RTC->CRL &= (uint16_t)~RTC_IT; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32f10x/stm32f10x_sdio.c b/example/libs_stm/src/stm32f10x/stm32f10x_sdio.c new file mode 100644 index 0000000..9d4a376 --- /dev/null +++ b/example/libs_stm/src/stm32f10x/stm32f10x_sdio.c @@ -0,0 +1,798 @@ +/** + ****************************************************************************** + * @file stm32f10x_sdio.c + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file provides all the SDIO firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_sdio.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup SDIO + * @brief SDIO driver modules + * @{ + */ + +/** @defgroup SDIO_Private_TypesDefinitions + * @{ + */ + +/* ------------ SDIO registers bit address in the alias region ----------- */ +#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE) + +/* --- CLKCR Register ---*/ + +/* Alias word address of CLKEN bit */ +#define CLKCR_OFFSET (SDIO_OFFSET + 0x04) +#define CLKEN_BitNumber 0x08 +#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4)) + +/* --- CMD Register ---*/ + +/* Alias word address of SDIOSUSPEND bit */ +#define CMD_OFFSET (SDIO_OFFSET + 0x0C) +#define SDIOSUSPEND_BitNumber 0x0B +#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4)) + +/* Alias word address of ENCMDCOMPL bit */ +#define ENCMDCOMPL_BitNumber 0x0C +#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4)) + +/* Alias word address of NIEN bit */ +#define NIEN_BitNumber 0x0D +#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4)) + +/* Alias word address of ATACMD bit */ +#define ATACMD_BitNumber 0x0E +#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4)) + +/* --- DCTRL Register ---*/ + +/* Alias word address of DMAEN bit */ +#define DCTRL_OFFSET (SDIO_OFFSET + 0x2C) +#define DMAEN_BitNumber 0x03 +#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4)) + +/* Alias word address of RWSTART bit */ +#define RWSTART_BitNumber 0x08 +#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4)) + +/* Alias word address of RWSTOP bit */ +#define RWSTOP_BitNumber 0x09 +#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4)) + +/* Alias word address of RWMOD bit */ +#define RWMOD_BitNumber 0x0A +#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4)) + +/* Alias word address of SDIOEN bit */ +#define SDIOEN_BitNumber 0x0B +#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4)) + +/* ---------------------- SDIO registers bit mask ------------------------ */ + +/* --- CLKCR Register ---*/ + +/* CLKCR register clear mask */ +#define CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100) + +/* --- PWRCTRL Register ---*/ + +/* SDIO PWRCTRL Mask */ +#define PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC) + +/* --- DCTRL Register ---*/ + +/* SDIO DCTRL Clear Mask */ +#define DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08) + +/* --- CMD Register ---*/ + +/* CMD Register clear mask */ +#define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800) + +/* SDIO RESP Registers Address */ +#define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14)) + +/** + * @} + */ + +/** @defgroup SDIO_Private_Defines + * @{ + */ + +/** + * @} + */ + +/** @defgroup SDIO_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup SDIO_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup SDIO_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup SDIO_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the SDIO peripheral registers to their default reset values. + * @param None + * @retval None + */ +void SDIO_DeInit(void) +{ + SDIO->POWER = 0x00000000; + SDIO->CLKCR = 0x00000000; + SDIO->ARG = 0x00000000; + SDIO->CMD = 0x00000000; + SDIO->DTIMER = 0x00000000; + SDIO->DLEN = 0x00000000; + SDIO->DCTRL = 0x00000000; + SDIO->ICR = 0x00C007FF; + SDIO->MASK = 0x00000000; +} + +/** + * @brief Initializes the SDIO peripheral according to the specified + * parameters in the SDIO_InitStruct. + * @param SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure + * that contains the configuration information for the SDIO peripheral. + * @retval None + */ +void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_SDIO_CLOCK_EDGE(SDIO_InitStruct->SDIO_ClockEdge)); + assert_param(IS_SDIO_CLOCK_BYPASS(SDIO_InitStruct->SDIO_ClockBypass)); + assert_param(IS_SDIO_CLOCK_POWER_SAVE(SDIO_InitStruct->SDIO_ClockPowerSave)); + assert_param(IS_SDIO_BUS_WIDE(SDIO_InitStruct->SDIO_BusWide)); + assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(SDIO_InitStruct->SDIO_HardwareFlowControl)); + +/*---------------------------- SDIO CLKCR Configuration ------------------------*/ + /* Get the SDIO CLKCR value */ + tmpreg = SDIO->CLKCR; + + /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */ + tmpreg &= CLKCR_CLEAR_MASK; + + /* Set CLKDIV bits according to SDIO_ClockDiv value */ + /* Set PWRSAV bit according to SDIO_ClockPowerSave value */ + /* Set BYPASS bit according to SDIO_ClockBypass value */ + /* Set WIDBUS bits according to SDIO_BusWide value */ + /* Set NEGEDGE bits according to SDIO_ClockEdge value */ + /* Set HWFC_EN bits according to SDIO_HardwareFlowControl value */ + tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv | SDIO_InitStruct->SDIO_ClockPowerSave | + SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide | + SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl); + + /* Write to SDIO CLKCR */ + SDIO->CLKCR = tmpreg; +} + +/** + * @brief Fills each SDIO_InitStruct member with its default value. + * @param SDIO_InitStruct: pointer to an SDIO_InitTypeDef structure which + * will be initialized. + * @retval None + */ +void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct) +{ + /* SDIO_InitStruct members default value */ + SDIO_InitStruct->SDIO_ClockDiv = 0x00; + SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising; + SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable; + SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable; + SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b; + SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable; +} + +/** + * @brief Enables or disables the SDIO Clock. + * @param NewState: new state of the SDIO Clock. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_ClockCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CLKCR_CLKEN_BB = (uint32_t)NewState; +} + +/** + * @brief Sets the power status of the controller. + * @param SDIO_PowerState: new state of the Power state. + * This parameter can be one of the following values: + * @arg SDIO_PowerState_OFF + * @arg SDIO_PowerState_ON + * @retval None + */ +void SDIO_SetPowerState(uint32_t SDIO_PowerState) +{ + /* Check the parameters */ + assert_param(IS_SDIO_POWER_STATE(SDIO_PowerState)); + + SDIO->POWER &= PWR_PWRCTRL_MASK; + SDIO->POWER |= SDIO_PowerState; +} + +/** + * @brief Gets the power status of the controller. + * @param None + * @retval Power status of the controller. The returned value can + * be one of the following: + * - 0x00: Power OFF + * - 0x02: Power UP + * - 0x03: Power ON + */ +uint32_t SDIO_GetPowerState(void) +{ + return (SDIO->POWER & (~PWR_PWRCTRL_MASK)); +} + +/** + * @brief Enables or disables the SDIO interrupts. + * @param SDIO_IT: specifies the SDIO interrupt sources to be enabled or disabled. + * This parameter can be one or a combination of the following values: + * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt + * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt + * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide + * bus mode interrupt + * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt + * @arg SDIO_IT_TXACT: Data transmit in progress interrupt + * @arg SDIO_IT_RXACT: Data receive in progress interrupt + * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt + * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt + * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt + * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt + * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt + * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt + * @param NewState: new state of the specified SDIO interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SDIO_IT(SDIO_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the SDIO interrupts */ + SDIO->MASK |= SDIO_IT; + } + else + { + /* Disable the SDIO interrupts */ + SDIO->MASK &= ~SDIO_IT; + } +} + +/** + * @brief Enables or disables the SDIO DMA request. + * @param NewState: new state of the selected SDIO DMA request. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_DMACmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) DCTRL_DMAEN_BB = (uint32_t)NewState; +} + +/** + * @brief Initializes the SDIO Command according to the specified + * parameters in the SDIO_CmdInitStruct and send the command. + * @param SDIO_CmdInitStruct : pointer to a SDIO_CmdInitTypeDef + * structure that contains the configuration information for the SDIO command. + * @retval None + */ +void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->SDIO_CmdIndex)); + assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->SDIO_Response)); + assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->SDIO_Wait)); + assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->SDIO_CPSM)); + +/*---------------------------- SDIO ARG Configuration ------------------------*/ + /* Set the SDIO Argument value */ + SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument; + +/*---------------------------- SDIO CMD Configuration ------------------------*/ + /* Get the SDIO CMD value */ + tmpreg = SDIO->CMD; + /* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */ + tmpreg &= CMD_CLEAR_MASK; + /* Set CMDINDEX bits according to SDIO_CmdIndex value */ + /* Set WAITRESP bits according to SDIO_Response value */ + /* Set WAITINT and WAITPEND bits according to SDIO_Wait value */ + /* Set CPSMEN bits according to SDIO_CPSM value */ + tmpreg |= (uint32_t)SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response + | SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM; + + /* Write to SDIO CMD */ + SDIO->CMD = tmpreg; +} + +/** + * @brief Fills each SDIO_CmdInitStruct member with its default value. + * @param SDIO_CmdInitStruct: pointer to an SDIO_CmdInitTypeDef + * structure which will be initialized. + * @retval None + */ +void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct) +{ + /* SDIO_CmdInitStruct members default value */ + SDIO_CmdInitStruct->SDIO_Argument = 0x00; + SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00; + SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No; + SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable; +} + +/** + * @brief Returns command index of last command for which response received. + * @param None + * @retval Returns the command index of the last command response received. + */ +uint8_t SDIO_GetCommandResponse(void) +{ + return (uint8_t)(SDIO->RESPCMD); +} + +/** + * @brief Returns response received from the card for the last command. + * @param SDIO_RESP: Specifies the SDIO response register. + * This parameter can be one of the following values: + * @arg SDIO_RESP1: Response Register 1 + * @arg SDIO_RESP2: Response Register 2 + * @arg SDIO_RESP3: Response Register 3 + * @arg SDIO_RESP4: Response Register 4 + * @retval The Corresponding response register value. + */ +uint32_t SDIO_GetResponse(uint32_t SDIO_RESP) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_SDIO_RESP(SDIO_RESP)); + + tmp = SDIO_RESP_ADDR + SDIO_RESP; + + return (*(__IO uint32_t *) tmp); +} + +/** + * @brief Initializes the SDIO data path according to the specified + * parameters in the SDIO_DataInitStruct. + * @param SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure that + * contains the configuration information for the SDIO command. + * @retval None + */ +void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->SDIO_DataLength)); + assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->SDIO_DataBlockSize)); + assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->SDIO_TransferDir)); + assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->SDIO_TransferMode)); + assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->SDIO_DPSM)); + +/*---------------------------- SDIO DTIMER Configuration ---------------------*/ + /* Set the SDIO Data TimeOut value */ + SDIO->DTIMER = SDIO_DataInitStruct->SDIO_DataTimeOut; + +/*---------------------------- SDIO DLEN Configuration -----------------------*/ + /* Set the SDIO DataLength value */ + SDIO->DLEN = SDIO_DataInitStruct->SDIO_DataLength; + +/*---------------------------- SDIO DCTRL Configuration ----------------------*/ + /* Get the SDIO DCTRL value */ + tmpreg = SDIO->DCTRL; + /* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */ + tmpreg &= DCTRL_CLEAR_MASK; + /* Set DEN bit according to SDIO_DPSM value */ + /* Set DTMODE bit according to SDIO_TransferMode value */ + /* Set DTDIR bit according to SDIO_TransferDir value */ + /* Set DBCKSIZE bits according to SDIO_DataBlockSize value */ + tmpreg |= (uint32_t)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir + | SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM; + + /* Write to SDIO DCTRL */ + SDIO->DCTRL = tmpreg; +} + +/** + * @brief Fills each SDIO_DataInitStruct member with its default value. + * @param SDIO_DataInitStruct: pointer to an SDIO_DataInitTypeDef structure which + * will be initialized. + * @retval None + */ +void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct) +{ + /* SDIO_DataInitStruct members default value */ + SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF; + SDIO_DataInitStruct->SDIO_DataLength = 0x00; + SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b; + SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard; + SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block; + SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable; +} + +/** + * @brief Returns number of remaining data bytes to be transferred. + * @param None + * @retval Number of remaining data bytes to be transferred + */ +uint32_t SDIO_GetDataCounter(void) +{ + return SDIO->DCOUNT; +} + +/** + * @brief Read one data word from Rx FIFO. + * @param None + * @retval Data received + */ +uint32_t SDIO_ReadData(void) +{ + return SDIO->FIFO; +} + +/** + * @brief Write one data word to Tx FIFO. + * @param Data: 32-bit data word to write. + * @retval None + */ +void SDIO_WriteData(uint32_t Data) +{ + SDIO->FIFO = Data; +} + +/** + * @brief Returns the number of words left to be written to or read from FIFO. + * @param None + * @retval Remaining number of words. + */ +uint32_t SDIO_GetFIFOCount(void) +{ + return SDIO->FIFOCNT; +} + +/** + * @brief Starts the SD I/O Read Wait operation. + * @param NewState: new state of the Start SDIO Read Wait operation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_StartSDIOReadWait(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) DCTRL_RWSTART_BB = (uint32_t) NewState; +} + +/** + * @brief Stops the SD I/O Read Wait operation. + * @param NewState: new state of the Stop SDIO Read Wait operation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_StopSDIOReadWait(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) DCTRL_RWSTOP_BB = (uint32_t) NewState; +} + +/** + * @brief Sets one of the two options of inserting read wait interval. + * @param SDIO_ReadWaitMode: SD I/O Read Wait operation mode. + * This parametre can be: + * @arg SDIO_ReadWaitMode_CLK: Read Wait control by stopping SDIOCLK + * @arg SDIO_ReadWaitMode_DATA2: Read Wait control using SDIO_DATA2 + * @retval None + */ +void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode) +{ + /* Check the parameters */ + assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode)); + + *(__IO uint32_t *) DCTRL_RWMOD_BB = SDIO_ReadWaitMode; +} + +/** + * @brief Enables or disables the SD I/O Mode Operation. + * @param NewState: new state of SDIO specific operation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_SetSDIOOperation(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) DCTRL_SDIOEN_BB = (uint32_t)NewState; +} + +/** + * @brief Enables or disables the SD I/O Mode suspend command sending. + * @param NewState: new state of the SD I/O Mode suspend command. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_SendSDIOSuspendCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CMD_SDIOSUSPEND_BB = (uint32_t)NewState; +} + +/** + * @brief Enables or disables the command completion signal. + * @param NewState: new state of command completion signal. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_CommandCompletionCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CMD_ENCMDCOMPL_BB = (uint32_t)NewState; +} + +/** + * @brief Enables or disables the CE-ATA interrupt. + * @param NewState: new state of CE-ATA interrupt. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_CEATAITCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)((~((uint32_t)NewState)) & ((uint32_t)0x1)); +} + +/** + * @brief Sends CE-ATA command (CMD61). + * @param NewState: new state of CE-ATA command. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_SendCEATACmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CMD_ATACMD_BB = (uint32_t)NewState; +} + +/** + * @brief Checks whether the specified SDIO flag is set or not. + * @param SDIO_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) + * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) + * @arg SDIO_FLAG_CTIMEOUT: Command response timeout + * @arg SDIO_FLAG_DTIMEOUT: Data timeout + * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error + * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error + * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) + * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) + * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) + * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide + * bus mode. + * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) + * @arg SDIO_FLAG_CMDACT: Command transfer in progress + * @arg SDIO_FLAG_TXACT: Data transmit in progress + * @arg SDIO_FLAG_RXACT: Data receive in progress + * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty + * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full + * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full + * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full + * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty + * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty + * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO + * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO + * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received + * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 + * @retval The new state of SDIO_FLAG (SET or RESET). + */ +FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_SDIO_FLAG(SDIO_FLAG)); + + if ((SDIO->STA & SDIO_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the SDIO's pending flags. + * @param SDIO_FLAG: specifies the flag to clear. + * This parameter can be one or a combination of the following values: + * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) + * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) + * @arg SDIO_FLAG_CTIMEOUT: Command response timeout + * @arg SDIO_FLAG_DTIMEOUT: Data timeout + * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error + * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error + * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) + * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) + * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) + * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide + * bus mode + * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) + * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received + * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 + * @retval None + */ +void SDIO_ClearFlag(uint32_t SDIO_FLAG) +{ + /* Check the parameters */ + assert_param(IS_SDIO_CLEAR_FLAG(SDIO_FLAG)); + + SDIO->ICR = SDIO_FLAG; +} + +/** + * @brief Checks whether the specified SDIO interrupt has occurred or not. + * @param SDIO_IT: specifies the SDIO interrupt source to check. + * This parameter can be one of the following values: + * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt + * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt + * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide + * bus mode interrupt + * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt + * @arg SDIO_IT_TXACT: Data transmit in progress interrupt + * @arg SDIO_IT_RXACT: Data receive in progress interrupt + * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt + * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt + * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt + * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt + * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt + * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt + * @retval The new state of SDIO_IT (SET or RESET). + */ +ITStatus SDIO_GetITStatus(uint32_t SDIO_IT) +{ + ITStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_SDIO_GET_IT(SDIO_IT)); + if ((SDIO->STA & SDIO_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the SDIO’s interrupt pending bits. + * @param SDIO_IT: specifies the interrupt pending bit to clear. + * This parameter can be one or a combination of the following values: + * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt + * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt + * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide + * bus mode interrupt + * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt + * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 + * @retval None + */ +void SDIO_ClearITPendingBit(uint32_t SDIO_IT) +{ + /* Check the parameters */ + assert_param(IS_SDIO_CLEAR_IT(SDIO_IT)); + + SDIO->ICR = SDIO_IT; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32f10x/stm32f10x_spi.c b/example/libs_stm/src/stm32f10x/stm32f10x_spi.c new file mode 100644 index 0000000..b1ff419 --- /dev/null +++ b/example/libs_stm/src/stm32f10x/stm32f10x_spi.c @@ -0,0 +1,907 @@ +/** + ****************************************************************************** + * @file stm32f10x_spi.c + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file provides all the SPI firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_spi.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup SPI + * @brief SPI driver modules + * @{ + */ + +/** @defgroup SPI_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + + +/** @defgroup SPI_Private_Defines + * @{ + */ + +/* SPI SPE mask */ +#define CR1_SPE_Set ((uint16_t)0x0040) +#define CR1_SPE_Reset ((uint16_t)0xFFBF) + +/* I2S I2SE mask */ +#define I2SCFGR_I2SE_Set ((uint16_t)0x0400) +#define I2SCFGR_I2SE_Reset ((uint16_t)0xFBFF) + +/* SPI CRCNext mask */ +#define CR1_CRCNext_Set ((uint16_t)0x1000) + +/* SPI CRCEN mask */ +#define CR1_CRCEN_Set ((uint16_t)0x2000) +#define CR1_CRCEN_Reset ((uint16_t)0xDFFF) + +/* SPI SSOE mask */ +#define CR2_SSOE_Set ((uint16_t)0x0004) +#define CR2_SSOE_Reset ((uint16_t)0xFFFB) + +/* SPI registers Masks */ +#define CR1_CLEAR_Mask ((uint16_t)0x3040) +#define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040) + +/* SPI or I2S mode selection masks */ +#define SPI_Mode_Select ((uint16_t)0xF7FF) +#define I2S_Mode_Select ((uint16_t)0x0800) + +/* I2S clock source selection masks */ +#define I2S2_CLOCK_SRC ((uint32_t)(0x00020000)) +#define I2S3_CLOCK_SRC ((uint32_t)(0x00040000)) +#define I2S_MUL_MASK ((uint32_t)(0x0000F000)) +#define I2S_DIV_MASK ((uint32_t)(0x000000F0)) + +/** + * @} + */ + +/** @defgroup SPI_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup SPI_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup SPI_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup SPI_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the SPIx peripheral registers to their default + * reset values (Affects also the I2Ss). + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @retval None + */ +void SPI_I2S_DeInit(SPI_TypeDef* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + if (SPIx == SPI1) + { + /* Enable SPI1 reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE); + /* Release SPI1 from reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE); + } + else if (SPIx == SPI2) + { + /* Enable SPI2 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE); + /* Release SPI2 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE); + } + else + { + if (SPIx == SPI3) + { + /* Enable SPI3 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE); + /* Release SPI3 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE); + } + } +} + +/** + * @brief Initializes the SPIx peripheral according to the specified + * parameters in the SPI_InitStruct. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that + * contains the configuration information for the specified SPI peripheral. + * @retval None + */ +void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct) +{ + uint16_t tmpreg = 0; + + /* check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Check the SPI parameters */ + assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction)); + assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode)); + assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize)); + assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL)); + assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA)); + assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS)); + assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler)); + assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit)); + assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial)); + +/*---------------------------- SPIx CR1 Configuration ------------------------*/ + /* Get the SPIx CR1 value */ + tmpreg = SPIx->CR1; + /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */ + tmpreg &= CR1_CLEAR_Mask; + /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler + master/salve mode, CPOL and CPHA */ + /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */ + /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */ + /* Set LSBFirst bit according to SPI_FirstBit value */ + /* Set BR bits according to SPI_BaudRatePrescaler value */ + /* Set CPOL bit according to SPI_CPOL value */ + /* Set CPHA bit according to SPI_CPHA value */ + tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode | + SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | + SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS | + SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit); + /* Write to SPIx CR1 */ + SPIx->CR1 = tmpreg; + + /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */ + SPIx->I2SCFGR &= SPI_Mode_Select; + +/*---------------------------- SPIx CRCPOLY Configuration --------------------*/ + /* Write to SPIx CRCPOLY */ + SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial; +} + +/** + * @brief Initializes the SPIx peripheral according to the specified + * parameters in the I2S_InitStruct. + * @param SPIx: where x can be 2 or 3 to select the SPI peripheral + * (configured in I2S mode). + * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that + * contains the configuration information for the specified SPI peripheral + * configured in I2S mode. + * @note + * The function calculates the optimal prescaler needed to obtain the most + * accurate audio frequency (depending on the I2S clock source, the PLL values + * and the product configuration). But in case the prescaler value is greater + * than 511, the default value (0x02) will be configured instead. * + * @retval None + */ +void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct) +{ + uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1; + uint32_t tmp = 0; + RCC_ClocksTypeDef RCC_Clocks; + uint32_t sourceclock = 0; + + /* Check the I2S parameters */ + assert_param(IS_SPI_23_PERIPH(SPIx)); + assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode)); + assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard)); + assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat)); + assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput)); + assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq)); + assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL)); + +/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/ + /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */ + SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask; + SPIx->I2SPR = 0x0002; + + /* Get the I2SCFGR register value */ + tmpreg = SPIx->I2SCFGR; + + /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/ + if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default) + { + i2sodd = (uint16_t)0; + i2sdiv = (uint16_t)2; + } + /* If the requested audio frequency is not the default, compute the prescaler */ + else + { + /* Check the frame length (For the Prescaler computing) */ + if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b) + { + /* Packet length is 16 bits */ + packetlength = 1; + } + else + { + /* Packet length is 32 bits */ + packetlength = 2; + } + + /* Get the I2S clock source mask depending on the peripheral number */ + if(((uint32_t)SPIx) == SPI2_BASE) + { + /* The mask is relative to I2S2 */ + tmp = I2S2_CLOCK_SRC; + } + else + { + /* The mask is relative to I2S3 */ + tmp = I2S3_CLOCK_SRC; + } + + /* Check the I2S clock source configuration depending on the Device: + Only Connectivity line devices have the PLL3 VCO clock */ +#ifdef STM32F10X_CL + if((RCC->CFGR2 & tmp) != 0) + { + /* Get the configuration bits of RCC PLL3 multiplier */ + tmp = (uint32_t)((RCC->CFGR2 & I2S_MUL_MASK) >> 12); + + /* Get the value of the PLL3 multiplier */ + if((tmp > 5) && (tmp < 15)) + { + /* Multplier is between 8 and 14 (value 15 is forbidden) */ + tmp += 2; + } + else + { + if (tmp == 15) + { + /* Multiplier is 20 */ + tmp = 20; + } + } + /* Get the PREDIV2 value */ + sourceclock = (uint32_t)(((RCC->CFGR2 & I2S_DIV_MASK) >> 4) + 1); + + /* Calculate the Source Clock frequency based on PLL3 and PREDIV2 values */ + sourceclock = (uint32_t) ((HSE_Value / sourceclock) * tmp * 2); + } + else + { + /* I2S Clock source is System clock: Get System Clock frequency */ + RCC_GetClocksFreq(&RCC_Clocks); + + /* Get the source clock value: based on System Clock value */ + sourceclock = RCC_Clocks.SYSCLK_Frequency; + } +#else /* STM32F10X_HD */ + /* I2S Clock source is System clock: Get System Clock frequency */ + RCC_GetClocksFreq(&RCC_Clocks); + + /* Get the source clock value: based on System Clock value */ + sourceclock = RCC_Clocks.SYSCLK_Frequency; +#endif /* STM32F10X_CL */ + + /* Compute the Real divider depending on the MCLK output state with a flaoting point */ + if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable) + { + /* MCLK output is enabled */ + tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5); + } + else + { + /* MCLK output is disabled */ + tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5); + } + + /* Remove the flaoting point */ + tmp = tmp / 10; + + /* Check the parity of the divider */ + i2sodd = (uint16_t)(tmp & (uint16_t)0x0001); + + /* Compute the i2sdiv prescaler */ + i2sdiv = (uint16_t)((tmp - i2sodd) / 2); + + /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */ + i2sodd = (uint16_t) (i2sodd << 8); + } + + /* Test if the divider is 1 or 0 or greater than 0xFF */ + if ((i2sdiv < 2) || (i2sdiv > 0xFF)) + { + /* Set the default values */ + i2sdiv = 2; + i2sodd = 0; + } + + /* Write to SPIx I2SPR register the computed value */ + SPIx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput)); + + /* Configure the I2S with the SPI_InitStruct values */ + tmpreg |= (uint16_t)(I2S_Mode_Select | (uint16_t)(I2S_InitStruct->I2S_Mode | \ + (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \ + (uint16_t)I2S_InitStruct->I2S_CPOL)))); + + /* Write to SPIx I2SCFGR */ + SPIx->I2SCFGR = tmpreg; +} + +/** + * @brief Fills each SPI_InitStruct member with its default value. + * @param SPI_InitStruct : pointer to a SPI_InitTypeDef structure which will be initialized. + * @retval None + */ +void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct) +{ +/*--------------- Reset SPI init structure parameters values -----------------*/ + /* Initialize the SPI_Direction member */ + SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex; + /* initialize the SPI_Mode member */ + SPI_InitStruct->SPI_Mode = SPI_Mode_Slave; + /* initialize the SPI_DataSize member */ + SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b; + /* Initialize the SPI_CPOL member */ + SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low; + /* Initialize the SPI_CPHA member */ + SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge; + /* Initialize the SPI_NSS member */ + SPI_InitStruct->SPI_NSS = SPI_NSS_Hard; + /* Initialize the SPI_BaudRatePrescaler member */ + SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; + /* Initialize the SPI_FirstBit member */ + SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB; + /* Initialize the SPI_CRCPolynomial member */ + SPI_InitStruct->SPI_CRCPolynomial = 7; +} + +/** + * @brief Fills each I2S_InitStruct member with its default value. + * @param I2S_InitStruct : pointer to a I2S_InitTypeDef structure which will be initialized. + * @retval None + */ +void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct) +{ +/*--------------- Reset I2S init structure parameters values -----------------*/ + /* Initialize the I2S_Mode member */ + I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx; + + /* Initialize the I2S_Standard member */ + I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips; + + /* Initialize the I2S_DataFormat member */ + I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b; + + /* Initialize the I2S_MCLKOutput member */ + I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable; + + /* Initialize the I2S_AudioFreq member */ + I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default; + + /* Initialize the I2S_CPOL member */ + I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low; +} + +/** + * @brief Enables or disables the specified SPI peripheral. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param NewState: new state of the SPIx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected SPI peripheral */ + SPIx->CR1 |= CR1_SPE_Set; + } + else + { + /* Disable the selected SPI peripheral */ + SPIx->CR1 &= CR1_SPE_Reset; + } +} + +/** + * @brief Enables or disables the specified SPI peripheral (in I2S mode). + * @param SPIx: where x can be 2 or 3 to select the SPI peripheral. + * @param NewState: new state of the SPIx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_23_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected SPI peripheral (in I2S mode) */ + SPIx->I2SCFGR |= I2SCFGR_I2SE_Set; + } + else + { + /* Disable the selected SPI peripheral (in I2S mode) */ + SPIx->I2SCFGR &= I2SCFGR_I2SE_Reset; + } +} + +/** + * @brief Enables or disables the specified SPI/I2S interrupts. + * @param SPIx: where x can be + * - 1, 2 or 3 in SPI mode + * - 2 or 3 in I2S mode + * @param SPI_I2S_IT: specifies the SPI/I2S interrupt source to be enabled or disabled. + * This parameter can be one of the following values: + * @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask + * @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask + * @arg SPI_I2S_IT_ERR: Error interrupt mask + * @param NewState: new state of the specified SPI/I2S interrupt. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState) +{ + uint16_t itpos = 0, itmask = 0 ; + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT)); + + /* Get the SPI/I2S IT index */ + itpos = SPI_I2S_IT >> 4; + + /* Set the IT mask */ + itmask = (uint16_t)1 << (uint16_t)itpos; + + if (NewState != DISABLE) + { + /* Enable the selected SPI/I2S interrupt */ + SPIx->CR2 |= itmask; + } + else + { + /* Disable the selected SPI/I2S interrupt */ + SPIx->CR2 &= (uint16_t)~itmask; + } +} + +/** + * @brief Enables or disables the SPIx/I2Sx DMA interface. + * @param SPIx: where x can be + * - 1, 2 or 3 in SPI mode + * - 2 or 3 in I2S mode + * @param SPI_I2S_DMAReq: specifies the SPI/I2S DMA transfer request to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request + * @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request + * @param NewState: new state of the selected SPI/I2S DMA transfer request. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_SPI_I2S_DMAREQ(SPI_I2S_DMAReq)); + if (NewState != DISABLE) + { + /* Enable the selected SPI/I2S DMA requests */ + SPIx->CR2 |= SPI_I2S_DMAReq; + } + else + { + /* Disable the selected SPI/I2S DMA requests */ + SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq; + } +} + +/** + * @brief Transmits a Data through the SPIx/I2Sx peripheral. + * @param SPIx: where x can be + * - 1, 2 or 3 in SPI mode + * - 2 or 3 in I2S mode + * @param Data : Data to be transmitted. + * @retval None + */ +void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Write in the DR register the data to be sent */ + SPIx->DR = Data; +} + +/** + * @brief Returns the most recent received data by the SPIx/I2Sx peripheral. + * @param SPIx: where x can be + * - 1, 2 or 3 in SPI mode + * - 2 or 3 in I2S mode + * @retval The value of the received data. + */ +uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Return the data in the DR register */ + return SPIx->DR; +} + +/** + * @brief Configures internally by software the NSS pin for the selected SPI. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param SPI_NSSInternalSoft: specifies the SPI NSS internal state. + * This parameter can be one of the following values: + * @arg SPI_NSSInternalSoft_Set: Set NSS pin internally + * @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally + * @retval None + */ +void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft)); + if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset) + { + /* Set NSS pin internally by software */ + SPIx->CR1 |= SPI_NSSInternalSoft_Set; + } + else + { + /* Reset NSS pin internally by software */ + SPIx->CR1 &= SPI_NSSInternalSoft_Reset; + } +} + +/** + * @brief Enables or disables the SS output for the selected SPI. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param NewState: new state of the SPIx SS output. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected SPI SS output */ + SPIx->CR2 |= CR2_SSOE_Set; + } + else + { + /* Disable the selected SPI SS output */ + SPIx->CR2 &= CR2_SSOE_Reset; + } +} + +/** + * @brief Configures the data size for the selected SPI. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param SPI_DataSize: specifies the SPI data size. + * This parameter can be one of the following values: + * @arg SPI_DataSize_16b: Set data frame format to 16bit + * @arg SPI_DataSize_8b: Set data frame format to 8bit + * @retval None + */ +void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_DATASIZE(SPI_DataSize)); + /* Clear DFF bit */ + SPIx->CR1 &= (uint16_t)~SPI_DataSize_16b; + /* Set new DFF bit value */ + SPIx->CR1 |= SPI_DataSize; +} + +/** + * @brief Transmit the SPIx CRC value. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @retval None + */ +void SPI_TransmitCRC(SPI_TypeDef* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Enable the selected SPI CRC transmission */ + SPIx->CR1 |= CR1_CRCNext_Set; +} + +/** + * @brief Enables or disables the CRC value calculation of the transfered bytes. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param NewState: new state of the SPIx CRC value calculation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected SPI CRC calculation */ + SPIx->CR1 |= CR1_CRCEN_Set; + } + else + { + /* Disable the selected SPI CRC calculation */ + SPIx->CR1 &= CR1_CRCEN_Reset; + } +} + +/** + * @brief Returns the transmit or the receive CRC register value for the specified SPI. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param SPI_CRC: specifies the CRC register to be read. + * This parameter can be one of the following values: + * @arg SPI_CRC_Tx: Selects Tx CRC register + * @arg SPI_CRC_Rx: Selects Rx CRC register + * @retval The selected CRC register value.. + */ +uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC) +{ + uint16_t crcreg = 0; + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_CRC(SPI_CRC)); + if (SPI_CRC != SPI_CRC_Rx) + { + /* Get the Tx CRC register */ + crcreg = SPIx->TXCRCR; + } + else + { + /* Get the Rx CRC register */ + crcreg = SPIx->RXCRCR; + } + /* Return the selected CRC register */ + return crcreg; +} + +/** + * @brief Returns the CRC Polynomial register value for the specified SPI. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @retval The CRC Polynomial register value. + */ +uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Return the CRC polynomial register */ + return SPIx->CRCPR; +} + +/** + * @brief Selects the data transfer direction in bi-directional mode for the specified SPI. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param SPI_Direction: specifies the data transfer direction in bi-directional mode. + * This parameter can be one of the following values: + * @arg SPI_Direction_Tx: Selects Tx transmission direction + * @arg SPI_Direction_Rx: Selects Rx receive direction + * @retval None + */ +void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_DIRECTION(SPI_Direction)); + if (SPI_Direction == SPI_Direction_Tx) + { + /* Set the Tx only mode */ + SPIx->CR1 |= SPI_Direction_Tx; + } + else + { + /* Set the Rx only mode */ + SPIx->CR1 &= SPI_Direction_Rx; + } +} + +/** + * @brief Checks whether the specified SPI/I2S flag is set or not. + * @param SPIx: where x can be + * - 1, 2 or 3 in SPI mode + * - 2 or 3 in I2S mode + * @param SPI_I2S_FLAG: specifies the SPI/I2S flag to check. + * This parameter can be one of the following values: + * @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag. + * @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag. + * @arg SPI_I2S_FLAG_BSY: Busy flag. + * @arg SPI_I2S_FLAG_OVR: Overrun flag. + * @arg SPI_FLAG_MODF: Mode Fault flag. + * @arg SPI_FLAG_CRCERR: CRC Error flag. + * @arg I2S_FLAG_UDR: Underrun Error flag. + * @arg I2S_FLAG_CHSIDE: Channel Side flag. + * @retval The new state of SPI_I2S_FLAG (SET or RESET). + */ +FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG)); + /* Check the status of the specified SPI/I2S flag */ + if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET) + { + /* SPI_I2S_FLAG is set */ + bitstatus = SET; + } + else + { + /* SPI_I2S_FLAG is reset */ + bitstatus = RESET; + } + /* Return the SPI_I2S_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the SPIx CRC Error (CRCERR) flag. + * @param SPIx: where x can be + * - 1, 2 or 3 in SPI mode + * @param SPI_I2S_FLAG: specifies the SPI flag to clear. + * This function clears only CRCERR flag. + * @note + * - OVR (OverRun error) flag is cleared by software sequence: a read + * operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read + * operation to SPI_SR register (SPI_I2S_GetFlagStatus()). + * - UDR (UnderRun error) flag is cleared by a read operation to + * SPI_SR register (SPI_I2S_GetFlagStatus()). + * - MODF (Mode Fault) flag is cleared by software sequence: a read/write + * operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a + * write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI). + * @retval None + */ +void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_I2S_CLEAR_FLAG(SPI_I2S_FLAG)); + + /* Clear the selected SPI CRC Error (CRCERR) flag */ + SPIx->SR = (uint16_t)~SPI_I2S_FLAG; +} + +/** + * @brief Checks whether the specified SPI/I2S interrupt has occurred or not. + * @param SPIx: where x can be + * - 1, 2 or 3 in SPI mode + * - 2 or 3 in I2S mode + * @param SPI_I2S_IT: specifies the SPI/I2S interrupt source to check. + * This parameter can be one of the following values: + * @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt. + * @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt. + * @arg SPI_I2S_IT_OVR: Overrun interrupt. + * @arg SPI_IT_MODF: Mode Fault interrupt. + * @arg SPI_IT_CRCERR: CRC Error interrupt. + * @arg I2S_IT_UDR: Underrun Error interrupt. + * @retval The new state of SPI_I2S_IT (SET or RESET). + */ +ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT) +{ + ITStatus bitstatus = RESET; + uint16_t itpos = 0, itmask = 0, enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT)); + + /* Get the SPI/I2S IT index */ + itpos = 0x01 << (SPI_I2S_IT & 0x0F); + + /* Get the SPI/I2S IT mask */ + itmask = SPI_I2S_IT >> 4; + + /* Set the IT mask */ + itmask = 0x01 << itmask; + + /* Get the SPI_I2S_IT enable bit status */ + enablestatus = (SPIx->CR2 & itmask) ; + + /* Check the status of the specified SPI/I2S interrupt */ + if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus) + { + /* SPI_I2S_IT is set */ + bitstatus = SET; + } + else + { + /* SPI_I2S_IT is reset */ + bitstatus = RESET; + } + /* Return the SPI_I2S_IT status */ + return bitstatus; +} + +/** + * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit. + * @param SPIx: where x can be + * - 1, 2 or 3 in SPI mode + * @param SPI_I2S_IT: specifies the SPI interrupt pending bit to clear. + * This function clears only CRCERR intetrrupt pending bit. + * @note + * - OVR (OverRun Error) interrupt pending bit is cleared by software + * sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData()) + * followed by a read operation to SPI_SR register (SPI_I2S_GetITStatus()). + * - UDR (UnderRun Error) interrupt pending bit is cleared by a read + * operation to SPI_SR register (SPI_I2S_GetITStatus()). + * - MODF (Mode Fault) interrupt pending bit is cleared by software sequence: + * a read/write operation to SPI_SR register (SPI_I2S_GetITStatus()) + * followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable + * the SPI). + * @retval None + */ +void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT) +{ + uint16_t itpos = 0; + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_I2S_CLEAR_IT(SPI_I2S_IT)); + + /* Get the SPI IT index */ + itpos = 0x01 << (SPI_I2S_IT & 0x0F); + + /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */ + SPIx->SR = (uint16_t)~itpos; +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32f10x/stm32f10x_tim.c b/example/libs_stm/src/stm32f10x/stm32f10x_tim.c new file mode 100644 index 0000000..c626dca --- /dev/null +++ b/example/libs_stm/src/stm32f10x/stm32f10x_tim.c @@ -0,0 +1,2834 @@ +/** + ****************************************************************************** + * @file stm32f10x_tim.c + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file provides all the TIM firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_tim.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup TIM + * @brief TIM driver modules + * @{ + */ + +/** @defgroup TIM_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup TIM_Private_Defines + * @{ + */ + +/* ---------------------- TIM registers bit mask ------------------------ */ +#define SMCR_ETR_Mask ((uint16_t)0x00FF) +#define CCMR_Offset ((uint16_t)0x0018) +#define CCER_CCE_Set ((uint16_t)0x0001) +#define CCER_CCNE_Set ((uint16_t)0x0004) + +/** + * @} + */ + +/** @defgroup TIM_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup TIM_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup TIM_Private_FunctionPrototypes + * @{ + */ + +static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +/** + * @} + */ + +/** @defgroup TIM_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup TIM_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup TIM_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup TIM_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the TIMx peripheral registers to their default reset values. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @retval None + */ +void TIM_DeInit(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + + if (TIMx == TIM1) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE); + } + else if (TIMx == TIM2) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE); + } + else if (TIMx == TIM3) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE); + } + else if (TIMx == TIM4) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE); + } + else if (TIMx == TIM5) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE); + } + else if (TIMx == TIM6) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE); + } + else if (TIMx == TIM7) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE); + } + else if (TIMx == TIM8) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE); + } + else if (TIMx == TIM9) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE); + } + else if (TIMx == TIM10) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE); + } + else if (TIMx == TIM11) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, DISABLE); + } + else if (TIMx == TIM12) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, DISABLE); + } + else if (TIMx == TIM13) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, DISABLE); + } + else if (TIMx == TIM14) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, DISABLE); + } + else if (TIMx == TIM15) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, DISABLE); + } + else if (TIMx == TIM16) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, DISABLE); + } + else + { + if (TIMx == TIM17) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, DISABLE); + } + } +} + +/** + * @brief Initializes the TIMx Time Base Unit peripheral according to + * the specified parameters in the TIM_TimeBaseInitStruct. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef + * structure that contains the configuration information for the specified TIM peripheral. + * @retval None + */ +void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) +{ + uint16_t tmpcr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode)); + assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision)); + + tmpcr1 = TIMx->CR1; + + if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM2) || (TIMx == TIM3)|| + (TIMx == TIM4) || (TIMx == TIM5)) + { + /* Select the Counter Mode */ + tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS))); + tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode; + } + + if((TIMx != TIM6) && (TIMx != TIM7)) + { + /* Set the clock division */ + tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CR1_CKD)); + tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision; + } + + TIMx->CR1 = tmpcr1; + + /* Set the Autoreload value */ + TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ; + + /* Set the Prescaler value */ + TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler; + + if ((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15)|| (TIMx == TIM16) || (TIMx == TIM17)) + { + /* Set the Repetition Counter value */ + TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter; + } + + /* Generate an update event to reload the Prescaler and the Repetition counter + values immediately */ + TIMx->EGR = TIM_PSCReloadMode_Immediate; +} + +/** + * @brief Initializes the TIMx Channel1 according to the specified + * parameters in the TIM_OCInitStruct. + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. + * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure + * that contains the configuration information for the specified TIM peripheral. + * @retval None + */ +void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST8_PERIPH(TIMx)); + assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); + assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CCER_CC1E); + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC1M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC1S)); + + /* Select the Output Compare Mode */ + tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1P)); + /* Set the Output Compare Polarity */ + tmpccer |= TIM_OCInitStruct->TIM_OCPolarity; + + /* Set the Output State */ + tmpccer |= TIM_OCInitStruct->TIM_OutputState; + + if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15)|| + (TIMx == TIM16)|| (TIMx == TIM17)) + { + assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); + assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); + + /* Reset the Output N Polarity level */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NP)); + /* Set the Output N Polarity */ + tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity; + + /* Reset the Output N State */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NE)); + /* Set the Output N State */ + tmpccer |= TIM_OCInitStruct->TIM_OutputNState; + + /* Reset the Ouput Compare and Output Compare N IDLE State */ + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1)); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1N)); + + /* Set the Output Idle state */ + tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState; + /* Set the Output N Idle state */ + tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState; + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Initializes the TIMx Channel2 according to the specified + * parameters in the TIM_OCInitStruct. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select + * the TIM peripheral. + * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure + * that contains the configuration information for the specified TIM peripheral. + * @retval None + */ +void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); + assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC2E)); + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC2M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S)); + + /* Select the Output Compare Mode */ + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); + + /* Reset the Output Polarity level */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2P)); + /* Set the Output Compare Polarity */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4); + + /* Set the Output State */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4); + + if((TIMx == TIM1) || (TIMx == TIM8)) + { + assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); + assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); + + /* Reset the Output N Polarity level */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NP)); + /* Set the Output N Polarity */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4); + + /* Reset the Output N State */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NE)); + /* Set the Output N State */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4); + + /* Reset the Ouput Compare and Output Compare N IDLE State */ + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2)); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2N)); + + /* Set the Output Idle state */ + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2); + /* Set the Output N Idle state */ + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2); + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Initializes the TIMx Channel3 according to the specified + * parameters in the TIM_OCInitStruct. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure + * that contains the configuration information for the specified TIM peripheral. + * @retval None + */ +void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); + assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC3E)); + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC3M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC3S)); + /* Select the Output Compare Mode */ + tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3P)); + /* Set the Output Compare Polarity */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8); + + /* Set the Output State */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8); + + if((TIMx == TIM1) || (TIMx == TIM8)) + { + assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); + assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); + + /* Reset the Output N Polarity level */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NP)); + /* Set the Output N Polarity */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8); + /* Reset the Output N State */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NE)); + + /* Set the Output N State */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8); + /* Reset the Ouput Compare and Output Compare N IDLE State */ + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3)); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3N)); + /* Set the Output Idle state */ + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4); + /* Set the Output N Idle state */ + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4); + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Initializes the TIMx Channel4 according to the specified + * parameters in the TIM_OCInitStruct. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure + * that contains the configuration information for the specified TIM peripheral. + * @retval None + */ +void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); + assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); + /* Disable the Channel 2: Reset the CC4E Bit */ + TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC4E)); + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC4M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC4S)); + + /* Select the Output Compare Mode */ + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); + + /* Reset the Output Polarity level */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC4P)); + /* Set the Output Compare Polarity */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12); + + /* Set the Output State */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12); + + if((TIMx == TIM1) || (TIMx == TIM8)) + { + assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); + /* Reset the Ouput Compare IDLE State */ + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS4)); + /* Set the Output Idle state */ + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6); + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Initializes the TIM peripheral according to the specified + * parameters in the TIM_ICInitStruct. + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. + * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure + * that contains the configuration information for the specified TIM peripheral. + * @retval None + */ +void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) +{ + /* Check the parameters */ + assert_param(IS_TIM_CHANNEL(TIM_ICInitStruct->TIM_Channel)); + assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity)); + assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler)); + assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter)); + + if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) + { + assert_param(IS_TIM_LIST8_PERIPH(TIMx)); + /* TI1 Configuration */ + TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2) + { + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + /* TI2 Configuration */ + TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3) + { + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + /* TI3 Configuration */ + TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else + { + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + /* TI4 Configuration */ + TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } +} + +/** + * @brief Configures the TIM peripheral according to the specified + * parameters in the TIM_ICInitStruct to measure an external PWM signal. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. + * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure + * that contains the configuration information for the specified TIM peripheral. + * @retval None + */ +void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) +{ + uint16_t icoppositepolarity = TIM_ICPolarity_Rising; + uint16_t icoppositeselection = TIM_ICSelection_DirectTI; + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + /* Select the Opposite Input Polarity */ + if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising) + { + icoppositepolarity = TIM_ICPolarity_Falling; + } + else + { + icoppositepolarity = TIM_ICPolarity_Rising; + } + /* Select the Opposite Input */ + if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI) + { + icoppositeselection = TIM_ICSelection_IndirectTI; + } + else + { + icoppositeselection = TIM_ICSelection_DirectTI; + } + if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) + { + /* TI1 Configuration */ + TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + /* TI2 Configuration */ + TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else + { + /* TI2 Configuration */ + TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + /* TI1 Configuration */ + TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } +} + +/** + * @brief Configures the: Break feature, dead time, Lock level, the OSSI, + * the OSSR State and the AOE(automatic output enable). + * @param TIMx: where x can be 1 or 8 to select the TIM + * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that + * contains the BDTR Register configuration information for the TIM peripheral. + * @retval None + */ +void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState)); + assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState)); + assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel)); + assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break)); + assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity)); + assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput)); + /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State, + the OSSI State, the dead time value and the Automatic Output Enable Bit */ + TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState | + TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime | + TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity | + TIM_BDTRInitStruct->TIM_AutomaticOutput; +} + +/** + * @brief Fills each TIM_TimeBaseInitStruct member with its default value. + * @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef + * structure which will be initialized. + * @retval None + */ +void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) +{ + /* Set the default configuration */ + TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF; + TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000; + TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1; + TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up; + TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000; +} + +/** + * @brief Fills each TIM_OCInitStruct member with its default value. + * @param TIM_OCInitStruct : pointer to a TIM_OCInitTypeDef structure which will + * be initialized. + * @retval None + */ +void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + /* Set the default configuration */ + TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing; + TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable; + TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable; + TIM_OCInitStruct->TIM_Pulse = 0x0000; + TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High; + TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High; + TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset; + TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset; +} + +/** + * @brief Fills each TIM_ICInitStruct member with its default value. + * @param TIM_ICInitStruct : pointer to a TIM_ICInitTypeDef structure which will + * be initialized. + * @retval None + */ +void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct) +{ + /* Set the default configuration */ + TIM_ICInitStruct->TIM_Channel = TIM_Channel_1; + TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising; + TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI; + TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1; + TIM_ICInitStruct->TIM_ICFilter = 0x00; +} + +/** + * @brief Fills each TIM_BDTRInitStruct member with its default value. + * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which + * will be initialized. + * @retval None + */ +void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct) +{ + /* Set the default configuration */ + TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable; + TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable; + TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF; + TIM_BDTRInitStruct->TIM_DeadTime = 0x00; + TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable; + TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low; + TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable; +} + +/** + * @brief Enables or disables the specified TIM peripheral. + * @param TIMx: where x can be 1 to 17 to select the TIMx peripheral. + * @param NewState: new state of the TIMx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the TIM Counter */ + TIMx->CR1 |= TIM_CR1_CEN; + } + else + { + /* Disable the TIM Counter */ + TIMx->CR1 &= (uint16_t)(~((uint16_t)TIM_CR1_CEN)); + } +} + +/** + * @brief Enables or disables the TIM peripheral Main Outputs. + * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIMx peripheral. + * @param NewState: new state of the TIM peripheral Main Outputs. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the TIM Main Output */ + TIMx->BDTR |= TIM_BDTR_MOE; + } + else + { + /* Disable the TIM Main Output */ + TIMx->BDTR &= (uint16_t)(~((uint16_t)TIM_BDTR_MOE)); + } +} + +/** + * @brief Enables or disables the specified TIM interrupts. + * @param TIMx: where x can be 1 to 17 to select the TIMx peripheral. + * @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg TIM_IT_Update: TIM update Interrupt source + * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source + * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source + * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source + * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source + * @arg TIM_IT_COM: TIM Commutation Interrupt source + * @arg TIM_IT_Trigger: TIM Trigger Interrupt source + * @arg TIM_IT_Break: TIM Break Interrupt source + * @note + * - TIM6 and TIM7 can only generate an update interrupt. + * - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1, + * TIM_IT_CC2 or TIM_IT_Trigger. + * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1. + * - TIM_IT_Break is used only with TIM1, TIM8 and TIM15. + * - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. + * @param NewState: new state of the TIM interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_IT(TIM_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the Interrupt sources */ + TIMx->DIER |= TIM_IT; + } + else + { + /* Disable the Interrupt sources */ + TIMx->DIER &= (uint16_t)~TIM_IT; + } +} + +/** + * @brief Configures the TIMx event to be generate by software. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param TIM_EventSource: specifies the event source. + * This parameter can be one or more of the following values: + * @arg TIM_EventSource_Update: Timer update Event source + * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source + * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source + * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source + * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source + * @arg TIM_EventSource_COM: Timer COM event source + * @arg TIM_EventSource_Trigger: Timer Trigger Event source + * @arg TIM_EventSource_Break: Timer Break event source + * @note + * - TIM6 and TIM7 can only generate an update event. + * - TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8. + * @retval None + */ +void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource)); + + /* Set the event sources */ + TIMx->EGR = TIM_EventSource; +} + +/** + * @brief Configures the TIMx’s DMA interface. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 15, 16 or 17 to select + * the TIM peripheral. + * @param TIM_DMABase: DMA Base address. + * This parameter can be one of the following values: + * @arg TIM_DMABase_CR, TIM_DMABase_CR2, TIM_DMABase_SMCR, + * TIM_DMABase_DIER, TIM1_DMABase_SR, TIM_DMABase_EGR, + * TIM_DMABase_CCMR1, TIM_DMABase_CCMR2, TIM_DMABase_CCER, + * TIM_DMABase_CNT, TIM_DMABase_PSC, TIM_DMABase_ARR, + * TIM_DMABase_RCR, TIM_DMABase_CCR1, TIM_DMABase_CCR2, + * TIM_DMABase_CCR3, TIM_DMABase_CCR4, TIM_DMABase_BDTR, + * TIM_DMABase_DCR. + * @param TIM_DMABurstLength: DMA Burst length. + * This parameter can be one value between: + * TIM_DMABurstLength_1Byte and TIM_DMABurstLength_18Bytes. + * @retval None + */ +void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_TIM_DMA_BASE(TIM_DMABase)); + assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength)); + /* Set the DMA Base and the DMA Burst Length */ + TIMx->DCR = TIM_DMABase | TIM_DMABurstLength; +} + +/** + * @brief Enables or disables the TIMx’s DMA Requests. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 15, 16 or 17 + * to select the TIM peripheral. + * @param TIM_DMASource: specifies the DMA Request sources. + * This parameter can be any combination of the following values: + * @arg TIM_DMA_Update: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_Trigger: TIM Trigger DMA source + * @param NewState: new state of the DMA Request sources. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST9_PERIPH(TIMx)); + assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the DMA sources */ + TIMx->DIER |= TIM_DMASource; + } + else + { + /* Disable the DMA sources */ + TIMx->DIER &= (uint16_t)~TIM_DMASource; + } +} + +/** + * @brief Configures the TIMx interrnal Clock + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 + * to select the TIM peripheral. + * @retval None + */ +void TIM_InternalClockConfig(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + /* Disable slave mode to clock the prescaler directly with the internal clock */ + TIMx->SMCR &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS)); +} + +/** + * @brief Configures the TIMx Internal Trigger as External Clock + * @param TIMx: where x can be 1, 2, 3, 4, 5, 9, 12 or 15 to select the TIM peripheral. + * @param TIM_ITRSource: Trigger source. + * This parameter can be one of the following values: + * @param TIM_TS_ITR0: Internal Trigger 0 + * @param TIM_TS_ITR1: Internal Trigger 1 + * @param TIM_TS_ITR2: Internal Trigger 2 + * @param TIM_TS_ITR3: Internal Trigger 3 + * @retval None + */ +void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource)); + /* Select the Internal Trigger */ + TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource); + /* Select the External clock mode1 */ + TIMx->SMCR |= TIM_SlaveMode_External1; +} + +/** + * @brief Configures the TIMx Trigger as External Clock + * @param TIMx: where x can be 1, 2, 3, 4, 5, 9, 12 or 15 to select the TIM peripheral. + * @param TIM_TIxExternalCLKSource: Trigger source. + * This parameter can be one of the following values: + * @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector + * @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1 + * @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2 + * @param TIM_ICPolarity: specifies the TIx Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @param ICFilter : specifies the filter value. + * This parameter must be a value between 0x0 and 0xF. + * @retval None + */ +void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, + uint16_t TIM_ICPolarity, uint16_t ICFilter) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_TIXCLK_SOURCE(TIM_TIxExternalCLKSource)); + assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity)); + assert_param(IS_TIM_IC_FILTER(ICFilter)); + /* Configure the Timer Input Clock Source */ + if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2) + { + TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); + } + else + { + TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); + } + /* Select the Trigger source */ + TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource); + /* Select the External clock mode1 */ + TIMx->SMCR |= TIM_SlaveMode_External1; +} + +/** + * @brief Configures the External clock Mode1 + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. + * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. + * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. + * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity: The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. + * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. + * @param ExtTRGFilter: External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter) +{ + uint16_t tmpsmcr = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); + assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); + assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); + /* Configure the ETR Clock source */ + TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + /* Reset the SMS Bits */ + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS)); + /* Select the External clock mode1 */ + tmpsmcr |= TIM_SlaveMode_External1; + /* Select the Trigger selection : ETRF */ + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS)); + tmpsmcr |= TIM_TS_ETRF; + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} + +/** + * @brief Configures the External clock Mode2 + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. + * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. + * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. + * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity: The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. + * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. + * @param ExtTRGFilter: External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); + assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); + assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); + /* Configure the ETR Clock source */ + TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + /* Enable the External clock mode2 */ + TIMx->SMCR |= TIM_SMCR_ECE; +} + +/** + * @brief Configures the TIMx External Trigger (ETR). + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. + * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. + * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. + * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity: The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. + * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. + * @param ExtTRGFilter: External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter) +{ + uint16_t tmpsmcr = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); + assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); + assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); + tmpsmcr = TIMx->SMCR; + /* Reset the ETR Bits */ + tmpsmcr &= SMCR_ETR_Mask; + /* Set the Prescaler, the Filter value and the Polarity */ + tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8))); + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} + +/** + * @brief Configures the TIMx Prescaler. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param Prescaler: specifies the Prescaler Register value + * @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode + * This parameter can be one of the following values: + * @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event. + * @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediately. + * @retval None + */ +void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode)); + /* Set the Prescaler value */ + TIMx->PSC = Prescaler; + /* Set or reset the UG Bit */ + TIMx->EGR = TIM_PSCReloadMode; +} + +/** + * @brief Specifies the TIMx Counter Mode to be used. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_CounterMode: specifies the Counter Mode to be used + * This parameter can be one of the following values: + * @arg TIM_CounterMode_Up: TIM Up Counting Mode + * @arg TIM_CounterMode_Down: TIM Down Counting Mode + * @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1 + * @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2 + * @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3 + * @retval None + */ +void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode) +{ + uint16_t tmpcr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode)); + tmpcr1 = TIMx->CR1; + /* Reset the CMS and DIR Bits */ + tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS))); + /* Set the Counter Mode */ + tmpcr1 |= TIM_CounterMode; + /* Write to TIMx CR1 register */ + TIMx->CR1 = tmpcr1; +} + +/** + * @brief Selects the Input Trigger source + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. + * @param TIM_InputTriggerSource: The Input Trigger source. + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal Trigger 0 + * @arg TIM_TS_ITR1: Internal Trigger 1 + * @arg TIM_TS_ITR2: Internal Trigger 2 + * @arg TIM_TS_ITR3: Internal Trigger 3 + * @arg TIM_TS_TI1F_ED: TI1 Edge Detector + * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 + * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 + * @arg TIM_TS_ETRF: External Trigger input + * @retval None + */ +void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) +{ + uint16_t tmpsmcr = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource)); + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + /* Reset the TS Bits */ + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS)); + /* Set the Input Trigger source */ + tmpsmcr |= TIM_InputTriggerSource; + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} + +/** + * @brief Configures the TIMx Encoder Interface. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_EncoderMode: specifies the TIMx Encoder Mode. + * This parameter can be one of the following values: + * @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level. + * @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level. + * @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending + * on the level of the other input. + * @param TIM_IC1Polarity: specifies the IC1 Polarity + * This parmeter can be one of the following values: + * @arg TIM_ICPolarity_Falling: IC Falling edge. + * @arg TIM_ICPolarity_Rising: IC Rising edge. + * @param TIM_IC2Polarity: specifies the IC2 Polarity + * This parmeter can be one of the following values: + * @arg TIM_ICPolarity_Falling: IC Falling edge. + * @arg TIM_ICPolarity_Rising: IC Rising edge. + * @retval None + */ +void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, + uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity) +{ + uint16_t tmpsmcr = 0; + uint16_t tmpccmr1 = 0; + uint16_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST5_PERIPH(TIMx)); + assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode)); + assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity)); + assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity)); + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = TIMx->CCMR1; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + + /* Set the encoder Mode */ + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS)); + tmpsmcr |= TIM_EncoderMode; + + /* Select the Capture Compare 1 and the Capture Compare 2 as input */ + tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S))); + tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0; + + /* Set the TI1 and the TI2 Polarities */ + tmpccer &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCER_CC1P)) & ((uint16_t)~((uint16_t)TIM_CCER_CC2P))); + tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4)); + + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmr1; + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Forces the TIMx output 1 waveform to active or inactive level. + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. + * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_ForcedAction_Active: Force active level on OC1REF + * @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF. + * @retval None + */ +void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST8_PERIPH(TIMx)); + assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC1M Bits */ + tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1M); + /* Configure The Forced output Mode */ + tmpccmr1 |= TIM_ForcedAction; + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Forces the TIMx output 2 waveform to active or inactive level. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. + * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_ForcedAction_Active: Force active level on OC2REF + * @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF. + * @retval None + */ +void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC2M Bits */ + tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2M); + /* Configure The Forced output Mode */ + tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8); + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Forces the TIMx output 3 waveform to active or inactive level. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_ForcedAction_Active: Force active level on OC3REF + * @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF. + * @retval None + */ +void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC1M Bits */ + tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3M); + /* Configure The Forced output Mode */ + tmpccmr2 |= TIM_ForcedAction; + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Forces the TIMx output 4 waveform to active or inactive level. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_ForcedAction_Active: Force active level on OC4REF + * @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF. + * @retval None + */ +void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC2M Bits */ + tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4M); + /* Configure The Forced output Mode */ + tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8); + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Enables or disables TIMx peripheral Preload register on ARR. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param NewState: new state of the TIMx peripheral Preload register + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Set the ARR Preload Bit */ + TIMx->CR1 |= TIM_CR1_ARPE; + } + else + { + /* Reset the ARR Preload Bit */ + TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_ARPE); + } +} + +/** + * @brief Selects the TIM peripheral Commutation event. + * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIMx peripheral + * @param NewState: new state of the Commutation event. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Set the COM Bit */ + TIMx->CR2 |= TIM_CR2_CCUS; + } + else + { + /* Reset the COM Bit */ + TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCUS); + } +} + +/** + * @brief Selects the TIMx peripheral Capture Compare DMA source. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 15, 16 or 17 to select + * the TIM peripheral. + * @param NewState: new state of the Capture Compare DMA source + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Set the CCDS Bit */ + TIMx->CR2 |= TIM_CR2_CCDS; + } + else + { + /* Reset the CCDS Bit */ + TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCDS); + } +} + +/** + * @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8 or 15 + * to select the TIMx peripheral + * @param NewState: new state of the Capture Compare Preload Control bit + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST5_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Set the CCPC Bit */ + TIMx->CR2 |= TIM_CR2_CCPC; + } + else + { + /* Reset the CCPC Bit */ + TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCPC); + } +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCR1. + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. + * @param TIM_OCPreload: new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OCPreload_Enable + * @arg TIM_OCPreload_Disable + * @retval None + */ +void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST8_PERIPH(TIMx)); + assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC1PE Bit */ + tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1PE); + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr1 |= TIM_OCPreload; + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCR2. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select + * the TIM peripheral. + * @param TIM_OCPreload: new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OCPreload_Enable + * @arg TIM_OCPreload_Disable + * @retval None + */ +void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC2PE Bit */ + tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2PE); + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8); + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCR3. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCPreload: new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OCPreload_Enable + * @arg TIM_OCPreload_Disable + * @retval None + */ +void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC3PE Bit */ + tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3PE); + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr2 |= TIM_OCPreload; + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCR4. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCPreload: new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OCPreload_Enable + * @arg TIM_OCPreload_Disable + * @retval None + */ +void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC4PE Bit */ + tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4PE); + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8); + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Configures the TIMx Output Compare 1 Fast feature. + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. + * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCFast_Enable: TIM output compare fast enable + * @arg TIM_OCFast_Disable: TIM output compare fast disable + * @retval None + */ +void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST8_PERIPH(TIMx)); + assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC1FE Bit */ + tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1FE); + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr1 |= TIM_OCFast; + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Configures the TIMx Output Compare 2 Fast feature. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select + * the TIM peripheral. + * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCFast_Enable: TIM output compare fast enable + * @arg TIM_OCFast_Disable: TIM output compare fast disable + * @retval None + */ +void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC2FE Bit */ + tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2FE); + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr1 |= (uint16_t)(TIM_OCFast << 8); + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Configures the TIMx Output Compare 3 Fast feature. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCFast_Enable: TIM output compare fast enable + * @arg TIM_OCFast_Disable: TIM output compare fast disable + * @retval None + */ +void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); + /* Get the TIMx CCMR2 register value */ + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC3FE Bit */ + tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3FE); + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr2 |= TIM_OCFast; + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Configures the TIMx Output Compare 4 Fast feature. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCFast_Enable: TIM output compare fast enable + * @arg TIM_OCFast_Disable: TIM output compare fast disable + * @retval None + */ +void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); + /* Get the TIMx CCMR2 register value */ + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC4FE Bit */ + tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4FE); + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr2 |= (uint16_t)(TIM_OCFast << 8); + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Clears or safeguards the OCREF1 signal on an external event + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCClear_Enable: TIM Output clear enable + * @arg TIM_OCClear_Disable: TIM Output clear disable + * @retval None + */ +void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); + + tmpccmr1 = TIMx->CCMR1; + + /* Reset the OC1CE Bit */ + tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1CE); + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr1 |= TIM_OCClear; + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Clears or safeguards the OCREF2 signal on an external event + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCClear_Enable: TIM Output clear enable + * @arg TIM_OCClear_Disable: TIM Output clear disable + * @retval None + */ +void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC2CE Bit */ + tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2CE); + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr1 |= (uint16_t)(TIM_OCClear << 8); + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Clears or safeguards the OCREF3 signal on an external event + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCClear_Enable: TIM Output clear enable + * @arg TIM_OCClear_Disable: TIM Output clear disable + * @retval None + */ +void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC3CE Bit */ + tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3CE); + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr2 |= TIM_OCClear; + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Clears or safeguards the OCREF4 signal on an external event + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCClear_Enable: TIM Output clear enable + * @arg TIM_OCClear_Disable: TIM Output clear disable + * @retval None + */ +void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC4CE Bit */ + tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4CE); + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr2 |= (uint16_t)(TIM_OCClear << 8); + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Configures the TIMx channel 1 polarity. + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. + * @param TIM_OCPolarity: specifies the OC1 Polarity + * This parmeter can be one of the following values: + * @arg TIM_OCPolarity_High: Output Compare active high + * @arg TIM_OCPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST8_PERIPH(TIMx)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + tmpccer = TIMx->CCER; + /* Set or Reset the CC1P Bit */ + tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1P); + tmpccer |= TIM_OCPolarity; + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx Channel 1N polarity. + * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral. + * @param TIM_OCNPolarity: specifies the OC1N Polarity + * This parmeter can be one of the following values: + * @arg TIM_OCNPolarity_High: Output Compare active high + * @arg TIM_OCNPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); + + tmpccer = TIMx->CCER; + /* Set or Reset the CC1NP Bit */ + tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1NP); + tmpccer |= TIM_OCNPolarity; + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx channel 2 polarity. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. + * @param TIM_OCPolarity: specifies the OC2 Polarity + * This parmeter can be one of the following values: + * @arg TIM_OCPolarity_High: Output Compare active high + * @arg TIM_OCPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + tmpccer = TIMx->CCER; + /* Set or Reset the CC2P Bit */ + tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 4); + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx Channel 2N polarity. + * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_OCNPolarity: specifies the OC2N Polarity + * This parmeter can be one of the following values: + * @arg TIM_OCNPolarity_High: Output Compare active high + * @arg TIM_OCNPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); + + tmpccer = TIMx->CCER; + /* Set or Reset the CC2NP Bit */ + tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2NP); + tmpccer |= (uint16_t)(TIM_OCNPolarity << 4); + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx channel 3 polarity. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCPolarity: specifies the OC3 Polarity + * This parmeter can be one of the following values: + * @arg TIM_OCPolarity_High: Output Compare active high + * @arg TIM_OCPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + tmpccer = TIMx->CCER; + /* Set or Reset the CC3P Bit */ + tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 8); + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx Channel 3N polarity. + * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_OCNPolarity: specifies the OC3N Polarity + * This parmeter can be one of the following values: + * @arg TIM_OCNPolarity_High: Output Compare active high + * @arg TIM_OCNPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); + + tmpccer = TIMx->CCER; + /* Set or Reset the CC3NP Bit */ + tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3NP); + tmpccer |= (uint16_t)(TIM_OCNPolarity << 8); + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx channel 4 polarity. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCPolarity: specifies the OC4 Polarity + * This parmeter can be one of the following values: + * @arg TIM_OCPolarity_High: Output Compare active high + * @arg TIM_OCPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + tmpccer = TIMx->CCER; + /* Set or Reset the CC4P Bit */ + tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC4P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 12); + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Enables or disables the TIM Capture Compare Channel x. + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. + * @param TIM_Channel: specifies the TIM Channel + * This parmeter can be one of the following values: + * @arg TIM_Channel_1: TIM Channel 1 + * @arg TIM_Channel_2: TIM Channel 2 + * @arg TIM_Channel_3: TIM Channel 3 + * @arg TIM_Channel_4: TIM Channel 4 + * @param TIM_CCx: specifies the TIM Channel CCxE bit new state. + * This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable. + * @retval None + */ +void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx) +{ + uint16_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST8_PERIPH(TIMx)); + assert_param(IS_TIM_CHANNEL(TIM_Channel)); + assert_param(IS_TIM_CCX(TIM_CCx)); + + tmp = CCER_CCE_Set << TIM_Channel; + + /* Reset the CCxE Bit */ + TIMx->CCER &= (uint16_t)~ tmp; + + /* Set or reset the CCxE Bit */ + TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel); +} + +/** + * @brief Enables or disables the TIM Capture Compare Channel xN. + * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral. + * @param TIM_Channel: specifies the TIM Channel + * This parmeter can be one of the following values: + * @arg TIM_Channel_1: TIM Channel 1 + * @arg TIM_Channel_2: TIM Channel 2 + * @arg TIM_Channel_3: TIM Channel 3 + * @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state. + * This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable. + * @retval None + */ +void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN) +{ + uint16_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel)); + assert_param(IS_TIM_CCXN(TIM_CCxN)); + + tmp = CCER_CCNE_Set << TIM_Channel; + + /* Reset the CCxNE Bit */ + TIMx->CCER &= (uint16_t) ~tmp; + + /* Set or reset the CCxNE Bit */ + TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel); +} + +/** + * @brief Selects the TIM Ouput Compare Mode. + * @note This function disables the selected channel before changing the Ouput + * Compare Mode. + * User has to enable this channel using TIM_CCxCmd and TIM_CCxNCmd functions. + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. + * @param TIM_Channel: specifies the TIM Channel + * This parmeter can be one of the following values: + * @arg TIM_Channel_1: TIM Channel 1 + * @arg TIM_Channel_2: TIM Channel 2 + * @arg TIM_Channel_3: TIM Channel 3 + * @arg TIM_Channel_4: TIM Channel 4 + * @param TIM_OCMode: specifies the TIM Output Compare Mode. + * This paramter can be one of the following values: + * @arg TIM_OCMode_Timing + * @arg TIM_OCMode_Active + * @arg TIM_OCMode_Toggle + * @arg TIM_OCMode_PWM1 + * @arg TIM_OCMode_PWM2 + * @arg TIM_ForcedAction_Active + * @arg TIM_ForcedAction_InActive + * @retval None + */ +void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode) +{ + uint32_t tmp = 0; + uint16_t tmp1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST8_PERIPH(TIMx)); + assert_param(IS_TIM_CHANNEL(TIM_Channel)); + assert_param(IS_TIM_OCM(TIM_OCMode)); + + tmp = (uint32_t) TIMx; + tmp += CCMR_Offset; + + tmp1 = CCER_CCE_Set << (uint16_t)TIM_Channel; + + /* Disable the Channel: Reset the CCxE Bit */ + TIMx->CCER &= (uint16_t) ~tmp1; + + if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3)) + { + tmp += (TIM_Channel>>1); + + /* Reset the OCxM bits in the CCMRx register */ + *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC1M); + + /* Configure the OCxM bits in the CCMRx register */ + *(__IO uint32_t *) tmp |= TIM_OCMode; + } + else + { + tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1; + + /* Reset the OCxM bits in the CCMRx register */ + *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC2M); + + /* Configure the OCxM bits in the CCMRx register */ + *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8); + } +} + +/** + * @brief Enables or Disables the TIMx Update event. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param NewState: new state of the TIMx UDIS bit + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Set the Update Disable Bit */ + TIMx->CR1 |= TIM_CR1_UDIS; + } + else + { + /* Reset the Update Disable Bit */ + TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_UDIS); + } +} + +/** + * @brief Configures the TIMx Update Request Interrupt source. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param TIM_UpdateSource: specifies the Update source. + * This parameter can be one of the following values: + * @arg TIM_UpdateSource_Regular: Source of update is the counter overflow/underflow + or the setting of UG bit, or an update generation + through the slave mode controller. + * @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow. + * @retval None + */ +void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource)); + if (TIM_UpdateSource != TIM_UpdateSource_Global) + { + /* Set the URS Bit */ + TIMx->CR1 |= TIM_CR1_URS; + } + else + { + /* Reset the URS Bit */ + TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_URS); + } +} + +/** + * @brief Enables or disables the TIMx’s Hall sensor interface. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param NewState: new state of the TIMx Hall sensor interface. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Set the TI1S Bit */ + TIMx->CR2 |= TIM_CR2_TI1S; + } + else + { + /* Reset the TI1S Bit */ + TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_TI1S); + } +} + +/** + * @brief Selects the TIMx’s One Pulse Mode. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param TIM_OPMode: specifies the OPM Mode to be used. + * This parameter can be one of the following values: + * @arg TIM_OPMode_Single + * @arg TIM_OPMode_Repetitive + * @retval None + */ +void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_OPM_MODE(TIM_OPMode)); + /* Reset the OPM Bit */ + TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_OPM); + /* Configure the OPM Mode */ + TIMx->CR1 |= TIM_OPMode; +} + +/** + * @brief Selects the TIMx Trigger Output Mode. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 9, 12 or 15 to select the TIM peripheral. + * @param TIM_TRGOSource: specifies the Trigger Output source. + * This paramter can be one of the following values: + * + * - For all TIMx + * @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output (TRGO). + * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output (TRGO). + * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output (TRGO). + * + * - For all TIMx except TIM6 and TIM7 + * @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag + * is to be set, as soon as a capture or compare match occurs (TRGO). + * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output (TRGO). + * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output (TRGO). + * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output (TRGO). + * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output (TRGO). + * + * @retval None + */ +void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST7_PERIPH(TIMx)); + assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource)); + /* Reset the MMS Bits */ + TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_MMS); + /* Select the TRGO source */ + TIMx->CR2 |= TIM_TRGOSource; +} + +/** + * @brief Selects the TIMx Slave Mode. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. + * @param TIM_SlaveMode: specifies the Timer Slave Mode. + * This paramter can be one of the following values: + * @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal (TRGI) re-initializes + * the counter and triggers an update of the registers. + * @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high. + * @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI. + * @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter. + * @retval None + */ +void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode)); + /* Reset the SMS Bits */ + TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_SMS); + /* Select the Slave Mode */ + TIMx->SMCR |= TIM_SlaveMode; +} + +/** + * @brief Sets or Resets the TIMx Master/Slave Mode. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. + * @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode. + * This paramter can be one of the following values: + * @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer + * and its slaves (through TRGO). + * @arg TIM_MasterSlaveMode_Disable: No action + * @retval None + */ +void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode)); + /* Reset the MSM Bit */ + TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_MSM); + + /* Set or Reset the MSM Bit */ + TIMx->SMCR |= TIM_MasterSlaveMode; +} + +/** + * @brief Sets the TIMx Counter Register value + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param Counter: specifies the Counter register new value. + * @retval None + */ +void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + /* Set the Counter Register value */ + TIMx->CNT = Counter; +} + +/** + * @brief Sets the TIMx Autoreload Register value + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param Autoreload: specifies the Autoreload register new value. + * @retval None + */ +void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + /* Set the Autoreload Register value */ + TIMx->ARR = Autoreload; +} + +/** + * @brief Sets the TIMx Capture Compare1 Register value + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. + * @param Compare1: specifies the Capture Compare1 register new value. + * @retval None + */ +void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST8_PERIPH(TIMx)); + /* Set the Capture Compare1 Register value */ + TIMx->CCR1 = Compare1; +} + +/** + * @brief Sets the TIMx Capture Compare2 Register value + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. + * @param Compare2: specifies the Capture Compare2 register new value. + * @retval None + */ +void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + /* Set the Capture Compare2 Register value */ + TIMx->CCR2 = Compare2; +} + +/** + * @brief Sets the TIMx Capture Compare3 Register value + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param Compare3: specifies the Capture Compare3 register new value. + * @retval None + */ +void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + /* Set the Capture Compare3 Register value */ + TIMx->CCR3 = Compare3; +} + +/** + * @brief Sets the TIMx Capture Compare4 Register value + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param Compare4: specifies the Capture Compare4 register new value. + * @retval None + */ +void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + /* Set the Capture Compare4 Register value */ + TIMx->CCR4 = Compare4; +} + +/** + * @brief Sets the TIMx Input Capture 1 prescaler. + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. + * @param TIM_ICPSC: specifies the Input Capture1 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST8_PERIPH(TIMx)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); + /* Reset the IC1PSC Bits */ + TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC1PSC); + /* Set the IC1PSC value */ + TIMx->CCMR1 |= TIM_ICPSC; +} + +/** + * @brief Sets the TIMx Input Capture 2 prescaler. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. + * @param TIM_ICPSC: specifies the Input Capture2 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); + /* Reset the IC2PSC Bits */ + TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC2PSC); + /* Set the IC2PSC value */ + TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8); +} + +/** + * @brief Sets the TIMx Input Capture 3 prescaler. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ICPSC: specifies the Input Capture3 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); + /* Reset the IC3PSC Bits */ + TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC3PSC); + /* Set the IC3PSC value */ + TIMx->CCMR2 |= TIM_ICPSC; +} + +/** + * @brief Sets the TIMx Input Capture 4 prescaler. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ICPSC: specifies the Input Capture4 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); + /* Reset the IC4PSC Bits */ + TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC4PSC); + /* Set the IC4PSC value */ + TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8); +} + +/** + * @brief Sets the TIMx Clock Division value. + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select + * the TIM peripheral. + * @param TIM_CKD: specifies the clock division value. + * This parameter can be one of the following value: + * @arg TIM_CKD_DIV1: TDTS = Tck_tim + * @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim + * @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim + * @retval None + */ +void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST8_PERIPH(TIMx)); + assert_param(IS_TIM_CKD_DIV(TIM_CKD)); + /* Reset the CKD Bits */ + TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_CKD); + /* Set the CKD value */ + TIMx->CR1 |= TIM_CKD; +} + +/** + * @brief Gets the TIMx Input Capture 1 value. + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. + * @retval Capture Compare 1 Register value. + */ +uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST8_PERIPH(TIMx)); + /* Get the Capture 1 Register value */ + return TIMx->CCR1; +} + +/** + * @brief Gets the TIMx Input Capture 2 value. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. + * @retval Capture Compare 2 Register value. + */ +uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + /* Get the Capture 2 Register value */ + return TIMx->CCR2; +} + +/** + * @brief Gets the TIMx Input Capture 3 value. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @retval Capture Compare 3 Register value. + */ +uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + /* Get the Capture 3 Register value */ + return TIMx->CCR3; +} + +/** + * @brief Gets the TIMx Input Capture 4 value. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @retval Capture Compare 4 Register value. + */ +uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + /* Get the Capture 4 Register value */ + return TIMx->CCR4; +} + +/** + * @brief Gets the TIMx Counter value. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @retval Counter Register value. + */ +uint16_t TIM_GetCounter(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + /* Get the Counter Register value */ + return TIMx->CNT; +} + +/** + * @brief Gets the TIMx Prescaler value. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @retval Prescaler Register value. + */ +uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + /* Get the Prescaler Register value */ + return TIMx->PSC; +} + +/** + * @brief Checks whether the specified TIM flag is set or not. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param TIM_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg TIM_FLAG_Update: TIM update Flag + * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag + * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag + * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag + * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag + * @arg TIM_FLAG_COM: TIM Commutation Flag + * @arg TIM_FLAG_Trigger: TIM Trigger Flag + * @arg TIM_FLAG_Break: TIM Break Flag + * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag + * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag + * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag + * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag + * @note + * - TIM6 and TIM7 can have only one update flag. + * - TIM9, TIM12 and TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1, + * TIM_FLAG_CC2 or TIM_FLAG_Trigger. + * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1. + * - TIM_FLAG_Break is used only with TIM1, TIM8 and TIM15. + * - TIM_FLAG_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. + * @retval The new state of TIM_FLAG (SET or RESET). + */ +FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG) +{ + ITStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_GET_FLAG(TIM_FLAG)); + + if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the TIMx's pending flags. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param TIM_FLAG: specifies the flag bit to clear. + * This parameter can be any combination of the following values: + * @arg TIM_FLAG_Update: TIM update Flag + * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag + * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag + * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag + * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag + * @arg TIM_FLAG_COM: TIM Commutation Flag + * @arg TIM_FLAG_Trigger: TIM Trigger Flag + * @arg TIM_FLAG_Break: TIM Break Flag + * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag + * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag + * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag + * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag + * @note + * - TIM6 and TIM7 can have only one update flag. + * - TIM9, TIM12 and TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1, + * TIM_FLAG_CC2 or TIM_FLAG_Trigger. + * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1. + * - TIM_FLAG_Break is used only with TIM1, TIM8 and TIM15. + * - TIM_FLAG_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. + * @retval None + */ +void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_CLEAR_FLAG(TIM_FLAG)); + + /* Clear the flags */ + TIMx->SR = (uint16_t)~TIM_FLAG; +} + +/** + * @brief Checks whether the TIM interrupt has occurred or not. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param TIM_IT: specifies the TIM interrupt source to check. + * This parameter can be one of the following values: + * @arg TIM_IT_Update: TIM update Interrupt source + * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source + * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source + * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source + * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source + * @arg TIM_IT_COM: TIM Commutation Interrupt source + * @arg TIM_IT_Trigger: TIM Trigger Interrupt source + * @arg TIM_IT_Break: TIM Break Interrupt source + * @note + * - TIM6 and TIM7 can generate only an update interrupt. + * - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1, + * TIM_IT_CC2 or TIM_IT_Trigger. + * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1. + * - TIM_IT_Break is used only with TIM1, TIM8 and TIM15. + * - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. + * @retval The new state of the TIM_IT(SET or RESET). + */ +ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT) +{ + ITStatus bitstatus = RESET; + uint16_t itstatus = 0x0, itenable = 0x0; + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_GET_IT(TIM_IT)); + + itstatus = TIMx->SR & TIM_IT; + + itenable = TIMx->DIER & TIM_IT; + if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the TIMx's interrupt pending bits. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param TIM_IT: specifies the pending bit to clear. + * This parameter can be any combination of the following values: + * @arg TIM_IT_Update: TIM1 update Interrupt source + * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source + * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source + * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source + * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source + * @arg TIM_IT_COM: TIM Commutation Interrupt source + * @arg TIM_IT_Trigger: TIM Trigger Interrupt source + * @arg TIM_IT_Break: TIM Break Interrupt source + * @note + * - TIM6 and TIM7 can generate only an update interrupt. + * - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1, + * TIM_IT_CC2 or TIM_IT_Trigger. + * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1. + * - TIM_IT_Break is used only with TIM1, TIM8 and TIM15. + * - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. + * @retval None + */ +void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_IT(TIM_IT)); + /* Clear the IT pending Bit */ + TIMx->SR = (uint16_t)~TIM_IT; +} + +/** + * @brief Configure the TI1 as Input. + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. + * @param TIM_ICPolarity : The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @param TIM_ICSelection: specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1. + * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2. + * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC. + * @param TIM_ICFilter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr1 = 0, tmpccer = 0; + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC1E); + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + /* Select the Input and set the filter */ + tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC1F))); + tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E); + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI2 as Input. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. + * @param TIM_ICPolarity : The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @param TIM_ICSelection: specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2. + * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1. + * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC. + * @param TIM_ICFilter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0; + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC2E); + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 4); + /* Select the Input and set the filter */ + tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC2S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC2F))); + tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12); + tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8); + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P)); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E); + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1 ; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI3 as Input. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ICPolarity : The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @param TIM_ICSelection: specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3. + * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4. + * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC. + * @param TIM_ICFilter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; + /* Disable the Channel 3: Reset the CC3E Bit */ + TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC3E); + tmpccmr2 = TIMx->CCMR2; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 8); + /* Select the Input and set the filter */ + tmpccmr2 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR2_CC3S)) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC3F))); + tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); + /* Select the Polarity and set the CC3E Bit */ + tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P)); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E); + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI1 as Input. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ICPolarity : The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @param TIM_ICSelection: specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4. + * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3. + * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC. + * @param TIM_ICFilter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC4E); + tmpccmr2 = TIMx->CCMR2; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 12); + /* Select the Input and set the filter */ + tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CCMR2_CC4S) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC4F))); + tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8); + tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12); + + /* Select the Polarity and set the CC4E Bit */ + tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC4P)); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E); + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32f10x/stm32f10x_usart.c b/example/libs_stm/src/stm32f10x/stm32f10x_usart.c new file mode 100644 index 0000000..fa0733e --- /dev/null +++ b/example/libs_stm/src/stm32f10x/stm32f10x_usart.c @@ -0,0 +1,1054 @@ +/** + ****************************************************************************** + * @file stm32f10x_usart.c + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file provides all the USART firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_usart.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup USART + * @brief USART driver modules + * @{ + */ + +/** @defgroup USART_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup USART_Private_Defines + * @{ + */ + +#define CR1_UE_Set ((uint16_t)0x2000) /*!< USART Enable Mask */ +#define CR1_UE_Reset ((uint16_t)0xDFFF) /*!< USART Disable Mask */ + +#define CR1_WAKE_Mask ((uint16_t)0xF7FF) /*!< USART WakeUp Method Mask */ + +#define CR1_RWU_Set ((uint16_t)0x0002) /*!< USART mute mode Enable Mask */ +#define CR1_RWU_Reset ((uint16_t)0xFFFD) /*!< USART mute mode Enable Mask */ +#define CR1_SBK_Set ((uint16_t)0x0001) /*!< USART Break Character send Mask */ +#define CR1_CLEAR_Mask ((uint16_t)0xE9F3) /*!< USART CR1 Mask */ +#define CR2_Address_Mask ((uint16_t)0xFFF0) /*!< USART address Mask */ + +#define CR2_LINEN_Set ((uint16_t)0x4000) /*!< USART LIN Enable Mask */ +#define CR2_LINEN_Reset ((uint16_t)0xBFFF) /*!< USART LIN Disable Mask */ + +#define CR2_LBDL_Mask ((uint16_t)0xFFDF) /*!< USART LIN Break detection Mask */ +#define CR2_STOP_CLEAR_Mask ((uint16_t)0xCFFF) /*!< USART CR2 STOP Bits Mask */ +#define CR2_CLOCK_CLEAR_Mask ((uint16_t)0xF0FF) /*!< USART CR2 Clock Mask */ + +#define CR3_SCEN_Set ((uint16_t)0x0020) /*!< USART SC Enable Mask */ +#define CR3_SCEN_Reset ((uint16_t)0xFFDF) /*!< USART SC Disable Mask */ + +#define CR3_NACK_Set ((uint16_t)0x0010) /*!< USART SC NACK Enable Mask */ +#define CR3_NACK_Reset ((uint16_t)0xFFEF) /*!< USART SC NACK Disable Mask */ + +#define CR3_HDSEL_Set ((uint16_t)0x0008) /*!< USART Half-Duplex Enable Mask */ +#define CR3_HDSEL_Reset ((uint16_t)0xFFF7) /*!< USART Half-Duplex Disable Mask */ + +#define CR3_IRLP_Mask ((uint16_t)0xFFFB) /*!< USART IrDA LowPower mode Mask */ +#define CR3_CLEAR_Mask ((uint16_t)0xFCFF) /*!< USART CR3 Mask */ + +#define CR3_IREN_Set ((uint16_t)0x0002) /*!< USART IrDA Enable Mask */ +#define CR3_IREN_Reset ((uint16_t)0xFFFD) /*!< USART IrDA Disable Mask */ +#define GTPR_LSB_Mask ((uint16_t)0x00FF) /*!< Guard Time Register LSB Mask */ +#define GTPR_MSB_Mask ((uint16_t)0xFF00) /*!< Guard Time Register MSB Mask */ +#define IT_Mask ((uint16_t)0x001F) /*!< USART Interrupt Mask */ + +/* USART OverSampling-8 Mask */ +#define CR1_OVER8_Set ((u16)0x8000) /* USART OVER8 mode Enable Mask */ +#define CR1_OVER8_Reset ((u16)0x7FFF) /* USART OVER8 mode Disable Mask */ + +/* USART One Bit Sampling Mask */ +#define CR3_ONEBITE_Set ((u16)0x0800) /* USART ONEBITE mode Enable Mask */ +#define CR3_ONEBITE_Reset ((u16)0xF7FF) /* USART ONEBITE mode Disable Mask */ + +/** + * @} + */ + +/** @defgroup USART_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup USART_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup USART_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup USART_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the USARTx peripheral registers to their default reset values. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5. + * @retval None + */ +void USART_DeInit(USART_TypeDef* USARTx) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + if (USARTx == USART1) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE); + } + else if (USARTx == USART2) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE); + } + else if (USARTx == USART3) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE); + } + else if (USARTx == UART4) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE); + } + else + { + if (USARTx == UART5) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE); + } + } +} + +/** + * @brief Initializes the USARTx peripheral according to the specified + * parameters in the USART_InitStruct . + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_InitStruct: pointer to a USART_InitTypeDef structure + * that contains the configuration information for the specified USART peripheral. + * @retval None + */ +void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct) +{ + uint32_t tmpreg = 0x00, apbclock = 0x00; + uint32_t integerdivider = 0x00; + uint32_t fractionaldivider = 0x00; + uint32_t usartxbase = 0; + RCC_ClocksTypeDef RCC_ClocksStatus; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate)); + assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength)); + assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits)); + assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity)); + assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode)); + assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl)); + /* The hardware flow control is available only for USART1, USART2 and USART3 */ + if (USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None) + { + assert_param(IS_USART_123_PERIPH(USARTx)); + } + + usartxbase = (uint32_t)USARTx; + +/*---------------------------- USART CR2 Configuration -----------------------*/ + tmpreg = USARTx->CR2; + /* Clear STOP[13:12] bits */ + tmpreg &= CR2_STOP_CLEAR_Mask; + /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/ + /* Set STOP[13:12] bits according to USART_StopBits value */ + tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits; + + /* Write to USART CR2 */ + USARTx->CR2 = (uint16_t)tmpreg; + +/*---------------------------- USART CR1 Configuration -----------------------*/ + tmpreg = USARTx->CR1; + /* Clear M, PCE, PS, TE and RE bits */ + tmpreg &= CR1_CLEAR_Mask; + /* Configure the USART Word Length, Parity and mode ----------------------- */ + /* Set the M bits according to USART_WordLength value */ + /* Set PCE and PS bits according to USART_Parity value */ + /* Set TE and RE bits according to USART_Mode value */ + tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity | + USART_InitStruct->USART_Mode; + /* Write to USART CR1 */ + USARTx->CR1 = (uint16_t)tmpreg; + +/*---------------------------- USART CR3 Configuration -----------------------*/ + tmpreg = USARTx->CR3; + /* Clear CTSE and RTSE bits */ + tmpreg &= CR3_CLEAR_Mask; + /* Configure the USART HFC -------------------------------------------------*/ + /* Set CTSE and RTSE bits according to USART_HardwareFlowControl value */ + tmpreg |= USART_InitStruct->USART_HardwareFlowControl; + /* Write to USART CR3 */ + USARTx->CR3 = (uint16_t)tmpreg; + +/*---------------------------- USART BRR Configuration -----------------------*/ + /* Configure the USART Baud Rate -------------------------------------------*/ + RCC_GetClocksFreq(&RCC_ClocksStatus); + if (usartxbase == USART1_BASE) + { + apbclock = RCC_ClocksStatus.PCLK2_Frequency; + } + else + { + apbclock = RCC_ClocksStatus.PCLK1_Frequency; + } + + /* Determine the integer part */ + if ((USARTx->CR1 & CR1_OVER8_Set) != 0) + { + /* Integer part computing in case Oversampling mode is 8 Samples */ + integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate))); + } + else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */ + { + /* Integer part computing in case Oversampling mode is 16 Samples */ + integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate))); + } + tmpreg = (integerdivider / 100) << 4; + + /* Determine the fractional part */ + fractionaldivider = integerdivider - (100 * (tmpreg >> 4)); + + /* Implement the fractional part in the register */ + if ((USARTx->CR1 & CR1_OVER8_Set) != 0) + { + tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07); + } + else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */ + { + tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F); + } + + /* Write to USART BRR */ + USARTx->BRR = (uint16_t)tmpreg; +} + +/** + * @brief Fills each USART_InitStruct member with its default value. + * @param USART_InitStruct: pointer to a USART_InitTypeDef structure + * which will be initialized. + * @retval None + */ +void USART_StructInit(USART_InitTypeDef* USART_InitStruct) +{ + /* USART_InitStruct members default value */ + USART_InitStruct->USART_BaudRate = 9600; + USART_InitStruct->USART_WordLength = USART_WordLength_8b; + USART_InitStruct->USART_StopBits = USART_StopBits_1; + USART_InitStruct->USART_Parity = USART_Parity_No ; + USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None; +} + +/** + * @brief Initializes the USARTx peripheral Clock according to the + * specified parameters in the USART_ClockInitStruct . + * @param USARTx: where x can be 1, 2, 3 to select the USART peripheral. + * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef + * structure that contains the configuration information for the specified + * USART peripheral. + * @note The Smart Card mode is not available for UART4 and UART5. + * @retval None + */ +void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct) +{ + uint32_t tmpreg = 0x00; + /* Check the parameters */ + assert_param(IS_USART_123_PERIPH(USARTx)); + assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock)); + assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL)); + assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA)); + assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit)); + +/*---------------------------- USART CR2 Configuration -----------------------*/ + tmpreg = USARTx->CR2; + /* Clear CLKEN, CPOL, CPHA and LBCL bits */ + tmpreg &= CR2_CLOCK_CLEAR_Mask; + /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/ + /* Set CLKEN bit according to USART_Clock value */ + /* Set CPOL bit according to USART_CPOL value */ + /* Set CPHA bit according to USART_CPHA value */ + /* Set LBCL bit according to USART_LastBit value */ + tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | + USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit; + /* Write to USART CR2 */ + USARTx->CR2 = (uint16_t)tmpreg; +} + +/** + * @brief Fills each USART_ClockInitStruct member with its default value. + * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef + * structure which will be initialized. + * @retval None + */ +void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct) +{ + /* USART_ClockInitStruct members default value */ + USART_ClockInitStruct->USART_Clock = USART_Clock_Disable; + USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low; + USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge; + USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable; +} + +/** + * @brief Enables or disables the specified USART peripheral. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param NewState: new state of the USARTx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected USART by setting the UE bit in the CR1 register */ + USARTx->CR1 |= CR1_UE_Set; + } + else + { + /* Disable the selected USART by clearing the UE bit in the CR1 register */ + USARTx->CR1 &= CR1_UE_Reset; + } +} + +/** + * @brief Enables or disables the specified USART interrupts. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_IT: specifies the USART interrupt sources to be enabled or disabled. + * This parameter can be one of the following values: + * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) + * @arg USART_IT_LBD: LIN Break detection interrupt + * @arg USART_IT_TXE: Tansmit Data Register empty interrupt + * @arg USART_IT_TC: Transmission complete interrupt + * @arg USART_IT_RXNE: Receive Data register not empty interrupt + * @arg USART_IT_IDLE: Idle line detection interrupt + * @arg USART_IT_PE: Parity Error interrupt + * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) + * @param NewState: new state of the specified USARTx interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState) +{ + uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00; + uint32_t usartxbase = 0x00; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_CONFIG_IT(USART_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + /* The CTS interrupt is not available for UART4 and UART5 */ + if (USART_IT == USART_IT_CTS) + { + assert_param(IS_USART_123_PERIPH(USARTx)); + } + + usartxbase = (uint32_t)USARTx; + + /* Get the USART register index */ + usartreg = (((uint8_t)USART_IT) >> 0x05); + + /* Get the interrupt position */ + itpos = USART_IT & IT_Mask; + itmask = (((uint32_t)0x01) << itpos); + + if (usartreg == 0x01) /* The IT is in CR1 register */ + { + usartxbase += 0x0C; + } + else if (usartreg == 0x02) /* The IT is in CR2 register */ + { + usartxbase += 0x10; + } + else /* The IT is in CR3 register */ + { + usartxbase += 0x14; + } + if (NewState != DISABLE) + { + *(__IO uint32_t*)usartxbase |= itmask; + } + else + { + *(__IO uint32_t*)usartxbase &= ~itmask; + } +} + +/** + * @brief Enables or disables the USART’s DMA interface. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3 or UART4. + * @param USART_DMAReq: specifies the DMA request. + * This parameter can be any combination of the following values: + * @arg USART_DMAReq_Tx: USART DMA transmit request + * @arg USART_DMAReq_Rx: USART DMA receive request + * @param NewState: new state of the DMA Request sources. + * This parameter can be: ENABLE or DISABLE. + * @note The DMA mode is not available for UART5. + * @retval None + */ +void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_1234_PERIPH(USARTx)); + assert_param(IS_USART_DMAREQ(USART_DMAReq)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the DMA transfer for selected requests by setting the DMAT and/or + DMAR bits in the USART CR3 register */ + USARTx->CR3 |= USART_DMAReq; + } + else + { + /* Disable the DMA transfer for selected requests by clearing the DMAT and/or + DMAR bits in the USART CR3 register */ + USARTx->CR3 &= (uint16_t)~USART_DMAReq; + } +} + +/** + * @brief Sets the address of the USART node. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_Address: Indicates the address of the USART node. + * @retval None + */ +void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_ADDRESS(USART_Address)); + + /* Clear the USART address */ + USARTx->CR2 &= CR2_Address_Mask; + /* Set the USART address node */ + USARTx->CR2 |= USART_Address; +} + +/** + * @brief Selects the USART WakeUp method. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_WakeUp: specifies the USART wakeup method. + * This parameter can be one of the following values: + * @arg USART_WakeUp_IdleLine: WakeUp by an idle line detection + * @arg USART_WakeUp_AddressMark: WakeUp by an address mark + * @retval None + */ +void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_WAKEUP(USART_WakeUp)); + + USARTx->CR1 &= CR1_WAKE_Mask; + USARTx->CR1 |= USART_WakeUp; +} + +/** + * @brief Determines if the USART is in mute mode or not. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param NewState: new state of the USART mute mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the USART mute mode by setting the RWU bit in the CR1 register */ + USARTx->CR1 |= CR1_RWU_Set; + } + else + { + /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */ + USARTx->CR1 &= CR1_RWU_Reset; + } +} + +/** + * @brief Sets the USART LIN Break detection length. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_LINBreakDetectLength: specifies the LIN break detection length. + * This parameter can be one of the following values: + * @arg USART_LINBreakDetectLength_10b: 10-bit break detection + * @arg USART_LINBreakDetectLength_11b: 11-bit break detection + * @retval None + */ +void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength)); + + USARTx->CR2 &= CR2_LBDL_Mask; + USARTx->CR2 |= USART_LINBreakDetectLength; +} + +/** + * @brief Enables or disables the USART’s LIN mode. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param NewState: new state of the USART LIN mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the LIN mode by setting the LINEN bit in the CR2 register */ + USARTx->CR2 |= CR2_LINEN_Set; + } + else + { + /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */ + USARTx->CR2 &= CR2_LINEN_Reset; + } +} + +/** + * @brief Transmits single data through the USARTx peripheral. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param Data: the data to transmit. + * @retval None + */ +void USART_SendData(USART_TypeDef* USARTx, uint16_t Data) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_DATA(Data)); + + /* Transmit Data */ + USARTx->DR = (Data & (uint16_t)0x01FF); +} + +/** + * @brief Returns the most recent received data by the USARTx peripheral. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @retval The received data. + */ +uint16_t USART_ReceiveData(USART_TypeDef* USARTx) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + /* Receive Data */ + return (uint16_t)(USARTx->DR & (uint16_t)0x01FF); +} + +/** + * @brief Transmits break characters. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @retval None + */ +void USART_SendBreak(USART_TypeDef* USARTx) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + /* Send break characters */ + USARTx->CR1 |= CR1_SBK_Set; +} + +/** + * @brief Sets the specified USART guard time. + * @param USARTx: where x can be 1, 2 or 3 to select the USART peripheral. + * @param USART_GuardTime: specifies the guard time. + * @note The guard time bits are not available for UART4 and UART5. + * @retval None + */ +void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime) +{ + /* Check the parameters */ + assert_param(IS_USART_123_PERIPH(USARTx)); + + /* Clear the USART Guard time */ + USARTx->GTPR &= GTPR_LSB_Mask; + /* Set the USART guard time */ + USARTx->GTPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08); +} + +/** + * @brief Sets the system clock prescaler. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_Prescaler: specifies the prescaler clock. + * @note The function is used for IrDA mode with UART4 and UART5. + * @retval None + */ +void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + /* Clear the USART prescaler */ + USARTx->GTPR &= GTPR_MSB_Mask; + /* Set the USART prescaler */ + USARTx->GTPR |= USART_Prescaler; +} + +/** + * @brief Enables or disables the USART’s Smart Card mode. + * @param USARTx: where x can be 1, 2 or 3 to select the USART peripheral. + * @param NewState: new state of the Smart Card mode. + * This parameter can be: ENABLE or DISABLE. + * @note The Smart Card mode is not available for UART4 and UART5. + * @retval None + */ +void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_123_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the SC mode by setting the SCEN bit in the CR3 register */ + USARTx->CR3 |= CR3_SCEN_Set; + } + else + { + /* Disable the SC mode by clearing the SCEN bit in the CR3 register */ + USARTx->CR3 &= CR3_SCEN_Reset; + } +} + +/** + * @brief Enables or disables NACK transmission. + * @param USARTx: where x can be 1, 2 or 3 to select the USART peripheral. + * @param NewState: new state of the NACK transmission. + * This parameter can be: ENABLE or DISABLE. + * @note The Smart Card mode is not available for UART4 and UART5. + * @retval None + */ +void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_123_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the NACK transmission by setting the NACK bit in the CR3 register */ + USARTx->CR3 |= CR3_NACK_Set; + } + else + { + /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */ + USARTx->CR3 &= CR3_NACK_Reset; + } +} + +/** + * @brief Enables or disables the USART’s Half Duplex communication. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param NewState: new state of the USART Communication. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ + USARTx->CR3 |= CR3_HDSEL_Set; + } + else + { + /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */ + USARTx->CR3 &= CR3_HDSEL_Reset; + } +} + + +/** + * @brief Enables or disables the USART's 8x oversampling mode. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param NewState: new state of the USART one bit sampling methode. + * This parameter can be: ENABLE or DISABLE. + * @note + * This function has to be called before calling USART_Init() + * function in order to have correct baudrate Divider value. + * @retval None + */ +void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the 8x Oversampling mode by setting the OVER8 bit in the CR1 register */ + USARTx->CR1 |= CR1_OVER8_Set; + } + else + { + /* Disable the 8x Oversampling mode by clearing the OVER8 bit in the CR1 register */ + USARTx->CR1 &= CR1_OVER8_Reset; + } +} + +/** + * @brief Enables or disables the USART's one bit sampling methode. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param NewState: new state of the USART one bit sampling methode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the one bit method by setting the ONEBITE bit in the CR3 register */ + USARTx->CR3 |= CR3_ONEBITE_Set; + } + else + { + /* Disable tthe one bit method by clearing the ONEBITE bit in the CR3 register */ + USARTx->CR3 &= CR3_ONEBITE_Reset; + } +} + +/** + * @brief Configures the USART’s IrDA interface. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_IrDAMode: specifies the IrDA mode. + * This parameter can be one of the following values: + * @arg USART_IrDAMode_LowPower + * @arg USART_IrDAMode_Normal + * @retval None + */ +void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_IRDA_MODE(USART_IrDAMode)); + + USARTx->CR3 &= CR3_IRLP_Mask; + USARTx->CR3 |= USART_IrDAMode; +} + +/** + * @brief Enables or disables the USART’s IrDA interface. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param NewState: new state of the IrDA mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the IrDA mode by setting the IREN bit in the CR3 register */ + USARTx->CR3 |= CR3_IREN_Set; + } + else + { + /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */ + USARTx->CR3 &= CR3_IREN_Reset; + } +} + +/** + * @brief Checks whether the specified USART flag is set or not. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5) + * @arg USART_FLAG_LBD: LIN Break detection flag + * @arg USART_FLAG_TXE: Transmit data register empty flag + * @arg USART_FLAG_TC: Transmission Complete flag + * @arg USART_FLAG_RXNE: Receive data register not empty flag + * @arg USART_FLAG_IDLE: Idle Line detection flag + * @arg USART_FLAG_ORE: OverRun Error flag + * @arg USART_FLAG_NE: Noise Error flag + * @arg USART_FLAG_FE: Framing Error flag + * @arg USART_FLAG_PE: Parity Error flag + * @retval The new state of USART_FLAG (SET or RESET). + */ +FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_FLAG(USART_FLAG)); + /* The CTS flag is not available for UART4 and UART5 */ + if (USART_FLAG == USART_FLAG_CTS) + { + assert_param(IS_USART_123_PERIPH(USARTx)); + } + + if ((USARTx->SR & USART_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the USARTx's pending flags. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5). + * @arg USART_FLAG_LBD: LIN Break detection flag. + * @arg USART_FLAG_TC: Transmission Complete flag. + * @arg USART_FLAG_RXNE: Receive data register not empty flag. + * + * @note + * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun + * error) and IDLE (Idle line detected) flags are cleared by software + * sequence: a read operation to USART_SR register (USART_GetFlagStatus()) + * followed by a read operation to USART_DR register (USART_ReceiveData()). + * - RXNE flag can be also cleared by a read to the USART_DR register + * (USART_ReceiveData()). + * - TC flag can be also cleared by software sequence: a read operation to + * USART_SR register (USART_GetFlagStatus()) followed by a write operation + * to USART_DR register (USART_SendData()). + * - TXE flag is cleared only by a write to the USART_DR register + * (USART_SendData()). + * @retval None + */ +void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_CLEAR_FLAG(USART_FLAG)); + /* The CTS flag is not available for UART4 and UART5 */ + if ((USART_FLAG & USART_FLAG_CTS) == USART_FLAG_CTS) + { + assert_param(IS_USART_123_PERIPH(USARTx)); + } + + USARTx->SR = (uint16_t)~USART_FLAG; +} + +/** + * @brief Checks whether the specified USART interrupt has occurred or not. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_IT: specifies the USART interrupt source to check. + * This parameter can be one of the following values: + * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) + * @arg USART_IT_LBD: LIN Break detection interrupt + * @arg USART_IT_TXE: Tansmit Data Register empty interrupt + * @arg USART_IT_TC: Transmission complete interrupt + * @arg USART_IT_RXNE: Receive Data register not empty interrupt + * @arg USART_IT_IDLE: Idle line detection interrupt + * @arg USART_IT_ORE: OverRun Error interrupt + * @arg USART_IT_NE: Noise Error interrupt + * @arg USART_IT_FE: Framing Error interrupt + * @arg USART_IT_PE: Parity Error interrupt + * @retval The new state of USART_IT (SET or RESET). + */ +ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT) +{ + uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00; + ITStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_GET_IT(USART_IT)); + /* The CTS interrupt is not available for UART4 and UART5 */ + if (USART_IT == USART_IT_CTS) + { + assert_param(IS_USART_123_PERIPH(USARTx)); + } + + /* Get the USART register index */ + usartreg = (((uint8_t)USART_IT) >> 0x05); + /* Get the interrupt position */ + itmask = USART_IT & IT_Mask; + itmask = (uint32_t)0x01 << itmask; + + if (usartreg == 0x01) /* The IT is in CR1 register */ + { + itmask &= USARTx->CR1; + } + else if (usartreg == 0x02) /* The IT is in CR2 register */ + { + itmask &= USARTx->CR2; + } + else /* The IT is in CR3 register */ + { + itmask &= USARTx->CR3; + } + + bitpos = USART_IT >> 0x08; + bitpos = (uint32_t)0x01 << bitpos; + bitpos &= USARTx->SR; + if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/** + * @brief Clears the USARTx’s interrupt pending bits. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_IT: specifies the interrupt pending bit to clear. + * This parameter can be one of the following values: + * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) + * @arg USART_IT_LBD: LIN Break detection interrupt + * @arg USART_IT_TC: Transmission complete interrupt. + * @arg USART_IT_RXNE: Receive Data register not empty interrupt. + * + * @note + * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun + * error) and IDLE (Idle line detected) pending bits are cleared by + * software sequence: a read operation to USART_SR register + * (USART_GetITStatus()) followed by a read operation to USART_DR register + * (USART_ReceiveData()). + * - RXNE pending bit can be also cleared by a read to the USART_DR register + * (USART_ReceiveData()). + * - TC pending bit can be also cleared by software sequence: a read + * operation to USART_SR register (USART_GetITStatus()) followed by a write + * operation to USART_DR register (USART_SendData()). + * - TXE pending bit is cleared only by a write to the USART_DR register + * (USART_SendData()). + * @retval None + */ +void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT) +{ + uint16_t bitpos = 0x00, itmask = 0x00; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_CLEAR_IT(USART_IT)); + /* The CTS interrupt is not available for UART4 and UART5 */ + if (USART_IT == USART_IT_CTS) + { + assert_param(IS_USART_123_PERIPH(USARTx)); + } + + bitpos = USART_IT >> 0x08; + itmask = ((uint16_t)0x01 << (uint16_t)bitpos); + USARTx->SR = (uint16_t)~itmask; +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32f10x/stm32f10x_wwdg.c b/example/libs_stm/src/stm32f10x/stm32f10x_wwdg.c new file mode 100644 index 0000000..cd4978b --- /dev/null +++ b/example/libs_stm/src/stm32f10x/stm32f10x_wwdg.c @@ -0,0 +1,223 @@ +/** + ****************************************************************************** + * @file stm32f10x_wwdg.c + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file provides all the WWDG firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_wwdg.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup WWDG + * @brief WWDG driver modules + * @{ + */ + +/** @defgroup WWDG_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup WWDG_Private_Defines + * @{ + */ + +/* ----------- WWDG registers bit address in the alias region ----------- */ +#define WWDG_OFFSET (WWDG_BASE - PERIPH_BASE) + +/* Alias word address of EWI bit */ +#define CFR_OFFSET (WWDG_OFFSET + 0x04) +#define EWI_BitNumber 0x09 +#define CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4)) + +/* --------------------- WWDG registers bit mask ------------------------ */ + +/* CR register bit mask */ +#define CR_WDGA_Set ((uint32_t)0x00000080) + +/* CFR register bit mask */ +#define CFR_WDGTB_Mask ((uint32_t)0xFFFFFE7F) +#define CFR_W_Mask ((uint32_t)0xFFFFFF80) +#define BIT_Mask ((uint8_t)0x7F) + +/** + * @} + */ + +/** @defgroup WWDG_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup WWDG_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup WWDG_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup WWDG_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the WWDG peripheral registers to their default reset values. + * @param None + * @retval None + */ +void WWDG_DeInit(void) +{ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE); +} + +/** + * @brief Sets the WWDG Prescaler. + * @param WWDG_Prescaler: specifies the WWDG Prescaler. + * This parameter can be one of the following values: + * @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1 + * @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2 + * @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4 + * @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8 + * @retval None + */ +void WWDG_SetPrescaler(uint32_t WWDG_Prescaler) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler)); + /* Clear WDGTB[1:0] bits */ + tmpreg = WWDG->CFR & CFR_WDGTB_Mask; + /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */ + tmpreg |= WWDG_Prescaler; + /* Store the new value */ + WWDG->CFR = tmpreg; +} + +/** + * @brief Sets the WWDG window value. + * @param WindowValue: specifies the window value to be compared to the downcounter. + * This parameter value must be lower than 0x80. + * @retval None + */ +void WWDG_SetWindowValue(uint8_t WindowValue) +{ + __IO uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_WWDG_WINDOW_VALUE(WindowValue)); + /* Clear W[6:0] bits */ + + tmpreg = WWDG->CFR & CFR_W_Mask; + + /* Set W[6:0] bits according to WindowValue value */ + tmpreg |= WindowValue & (uint32_t) BIT_Mask; + + /* Store the new value */ + WWDG->CFR = tmpreg; +} + +/** + * @brief Enables the WWDG Early Wakeup interrupt(EWI). + * @param None + * @retval None + */ +void WWDG_EnableIT(void) +{ + *(__IO uint32_t *) CFR_EWI_BB = (uint32_t)ENABLE; +} + +/** + * @brief Sets the WWDG counter value. + * @param Counter: specifies the watchdog counter value. + * This parameter must be a number between 0x40 and 0x7F. + * @retval None + */ +void WWDG_SetCounter(uint8_t Counter) +{ + /* Check the parameters */ + assert_param(IS_WWDG_COUNTER(Counter)); + /* Write to T[6:0] bits to configure the counter value, no need to do + a read-modify-write; writing a 0 to WDGA bit does nothing */ + WWDG->CR = Counter & BIT_Mask; +} + +/** + * @brief Enables WWDG and load the counter value. + * @param Counter: specifies the watchdog counter value. + * This parameter must be a number between 0x40 and 0x7F. + * @retval None + */ +void WWDG_Enable(uint8_t Counter) +{ + /* Check the parameters */ + assert_param(IS_WWDG_COUNTER(Counter)); + WWDG->CR = CR_WDGA_Set | Counter; +} + +/** + * @brief Checks whether the Early Wakeup interrupt flag is set or not. + * @param None + * @retval The new state of the Early Wakeup interrupt flag (SET or RESET) + */ +FlagStatus WWDG_GetFlagStatus(void) +{ + return (FlagStatus)(WWDG->SR); +} + +/** + * @brief Clears Early Wakeup interrupt flag. + * @param None + * @retval None + */ +void WWDG_ClearFlag(void) +{ + WWDG->SR = (uint32_t)RESET; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ From a7d14c7d4e76f19901bb8dbd99bfafe9a69b5490 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Tue, 8 Nov 2011 01:13:21 +0000 Subject: [PATCH 49/63] Adding original source of vl factory demo It compiles, but I've got bugs preventing me from running this yet :( --- example/32vl_factory_demo/Makefile | 53 + example/32vl_factory_demo/README | 5 + example/32vl_factory_demo/main.c | 234 ++++ example/32vl_factory_demo/stm32f10x_conf.h | 76 ++ example/32vl_factory_demo/stm32f10x_it.c | 160 +++ example/32vl_factory_demo/stm32f10x_it.h | 46 + example/32vl_factory_demo/system_stm32f10x.c | 1019 ++++++++++++++++++ 7 files changed, 1593 insertions(+) create mode 100644 example/32vl_factory_demo/Makefile create mode 100644 example/32vl_factory_demo/README create mode 100644 example/32vl_factory_demo/main.c create mode 100644 example/32vl_factory_demo/stm32f10x_conf.h create mode 100644 example/32vl_factory_demo/stm32f10x_it.c create mode 100644 example/32vl_factory_demo/stm32f10x_it.h create mode 100644 example/32vl_factory_demo/system_stm32f10x.c diff --git a/example/32vl_factory_demo/Makefile b/example/32vl_factory_demo/Makefile new file mode 100644 index 0000000..81cdd56 --- /dev/null +++ b/example/32vl_factory_demo/Makefile @@ -0,0 +1,53 @@ +# build an elf from the an3268 demonstration code +APP=32vl_factory_demo + +CC=arm-none-eabi-gcc +OBJCOPY=arm-none-eabi-objcopy + +CFLAGS=-O2 -mlittle-endian -mthumb +CFLAGS+=-mcpu=cortex-m3 -ffreestanding -nostdlib -nostdinc +ifeq ($(DEBUG),1) + CFLAGS+=-g +endif + +# to run from SRAM +CFLAGS+=-Wl,-Ttext,0x20000000 -Wl,-e,0x20000000 + +# to write to flash then run +# CFLAGS+=-Wl,-Ttext,0x08000000 -Wl,-e,0x08000000 + +PLATFORM=stm32f10x +BOARD_SUPPORT=../board_support/discovery_32vl +LIBS_STM_PATH=../libs_stm + +CFLAGS+=-I. +CFLAGS+=-I$(LIBS_STM_PATH)/inc/base +CFLAGS+=-I$(LIBS_STM_PATH)/inc/core_support +CFLAGS+=-I$(LIBS_STM_PATH)/inc/device_support +CFLAGS+=-I$(LIBS_STM_PATH)/inc/$(PLATFORM) +CFLAGS+=-I$(BOARD_SUPPORT) + +LDFLAGS+=-L$(LIBS_STM_PATH)/build -lstm32_stdperiph_f10x + + +SRCS=$(wildcard *.c) +SRCS+=$(wildcard $(BOARD_SUPPORT)/*.c) + +OBJS=$(SRCS:.c=.o) + +all: $(APP).elf + +%.bin: %.elf + $(OBJCOPY) -O binary $^ $@ + +$(APP).elf: $(OBJS) + $(CC) $(CFLAGS) -o $@ $(OBJS) $(LDFLAGS) + +%.o: %.c + $(CC) $(CFLAGS) -c -o $@ $^ + +clean: + rm -rf $(OBJS) + rm -rf $(APP).* + +.PHONY: all clean diff --git a/example/32vl_factory_demo/README b/example/32vl_factory_demo/README new file mode 100644 index 0000000..28c8395 --- /dev/null +++ b/example/32vl_factory_demo/README @@ -0,0 +1,5 @@ +This source is copied from AN3268, the STM demo code for the VL discovery board. + +It was modified to add includes and things where needed, but nothing else was touched. + +Eventually, this should be usable to restore a board to virgin state. (but not yet) diff --git a/example/32vl_factory_demo/main.c b/example/32vl_factory_demo/main.c new file mode 100644 index 0000000..0043b65 --- /dev/null +++ b/example/32vl_factory_demo/main.c @@ -0,0 +1,234 @@ +/** + ****************************************************************************** + * @file Demo/src/main.c + * @author MCD Application Team + * @version V1.0.0 + * @date 09/13/2010 + * @brief Main program body + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" +#include "stm32f10x_conf.h" +#include "STM32vldiscovery.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define LSE_FAIL_FLAG 0x80 +#define LSE_PASS_FLAG 0x100 +/* Private macro -------------------------------------------------------------*/ +/* Private consts ------------------------------------------------------------*/ + +/* Private variables ---------------------------------------------------------*/ +u32 LSE_Delay = 0; +u32 count = 0; +u32 BlinkSpeed = 0; +u32 KeyState = 0; +static __IO uint32_t TimingDelay; +/* Private function prototypes -----------------------------------------------*/ +void Delay(uint32_t nTime); +void TimingDelay_Decrement(void); + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program. + * @param None + * @retval None + */ + +int main(void) +{ + /* Enable GPIOx Clock */ + RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE); + + /* Initialise LEDs LD3&LD4, both off */ + STM32vldiscovery_LEDInit(LED3); + STM32vldiscovery_LEDInit(LED4); + + STM32vldiscovery_LEDOff(LED3); + STM32vldiscovery_LEDOff(LED4); + + /* Initialise USER Button */ + STM32vldiscovery_PBInit(BUTTON_USER, BUTTON_MODE_GPIO); + + /* Setup SysTick Timer for 1 msec interrupts */ + if (SysTick_Config(SystemCoreClock / 1000)) + { + /* Capture error */ + while (1); + } + + /* Enable access to the backup register => LSE can be enabled */ + PWR_BackupAccessCmd(ENABLE); + + /* Enable LSE (Low Speed External Oscillation) */ + RCC_LSEConfig(RCC_LSE_ON); + + /* Check the LSE Status */ + while(1) + { + if(LSE_Delay < LSE_FAIL_FLAG) + { + /* check whether LSE is ready, with 4 seconds timeout */ + Delay (500); + LSE_Delay += 0x10; + if(RCC_GetFlagStatus(RCC_FLAG_LSERDY) != RESET) + { + /* Set flag: LSE PASS */ + LSE_Delay |= LSE_PASS_FLAG; + /* Turn Off Led4 */ + STM32vldiscovery_LEDOff(LED4); + /* Disable LSE */ + RCC_LSEConfig(RCC_LSE_OFF); + break; + } + } + + /* LSE_FAIL_FLAG = 0x80 */ + else if(LSE_Delay >= LSE_FAIL_FLAG) + { + if(RCC_GetFlagStatus(RCC_FLAG_LSERDY) == RESET) + { + /* Set flag: LSE FAIL */ + LSE_Delay |= LSE_FAIL_FLAG; + /* Turn On Led4 */ + STM32vldiscovery_LEDOn(LED4); + } + /* Disable LSE */ + RCC_LSEConfig(RCC_LSE_OFF); + break; + } + } + + /* main while */ + while(1) + { + if(0 == STM32vldiscovery_PBGetState(BUTTON_USER)) + { + if(KeyState == 1) + { + if(0 == STM32vldiscovery_PBGetState(BUTTON_USER)) + { + /* USER Button released */ + KeyState = 0; + /* Turn Off LED4 */ + STM32vldiscovery_LEDOff(LED4); + } + } + } + else if(STM32vldiscovery_PBGetState(BUTTON_USER)) + { + if(KeyState == 0) + { + if(STM32vldiscovery_PBGetState(BUTTON_USER)) + { + /* USER Button released */ + KeyState = 1; + /* Turn ON LED4 */ + STM32vldiscovery_LEDOn(LED4); + Delay(1000); + /* Turn OFF LED4 */ + STM32vldiscovery_LEDOff(LED4); + /* BlinkSpeed: 0 -> 1 -> 2, then re-cycle */ + BlinkSpeed ++ ; + } + } + } + count++; + Delay(100); + /* BlinkSpeed: 0 */ + if(BlinkSpeed == 0) + { + if(4 == (count % 8)) + STM32vldiscovery_LEDOn(LED3); + if(0 == (count % 8)) + STM32vldiscovery_LEDOff(LED3); + } + /* BlinkSpeed: 1 */ + if(BlinkSpeed == 1) + { + if(2 == (count % 4)) + STM32vldiscovery_LEDOn(LED3); + if(0 == (count % 4)) + STM32vldiscovery_LEDOff(LED3); + } + /* BlinkSpeed: 2 */ + if(BlinkSpeed == 2) + { + if(0 == (count % 2)) + STM32vldiscovery_LEDOn(LED3); + else + STM32vldiscovery_LEDOff(LED3); + } + /* BlinkSpeed: 3 */ + else if(BlinkSpeed == 3) + BlinkSpeed = 0; + } +} + +/** + * @brief Inserts a delay time. + * @param nTime: specifies the delay time length, in milliseconds. + * @retval None + */ +void Delay(uint32_t nTime) +{ + TimingDelay = nTime; + + while(TimingDelay != 0); +} + +/** + * @brief Decrements the TimingDelay variable. + * @param None + * @retval None + */ +void TimingDelay_Decrement(void) +{ + if (TimingDelay != 0x00) + { + TimingDelay--; + } +} + +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/32vl_factory_demo/stm32f10x_conf.h b/example/32vl_factory_demo/stm32f10x_conf.h new file mode 100644 index 0000000..706b92e --- /dev/null +++ b/example/32vl_factory_demo/stm32f10x_conf.h @@ -0,0 +1,76 @@ +/** + ****************************************************************************** + * @file Demo/inc/stm32f10x_conf.h + * @author MCD Application Team + * @version V1.0.0 + * @date 09/13/2010 + * @brief Library configuration file. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_CONF_H +#define __STM32F10x_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +/* #include "stm32f10x_adc.h" */ +/* #include "stm32f10x_bkp.h" */ +/* #include "stm32f10x_can.h" */ +/* #include "stm32f10x_crc.h" */ +/* #include "stm32f10x_dac.h" */ +/* #include "stm32f10x_dbgmcu.h" */ +/* #include "stm32f10x_dma.h" */ +#include "stm32f10x_exti.h" +#include "stm32f10x_flash.h" +/* #include "stm32f10x_fsmc.h" */ +#include "stm32f10x_gpio.h" +/* #include "stm32f10x_i2c.h" */ +/* #include "stm32f10x_iwdg.h" */ +#include "stm32f10x_pwr.h" +#include "stm32f10x_rcc.h" +/* #include "stm32f10x_rtc.h" */ +/* #include "stm32f10x_sdio.h" */ +/* #include "stm32f10x_spi.h" */ +/* #include "stm32f10x_tim.h" */ +/* #include "stm32f10x_usart.h" */ +/* #include "stm32f10x_wwdg.h" */ +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F10x_CONF_H */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/32vl_factory_demo/stm32f10x_it.c b/example/32vl_factory_demo/stm32f10x_it.c new file mode 100644 index 0000000..c103527 --- /dev/null +++ b/example/32vl_factory_demo/stm32f10x_it.c @@ -0,0 +1,160 @@ +/** + ****************************************************************************** + * @file Demo/src/stm32f10x_it.c + * @author MCD Application Team + * @version V1.0.0 + * @date 09/13/2010 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and peripherals + * interrupt service routine. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_it.h" +void TimingDelay_Decrement(void); +/** @addtogroup Demo + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles PendSV_Handler exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ + TimingDelay_Decrement(); +} + +/******************************************************************************/ +/* STM32F10x Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f10x_xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/32vl_factory_demo/stm32f10x_it.h b/example/32vl_factory_demo/stm32f10x_it.h new file mode 100644 index 0000000..e8d2b31 --- /dev/null +++ b/example/32vl_factory_demo/stm32f10x_it.h @@ -0,0 +1,46 @@ +/** + ****************************************************************************** + * @file Demo/inc/stm32f10x_it.h + * @author MCD Team + * @version V1.0.0 + * @date 09/13/2010 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_IT_H +#define __STM32F10x_IT_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/* Exported types ------------------------------------------------------------*/ +extern vu32 TickValue; +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +#endif /* __STM32F10x_IT_H */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/32vl_factory_demo/system_stm32f10x.c b/example/32vl_factory_demo/system_stm32f10x.c new file mode 100644 index 0000000..aed930e --- /dev/null +++ b/example/32vl_factory_demo/system_stm32f10x.c @@ -0,0 +1,1019 @@ +/** + ****************************************************************************** + * @file system_stm32f10x.c + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + ****************************************************************************** + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f10x_system + * @{ + */ + +/** @addtogroup STM32F10x_System_Private_Includes + * @{ + */ + +#include "stm32f10x.h" + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Defines + * @{ + */ + +/*!< Uncomment the line corresponding to the desired System clock (SYSCLK) + frequency (after reset the HSI is used as SYSCLK source) + + IMPORTANT NOTE: + ============== + 1. After each device reset the HSI is used as System clock source. + + 2. Please make sure that the selected System clock doesn't exceed your device's + maximum frequency. + + 3. If none of the define below is enabled, the HSI is used as System clock + source. + + 4. The System clock configuration functions provided within this file assume that: + - For Low and Medium density Value line devices an external 8MHz crystal + is used to drive the System clock. + - For Low, Medium and High density devices an external 8MHz crystal is + used to drive the System clock. + - For Connectivity line devices an external 25MHz crystal is used to drive + the System clock. + If you are using different crystal you have to adapt those functions accordingly. + */ + +#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) +/* #define SYSCLK_FREQ_HSE HSE_Value */ + #define SYSCLK_FREQ_24MHz 24000000 +#else +/* #define SYSCLK_FREQ_HSE HSE_Value */ +/* #define SYSCLK_FREQ_24MHz 24000000 */ +/* #define SYSCLK_FREQ_36MHz 36000000 */ +/* #define SYSCLK_FREQ_48MHz 48000000 */ +/* #define SYSCLK_FREQ_56MHz 56000000 */ +#define SYSCLK_FREQ_72MHz 72000000 +#endif + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM3210E-EVAL board (STM32 High density and XL-density devices) as data memory */ +#if defined (STM32F10X_HD) || (defined STM32F10X_XL) +/* #define DATA_IN_ExtSRAM */ +#endif + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Variables + * @{ + */ + +/******************************************************************************* +* Clock Definitions +*******************************************************************************/ +#ifdef SYSCLK_FREQ_HSE + uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_24MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_36MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_48MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_56MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_72MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */ +#else /*!< HSI Selected as System Clock source */ + uint32_t SystemCoreClock = HSI_Value; /*!< System Clock Frequency (Core Clock) */ +#endif + +__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); + +#ifdef SYSCLK_FREQ_HSE + static void SetSysClockToHSE(void); +#elif defined SYSCLK_FREQ_24MHz + static void SetSysClockTo24(void); +#elif defined SYSCLK_FREQ_36MHz + static void SetSysClockTo36(void); +#elif defined SYSCLK_FREQ_48MHz + static void SetSysClockTo48(void); +#elif defined SYSCLK_FREQ_56MHz + static void SetSysClockTo56(void); +#elif defined SYSCLK_FREQ_72MHz + static void SetSysClockTo72(void); +#endif + +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemCoreClock variable. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +void SystemInit (void) +{ + /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ +#ifndef STM32F10X_CL + RCC->CFGR &= (uint32_t)0xF8FF0000; +#else + RCC->CFGR &= (uint32_t)0xF0FF0000; +#endif /* STM32F10X_CL */ + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ + RCC->CFGR &= (uint32_t)0xFF80FFFF; + +#ifdef STM32F10X_CL + /* Reset PLL2ON and PLL3ON bits */ + RCC->CR &= (uint32_t)0xEBFFFFFF; + + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x00FF0000; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000; +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000; +#else + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_HD) || (defined STM32F10X_XL) + #ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); + #endif /* DATA_IN_ExtSRAM */ +#endif + + /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */ + /* Configure the Flash Latency cycles and enable prefetch buffer */ + SetSysClock(); +} + +/** + * @brief Update SystemCoreClock according to Clock Register Values + * @note None + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0; + +#ifdef STM32F10X_CL + uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0; +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) + uint32_t prediv1factor = 0; +#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL */ + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock */ + SystemCoreClock = HSI_Value; + break; + case 0x04: /* HSE used as system clock */ + SystemCoreClock = HSE_Value; + break; + case 0x08: /* PLL used as system clock */ + + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; + pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + +#ifndef STM32F10X_CL + pllmull = ( pllmull >> 18) + 2; + + if (pllsource == 0x00) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_Value >> 1) * pllmull; + } + else + { + #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_Value / prediv1factor) * pllmull; + #else + /* HSE selected as PLL clock entry */ + if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET) + {/* HSE oscillator clock divided by 2 */ + SystemCoreClock = (HSE_Value >> 1) * pllmull; + } + else + { + SystemCoreClock = HSE_Value * pllmull; + } + #endif + } +#else + pllmull = pllmull >> 18; + + if (pllmull != 0x0D) + { + pllmull += 2; + } + else + { /* PLL multiplication factor = PLL input clock * 6.5 */ + pllmull = 13 / 2; + } + + if (pllsource == 0x00) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_Value >> 1) * pllmull; + } + else + {/* PREDIV1 selected as PLL clock entry */ + + /* Get PREDIV1 clock source and division factor */ + prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC; + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + + if (prediv1source == 0) + { + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_Value / prediv1factor) * pllmull; + } + else + {/* PLL2 clock selected as PREDIV1 clock entry */ + + /* Get PREDIV2 division factor and PLL2 multiplication factor */ + prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1; + pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; + SystemCoreClock = (((HSE_Value / prediv2factor) * pll2mull) / prediv1factor) * pllmull; + } + } +#endif /* STM32F10X_CL */ + break; + + default: + SystemCoreClock = HSI_Value; + break; + } + + /* Compute HCLK clock frequency ----------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +#ifdef SYSCLK_FREQ_HSE + SetSysClockToHSE(); +#elif defined SYSCLK_FREQ_24MHz + SetSysClockTo24(); +#elif defined SYSCLK_FREQ_36MHz + SetSysClockTo36(); +#elif defined SYSCLK_FREQ_48MHz + SetSysClockTo48(); +#elif defined SYSCLK_FREQ_56MHz + SetSysClockTo56(); +#elif defined SYSCLK_FREQ_72MHz + SetSysClockTo72(); +#endif + + /* If none of the define above is enabled, the HSI is used as System clock + source (default after reset) */ +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f10x.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f10x_xx.s/.c before jump to main. + * This function configures the external SRAM mounted on STM3210E-EVAL + * board (STM32 High density devices). This SRAM will be used as program + * data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is + required, then adjust the Register Addresses */ + + /* Enable FSMC clock */ + RCC->AHBENR = 0x00000114; + + /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */ + RCC->APB2ENR = 0x000001E0; + +/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/ +/*---------------- SRAM Address lines configuration -------------------------*/ +/*---------------- NOE and NWE configuration --------------------------------*/ +/*---------------- NE3 configuration ----------------------------------------*/ +/*---------------- NBL0, NBL1 configuration ---------------------------------*/ + + GPIOD->CRL = 0x44BB44BB; + GPIOD->CRH = 0xBBBBBBBB; + + GPIOE->CRL = 0xB44444BB; + GPIOE->CRH = 0xBBBBBBBB; + + GPIOF->CRL = 0x44BBBBBB; + GPIOF->CRH = 0xBBBB4444; + + GPIOG->CRL = 0x44BBBBBB; + GPIOG->CRH = 0x44444B44; + +/*---------------- FSMC Configuration ---------------------------------------*/ +/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/ + + FSMC_Bank1->BTCR[4] = 0x00001011; + FSMC_Bank1->BTCR[5] = 0x00000200; +} +#endif /* DATA_IN_ExtSRAM */ + +#ifdef SYSCLK_FREQ_HSE +/** + * @brief Selects HSE as System clock source and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockToHSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + +#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 0 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + +#ifndef STM32F10X_CL + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; +#else + if (HSE_Value <= 24000000) + { + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; + } + else + { + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + } +#endif /* STM32F10X_CL */ +#endif + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + + /* Select HSE as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE; + + /* Wait till HSE is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_24MHz +/** + * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo24(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { +#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 0 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; +#endif + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL6); + + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) + /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6); +#else + /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_36MHz +/** + * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo36(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 1 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + + /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL9); + + /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + +#else + /* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_48MHz +/** + * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo48(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 1 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL6); +#else + /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +#elif defined SYSCLK_FREQ_56MHz +/** + * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo56(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 2 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL7); +#else + /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7); + +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +#elif defined SYSCLK_FREQ_72MHz +/** + * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo72(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 2 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; + + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL9); +#else + /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | + RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ From a7c80d038f3bc0ebe3a61e76c26f4dabc25977d8 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Tue, 8 Nov 2011 01:13:50 +0000 Subject: [PATCH 50/63] Fix linking with new names --- example/32l_dac/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/example/32l_dac/Makefile b/example/32l_dac/Makefile index 4bd6eb4..87773ef 100644 --- a/example/32l_dac/Makefile +++ b/example/32l_dac/Makefile @@ -20,7 +20,7 @@ CFLAGS+=-I$(LIBS_STM_PATH)/inc/core_support CFLAGS+=-I$(LIBS_STM_PATH)/inc/device_support CFLAGS+=-I$(LIBS_STM_PATH)/inc/$(PLATFORM) -LDFLAGS+=-L$(LIBS_STM_PATH)/build -lstm32l_discovery +LDFLAGS+=-L$(LIBS_STM_PATH)/build -lstm32_stdperiph_l1xx all: $(BIN_IMAGE) From b48420e3941991b9d3f646e539499327c2417a3c Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Sat, 12 Nov 2011 18:21:46 +0000 Subject: [PATCH 51/63] Don't refetch the chip id on every single page erase. And update some of the logging to be a bit tidier --- src/stlink-common.c | 27 +++++++++++++++++++-------- 1 file changed, 19 insertions(+), 8 deletions(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index 4286cf0..f7904c0 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -135,10 +135,12 @@ static int unlock_flash_if(stlink_t *sl) { if (is_flash_locked(sl)) { unlock_flash(sl); - if (is_flash_locked(sl)) + if (is_flash_locked(sl)) { + WLOG("Failed to unlock flash!\n"); return -1; + } } - + ILOG("Successfully unlocked flash\n"); return 0; } @@ -741,10 +743,16 @@ int write_buffer_to_sram(stlink_t *sl, flash_loader_t* fl, const uint8_t* buf, s return 0; } +/** + * Erase a page of flash, assumes sl is fully populated with things like chip/core ids + * @param sl stlink context + * @param page + * @return 0 on success -ve on failure + */ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t page) { /* page an addr in the page to erase */ - ILOG("Erasing flash page at addr: %#x\n", page); + ILOG("Erasing flash page at addr: %#x\n", page); if (sl->core_id == STM32L_CORE_ID) { #define STM32L_FLASH_REGS_ADDR ((uint32_t)0x40023c00) @@ -771,7 +779,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t page) val = read_uint32(sl->q_buf, 0); if (val & (1 << 0)) { - fprintf(stderr, "pecr.pelock not clear (0x%x)\n", val); + WLOG("pecr.pelock not clear (%#x)\n", val); return -1; } @@ -786,7 +794,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t page) val = read_uint32(sl->q_buf, 0); if (val & (1 << 1)) { - fprintf(stderr, "pecr.prglock not clear (0x%x)\n", val); + WLOG("pecr.prglock not clear (%#x)\n", val); return -1; } @@ -994,11 +1002,11 @@ int stlink_fcheck_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned len) { size_t off; flash_loader_t fl; - ILOG("Attempting to write %d (%#x) bytes to stm32 address: %u (%#x)\n", + ILOG("Attempting to write %d (%#x) bytes to stm32 address: %u (%#x)\n", len, len, addr, addr); /* check addr range is inside the flash */ if (addr < sl->flash_base) { - WLOG("addr too low\n"); + WLOG("addr too low %#x < %#x\n", addr, sl->flash_base); return -1; } else if ((addr + len) < addr) { WLOG("addr overruns\n"); @@ -1014,6 +1022,8 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned return -1; } + // Make sure we've loaded the context with the chip details + stlink_core_id(sl); /* erase each page */ int page_count = 0; for (off = 0; off < len; off += sl->flash_pgsz) { @@ -1226,7 +1236,8 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons DLOG("Running flash loader, write address:%#x, size: %zd\n", target, size); // FIXME This can never return -1 if (write_buffer_to_sram(sl, fl, buf, size) == -1) { - fprintf(stderr, "write_buffer_to_sram() == -1\n"); + // IMPOSSIBLE! + WLOG("write_buffer_to_sram() == -1\n"); return -1; } From 2600d78b7cf1910d9d74f5b7057a7ddc6cd3fead Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Mon, 14 Nov 2011 02:59:38 +0000 Subject: [PATCH 52/63] Start to keep an uptodate list of what's been tested in what combinations --- README | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/README b/README index 470c52a..082a8f2 100644 --- a/README +++ b/README @@ -119,3 +119,24 @@ Q: At some point I use GDB command `next', and it hangs. A: Sometimes when you will try to use GDB `next' command to skip a loop, it will use a rather inefficient single-stepping way of doing that. Set up a breakpoint manually in that case and do `continue'. + +Currently known working combinations of programmer and target +============================================================= + +STLink v1 (as found on the 32VL Discovery board) + +Known Working Targets: +* STM32F100xx (Medium Density VL) +* STM32F103 (according to jpa- o n##stm32 + +No information: +* everything else! + + +STLink v2 (as found on the 32L and F4 Discovery boards) +Known Working Targets: +* STM32F100xx (Medium Density VL, as on the 32VL Discovery board) +* ? + +Please report any and all known working combinations so I can update this! + From 93da0169c08cb7d81ba2b530ac93482de6ec7bc1 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Mon, 14 Nov 2011 03:03:07 +0000 Subject: [PATCH 53/63] Remove confusing distclean/clean dichotomy in the top level, make clean cleans all stlink code. in an application level, it only cleans that application --- Makefile | 2 -- 1 file changed, 2 deletions(-) diff --git a/Makefile b/Makefile index d35b3c4..f24ed13 100644 --- a/Makefile +++ b/Makefile @@ -42,8 +42,6 @@ clean: rm -rf $(LIBRARY) rm -rf test_usb* rm -rf test_sg* - -distclean: clean $(MAKE) -C flash clean $(MAKE) -C gdbserver clean From 55dd45cb49e5a2c639d9f60d3a1de7b1a88b93c2 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Mon, 14 Nov 2011 03:24:12 +0000 Subject: [PATCH 54/63] Note that many of these "examples" are busted --- example/README | 6 ++++++ 1 file changed, 6 insertions(+) create mode 100644 example/README diff --git a/example/README b/example/README new file mode 100644 index 0000000..5d72e82 --- /dev/null +++ b/example/README @@ -0,0 +1,6 @@ +Don't trust many of these examples yet... A lot of them are a work in +progress... + +A good source of examples is in the libopencm3 sources: http://sourceforge.net/projects/libopencm3/ + + From a76c9ccfb34acf2fdca97db1a8e087e43a43d9b0 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Mon, 14 Nov 2011 03:47:47 +0000 Subject: [PATCH 55/63] Remove lots of dead code and superfluous trace Lots of the debug code is far too verbose for anything but usb tracing. Likewise, remove all the old scsi code that was simply ifdefd out. --- src/stlink-sg.c | 182 ++---------------------------------------------- 1 file changed, 6 insertions(+), 176 deletions(-) diff --git a/src/stlink-sg.c b/src/stlink-sg.c index c4392db..f917000 100644 --- a/src/stlink-sg.c +++ b/src/stlink-sg.c @@ -113,15 +113,13 @@ static void clear_cdb(struct stlink_libsg *sl) { sl->q_data_dir = Q_DATA_IN; } -// close the device, free the allocated memory - -void _stlink_sg_close(stlink_t *sl) { +/** + * Close and free any _backend_ related information... + * @param sl + */void _stlink_sg_close(stlink_t *sl) { if (sl) { -#if FINISHED_WITH_SG struct stlink_libsg *slsg = sl->backend_data; - scsi_pt_close_device(slsg->sg_fd); free(slsg); -#endif } } @@ -141,11 +139,11 @@ static int get_usb_mass_storage_status(libusb_device_handle *handle, uint8_t end try++; } while ((ret == LIBUSB_ERROR_PIPE) && (try < 3)); if (ret != LIBUSB_SUCCESS) { - fprintf(stderr, "%s: receiving failed: %d\n", __func__, ret); + WLOG("%s: receiving failed: %d\n", __func__, ret); return -1; } if (transferred != sizeof(csw)) { - fprintf(stderr, "%s: received unexpected amount: %d\n", __func__, transferred); + WLOG("%s: received unexpected amount: %d\n", __func__, transferred); return -1; } @@ -157,10 +155,8 @@ static int get_usb_mass_storage_status(libusb_device_handle *handle, uint8_t end WLOG("status signature was invalid: %#x\n", rsig); return -1; } - DLOG("residue was= %#x\n", residue); *tag = rtag; uint8_t rstatus = csw[12]; - DLOG("rstatus = %x\n", rstatus); return rstatus; } @@ -223,11 +219,9 @@ int send_usb_mass_storage_command(libusb_device_handle *handle, uint8_t endpoint memcpy(&(c_buf[i]), cdb, cdb_length); int sending_length = STLINK_SG_SIZE; - DLOG("sending length set to: %d\n", sending_length); // send.... do { - DLOG("attempting tx...\n"); ret = libusb_bulk_transfer(handle, endpoint_out, c_buf, sending_length, &real_transferred, SG_TIMEOUT_MSEC); if (ret == LIBUSB_ERROR_PIPE) { @@ -239,7 +233,6 @@ int send_usb_mass_storage_command(libusb_device_handle *handle, uint8_t endpoint WLOG("sending failed: %d\n", ret); return -1; } - DLOG("Actually sent: %d, returning tag: %d\n", real_transferred, tag); return this_tag; } @@ -298,93 +291,6 @@ get_sense(libusb_device_handle *handle, uint8_t endpoint_in, uint8_t endpoint_ou } } - -//TODO rewrite/cleanup, save the error in sl - -#if FINISHED_WITH_SG -static void stlink_confirm_inq(stlink_t *stl, struct sg_pt_base *ptvp) { - struct stlink_libsg *sl = stl->backend_data; - const int e = sl->do_scsi_pt_err; - if (e < 0) { - fprintf(stderr, "scsi_pt error: pass through os error: %s\n", - safe_strerror(-e)); - return; - } else if (e == SCSI_PT_DO_BAD_PARAMS) { - fprintf(stderr, "scsi_pt error: bad pass through setup\n"); - return; - } else if (e == SCSI_PT_DO_TIMEOUT) { - fprintf(stderr, " pass through timeout\n"); - return; - } - const int duration = get_scsi_pt_duration_ms(ptvp); - if ((stl->verbose > 1) && (duration >= 0)) - DLOG(" duration=%d ms\n", duration); - - // XXX stlink fw sends broken residue, so ignore it and use the known q_len - // "usb-storage quirks=483:3744:r" - // forces residue to be ignored and calculated, but this causes aboard if - // data_len = 0 and by some other data_len values. - - const int resid = get_scsi_pt_resid(ptvp); - const int dsize = stl->q_len - resid; - - const int cat = get_scsi_pt_result_category(ptvp); - char buf[512]; - unsigned int slen; - - switch (cat) { - case SCSI_PT_RESULT_GOOD: - if (stl->verbose && (resid > 0)) - DLOG(" notice: requested %d bytes but " - "got %d bytes, ignore [broken] residue = %d\n", - stl->q_len, dsize, resid); - break; - case SCSI_PT_RESULT_STATUS: - if (stl->verbose) { - sg_get_scsi_status_str( - get_scsi_pt_status_response(ptvp), sizeof (buf), - buf); - DLOG(" scsi status: %s\n", buf); - } - return; - case SCSI_PT_RESULT_SENSE: - slen = get_scsi_pt_sense_len(ptvp); - if (stl->verbose) { - sg_get_sense_str("", sl->sense_buf, slen, (stl->verbose - > 1), sizeof (buf), buf); - DLOG("%s", buf); - } - if (stl->verbose && (resid > 0)) { - if ((stl->verbose) || (stl->q_len > 0)) - DLOG(" requested %d bytes but " - "got %d bytes\n", stl->q_len, dsize); - } - return; - case SCSI_PT_RESULT_TRANSPORT_ERR: - if (stl->verbose) { - get_scsi_pt_transport_err_str(ptvp, sizeof (buf), buf); - // http://tldp.org/HOWTO/SCSI-Generic-HOWTO/x291.html - // These codes potentially come from the firmware on a host adapter - // or from one of several hosts that an adapter driver controls. - // The 'host_status' field has the following values: - // [0x07] Internal error detected in the host adapter. - // This may not be fatal (and the command may have succeeded). - DLOG(" transport: %s", buf); - } - return; - case SCSI_PT_RESULT_OS_ERR: - if (stl->verbose) { - get_scsi_pt_os_err_str(ptvp, sizeof (buf), buf); - DLOG(" os: %s", buf); - } - return; - default: - fprintf(stderr, " unknown pass through result " - "category (%d)\n", cat); - } -} -#endif - /** * Just send a buffer on an endpoint, no questions asked. * Handles repeats, and time outs. Also handles reading status reports and sense @@ -401,7 +307,6 @@ int send_usb_data_only(libusb_device_handle *handle, unsigned char endpoint_out, int real_transferred; int try; do { - DLOG("attempting tx...\n"); ret = libusb_bulk_transfer(handle, endpoint_out, cbuf, length, &real_transferred, SG_TIMEOUT_MSEC); if (ret == LIBUSB_ERROR_PIPE) { @@ -413,7 +318,6 @@ int send_usb_data_only(libusb_device_handle *handle, unsigned char endpoint_out, WLOG("sending failed: %d\n", ret); return -1; } - DLOG("Actually sent: %d\n", real_transferred); // now, swallow up the status, so that things behave nicely... uint32_t received_tag; @@ -452,7 +356,6 @@ int stlink_q(stlink_t *sl) { int ret; if (rx_length > 0) { do { - DLOG("attempting rx\n"); ret = libusb_bulk_transfer(sg->usb_handle, sg->ep_rep, sl->q_buf, rx_length, &real_transferred, SG_TIMEOUT_MSEC); if (ret == LIBUSB_ERROR_PIPE) { @@ -493,40 +396,6 @@ int stlink_q(stlink_t *sl) { return -1; } return 0; - - - DLOG("Actually received: %d\n", real_transferred); - -#if FINISHED_WITH_SG - // Get control command descriptor of scsi structure, - // (one object per command!!) - struct sg_pt_base *ptvp = construct_scsi_pt_obj(); - if (NULL == ptvp) { - fprintf(stderr, "construct_scsi_pt_obj: out of memory\n"); - return; - } - - set_scsi_pt_cdb(ptvp, sg->cdb_cmd_blk, sizeof (sg->cdb_cmd_blk)); - - // set buffer for sense (error information) data - set_scsi_pt_sense(ptvp, sg->sense_buf, sizeof (sg->sense_buf)); - - // Set a buffer to be used for data transferred from device - if (sg->q_data_dir == Q_DATA_IN) { - //clear_buf(sl); - set_scsi_pt_data_in(ptvp, sl->q_buf, sl->q_len); - } else { - set_scsi_pt_data_out(ptvp, sl->q_buf, sl->q_len); - } - // Executes SCSI command (or at least forwards it to lower layers). - sg->do_scsi_pt_err = do_scsi_pt(ptvp, sg->sg_fd, SG_TIMEOUT_SEC, - sl->verbose); - - // check for scsi errors - stlink_confirm_inq(sl, ptvp); - // TODO recycle: clear_scsi_pt_obj(struct sg_pt_base * objp); - destruct_scsi_pt_obj(ptvp); -#endif } // TODO thinking, cleanup @@ -552,14 +421,11 @@ void stlink_stat(stlink_t *stl, char *txt) { void _stlink_sg_version(stlink_t *stl) { struct stlink_libsg *sl = stl->backend_data; - DLOG("\n*** stlink_version ***\n"); clear_cdb(sl); sl->cdb_cmd_blk[0] = STLINK_GET_VERSION; stl->q_len = 6; sl->q_addr = 0; stlink_q(stl); - // HACK use my own private version right now... - } // Get stlink mode: @@ -681,7 +547,6 @@ void _stlink_sg_reset(stlink_t *sl) { void _stlink_sg_status(stlink_t *sl) { struct stlink_libsg *sg = sl->backend_data; - DLOG("\n*** stlink_status ***\n"); clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_GETSTATUS; sl->q_len = 2; @@ -693,7 +558,6 @@ void _stlink_sg_status(stlink_t *sl) { void _stlink_sg_force_debug(stlink_t *sl) { struct stlink_libsg *sg = sl->backend_data; - DLOG("\n*** stlink_force_debug ***\n"); clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_FORCEDEBUG; sl->q_len = 2; @@ -820,7 +684,6 @@ void stlink_write_dreg(stlink_t *sl, uint32_t reg, uint32_t addr) { void _stlink_sg_run(stlink_t *sl) { struct stlink_libsg *sg = sl->backend_data; - DLOG("\n*** stlink_run ***\n"); clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_RUNCORE; sl->q_len = 2; @@ -935,39 +798,6 @@ void _stlink_sg_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { stlink_print_data(sl); } -#if 0 /* not working */ - -static int write_flash_mem16 -(struct stlink* sl, uint32_t addr, uint16_t val) { - /* half word writes */ - if (addr % 2) return -1; - - /* unlock if locked */ - unlock_flash_if(sl); - - /* set flash programming chosen bit */ - set_flash_cr_pg(sl); - - write_uint16(sl->q_buf, val); - stlink_write_mem16(sl, addr, 2); - - /* wait for non business */ - wait_flash_busy(sl); - - lock_flash(sl); - - /* check the programmed value back */ - stlink_read_mem16(sl, addr, 2); - if (*(const uint16_t*) sl->q_buf != val) { - /* values differ at i * sizeof(uint16_t) */ - return -1; - } - - /* success */ - return 0; -} -#endif /* not working */ - // Exit the jtag or swd mode and enter the mass mode. void _stlink_sg_exit_debug_mode(stlink_t *stl) { From e509310406ba4db9e88ce7c0ea2aad985cb25008 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Mon, 14 Nov 2011 03:52:19 +0000 Subject: [PATCH 56/63] Start up stlinkv1 faster. Now that we're not using sg, and we've told the kernel to ignore the device in usb-mass storage, we don't need to close and wait 5 seconds. We can just immediately issue the command to switch modes. --- src/stlink-sg.c | 14 +------------- 1 file changed, 1 insertion(+), 13 deletions(-) diff --git a/src/stlink-sg.c b/src/stlink-sg.c index f917000..7f0badc 100644 --- a/src/stlink-sg.c +++ b/src/stlink-sg.c @@ -467,7 +467,7 @@ void _stlink_sg_enter_jtag_mode(stlink_t *sl) { } // XXX kernel driver performs reset, the device temporally disappears - +// Suspect this is no longer the case when we have ignore on? RECHECK void _stlink_sg_exit_dfu_mode(stlink_t *sl) { struct stlink_libsg *sg = sl->backend_data; DLOG("\n*** stlink_exit_dfu_mode ***\n"); @@ -964,18 +964,6 @@ stlink_t* stlink_v1_open_inner(const int verbose) { DLOG("Attempting to exit DFU mode\n"); _stlink_sg_exit_dfu_mode(sl); - // exit the dfu mode -> the device is gone - DLOG("\n*** reopen the stlink device ***\n"); - delay(1000); - stlink_close(sl); - delay(5000); - - DLOG("Attempting to reopen the stlink...\n"); - sl = stlink_open(verbose); - if (sl == NULL) { - fputs("Error: could not open stlink device\n", stderr); - return NULL; - } // re-query device info (and retest) stlink_version(sl); if ((sl->version.st_vid != USB_ST_VID) || (sl->version.stlink_pid != USB_STLINK_PID)) { From d019d3fc4f34297a78bf8c38c5a06053b2707862 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Mon, 14 Nov 2011 04:11:10 +0000 Subject: [PATCH 57/63] Turn down default logging level. And remove dead/duplicate code that is included in the opening of the device --- gdbserver/gdb-server.c | 15 +++------------ 1 file changed, 3 insertions(+), 12 deletions(-) diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index ce0549e..e767621 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -21,7 +21,7 @@ #include "gdb-remote.h" -#define DEFAULT_LOGGING_LEVEL 100 +#define DEFAULT_LOGGING_LEVEL 50 #define DEFAULT_GDB_LISTEN_PORT 4242 #define STRINGIFY_inner(name) #name @@ -169,17 +169,8 @@ int main(int argc, char** argv) { break; } - // ALLLL of this should move into "stlink_open_xxx" - - if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) { - if (stlink_current_mode(sl) == STLINK_DEV_DFU_MODE) { - stlink_exit_dfu_mode(sl); - } - stlink_enter_swd_mode(sl); - } - - uint32_t chip_id = stlink_chip_id(sl); - uint32_t core_id = stlink_core_id(sl); + uint32_t chip_id = sl->chip_id; + uint32_t core_id = sl->core_id; /* Fix chip_id for F4 */ if (((chip_id & 0xFFF) == 0x411) && (core_id == CORE_M4_R0)) { From dbe5391bd1354d651cda7c10be3c4b601ea4cdc9 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Mon, 14 Nov 2011 04:12:29 +0000 Subject: [PATCH 58/63] Remove dead code and unused variables --- src/stlink-common.c | 4 ++-- src/stlink-sg.c | 8 -------- src/stlink-usb.c | 31 ------------------------------- 3 files changed, 2 insertions(+), 41 deletions(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index f7904c0..a853d13 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -314,7 +314,7 @@ void stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid) { */ int stlink_load_device_params(stlink_t *sl) { ILOG("Loading device parameters....\n"); - chip_params_t *params = NULL; + const chip_params_t *params = NULL; uint32_t chip_id = stlink_chip_id(sl); sl->chip_id = chip_id; for(size_t i = 0; i < sizeof(devices) / sizeof(devices[0]); i++) { @@ -547,7 +547,7 @@ void stlink_core_stat(stlink_t *sl) { } void stlink_print_data(stlink_t * sl) { - if (sl->q_len <= 0 || sl->verbose < 2) + if (sl->q_len <= 0 || sl->verbose < UDEBUG) return; if (sl->verbose > 2) fprintf(stdout, "data_len = %d 0x%x\n", sl->q_len, sl->q_len); diff --git a/src/stlink-sg.c b/src/stlink-sg.c index 7f0badc..b6ac496 100644 --- a/src/stlink-sg.c +++ b/src/stlink-sg.c @@ -97,14 +97,6 @@ #define WLOG(format, args...) ugly_log(UWARN, LOG_TAG, format, ## args) #define fatal(format, args...) ugly_log(UFATAL, LOG_TAG, format, ## args) -// Suspends execution of the calling process for -// (at least) ms milliseconds. - -static void delay(int ms) { - //fprintf(stderr, "*** wait %d ms\n", ms); - usleep(1000 * ms); -} - static void clear_cdb(struct stlink_libsg *sl) { for (size_t i = 0; i < sizeof (sl->cdb_cmd_blk); i++) sl->cdb_cmd_blk[i] = 0; diff --git a/src/stlink-usb.c b/src/stlink-usb.c index b4df70e..58c4e1d 100644 --- a/src/stlink-usb.c +++ b/src/stlink-usb.c @@ -150,33 +150,6 @@ static inline int send_only } -/* Search for a STLINK device, either any or teh one with the given PID - * Return the protocoll version - */ -static int is_stlink_device(libusb_device * dev, uint16_t pid) { - struct libusb_device_descriptor desc; - int version; - - if (libusb_get_device_descriptor(dev, &desc)) - return 0; - - if (desc.idVendor != USB_ST_VID) - return 0; - - if ((desc.idProduct != USB_STLINK_32L_PID) && - (desc.idProduct != USB_STLINK_PID )) - return 0; - - if(pid && (pid != desc.idProduct)) - return 0; - if (desc.idProduct == USB_STLINK_PID ) - version = 1; - else - version = 2; - - return version; -} - static int fill_command (stlink_t * sl, enum SCSI_Generic_Direction dir, uint32_t len) { struct stlink_libusb * const slu = sl->backend_data; @@ -580,11 +553,7 @@ stlink_t* stlink_open_usb(const int verbose) { struct stlink_libusb* slu = NULL; int error = -1; libusb_device** devs = NULL; - libusb_device* dev; - ssize_t i; - ssize_t count; int config; - char *iSerial = NULL; sl = malloc(sizeof (stlink_t)); slu = malloc(sizeof (struct stlink_libusb)); From 9ac1f0d9d69d7f30a932fcc8977d40b12a9377f6 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Mon, 14 Nov 2011 04:12:49 +0000 Subject: [PATCH 59/63] Fix memory leaks closing v1 hardware. Thanks valgrind --- src/stlink-sg.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/stlink-sg.c b/src/stlink-sg.c index b6ac496..062e83d 100644 --- a/src/stlink-sg.c +++ b/src/stlink-sg.c @@ -111,6 +111,8 @@ static void clear_cdb(struct stlink_libsg *sl) { */void _stlink_sg_close(stlink_t *sl) { if (sl) { struct stlink_libsg *slsg = sl->backend_data; + libusb_close(slsg->usb_handle); + libusb_exit(slsg->libusb_ctx); free(slsg); } } From 09d732d776a869d1f8cbfcb62bbed4b0a9c79a4d Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Mon, 14 Nov 2011 04:14:41 +0000 Subject: [PATCH 60/63] Keep netbeans happy --- nbproject/Package-flash.bash | 75 ++ nbproject/configurations.xml | 1442 +++++++++++----------------------- nbproject/project.xml | 4 - 3 files changed, 528 insertions(+), 993 deletions(-) create mode 100644 nbproject/Package-flash.bash diff --git a/nbproject/Package-flash.bash b/nbproject/Package-flash.bash new file mode 100644 index 0000000..44fd0fc --- /dev/null +++ b/nbproject/Package-flash.bash @@ -0,0 +1,75 @@ +#!/bin/bash -x + +# +# Generated - do not edit! +# + +# Macros +TOP=`pwd` +CND_PLATFORM=GNU-Linux-x86 +CND_CONF=flash +CND_DISTDIR=dist +CND_BUILDDIR=build +NBTMPDIR=${CND_BUILDDIR}/${CND_CONF}/${CND_PLATFORM}/tmp-packaging +TMPDIRNAME=tmp-packaging +OUTPUT_PATH=MissingOutputInProject +OUTPUT_BASENAME=MissingOutputInProject +PACKAGE_TOP_DIR=stlink/ + +# Functions +function checkReturnCode +{ + rc=$? + if [ $rc != 0 ] + then + exit $rc + fi +} +function makeDirectory +# $1 directory path +# $2 permission (optional) +{ + mkdir -p "$1" + checkReturnCode + if [ "$2" != "" ] + then + chmod $2 "$1" + checkReturnCode + fi +} +function copyFileToTmpDir +# $1 from-file path +# $2 to-file path +# $3 permission +{ + cp "$1" "$2" + checkReturnCode + if [ "$3" != "" ] + then + chmod $3 "$2" + checkReturnCode + fi +} + +# Setup +cd "${TOP}" +mkdir -p ${CND_DISTDIR}/${CND_CONF}/${CND_PLATFORM}/package +rm -rf ${NBTMPDIR} +mkdir -p ${NBTMPDIR} + +# Copy files and create directories and links +cd "${TOP}" +makeDirectory "${NBTMPDIR}/stlink" +copyFileToTmpDir "${OUTPUT_PATH}" "${NBTMPDIR}/${PACKAGE_TOP_DIR}bin/${OUTPUT_BASENAME}" 0755 + + +# Generate tar file +cd "${TOP}" +rm -f ${CND_DISTDIR}/${CND_CONF}/${CND_PLATFORM}/package/stlink.tar +cd ${NBTMPDIR} +tar -vcf ../../../../${CND_DISTDIR}/${CND_CONF}/${CND_PLATFORM}/package/stlink.tar * +checkReturnCode + +# Cleanup +cd "${TOP}" +rm -rf ${NBTMPDIR} diff --git a/nbproject/configurations.xml b/nbproject/configurations.xml index e129c44..f1fcd48 100644 --- a/nbproject/configurations.xml +++ b/nbproject/configurations.xml @@ -7,21 +7,42 @@ - - main.c - - + + discover_board.h main.c startup_stm32l1xx_md.s system_stm32l1xx.c - + discover_board.h main.c stm32l_discovery_lcd.c stm32l_discovery_lcd.h - + + main.c + startup_stm32f10x_md_vl.S + stm32f10x_conf.h + stm32f10x_it.c + stm32f10x_it.h + system_stm32f10x.c + + + main.c + + + discover_board.h + main.c + startup_stm32l1xx_md.s + system_stm32l1xx.c + + + + STM32vldiscovery.c + STM32vldiscovery.h + + + @@ -33,71 +54,149 @@ core_cm3.h + stm32f10x.h stm32l1xx.h + system_stm32f10x.h system_stm32l1xx.h - misc.h - stm32l1xx_adc.h - stm32l1xx_comp.h - stm32l1xx_crc.h - stm32l1xx_dac.h - stm32l1xx_dbgmcu.h - stm32l1xx_dma.h - stm32l1xx_exti.h - stm32l1xx_flash.h - stm32l1xx_gpio.h - stm32l1xx_i2c.h - stm32l1xx_iwdg.h - stm32l1xx_lcd.h - stm32l1xx_pwr.h - stm32l1xx_rcc.h - stm32l1xx_rtc.h - stm32l1xx_spi.h - stm32l1xx_syscfg.h - stm32l1xx_tim.h - stm32l1xx_usart.h - stm32l1xx_wwdg.h + + misc.h + stm32f10x_adc.h + stm32f10x_bkp.h + stm32f10x_can.h + stm32f10x_cec.h + stm32f10x_crc.h + stm32f10x_dac.h + stm32f10x_dbgmcu.h + stm32f10x_dma.h + stm32f10x_exti.h + stm32f10x_flash.h + stm32f10x_fsmc.h + stm32f10x_gpio.h + stm32f10x_i2c.h + stm32f10x_iwdg.h + stm32f10x_pwr.h + stm32f10x_rcc.h + stm32f10x_rtc.h + stm32f10x_sdio.h + stm32f10x_spi.h + stm32f10x_tim.h + stm32f10x_usart.h + stm32f10x_wwdg.h + + + misc.h + stm32l1xx_adc.h + stm32l1xx_comp.h + stm32l1xx_crc.h + stm32l1xx_dac.h + stm32l1xx_dbgmcu.h + stm32l1xx_dma.h + stm32l1xx_exti.h + stm32l1xx_flash.h + stm32l1xx_gpio.h + stm32l1xx_i2c.h + stm32l1xx_iwdg.h + stm32l1xx_lcd.h + stm32l1xx_pwr.h + stm32l1xx_rcc.h + stm32l1xx_rtc.h + stm32l1xx_spi.h + stm32l1xx_syscfg.h + stm32l1xx_tim.h + stm32l1xx_usart.h + stm32l1xx_wwdg.h + - misc.c - stm32l1xx_adc.c - stm32l1xx_comp.c - stm32l1xx_crc.c - stm32l1xx_dac.c - stm32l1xx_dbgmcu.c - stm32l1xx_dma.c - stm32l1xx_exti.c - stm32l1xx_flash.c - stm32l1xx_flash_ramfunc.c - stm32l1xx_gpio.c - stm32l1xx_i2c.c - stm32l1xx_iwdg.c - stm32l1xx_lcd.c - stm32l1xx_pwr.c - stm32l1xx_rcc.c - stm32l1xx_rtc.c - stm32l1xx_spi.c - stm32l1xx_syscfg.c - stm32l1xx_tim.c - stm32l1xx_usart.c - stm32l1xx_wwdg.c + + misc.c + stm32f10x_adc.c + stm32f10x_bkp.c + stm32f10x_can.c + stm32f10x_cec.c + stm32f10x_crc.c + stm32f10x_dac.c + stm32f10x_dbgmcu.c + stm32f10x_dma.c + stm32f10x_exti.c + stm32f10x_flash.c + stm32f10x_fsmc.c + stm32f10x_gpio.c + stm32f10x_i2c.c + stm32f10x_iwdg.c + stm32f10x_pwr.c + stm32f10x_rcc.c + stm32f10x_rtc.c + stm32f10x_sdio.c + stm32f10x_spi.c + stm32f10x_tim.c + stm32f10x_usart.c + stm32f10x_wwdg.c + + + misc.c + stm32l1xx_adc.c + stm32l1xx_comp.c + stm32l1xx_crc.c + stm32l1xx_dac.c + stm32l1xx_dbgmcu.c + stm32l1xx_dma.c + stm32l1xx_exti.c + stm32l1xx_flash.c + stm32l1xx_flash_ramfunc.c + stm32l1xx_gpio.c + stm32l1xx_i2c.c + stm32l1xx_iwdg.c + stm32l1xx_lcd.c + stm32l1xx_pwr.c + stm32l1xx_rcc.c + stm32l1xx_rtc.c + stm32l1xx_spi.c + stm32l1xx_syscfg.c + stm32l1xx_tim.c + stm32l1xx_usart.c + stm32l1xx_wwdg.c + - - discover_board.h - discover_functions.c - discover_functions.h - icc_measure.c - icc_measure.h - icc_measure_Ram.c - main.c - stm32_tsl_conf.h - stm32l1xx_conf.h - stm32l1xx_it.c - stm32l1xx_it.h - stm32l_discovery_lcd.c - stm32l_discovery_lcd.h - system_stm32l1xx.c + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -154,18 +253,22 @@ ${MAKE} -f Makefile ${MAKE} -f Makefile clean gdbserver/st-util - - - . - - - DEBUG=1 - - + + + + + + - + - + - + - + - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + - src + . - CONFIG_USE_LIBSG=1 - CONFIG_USE_LIBUSB=1 + DEBUG=1 + + + + + + + src + + + CONFIG_USE_LIBUSB=1 + DEBUG - - - - - - - - - - - - LOCAL_SOURCES - default - - - - gdbserver - ${MAKE} -f Makefile - ${MAKE} -f Makefile clean - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - src - CONFIG_USE_LIBSG=1 CONFIG_USE_LIBUSB=1 @@ -834,8 +591,6 @@ - - @@ -857,6 +612,11 @@ + + @@ -871,307 +631,12 @@ tool="0" flavor="0"> - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - src - CONFIG_USE_LIBSG=1 CONFIG_USE_LIBUSB=1 @@ -1192,13 +657,12 @@ . - - DEBUG=1 - + + diff --git a/nbproject/project.xml b/nbproject/project.xml index 946c06f..7526e4b 100644 --- a/nbproject/project.xml +++ b/nbproject/project.xml @@ -17,10 +17,6 @@ Default 0 - - gdbserver - 0 - flash 0 From b55b75c3b98f4b80334cd8fb742e06e0ebe9b981 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Mon, 14 Nov 2011 23:01:03 +0000 Subject: [PATCH 61/63] Remove final reference to old sg/usb compilation flags --- flash/Makefile | 1 - gdbserver/Makefile | 1 - 2 files changed, 2 deletions(-) diff --git a/flash/Makefile b/flash/Makefile index dc16b62..412c366 100644 --- a/flash/Makefile +++ b/flash/Makefile @@ -1,5 +1,4 @@ CFLAGS+=-g -CFLAGS+=-DCONFIG_USE_LIBUSB=1 CFLAGS+=-DDEBUG CFLAGS+=-std=gnu99 CFLAGS+=-Wall -Wextra diff --git a/gdbserver/Makefile b/gdbserver/Makefile index c0b927e..c81ea52 100644 --- a/gdbserver/Makefile +++ b/gdbserver/Makefile @@ -2,7 +2,6 @@ PRG := st-util OBJS = gdb-remote.o gdb-server.o CFLAGS+=-g -Wall -Werror -std=gnu99 -I../src -CFLAGS+=-DCONFIG_USE_LIBUSB=1 LDFLAGS=-L.. -lstlink -lusb-1.0 all: $(PRG) From 8542b23c6e899fbb0ecc7f6de27eed8133988003 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Mon, 14 Nov 2011 23:32:50 +0000 Subject: [PATCH 62/63] Update readme, as this is about to get messy! --- README | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/README b/README index 470c52a..28caaf8 100644 --- a/README +++ b/README @@ -1,3 +1,11 @@ +IMPORTANT SHORT TERM NOTICE: +If you are targetting F1 devices, with either stlinkv1 or v2 hardware, you +_need_ to use karlp's libwork2 branch. + +If you are targetting F4, you _need_ to use texane's master + +If you are targetting F2 or L1, please let us know how it goes! + HOWTO ===== From fd332562a79737a73c8a7e7c66b4ebbe999829be Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Tue, 15 Nov 2011 19:56:14 +0000 Subject: [PATCH 63/63] Fix merge problem with flash verify for F4 The F4 code had #ifdefd out the verification, as the page/sector size can be too large to read in via a single transfer. Pull the verification out to a separate function, the flash write was getting far too large anyway. --- src/stlink-common.c | 64 +++++++++++++++++++++++++++++---------------- src/stlink-common.h | 1 + 2 files changed, 43 insertions(+), 22 deletions(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index 214f6c5..3b84cc6 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -1148,6 +1148,46 @@ int stlink_fcheck_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { return res; } +/** + * Verify addr..addr+len is binary identical to base...base+len + * @param sl stlink context + * @param address stm device address + * @param data host side buffer to check against + * @param length how much + * @return 0 for success, -ve for failure + */ +int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, unsigned length) { + size_t off; + if ((sl->chip_id & 0xFFF) == STM32_CHIPID_F4) { + DLOG("(FIXME)Skipping verification for F4, not enough ram (yet)\n"); + return 0; + } + ILOG("Starting verification of write complete\n"); + for (off = 0; off < length; off += sl->flash_pgsz) { + size_t aligned_size; + + /* adjust last page size */ + size_t cmp_size = sl->flash_pgsz; + if ((off + sl->flash_pgsz) > length) + cmp_size = length - off; + + aligned_size = cmp_size; + if (aligned_size & (4 - 1)) + aligned_size = (cmp_size + 4) & ~(4 - 1); + + fprintf(stdout, "AlignedSize:%#zx\n", aligned_size); + stlink_read_mem32(sl, address + off, aligned_size); + + if (memcmp(sl->q_buf, data + off, cmp_size)) { + WLOG("Verification of flash failed at offset: %zd\n", off); + return -1; + } + } + ILOG("Flash written and verified! jolly good!\n"); + return 0; + +} + int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned len) { size_t off; flash_loader_t fl; @@ -1370,28 +1410,8 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned WLOG("unknown coreid, not sure how to write: %x\n", sl->core_id); return -1; } - - ILOG("Starting verification of write complete\n"); - for (off = 0; off < len; off += sl->flash_pgsz) { - size_t aligned_size; - - /* adjust last page size */ - size_t cmp_size = sl->flash_pgsz; - if ((off + sl->flash_pgsz) > len) - cmp_size = len - off; - - aligned_size = cmp_size; - if (aligned_size & (4 - 1)) - aligned_size = (cmp_size + 4) & ~(4 - 1); - - fprintf(stdout, "AlignedSize:%#zx\n", aligned_size); - stlink_read_mem32(sl, addr + off, aligned_size); - - if (memcmp(sl->q_buf, base + off, cmp_size)) - return -1; - } - ILOG("Flash written and verified! jolly good!\n"); - return 0; + + return stlink_verify_write_flash(sl, addr, base, len); } /** diff --git a/src/stlink-common.h b/src/stlink-common.h index 82967d4..ae02961 100644 --- a/src/stlink-common.h +++ b/src/stlink-common.h @@ -348,6 +348,7 @@ extern "C" { int stlink_erase_flash_mass(stlink_t* sl); int stlink_write_flash(stlink_t* sl, stm32_addr_t address, uint8_t* data, unsigned length); int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr); + int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, unsigned length); // PUBLIC uint32_t stlink_chip_id(stlink_t *sl);

?iVY`v!yBdIq!d^z={zrYab>P9s%h*vTysrciDvL=r4{sqt@QJDujm)O&xVbt0(tczd0Qj(C*EnNM#k zt6rvABd?*awiEn5j&R0zGB?ZUYujdC4OLAN5RGbMK+O zsu<7~esk(5K7={i)1(E;cy~XJ3hLR>H>&@R5mezJ45j1C$(R?!7<0@}nE0;iVQG}V znXUrYN%()=Hg16mZ>0<|)r~})vW!?LK;$<`vrAi>xVip<#=cldVpzG48Lvs~=gFEs~MoLEs>uTxkwg z?@YpkSzi}|17k=6MH*gGsVSo5MGmll8jH`8L=Cs_xQc!wX%pZQL-oq0KieD2Dv z_a!u$Jbx#%pK}~G8*4buL*GfBcaNaz&kMW(2-s+bKQ(?zz1?^NE5S;MrSuyT*3 za~`wJXfnY9iX%d^`0{)%E)zCKhL9j?o4d;XIvHM2?$|n}(Mhik{x?B6#@98)m}aU4 z9i$b!@@9m`JT5?6KrMC%bHPgeC&GXA$L_9h$I&SXO{4@XTq6qdgbanHBr}#QATs)Z z04Blh@TZV(%-Q>#m9Ig$jyt1Jx5{_tuY_Pn1GWS=0(ecQHKK2zr#^sN!zityZYf-^ zhOP*$!_((^m;?pTU0Yb9LAk(kXE|F)#WD)~?jEo3QPiXWb7C)P*I*McZ);ddj_0d z8B4VWa+htWPXv-vjU2aQjX8h2c(u2FSYFPIqtJk&nwTG0IV>3cw)vD1LY(H7m}b{2l@C_ZE}V)R~5%MKPBL2GSjC?Gil77NMK}ROluUyfY<%3bq{8ISRAw}Bc%tU`=tbrCN^!%{= zKSV4hL=aR5pQdETh5d#bMpI`&c^3^zt*pbo&+L`s!)52Y@-dl{4pL~d^-uG~UU8Q>5)}27%J5Q&1b(((=rGk8&uqo!)fl=yq zG=k(+!~IYC7sP>#$W7xQss6T9viG-KqGJs$t89lo|;A z2^x(#yfR`#5tY-~93uu9<&GW5zYZu_6m1Z%&V)svv!~NtXQox6rMKQY2qOYAa|BW* zRnkO$yt>Pz@>x@Ck1)j3^}N+*r96HG2edem-5*j=GZD7|$)FU2!$f5se$h)cJc}JF zbx1uGk+fUFZ8ll4HL82gL6*P;jw?|fqB%9tJTJnv66~;r{6CR)&yABI(i4+-wJilf zPfJ5gld83-vsAX(91t-IFHB`_XLM*XATlyFHZhZsH53IhG%zzWmobR}Cx49g1yCI7 z(gliQ!6CsR*x>H&?(Xgk?(Xg+xVr||K=9xi+}$lmaJM_z`<$J9{`acxEvjHvd#~>P z1~MW=6*?hPdt;!uy`2jk6Fnn0KtxWNi4nla$U@J^$P7DF>W=2M?{~FpmaRWq++$>E2 za`XUcdpn>rJei2SgQt_FxrGZT&3``vC{3sUOk7+Xw12q+glvIMmL^7a068NU3!p71 zqlu9XK*ip~66oUjKOrc2EnHk2xEUDS-QDSpY@O-toy_^EXaVk)E`JsPWuP2Eatm^iR0|c>fM$Y4?}2k%@`Dt%H%Br=^`az|7JH2v880rFZdg zp#>P(nf^93vT?Qt`F|U^8ClvG8G{V|s@w=5E~Er70yX%b_MA76ZYez(Z* zI}C_rF*{Qcds|zeor^R4@A^b7oq#4F+C3Tmo~*T`giQxap%z-WdHbzE94lWh|&=COiFtK3x9bVPb0e|?HlIgb?)Pb+JgS`X5 z4AcbB*U}6K`UCInY~%(6xH!22eZBv!_+JFi!~`(4G;skK1I;b%;QvGiiGgN+W6E25O0nLU8(?;b$p{kIRd|EvY&e@=!9 z@V^=4?LoT?1W^82eO*R2MibC4rvJ|e@R!T~zrFt*<^OH<|8GI!t~NG*sVV=`|Np3s zY%Og(|6>4JWmgx_S;*Ogj>GQ%nrZ<5K4m$esimv!|9{m=xfp@YL&(nD<{ug@oy9FZ zfToI;E+!U#@6dmz019toX$Mraceecf*Z}B21N%QZ(7~BlgB}!T(5(Ja0YUflzbVD+ zOzcg6A09IsJHW`v$;cBPGqASM8V#2>^AV37QSSO5%C ze-JBxLHZ8@)gto;fohTcgFv;&{Xw8w{|aIE|8_sAAbb0H2#A?mL~roHjvK5-Uc-I|4LX{ ze@kp_|M>sj2nN%CAPcA{Q+pd5Bd32^fXD{^2@10Kdqe*j)Nj3`E9kKPi2@=4v=KH& zw*QI(qRH$J1o@c#3;tGG{>j1e8@l~T%Jf_CCqCP6b9>i+*9bB&{}%-HY4N9P5bqYA z4u2LvyMI}LWS0MepsuX`1wkBJ{|kbMwD}hVvHY*jKo2CtpU7+=S3A&Q{UHOC$)qe|a(ero`co8kEBU^yO-212p@?JS)?Gq)z`c5LQq#4xoq6 z{?A<5LHvN8Waq!0fqyFF`Yp5vJw^ZH&VR%NV((wvGJzU!{?i}G$r)&C`M-(io#>m;?Ux7h&{z(gZxfxt6oPhsYHBi$o?)Lw30L5_q7X*#P z?Oza7nft$13gqqaF9-_n`KKC?s~6De@7VwI+?lvKfe3Z^>kA3=7XBCi^-l*7=zjq; zfnS=pH{l7fst;+uuNA^|r`sFnn<3lNNTZ_jUUKSieME*yrmD#b+HkrRN*?a{u(~5g zc_X+?_~L!s(f||QnyA$F9}bUBRdCFG@ zyi=Mi&(W0=S+M}^-n~!4<7B- zboj8;sOKKQc2AD#@Si}so!YK1I#kwQ&*JCM^cO9zq{XaK z61{s1)x%M`L7r9*T!r+%)T`9m;@Aq6h;~n+>BbHl1BZlzL;JXHO@9x!Z!0Q<^)Y_h zt3RAqxkm^O$84!`gyctlR}RSSa#l!}5Q>KQadNqq`URQG$YFNgr%bXnmZk!B_LJ5<=bg(d@^N*iM0*cBgvespbY0%&16LYM# zy|M)#31gf2s-1P~*U@iyLo4`nyR^VbH$(*@)Q;dL_n+C5bAP8jB=VK)1}ktgqHuOC zYslu4a)=hD;ANS?uf<9UI$MSs6N>{*>yZOFFA*s zcoof1Hi9g^V1MpTEY6k`>wcjULF!ZU7HF@;JAN>pihwX>==Y5`n}CV2%m+68jkoQm z?O8+9!(!I@u*La$UdTq(&j8rQ#@gCUfngj&fh&%bV@w2t(Y$v$$=|OyJrsFandb1X z_*^FLCBc^8Bk{1Ow>0}Y$+$B8WO>R^69Ic?nSt3L>3>pHKQ-ff>xoS;|LSK#K&HFl zcov}B+PcrG!0JY%lWA}#)ml({_O<32V_@GT`Xl28e#NDn^n+Zk7GvdTteZFc26ocC z?tL!+!YS8rID?o4hwlzDDO+_~ONM?`2K#83s+$%|VnoK8CGuFmn&4S~KwnIudTD(oK< zcU!vW=D99aEf)dnvDQWihnyB_8X+x`-V#^P>dLWW&TF@-G~@?^gY>RMh0;EN-bhG5Iuv8i0T zlYf`d9naL({5=tv`al($UipBd+#cs0+7>~AZ6W5=4>(ESvG#@ zA|E1_J2|rL6Kv9$3#-B|s>R1K7kSG@QRB+p&B!#DPTio81gjyofl970$@ z1*YSChHNnL3&NytES>};={qLx<>VG7CHl2r)^s3kE8kkZCO(P#L&Krkls{Au_kT$9 zR|BCI)rDgpEOBV_&jQy=&XiFxn=y+!+QdH(LY8+ZX44;b$U;p8 zc-%vM!8Xtt*Hn){!5X}}R?4eEQdNAraSP6SfCrAyCOEt8j6bM9qigb18E_bhlm}jDJ{_n6PR` z{QwnQ+m7nR%_XD7fCOiK>(c^f)0j*^^f_gZ@k4HQe`V1F9RlY7DBT?LGRGJsbcj0^@#ILoDJS2*LGk3AyroP&K{ zLXyRExh&xDp7fVGc^)m>Yc5Peu2tpPhz>#%^g67CDvQja}Gk8AHqS^ zU=sJ3_%(Z&x&bhMwT=JW=%Ma;)3}T>l})Ti;^l{(TH@e#*^QKq9~Pf}yVze!? zNs3|DtR+$DE>$Zjj;Gh{wnGV zIM3!*vFU4N&(kS*Le+=o4eItN-hnUq$vgdMA!y~0&Rt))cpD{RkwnA{L)Cv4SZsC- z_mN>JC60?1+beeTZBL;D`;(T(br4Unu(aPPaxHM3Xn%I*3V#QuFx;skKss?+)_CBS zPbxkca-O*vOll$&gfLQQ$IuE8HVi z_>zk@GN#c>EsmkQMH}rDS#Klu~i@k$->AvlzF_My$j6 zsYNlnV$}0ZwfBNT)5(8!Bb~v{z%Ch5S~edO0hTgF5P!b@An(Uy27FbcJifP#c;m*( zxxRI#@p_Nlkss!%p=?c|9_)%yky<`@OTYJX1ghKine4`D>wW=i;x$tmsXv;Nt9IlndGv(4xLb_&F^i{5Pe$wG8;G#AL)ntQohlcjSqTx zmbwKKZW+`IdsUBw=Z0M~3%Jd;!$LzGUA5mVg!gKK8x<09;>;DLR{N;{8c8lVWblg zWOlFU!5SbLnupUsZuOH!A3ra}k$o+)KK{nUg_ z{+_GcfuET}x=r}ys?nJN@>kS1bIR*74-6$*WEXy&>TS-kL<#5q=0I*jWl}CZc69QH zM}J$-YAVY{oG7>9pH@A$8l};)eagc6_{zdYHl4>FUk&mWw6eMD+2l%Upf>h@t)QPp z!Jx&oRlRS-^)G#5uqq1O>|e?!@?AGf`gJTyu7MXYRK7c}q}f6WExA#0@P5=qs;H_R z&VOi*en|`OLU7RzqrxfWgTeKQ-D+SDEPv8>h36d?A^CT7vPgC*(WwIO4AwFA4MJDU z(Gwc|axe#Cc|IEw)J~q3$_R(ApR)t|zICq>*2Fi%^CunJbSgQ-hkdLl@SmaT3j3D* z&{%xQ@REb|v-RMa#CJ_~yF1$iTrd~e+ z;4p*=^B4k4g>;JC@<>Rs4dum5BPlFFD{xq8kHOYKo=t`WT;l~8k#BSkCu5 zeGmWg>FmSKKSpuxYSKpkPPJ1WZsxl01d? z?Ol7qFDRg!9T+ECV77P=p6-r%T{%ntl~I)tk*8<-4)?_j4SJ3VQK85AyObc~3Axw# z$SnplUzUxO%;O(l26u=h%70Q&stzd3mvlrE|6J` z4H8LyKZ{n7e1jbxiy<_4_!iA`7+ybq=^wu>-Rzc+Tpy^nN&-*11XKQgg+jzaAdoGc zH$(;d1;6d|M{W0oU}6<^He7~LWkUcRdb*ImNmSTR8+#4#206;hSbu0Iu%;4{6~l!| zJ1uXk6+;#u8wfZ2YQt6vDVw|(|IIq0y@u!fn;FHPkrVHv0%)8vqpof8vX)e}8qHgvR8rbUobcqm$r{*t+QR3eE}5 zl+@NGi&Z;yTkHZOK$`U0(Z}BWA^h2sEI?j$yZIXnA9l6o@uon#ExL5VJto}@OUNC* z<<5en;A&i;*+lS*b+a=4apuj78%4mNEj=p5n95F%Xxr$LjeqAeAvQ-MW&xts&AiCh zs(#y_jr!keBwX1HBr;*{8<&{AJiT{e_%w^~y7_r@`y76gHL{MW$}Ym-NtEB$0h(st ztlXT-f)xL;v>#kg@J#N(a8ZA{MMCD5hphs-$bIm*4Qf})$?;66l*LRaXhRFd(zP<6 zXKlClvSaG(WPch}%jv^Ue9@a*?%2=ErUWp`#gJ=&L?IUx#ACYhI9hb7?N+1mqTyDH z?FlZO*%H?`Sd{~8E|~0q> zVUPRA?sq3f1h|O#Ui+4pvPL0TsJ>PswFkq3PlZu?zWx3l@AuC%zP*D<-?IyMj!9#* zqek{du79x+&@S`3icTIujplDY;5;RCpp%^`IymeOq^?j zc-~YxZ!enWqvu+4dF3R;BXv8(kooN!tAHl6UVl#$nCd@mnRyur7xOdCnYH#hUkyBh`J_wiK(SmR5*~kmbD0KVDS#$oms6Q z;eV4)F9{t=BhpmtM|8Hd!J;ms^4+A!=kJlSyVa|FRMkR>Bw4|(mQ8(Q9WVKHAdm?* zL2-L>*Zbfvj%BJYAv;e?bAaiLQ7Q3Sw5iX~T;|x&3pIQTZt+5yUgtj$#}eKUK6tT-J|Zo$Co?(*+fYEkB|sF z>2O^>N6G+E-M%0sN!MBSH>LiU$ux>=C6*y$9uJb{7($jSLX}bOaw}t$(-pF27k}w^ z7zX~4e1*4PS@=%s>w!Hu9(uJc(Cz$G+h@7mjd}q#*$;kmb#Rj9lM?+>=IDrJ{4RPKf^kZe?x##(d=GhtmCbuYO~nXn1>GRU^QzI z7j3eLU7=t6stQ4+ukvn+jv&;|-GBFm79m1gzF7=oQUv_E<_@~^ zi;LiVAM~tNob~8VRef%b7WD(eah7}2)QY6IrDhc)!UD!|5TQ7$-PsE-Mb8suBpCp*`mf)-WG9bi^IXWL%VBgAqRJAbZ%z}&}& z6F;x>)wF3b@mV@ccl9eKL4OtAC8o*AGIqf8!+Rg-A1>dmn5G6Yg$|rvqcEzwrmA0Y zMy1_)Xk`d}z~L?%LMM{d*W=={;M1Nnl|mYHR@Zsex;44+pn{fH1Wagd$u{fYPUYKH zg;m(N!tR5+zk+`*&mr!e@5}mXeyIAheQj6YxJ;uT7J7xUo|+W!$$uTX^8SztBkEJ) zPN+V*JdsmXua;LaZ*dqomQyN^kg1dit|3E2pf5a~6#$&wOZSJ(<@?c>s4N-QkJMv< zGITf#YZ}EWdy3Ix)k5VG6v2I%eXEaHUni$W#m<-)CnXg*y0K~qPPKM5hUx0Xhf&4k z;urKXhJ+)xb4gLb^nWgx$#|7o_P71^AuaT`2zGvsp49pm4w5VndYgW6aGwgn2eW*% zJR-D*<#I|KQ}ed-`r*s2qIbooXs~mN85r593TRhSbxK+(deKl|FQ+#h z*sA&{NOZ7}dMKp-u^Q_@2BCUYq=|>jWp#8uw2k52z6wpVMt?VwPBU6Q0O=UfdR$VN z#CV1gp3qO?0YQu>rkr3X9ZEiRTD%>j>w4GJ{{F$DUv$wET%<{oMagb^4}LUYmv$7{ zLI+cX90~4Qe=eA1uFvc174T<+%SLb{2`gPRNp-{)K~2PV`MmIFgI`(FZHa**hxjR< zNbw}C&I-KEmJJ&exw{-G3GvX`QAuCxqu_@SlXgc5z-4lv*p%rz%TpJ5!$3GAF$aS#WruU z@9sP9kwt7_>4T-r&j;x!!fFvA4k118d%Jkg7bB7+i1g&K+gfBq7|{6o%exD|@ZK}o zD062Elz$8w(e9O2_hO`G+0eC+dWnayBG9~7)8=#B`WX!0T{I+CX5?A+$@je%Pf5J~ zc6R4hHT&xMU|jCqV3z>CfrRAg?a`VGEJ}5VdI$_G+4b^E(uH5iPfdh?4!1m8u0cOP z8`SSc+xxTi{JFFj&wVoMjceiR+(&$e@TKUM9DgLxO2>hGxt}eR(NIi|S;u{<-`R*6 zwDzC!&$+_NbOiOY**Z{EN$+8HcEGCfR$@ZUlb#=Mf+B z)_)O#K*5g4D-JS<`QQ%7H}DtjS(D|Y5pC@({VRu!b0z}bAB>17=1AyB!Q&~{mv7ti%wL{k9s(3}>8m~RDZJMu`@zUx z-WO*eoz}(CCwfEPt}k~5H6<^$JH#D-d4I>IK##n>HVs>jgvJ{Tw@#|3U36*-pU@Q} z;~7TYU3Oi5VOux;>-FVO+C-+GlRHPaJeabwTUvo94v`gyKZ!>~CnHAnptef6EdvVK zCb?oFB-khKuEz*h4mfM4>A}x_JZ`<)QR%JD8O}v)5%{_Dp?n-7{ZQe#?h%vybbrIq zh$+Ehp`KbfhUi=6Y5kH{je$ZB1$HdL;XuLCsR~2H$R`oz$5z{fxJ&e#*E&q>JBUFW z1QV-HBOE{>VWD2f{OH2u2X3Mrda>I?JgJlPiXSANntPE3yP6jjD12+{cNk) zItdwwryj?$!B>2~xhKuVTtX3p!^bY#OFtA&^pKn|lI-tSR0D$xS$&Z`v_~!9>T^WK z=|#_ia74J=omd9HP_YB8;D562_AOTi75<3_+zlYA)}&c@8h8WE;*FuPE6eVVkDFE> zi#EDJVCiTcQz%7^*-apJ7g|O#%aql4Z{{Pw)nAz_F7#?fafk!sL;K!W7bik;#XQyY zN)dsJUxmQEU!@*-Kx-JHc}aU^YWPb-Xu>gi@-NZGH7X3B8%N+*e}AEF;k==2AZ7I@9wRa9X#Urhn&6Ba63sAD*U&oSbEV;I#2>NU5{S053rsZ9WJD13+ z7AUbZnx+C&b=hWP%FULw7%hxU82PBZnu3;1HL@HSHm=;eUdw06eAdD)M=&k#1Q((lCrgGA6id&nHFi68P*VM=C+%1 z-*}Up!BvU&Ez@v*cywCsutzuuw>p1zYsV#=1tfdEdo*&o(|;KZ(>yhp5}I=m!>u|$ zE>&Hct}XBaEJ9V-W?6!xko1kcjA_?m&nv%0Y00zr<3cEP@x4WM)l@brvd9eJXPL?i z46+4giO7Zw_F7sk@@_OVHZztu3mIu8++nlN=CCoqIen9Z%yg?IW*_8L@Ug-Bloxsv zD^uF_He#m=)2j?jHPECq7+ zRLPaY$X0By6@%;bqIIf6Kh2G8zc&M72iveV9=Z!hcQwgz*7tNq({K&Q)H_NhJ{mmb zLe?)zJWK(VBAw{(97Ekdd^a>}T+Yo6*+wkRzglEc@qY{f=gCZ*snCL181KVW?{OqZ zwH_Woj3K~)PUnsP*g;KLpP^K<+qf?O9domun@>L?T=qL9-&L~zrkJI`Vxv|R(`Kt| z08)2CXCeuct0_&cx(y0jdt#pV;&|>HJQQ4P&LJ$L5Y%-ugyIb9%0|d1XIA3aM9$*a zsNgOYNPh<wa;o#?GJ zHG{5%m7bT9xqS*%Fkn0Xuzncbxi#{nZ-)F)F%a6Pr&ve5=jIR^;))4H9DGSnjTA-z zX@7DastB+JLO0JC2f|dtmbXY={l{2FMDB7u2oKv*t#T15w`tRmMf}?t!XByo# zvUt_tZRsF8T9}_z5+q8Y&qY;hUOI35b$=DcUx-(iSi*W#$J?)S!cYc)C#c5lT{Vv2pJHkgC-^LWZp)*#if{XwbhXsK z{@^LUuTucttK!$AmMSBCjw!d(1_SOwa)qkXt zGoj@3dj2vqAKK|Bma3Jw|G9AM#D2#uepw+f%U6S1+}j#aJTfRCx;|?&Jqs3HJpD_t zmF}s^=CN=Ccg_HB^o!`QfsqvNPwj)9>V5r|k|a3Tc>`1_lgvmisxN#;0gM~*J>RtA z(1p)xOCBHIBYSu@0NQdOKMsC;m49RQI~-f)HH9#=Qi|}`q!jjMd6+W}Bvvsw!}`(E zt8g-~jlqFhV19~9GBiQ;;utte=JM(4<}x5-)=}E&VRTPQzjvQB9Hc9{w|f9uPx7ZuMlr9;g#RsuRiq(}|tWCq!b**JxghKK_w zy(=zP^S8q{g>pCS;?vE;ntyh+tm6-irDe&vT=eWio6^5FS$_@{s;?WlFcPET;taN> zZ`)|zP~bh!qAdFpXP}8wCe>0l!FHi1O>hz_#6YNq9XbF*K)k=FVdl-2%YF)$Tb&Ki zlEeSpidw{jAWZE8ZDonG&c)MDSkUGQw6Wr*Hp|N3&lQ9UAO-&rJLx&l&$%)AhQY8VJ9chy$7~epm4z^);fH{rR@`q!6cL9k+ zDnml+QdQ>mVf07+X1XWvk73JahB?8hJhpLQcXjZ?du>F)m5}@fgNAmVWP-ZpB z!GFID{#+q^zlTH^sof&X+OK~-4s%7phB#21RS>}me*ng|9T)JGaRqNT=qb2Gf^|^( zrn6JGe*&7r{Fl+Ew+>@fYoSlScJLbp^-eySKXSW&MW>M%2On(0L*^iM{R*eTEGV<4tjFV9t^Vg}dIc z4@&e5_>PO9QF2;Z?uN%nI}L%vuZ${?8u*>871(7y@R35ibn zg6UsGM4EaWJx6U`PL(tK|_N@zZmfBQ<@g+Z*P3U!gs%$`nzE)~+ zk1i$f^VRp-)EUY(S~0Un)Cj~6i7j5a)CZj@dDT$9k^{0hg)YY6nLpr^0U?R>{kHqpf;d3xel8Zd1H{AGovJ|lTsil8xNecg(I?UtyS3M5; z!+{pDa;&<{$L9J&iFdNJT%-LpB=Fze>s3420q0YkVYXtl1r0;JTy98sTmGxdX~x$4 zQV_6k)u?DoUfM`8$j*3#7BXsMZr6_AOe8&xeLp%-e&Xf+pp=fKrW`eO*Yk-`FQTcC ze0JwzRd>xS=<0uQ!Abti=+lA?Usp!Mn7x=;(0ota;ni_k8bM*{S0^4`BS1k*9&|El zNBA??*>w$$@<@ua^2L~5KX%ny#J^?GR%7T-kJHTA=53#RI($6rO)DKZ`jvM$&Yi@sXw6MY?4| z#ZWbeK5C>Qd~brJ#;@MnwoWua^j%(zta0X^ z$D#<1DEoqkBr`Q$+O<8(CQ|ppYT2TN)P#zS#ocs}!UnfDKCjFNX)E7Q=kP0@8)Mk>&T#Ag2d{s$Ak46|RUtzIL8{b!Q;~ZkEAS#?6Lq2k$#dT zuakd)hZJW(+1nzvgzIR=5H+g|#=1|3yaLBQL)(J#1^GO~sV+Gg3kheZ;Pd#e4+^@* z4?l0RyQfiVqhgd)RU-`$;t&ObWzxyY&_Wny81i3#nV~<`(*fsU0HP@!_$@wGYF(&4 zmx?J3kq{S4G@Q_$A^~^CGqBk+=;Z-Q_@)*MHI(OO5-`7R2^>a*sf#^Po zV%LaGkI?(7he=MUmT~ah5-irSB7S>pPlq@x|Fs(%$kPPF3(YMk!`a+|8i%MPz0SCkj0}geJMAgPbJ%y#@;H#u&OpNyM`?k%7?w5bz5!;;= zPoSE9wG>b@bV^#srEWoq(eE8~VmFkk-$De}f$@&TC_^TEuyyNkDE37CfaGTbOK?gi zF&8&Al#a(5;~4fzt}mV-Yp${G`I_owtxhYZXKN88N10fHDdaG%*A1CDM&>X~Kvy~@tb zr6%gV@Wp(~3;A@M{3geib<6sw5V`>LgHH$j5?zKnduRwGg=kMy&9&{#jG!9{S<%wlX7LXU2}DZ0r(wmr>Y>v1Uh?zVd|y#W-{pxErmEb|5yP% z9IxD62LM^*pn+G4#wF^!F|GDOQnBA;lY$;$M+(I&h-b!RxaWQvJv%_Kc@l+FTiOQ? zI?4@LtQoD;F5Ve9tYz5u`Hm&VB!dTM?yVs1V&U16%ETS4;ktj9K0rLLyjODE`-Yz( z3v$%pfZW7^ds3#zI=zs6!dJqE__VV)JNqE-w6jLb2U={?Qv<8O#V*#f@-%Q%7XKrR zyO69jUpQH;TSjS%VW6y0;V+GuUwaBi&MJ5cwe@pZRm>u4N%RsHDbH&9&v>oK?0eYV zd+9p4FclYAyb6C;B9+Y^fjxlhU2Uv*dqGRDOIK}V1v!YVhhgq*hvFskfMH_tqhHs{ z(-y%e)xYlD97Dc)uWNqLp#JuOwU)|Bao-UZR$aOE-OG@PNF>i!PP|uj?~ROC#A1IP`;1W%NoPc9y^XN3`P(cjVkB6TJQop~g6DsOOmu~X5rsW5k`iKXtgUg{ zn8VyC6@D9Xy$Lf!rD;_ROOr}u!W_%(^p6WagdeDPSC^LXM8+iN#B6Mc!&|we^yRD# z`l~(Zt@={iVza15BKl!bs`xs@Yf;eR^+?EUNkj%v;tmbf0POR%hRrs4p9utS^KlEYr_V5OFK#snsKEI?hUNi+X4wW?i z1UEG%$dz`Sqx!MMlEyv7H<|kKQWQ=4twnQkkFO?0nSwb%;r%*H$qgBGWnMO-JGNUt zp}EH4;S6lc(|dGXxUymo6XYy&?O<=-=efd=z?y%qguKPrcQi)Ieq&T((qD;1qs_nM zNR@;$oD#qu8II&aMU&!w4#3Rqh-a)mk8Nek9v=U|z4CPIhu-*VcR>$5HmmR$ejrSg zftu%H;1ntk9rqK?-(AtePbR8^z20nC6}BfNW_KmNNp^Fx>uyoVoU!I*|D6g$cBKH5 ze$9Vvzf=`B#l@#nGub>}OAX3*T)wXBGkxVBb1wtUI@DNBMy6!8*xiweFas-QJ74p? z7HCNMoW`jNF9v8VR~0UbSg#?lo(?S3r0`#8nOQ`>_^Ll#aQvVE__}GgV~<*7HrBUZ zXUZ6XM^dUdLXDc!*n?W` zl!q*5b4qzK$?j&%tXvf=V7EG_fY}3g$7C79)hKr?k62?D`6zGi|KmbyhId8y`o`Sr zK2vIqV+9qOOiO^%ot9Ohzx>y#SkdzcMJO*^Rmw!hq;iGruuop?mM&?ct<}^C8a97E zI!zXYCwgeT0cU7)G06kRI;rt}*}_abdz3S4{vDyUf?--(!aQ}@`thj-wT{Pzna-HZ zo#!=d*?b;XNi=_-qW|YE6i37~|T0OspuPflGyhENMRJN!-V!pc_Z2{xoEQ^0(hiKON zHj4~QIaa3{Ath zx`$fn5{zN^;MHO|XG?F+WFKFo?QtQ4Et@{ge5!xEX*!_R1!r7#YlT3aJP!O-zF^Fu zwL4M!b3s+C?~!`;7%# zeF#+h<7K)d5*|&6q z_eo+-6@VCW?(4z zIs;2`63<|u*q($stDS!uyhKquLRHeA&bf@&i0oNg$VNL^uKZl_N_$YG@=>yCfv{$Jew{R2$hXcL zBjH`+QS8NbPus3ec=Mx9eC$PW1mb@wT%GOVl9->idUuKI z`y?hmmphFzKKB*~nq%r>G+c>ojED7J1)z3R5}il``m)S0!h}mjo$D}}sr`sbFNH!% zvb&y_W%-Mv#@P!z*POwGUk(%&{Yt1#|xB{Qc*+=hI-n0xS+;roed={%n z-_6vWlzbcIeLi|iXNa%t-D1KUE?x|OpH`xDzcE_G4lRFaMi`8K6uuW838sjAc4rsU z4sNV*c+F)gnYX%{8a=$Jqq8-Li*5HaBqn0cClGlS<>4gfAXDhBReKX&egEoo0-0~L zU4!R|^VZQT{B46MU1R+1#7u@r!W$T+cQ!~$|3LY?b#FZ6xz~bv@Ak2RM$Cm6ZD<%> z(9&gd%N~CjZ>kwwstBDggk;)5iuNXmz*N`4gkvx(rR<0h5*V%GdvfF@uyAwRdCQrtKVErh!bU{gXykfq zvq+I9lJYe?cIZMy@27Z})wNk07Yh5j3-?0E$6od`6>ahM(i}`>4k63c3pp2d960W| zomPKFmd}R2Y~j9zm$a6shG6BBpW)h^M=|Jqa>@Kw%38tCk4bPfz7Y7pdUbpt?a3X9 zHxu#rHH`h6hp*+V!nL6t8s*lLoU;ul*gb8=XZ*&-1(!SbY?#l+yA+$zc82f|;PQ7C z-GYV+tI!XuMaxkT9bzjG;-xPvL8Q#$5AJ{8;(z%1aiFO4HPN2XS_i?!;G>Y(M4C(i zl?gso*C5pMZ=C+%LdZ@aU$feXm{S`ZQtoum7d6q&f=`dC$UWpbPoU{e{s2ef7fB9* zAk6z1$o2jGya3KJSNLdNbcV+B7!{AlR3to(S15bLPI+>mLVHWJXU_M@`>7@%#g~7W zwFVqbisT9|p=W@~65K>T+6#Y2VcJvso$l?+5!@$}3H_PqY_<_Co+-QyKQ-Qh56QV^ zc^}b}2=BH}bU8ZetsYUA6D1ZHG4Fhn`Y})GL3i9KQCd%reKqtPzF^WiV0dlGM&HcrtoLLLj&@ z`G}z@2Zx9oMV$pFpynN<-y7-bgW0MR4nc_S5Z}FMldKYaOHFIzDn&hK>$2JpstbX> z_U(U%2yKF6V%#%Rzmfs zfkRuoQXOWYj;!8e0&2VGxoKvBdu!5$kL>Odiv6=IAFJTW!QZeESBDFpR&Gp@l;|Xc zymED)Svx$gCa7RL-20zof|F+)6xjJMQMh`a+_%(evG~FE9`@JeMQ<;^Lc4A^c=btI zA-3YqsH@<9mnm2p^9@ZXf~tQdo+WVa|Crb)idHMGi3Ddw_#Gdf^YIL)C(<5S>QkFm z<*1N>IrEQB=Y(wez9oV?^*ZZ1+{K?ySp<6f4iOf<-O+|Y(Ch~5ra@?5h9OsPqZi(* z25TUpDycCR;d^OMX}wX{6`p4q`M2+SZDr<`7st`eB%Q9cBa@?W1!{l!uy)i2$q>V% zU=?W0UtsNQvrz{3tbcu03Z%|&q>lLJ-^?nFSadm1jU4a3f)HlBY7QD&aNB2vBpl-F z_>DMlBR4(5?l_>He`OOY`qD&$k5hA<+yi^4Zr<9Zpydy_ez;gTBe%j$sy#9p;JTl0 zG%k(|=co&EAU_ybu29HCa=~ktUG^+MdF)_`kDIQHclic z+%aLkVWqj#*cZ?|PCqIwRle1Lm)UCfb9&vdE>tH<1)kXrH%9r0Re^-c^#}uc)cW8U23>TN zD=@JGZauQXT;+ddE>Q|^fkY^i5i1!d)yL9bV0E+X@U)+%JdB|tG}!KgloaPgJ3o^_ z6e?Hq?JYPC3?~gzQ%O!<_+mj^YCbA9>9T!tXIb~y`hFj(?8|BhF_ZzUY!zPodXU~< z*eSJJ>HbYAHn!9}nipq8HcL!_x^_;0wstTa3|tb8X~8Y>3v_@xIGWe<|o1`tHuz>73M#v>cG54=l;x?v7QYE7a$fR%tZ zn9LaYW1{>3^XDsrP4z}c*$7*7on3mPv&_)sAqA7{K2x*t1Ya2=l@ikEa(DD5)R)XO zNH)qhQ6hiFi`9HmmGm5Q+rcsWP27v!id&Z{s6#y}}fOG7kUNFT2wcNP+}$Y^5e zdVGI;AwIcsdtxjh?ec`S|Qnk8a&p4U&|0@AnnP8JLKR zkga)SpB$uW_9UZU#2TC_cW^+y+#bT+9sf80w|q;f9(lC>kxVwQhU_L!VYI*BlAaSt zjn@KcSyjSeD~G%Rfw<|#JqIqxtwd%m9z7uyBfA=9ky+0D#-oBrGeypl=DdbDmV19X z6LSnjN7gfK=2z`RAD>@Veu|PT)_E3b^X&MjO}EqB@ym?Kc@@q{mr)(%BjZigB-PTv zOI7t7X}A_8YKX-ApawK%(9oXe>V$Q>0|Gd4f&0!aSAI!&OsJOlcM*1EW*povQ?JXb z$Ox{0^DP^KvA zaWl19Ah>2hG_1Ak)J4ONen;JT^JcXqipbc^&bR~1EO60(Az8JzXqh8I z1}DRuEde21RvMFi)c`g0sJ?5YU(_BehFhf`TvOgr+9dP><)PttJY#Q+?d5=1R|ErB z6It{F*`5E{BywtfEQzn_m|eIhJ-A_8#jb=FhdGMJ!sh(&(hG-E>?wa~WNZx$Xp@{= zIO!I8VikcKh6w@4BlQA2TAOdtY7hZIc*EeJ_lS(M*4+yA9=2sqTm}Nnd-}1g8#o5n@fP9d_$*`t&%X=MMdUXd|9cw51+&Ue655j<+jv;n&?>h=(v~A zz`F$gO+O=Nsz|Dlh$(+F^gdcfX6;Lfe)gURrBuVAl|xBt#4fzQmYH0< z`DG8}ziatYu0SM5Ih~iezBO7tYA4?WgxSt`u24;9px1utXg`05d#&;*!4P$k?DScI zO|Aw3+qGFjopYh;R~TY<{gYJb)(@=tvI!GuC`p+b|;PXn9K;&NWMPYl% zf^3|Sjo^M})}vMGDw^mHuf6JicQpr+7%lWYx4sRateK z|IG@>RDgyen%aNFmG<@L*NZZ{IKQ=k5?~=FuiTZZnzgoc7XfB@@dpWHE-_}D*PZh| z0KN*EYdIK_M;u3Qd^mkUuJZQ6PwO2V>Uox8n4S;bNbb#@5(!VS94jKR@pJy{?3y-_ z6V-)(GA|megkf=n5X3g$AjyTCWdfCMX5yKBS^+AmMAm=A#DeC;m#ESsxZw=X*+Uo0 z;quGukJe2eOSLSdTH#9T+ma8KIplMdM*Vs!KSH*e%ZbY0vX!CHTbZmFbZW_C`i*<+ z%<BfH&i@FtAHv~`5UcN}K;>xhG zkP}icZG2Xc%=yh)4^z18KL6n6#CELs&zC3nO2NOC+7;26_7ajS(I1Rk7JF$e5A>`z zDj*C0TgJ106F`7ynetH(@hPnCb-(^ZQne#>*O;?Lwh1>z*f#*0Rc zF^;=nw`64so%Ummi8gvn-P*%;^m*RJb%X9p#hb~4`6wYQYKk}^;3yEgIJQ{S7ji4G zhT>}AnHkU>uwFp)FrqNIh;4~PQBAdi_Kz6xi|JUNW_h#P0n3Ei z&`*Cn%zk>;{tuFxG4cHF128SM6?Z5*o01XxUBogfIwso^j#@js?G_V`v{ctNGBao) zLM+qH^>sejy1XTowJ*wu9T;QIv;HEpnYBphbC40Oyh&dmws;U`@4dVd<<>fpg2~&Tl+1VI{0d!ZZrHXGaSmk~yNYOKHneq) zsP5Uw|;*GgeVf>r78@@91Nz>%cv@dK(n+ieH8kV*U8t3 zh>g;(*F-G-amLfZI>TW>ba=c$>l2hq=-+@2#!wBB1NGh;B>d_vf@))Ytasd^I(PPG zI4Mcg1>M*VW@>6Nw(-idtx0L&Fc)1(pY8>5y|SY(x4^BU%# zZooz)Db@9g8=IVIh*w1o`w@S$T;kUdM#GZqo3-Pp7^4Ab1kx4jUY+RT^|pVn$M3#8 zyYLb9XPrgmH64UIqFM6Z63P}0`k-r&g<5p?ewT}54_sHLlQ{{lvb5?x6m;$f81E37 zLNbsA-pf+~`h`O6zm-If*QQCM!}x-r#a?8IlcUq&5~)EbxG+P%)s5c&(>tw8CZOawuu<8{~;Zoom`Ga=aKPAjhoMas%kp}!Q-b> zvde=W$(^sujp7brB|V5w0;d}TAMV){R#kTcSpzXWKK(7DjeM@*(Z*NKVATx)#+9$^pm`NB)L^8Y0WKo=cdStjB-QOyJtCi%pE3|KI|- z-?R1)+`9RB7q(VOW|Iu4qcX?zVmqgO=l2UzKFgT~RjUL@JRy=uM1mA8>_*Ef!{I(# zirJs{8P>&DdSWLi21^t8>1Th~=&DZ_A`nj?R(vXh4l5yx!(CCb_GPpRNQk*(XV?5|Hy$Kl$_DWoRMT zF919^8|`f)rxZZ1bQ|z@L1*RGx1 z|H)Uhvf7bAl)FsH^W!jKu$b8aJoLltMzFuU{c}ad_Xo?Yc;NmhaAicdh(tjW;6_T` zMo~)}BrJbD_Wl@evv42b$GS<}7lTz5R~_U%uwojr7_(aENuU&@SSqwIos%JSu=&>m znLs3?yxf|!gO5rohpkBe^$NU?o~|^BTZ>-oeNhA)(-P3 z>U@8qyUcy&s2{mUZIhK_h0*bT3V_eiZbp>cE$^T*mz}$Tt-Rf_n0Jkj<}vb;-QhT` z85=wN8-3Pix&x0WIHS#H@mt?u@sw+79RJYf=B`*g(4zAz$5zTbbU$-F%#VMgq7)@o zl}lX`jW~9-7++|9bTOx5R{?aZPMeWpz#)HRCoGJ#KIv!_qjA}EtBW7$Tb?qBNLvin z9DK=2$NL^Va5wYsZL1ID%dN~w%@CoDd_3T1JxjE)QR8R*mnjWrnm{R5l;eujs9jCU zhoXM+T=u+we8K1D5v}k=;IBMJ;->$U1`Y|&;e>4YSs|{iKO-(8%z=OsCcQ53UQ&OE zt8#HQI4vJM>D{6{antm(DsQki-dT5pKMRAHb;O|3%yMq>N$#mn_!(_*}Y`=*zl3o+X-+6YU!gxpL2ggdABe*-U{kHa;KZ;K@Dt?2=v4>_-U3rw_~%0 zP~P@&>CAFo`xq4c_JDuDGnh4FyogtjMW6fv>^%Bg1dWZWae#>$i`2N)4zp(9 zuoKNFT~`~2#+RlNeB_SK;NXDgRmar%g5*v)NBvQ#@0~=-Vf|Ke#HSCeb0g9CJrW=k zn1F>ce|I)J>b5yp2Np!i_l!J$ms?pPUg2(aAFR2S?Zx{^qI>CWeq?`rZT1~)0s4@! z#1~k!5-y14?*{AlOR~Oeept0x={}bU0gFHe8ppU6Nm82VLy#3k=tU1ip@YZvLYfp? z+Nc+z$0~{-^`LNcT0XiRuvkL;*%;G7Ayg5MO;HmlpK70OG$dx?xUUo(2venP*T;GF zJd%91;0=_Xdp~1KFPDGT#RC{>6%hm(xbJ5P>bz!YLINCBbsX^kab=GY+tHJpSFt9~ z`twsb8QHwaL{-+=rB)XpMd^EIOBYSX&mMfvQUc{bfGkX6?Juy|Hm7oU8qJ?Q0IdaP zJqbE)A9T{LKXd%yAS%&fGvM&1-+v-V3dfwOQ>Fi>=At zhEYzOKX`F##$|5+ilU{ar+wa2;8!Tfi()6DZ?PK3QZoCgcs?o9ZO~GICYToEyeNa zJOwm!+@XyZqw;?rrNV)2aa9ovFF{SHW&&H#==(09MG_#rl6H+3Ko(Er1Up?7BHiDe zA7m@9bB)4U7qMFs70Sh0DM+*-(0TK88!5_rB9)+4+l#Gu3F7E9g%5Rg2&=X&kI{Jo zAU2aUY#|pDTAm2S-Q)NdLGiO0YI7!e{PLEm+>M-MIN>QrXWbJh2AIMsp-J%UfPwlm6di0{Q9Db zmcwy9v{gQRcVKdDV)?G}oMauF~45ikcQ!DCU`=sINP_mECja2Dh=A!;VOEp1MptzUP}- zsflu0!oUi#Y-2bv+0cnAY$Qyx@m2oB`@_RxheUr4^OPGU%Ztj8&R$SkQ9e4)cZji+ z6`bAPx1&1ZFgGq$tYikINpCtYf1+5RewH*=iyMR(uSd8kABK!z;V6by%rI{0NtPIP zCPY5J4VAM{M;3@ept4Ugd2J#f^GsjaC!vlR)ezZI^BW5lYe0VE-9uUEl$Kugfqd2( z%nE(8fPvvw$Xls&qo{F}UY8VS{QjF299o~}^h@}v1UK5-EJ+1^=RK%ACW+7}V|W3uu|{H549RD9`3#y}arDE3<|gc~ zSvJ$cswg@jKHLB=dc#qKWjO>Ey;6ToJnk3T6Xy3(8?&({B>vD6&;+~&I!Q6AZMizm zLwLWlIU<7`tI&mHrq7h=2053HT&h4MCyYmx!A3Re2I*@)D=awDmpd?&qk!V?ju|^P z@eumW_8%1gt#<&42T|?4N(>LS!Bh zI3jO8M%};ZNmP*m#dt5jFSa;WLMt5PE9tI5-?7Ex0JiY`$T-l9=rwj)7C6Xo4?JQq z7+kT>Ib(+)nYZ&xXU!G}%ErK9b4g}}vjG*tdV}HF%cC3$l1fiSS3t_JY4^6WQe7$Z zMAQziOKaQhRIey?bucmu<=cRIH^sB&Os8d59i5FQqvxG4ElXYZ7S_Ydz%G z4)>lbt(sGSvN?V87MOY|-^|kJ=1;3xtL2Agy8u_-DXg@KNcABsBqD!#MB!4#J$*ej zyN-a*3OIF|IPNrdYL+iXTO1$4fHF9B$Xm)7l~aJ9hf@WIjq2QnxWMj8{PcHf8Zu;b zc&oToY%2b|fn3@Kh84@gn00p_uDgXjBtO7UDWx)FQ`uNCw1X1%oJTmaJfqPm6}yyU zj#RrNhxBsbM}+f8J$rw6OX-E&SKa3SY34P3Vwd#J=n4f@c|6Z0Xuu!omQ3mC^Bo16 zCH_D4;I1D)Ew?&pR5Dbz3efY#cDrBeJY99R86)ciJoamvp9w+QbdR3^y=^GLTgSaU z$=h)7=)kV<;GW|9HZT6&!52vNS!Vsd_w%)uVSpcSHTiG%b&Y>s?LB1Zzlb({he%Qh zC997O8R?VnM`8FR&K-tJH3AbzqW`D%5^jxr|LUYJvd0uf{t~x`2;G#rC$4Fcm?E~rP z1-d&UKZN0ArLQHRo%uybhoOx{+|!-D@54>TC^X;hpXir1ev)HCUaoRiMb|$INETfv z+I}kjtu#H_z_pdhNK`$Y?7pq7$h8s3j?nQI&5_Z+)Mr~@bg|Q902Ufgz`zD2ai>RCyUP8 zlRJI~fFg~OZJ3Rj69mRUBIR8Hi9W2IRgV@tL7!~6{SBS+Ncjsh+N51*nw03`X5=q==wRG4bmx<=y3+$f_2L#L^ z(I|cm5ss;t3fNJ%HPq~CNj<~-W61Jc((YQN4b(k*_(Vge8g2AOtFMuMg=IT<(l~~R zUP4>f>~{6n+zd0GJ#Wti8`|VI-CuT+2*bh|ahcgjG1W9ihRE>P)TsFZi!3 zwrPL6PD{ZSK8kn@I}|zhvzZDbZLCA$C^$*JUUP}qf9W7==PWRjSrIqC_=D(y3u@*W zc>RcKK3feb#1F&4KjA0Ty4>6~_8@MYN@z^M$ z>mrKOZ~->V=%i9cBkd5gK-!lZcKwo+&*pzEmzF+mFH#C%)ap^8r3B@KTrU9zE-h|u ztg)02EDRb<3^$f{(8l(PKD#SnLPlX89>@v+yE2Lsv=NXO5Xjy5#&CfK7)l8%$F>m7J}AwfYAXWFCm<-+&qYhg;Bx?_&f{VT&#h| zUQC6sM@vMVlT3i_r`sGvjAM$CzHxsNr)wY&IJsDny&DkPyi@jt>L5#g@%Y0heme0`52h{OZ@`ls$Tz{O9EXnLz!MEP)zO`orhg|Qpg2-pZRT5 zXOWdbQhI|Z`E|GGE3Lxb6zZHIqn5{QusQIO>+l;E;jvt19r@`c90h+=X6tUy zA8Zm-7*DY7kTx4&tR(#LF-|I-WK?63SIi0#@!ejgeY5pemJm2>cd>bH86q*}hbII6 z^4^I`=wF1x7fDq#z7Z+eo`f))sXSr-%fzG_mFR2mV%mgD#N+pWowRIr92J2f*4>|B z5$^`HPfa{8@je^SH$;p)7Zra{ph)_(fMF-GSi-D3I$}~w16w(-9b1l2R<*9{;fF$X z+^hJF09l1Jq9l1Xc|LJC=fESswHMOJawttu(?5jDN;X?&Zk}UqkYy`1Mf_Q#t48l#9jK|V8>94oJKc!mH&k1=Rb=R3tWKkqf= zMAE`t%4vOrU!UBG`9q*oF2Kf9m!jNt&X?k~U6CLaSdl5R<+b>Xlx9qx?c$DhYIYRP zugI2pxee5<;OfE6WBFY@hGK}A<`3bO}N97Cnd-iQa+;@lEpPJ?FgV|JVAyHEYd0_jR{@?S0*QW(_No zo*}Qi1Kb|00*4`a1^9px07Y#>a{(X#2o&N20tN9{S&bk_DEMz2kJSY1iGaXi68{mQ z=zj^eL!vMxJ0vPl8x8|#ctHUILI42~2?0?FAP^u31d9J12=|l#DA{>K901yU01Y?{ zjKE`6guDBBLY$nDs6Kx`0ysdN00D7vQJ&xF0C_jCCj?{%18CbJoxyIXjvzZIzz`0C zfRTRxD8V7+j6}Li@bmll`0&}eA^6~)PJc3-JOCdE(iva?Mu0uN!4805lmR++Zs0%E z`0!W(M$Qn#Uk*dKBhtst6AVBBPzVSNL!eT;U=CnU0IEB{P+be4>kfwf6|D7F01x2L z<^Tlv1pZa-Pxh}u5ZLczI}ix&=57b`gTR~sju0pqpsS+AhxA4A0PJ86zXI)`2!A*# z-_F|(0=2V81^iyR9Y951A7F=K_=g_?!;lEP zU+YtXc!EKwefQ)4bGWWBxDPDgZ_5z^b8!4c!@l(nz({~F zP+UYrSO5U_0Dyf#&iua`82Pz_e}6lF!zd0x0q$^jfFp_qI0)hhMt$G~And%s0HmiE zI4Iyh9sjiO1OxyM5D*ez4|amU@cvyL1%n;`vQg*n3GoG30#Wi4004iz{`F*yQkVlA z2KD=Q`0pd;H&ZlLH#Xz`L-}7$1qHY-Ab?j;9Kb6s0t5&M2#5egMTG%D|9`CWuO0ZC z{clvy4)SMp|4~sL<_HIf|3w0|dw&!0{-X?zKV!oQ_-6+lI7-i80LQ=OZv_+vf>3V) z|K}n2o$~+F{;w+ktNj0aMJirU=x;yAUjhG*-_8vJ_4^Zn(z6#5H5=M+)P%tPJJb~X z*FbB79UxwA|Ls*r+M#Ad9)IS9(mAidLq6ccziy^K(1RdB&VOm?@54a#fI?tk zJvajL>)t_S0fGPJLyaED6?L~DP)GLL1x8KQKl>`fKyZg&BPb{=0w9D@Lka8JBn2P*&+0r1<~dHzEG0)K>2HfqyQbMQ9= z1n|2-U|xvdz(2Z!ygWTo1NvJgsHOdF|Go{tU|%o@Z($Y=l8kV971427Cr|6cyETfn zy4Dq&Y~B|mjAWa87T~OfovS+Kq43Dz1=Vnt-h5@$h_zn6KNaBS;M?Cd+zYWX8 zoT26A_xb&OSwbhpn!U9mFQQ1P$^12#3Wie$sL50EHC`jo*nbp+&lM{(l9{PX-J;l5 zFdm7n{FpB8Z%-Kz@@jI@Q4GDO`*@_;s{t-ND_zjDazbajnP>E!pMa_*HP)G@E{jEh zwblXcd?@>{RtQ?yi%G!%z-s7Py49YBmsebvYoRYT$74SZ7qa<0L3Q~kAvZ-p&^kjJ zDmL)xxq^rulz+i}*wJ+HS}FrTO2bO3r;ee+F*^G*Kgd@@A-b$CfVNeh+h!LMzgTX!ue6T4!Z{OVKSt7H~IRDg85YFk?8D7p~6q& zU|Z6P$5w@o2|p6QZJ#wA7MjU7#8^OM)4QjFH*BAe(05w&C(>oVnb_;?WY5_4RcpFB z$2=mnAAeGn7+{Vlg;qBw3AZUO_mjsOTlU*&b)2=}c=n7qHlKaR7qGmLe7G6vZu6x{ z=g|E}m4|{7;64%ie5AP0#tZEbHt_&V{1}s9C4z5a_X+GKn!*HUVSH%Lj?H+RP+84I zisD^MmM1N7Bn?-p?nmdnbjze|^>q9i1OA{3jDONF6|o=QdO{yR@tf(2y!Vrbch?_0 z-rcq~^`KP>({9CzF@LyPej3$6Qf!_yGg54(r+lP!Be-EJ*n00pYb9JQBLGi;(szoQ zY;cFYyTgk*upLftd46T8!$@zCtDJsPwx83QG>v}tgDrg{8_KA1OJNnPMS^bNEbx*+ zrGLQwxa`Gv5O*|`K=INVP*%Fs!+{e)=j}KH59f9qr^?sf-DhkFx`4{kfw)#;m=9jq z1RK6uWZ^&BmZY$VJmF;OrXOv9Oua_SFD8m!czfoS@WyM_my*VS7a?)V`uD5|= z#(XJezP^$(9yQ^#oGnkm0L5@VQK##DiUfN{=(fE2rJfCXRYQ)?LM~~UgZiMFzke$S z=t3ym_eU~A++gUQ;gGSOdV^zt=2+z@f+iCGVAQ;}qiCOh&--oCxMfl6k9md`Emqwk zx!oMK@Tj!=QY(7wi5ky`mx8@hW_bEp8kwDq%e7_C8g^yZ(%iXbBSgIk=P0F@^aKz= z8>&QUawR&c!Zt@j8L>uN4PuUMQGWm$KmD@k@K#;Uh(>}Mpy>4HDOSQr+z3_tlB-k$ z|L3Hqr;c9(q9<%fl$<}FNo^Jf(0n=PzI(^J@Z+sN8DsACt#7XR&7CoJGS{Br1*2v=#yLgP>u9K(aLMY)BGDeg7u4Lq{@DoU(dhjzQ&}}3yrn7dx zToxShIsP`HlSVy;7bUp=LS+7q!*s(JWIo%bNmOb>E_c;J2h%(iHF;>t8XGo2D7AOa zUk*pX(cq?ey`0(YC6%ZHLU|^eh5Hi2B`ZR33_eN?^TG-bc3(W}5Ph;o` znf3N7PPUH1b{=P;Kbu^S4O(+;WQ6kyJgoKhn!{7*unh6;h#w2?Xc*H6GJ%@wp~8En zB}{8>!o3mW*Lo{xNe8g=B~JSjoIeI;IzpS|NGDr<4Q(C>vT3Y3RmC=k@^AY-W=c+~ zT%}oAM=v?SxLJnV~w;npGH7U)eHBXI4wdHuD`C`#P#J$NWqvJ*4`0 zP(~|-bgY1t`eBL<=~q~No)38CJ$2qGK?VxBcc^N!rzd~8x?OM*y@dUuw2Pt2ZP=W; z`_K&SHR38LQ+mrVh;Hb&f22>7f#kj|(;EdCo#q_vo7~|eS5eBS<*a0O+-+=n>Ivt0NE8c26 zMGr6(lyCdPEv1d_oD|Mx#T(kTG`KNPbmRFxVv%=@`I(sdvV~9ByEu+&FQ+FnniT2s zv~JTqxH9@P%!c#DD!hTp;iysvsa^kc`8N=)7#Cb`>BDwfX{8t%oS zuQ4;nz7k#Qu)38VEGsT{6t{B-HY`&gKg)le7NJ~HMP(nw z`9}_L?RyLs8)oO7={)@tY9kn_Q?z5r1Nkg1_sBzL8jmer^h+MPVR|e)#G26mQb=0u z>}Jx+hEYL_w&7NhKhOAazozF8G$k)NUPlfT@{6CfS6c~h#k*Bxr*E0br4wl9t`I&& zgMkDz=tw2@h>j@4y+J&0V7U|71ux^zSQ*y;&{;)ioAW)W$$YSTquInof>X8mOBjVD zjIDVTV1^xzRT+E}-;gC%{W!PG*K2!3@w$eK8R{8#K#b2(nL_Eydh4Urv^ zZ=UG*P{R)7Y%R-;#{SIk)x7)5EM*>^8Uj?DxdH=Nht$71%_ojSdIW!1MXxc8&>K~-8rX~#s$C45399)+C zy4?{bepXB?j&hALR?|Hw@q>8MNNcb628O3TmP_MCqC0@{IBwOu*BXZ1vW}kXyL|=Qjp^{aRu8z~Hd3sRbrxT@^*0}8{FZ#Z zg5_3A_qcj&lv_S=Yfv#^BVy+YLsiryGZJekOK@pWvVichXz66Uq2*QHn{Mi((7b0#$*h72E~-&eZ{T}}&Npmm)Ub^(<~AvVpTfk9V2LA3 z4>Avfq@S?YJt2IPawGXBPnYyOBrzV+`t*}U{3Dr|7JsU^2V8m|>Mebx@9h&i<-7*KB7A_tZW&XALN>SdIUF`+x^LZR~+8{j%l8lH`j@@0Ut~8o_ z<6~jvKW-|*Ij4G8;LXR&X*oky?us_7hJx{?$<;Deb4U$58lQE#Q%1x?3g*o1F&C*BW34PJu>-Zg|y5%A^KB~lMRD!pP`A%TviGhy8saINOqpXUm zjv4J%KjZvwz@WBlWujzS1GG4>#}asMhxGf+f~F#?sB!X<2{CZGDs`gH4UyRRaFzPk z?$?j{P{q1N$oK(2@;6<$NtYNb-6a=VeG2UXbJ~sWeqyf=SDUMO1ABvWej*|dZ7p)hSRP>}1eCS;tVj zc}&fDExpJ6q~>PpiE+XvWqeeRxAr60_ZUP@8L=1HG#WavXMX1M`}ncl4}^Oib9Iw3 z{PE|PPsFlA=;)YG2Xyw$*v`VIphkwL49oka=>h&B)`dGEJDl1*-qMRNIwT^KM3Pq? zR7(OmUcnwJ(w_-wM%9kjY7C_;Z;ih7WR;f32nkVi+m?Dx6pB*Js&t#H%AIpKngtUH;74URSoa(Dhqu8Cg-A zap0&C!u+!>#OsAMm&Hkz-TPXo+&TlWo^|}DJLj?Wy!2{#=2{O9W5GE3!LzVebb;dP za;4mWXKVQG;Fx^uBP{2x+dXY8Qu)Kn@DK6VDdS2SVJXefM@AS(_m{P;jk}2Yvz)_P z*=l{RhBO)N5L8=o2{nI3WQc$Jsk$as;?koYDTtx8KqIqH#9@6o+XlsGsnMGPQ>LxD zTLXp*6h0a^11DIhZ}Gwfp(wUu`{`m10gU0!OpjQjwLuV&6Dxc$Z*S53bN^dE9%BE# z#Y^Frown)+53@qgwiYg7ugmp{Aq%C@YsvF0hl|Bh|4?Ef%xz|3d#Se;-~7A*V0o0SaSJGd5*VJ;qP2Vq1R9Sk0U#$=p5)6wmC9?uivRD zI7-UQtBo+TRGYUW*3Qo37r-3m?rwVy`msvdS|}%WH}BcSil8}ELrZ|H(zZlnv3yw;)=&kmflzFReqw@G`F zTSrd)8;+OGZmQJz+CIDAWgAj|E!#9_A(E4RwksStEDe#EisnVO>e}_cVoS#Uj5rnzur&P zHBJN{GpA(_ft`F!3EYy(3MO|nWH?=-MB0>6?t2YaF+P##UrCHcrs5D zL-9V}{G?*k?`^{%fY0B3Xxw)^ap_Y_N)6t;P5nDN$=()&Ges}asgK>;UI zTv1Jr>Yke~UN9&PA9`zMEfo)_A(vk8_o6T!8fcB+>U#SFsm~s}ew*Jmk$N8@hRLA#$MP+kc$RuYKk^1@au5DUaMn-( zO{r1!KkxiN8z#Usd*xH-trXdS-k*W?t5{pO2T8Wh zn+n4c|I`dNKII?du~Q6<8ICH6Ltg%bGwYWRjqX6Rn(}FJpEB9dzXi4 zC^viW0auwhUhw{MlWg*yVfD9lt*ljOK1Sa;No%QUn=K8|kB;%kAc@{TV7kAyTONd7 zeMi`0d~*wN^2Msm{z_M`9PwnhIV>|pOr(I1yX=-z_0A@6AaB!w4=dK>llQLfK;)|} zihXU5UMy8a%O`5|C!el0C))daJ)K!;QgklUe$e#T>AGQq4dte8t{LQmwwpm+aAyGx zredb%_wGcv$;Vd4_C<3FZWrDUZ+}*y`zudR zdOB8`i`ozDL9IZaMXbe10I_ev=A&z)-jT9sr8f>%Pu?4osS?k$fcbtg9r&R$5&O%b zwrWZmh)?r;kFN{fs8ZfM6*Ry_{GhEAa>3jv(6M~OLm4f*i&wtSlQPj56P7(5Zog=c z?5uUV4B>ezHhM%$rvfnuhv8bOzpv{ge(dV6UIqkmtgqf|(#HxaELluiZZW4Qyt8BX zd9ns7ve1(2*B`MbXIR1K2%tykT5g@=7f5TKbu)M+E6hADX}FsLPkAe&BElD4XF=>0y1n@9e0T z^{d(=LQ2MKC?%+T9uGwB2xOezXwn{&!>whJ$dKti&_-(O;(*yC5tq=eID9tA>c1Ll z*A(QC(31S`|ByAUA4pP3{yo_uk3{?u09uolN0LRt3j{y_AP}+gS5JWap0bm zT>!wuA>z1$LXuEnxEKuj-%tPm0s=xV*nj{4uAqp78w&@3&XEBCP%!}TJOT=aopYYJ zG8lLPD-HvK&SS-)@C#Td6!5pF*#C|O4156$2V8U?27_NDh6BXT5d#5Gz=7=sYn*93T!pw>yY9ZpT6Mu1H5YC4X1_yyI+91$#=}pXI_<5Ot03Zl@j+iK%*!l1i z?>@NTd9VLA!q0<=ED#88r<4R?0uxh&fEA!%F{m6E28BVvV8{cI+yk%zoG1s;j9{1g if2SC-BM{_n?r2wcFINjoa^m*{2o59X;ZaakB>x`;q7fnh delta 55055 zcmV)BK*PWI=mwGF2C$L@f3a@EAQ0XC6*s~F;Q$+Zt<+SiRCOp@)giJ;f|5dIV^{tA z+JQ#ubWiWzy?b{8P9Wf^5~V)aYPXjLP;;dl3HAtxhPSc>BQ!_VfF0nSAZ3WMCa()s zNZh!1_f0?S^KOqdpx~Y8@HTvdz~t&z%RFn(exgjFCa2jCF2lj4e}lgkKAj6YPX)wd zu5b3m_hY0?w!~dspT-z`Ki!*37CS%nk*=bJO0(ws$@ImiqV-{m3+yi-Dqia@2RwvT zqZEl>c~6+)JoYY=E^LmAUl)IFxFv~iR`(YInua&PYNL50%FXJZ)M{TQc>QM-QN+J))t9n;=tvhzv zkjEdm;ZN`t@q-{5UDeDhhsDG+I7x=Di4j31WK>!*MgA5PI;6^_XuPF#y{s@xaJ50A% z=!ha>@Iw2xUILzpiSfc1;TlvNDc`-iyCvSPaBkT2`*Ti?5X3txg-B}fvPwgciA5H1 z)fW^?zkwQ}B%sl$0a<2+Cd*gVs`C*C;U(59poc=f2M~ty2v4wBb$?CcyT&6S6dWik zjF2yV5x0-qee|Tg(LG&mJ^&J%5z>+N0chKh%v23Bh!Cy8%Gh77gYgG}x4>REHdxPlf=f zxlOlkN{SF*0YmE7U4Kj8i+1d7z;p*UR9pJ6t*Rj;WlETii-k{4hk2#Cm{RQk-l4c0 z8$l;CCc|i&k4b-WPalt;u~gA%U&rVz%_)T?;B#FDiFyQQHS~2wv!Wc43vLq5QelklG7|p$CUmw4e=v8nrSg59ilCux7A2;>`~TQKdodQH$W7J z$a~Tf6QW^t4if-&92JD{dbr!s4gw_&k6)smh%ZSUh}7Jl2NMX-_>4ej={^ZDj6 zbX}49$(f=H27d~11~U-N;Y>u8)R!zb@!zy7h_uASZ=@iF^$AXW7Zxd9Ev0J%X^Gq? zvs`5-l9nX%&m|Saf+682F%0AUUvQuV6VMR900;cs+wPMphC<9#7HN*wDXp)=1UU?w zsiKxeD8$9s?fhn6H=(z!Xt*60-+(VTfpQ$0cgpn?kjd+&cC6Dhaxt3=57 z_e6;JE&g2N&n^Dke4Y@=4YP20AMN~Eyh)bZ{F!t}4koPfrotuP;i-4{^ZLxu9*p1T zXsDJ{oPQksX1euNa6-cUp=N(fWE%5lpa~C%Oq%aqd82h@n6hEO--c>}XK%AFEBE{h zVH&1iKevl<9v;8g>T%k_RPT%a@HElg0RQyv*}5JsapKdi!14a#3!WJ1x43%q%T<`g zRsS%)L(llPE*DP{mu{Hh>*Rm+6tqm?HsQHfv@i8;-@qGTiZ4Bw@pavty+P0)>GY7D zynu0>Gx);;PG>2TJa}tPgaFe209NSCK$GDZ6O#oH?gKJ1F_+DY0V#jo8EcQ*#_{|8 z3Ig>93OLdGexzstKjI{X-K0GsUmSnnNxTzbio8-(?ECkf$CBcuy1N8t18wzTXJ>bI zIXgSA9f|BZ6WMoXBEgrdv*&M=&!j1|aVlF~Wm5VgsE~PK3aMST+GOu@vsg;0Z2t04 zH=DY>UM#h@dD(8b(;t7@_BhJmrthx%a<}-f`rGq2(q>W=QACNK5ZO|x!rQ=`zkmf+ z<@SLovWV6)kC$+8B+xoP?16uoZ;&Lq%^ zOiqGxRu($QY`r^s|3PFMn1t;L9YgksNOzgGp>VLZ$eQfp>>qp$Afs4BrySpcE1Ywg z(-Af`%*3A-OY35OSS*9fZ=kjLhWaJ71GR8O9|9s$=zPln2bIisfJLN+_9L}8p_j9oKmc<>fB(~+4pxExu&r4x13 z9;oe+%+ojF)^K~cpfzJ#1~m^3j8zO0$-r}m*>WVo>y;o?clU~6k@F-_;1d)}I+h}U zh5>#H5=HCG}OHmJ;jhDxa)Qgc4*D^B^; zyAE&M-9}x6;Q64dEx9l7s_0xcsXuJ{s^ac1LYk)9pCbll*rwsDuE&lcmC4IBdcG}B zbywpiiS~89U$bk(rUHk@9|X~byes?htLsDGS1o_i3{9dbd6|V?-7F`cs0#}>Mh7S_ zo2p=IqN9RWcZC--uWoGq-Rqa!*;jpHg7F<9hyB19b5teLq3qN6&>=MF&p`%5)tBpm zM?TfVHqmU;x{K92tAwp0PD!9fMzauwtxdfDS*9 zLqo@O^yI;MP<|`WSSh#!LE%TBngp3fN@{<5YJmgiByg+H<#Ebk=AH)3+C&3Fpu_zl zgqRYOBUOO7J(4uD@S@1|f&&6h74s%plN5*!*4)vgXK80S+u0N#*R=CrPkb57%0U{I zC_sXq!aTGaYVpL9VvRHs-JvoZqabjrdt7HH8Vr&k$bmu4pgAQ{GXs~uKXpV1KUO_{qk1Gk9r21{ zi6otMoMSpxSxjF_JDvQr?InhQJ$h2#kMGuu<#4 z>K$3VBO3zqqL~*>yeNqAlfp>y-cQ#SQz$bzgx{?c3X*K4|2w>?6>_AW>j}RV0K2(A zSul7G*zXJHwki}}`%FV_tArVI+p1035GR1($JS-bBgb5i5+{1HWBSuEUCnvunCihy zO7&oF%F-Ymdmt^+-WJlSr>1{J0XE6B0~aHnqI9ZIa&nl@@KLjxUS9MDdyBnS*c+c; z3ZGy4)bmS5M;;H^3Lx$$JilZNMFg|DbHYFJ{6d!xbI$S$onP4b?u43qU1;~1TlIy} zcBFyrE!7@uNd4-R`KZEJ^XR@IPB&DsnU{QsOUCNcMjxYkbZdP~Fs^^`<$-Yr+RF!& z6Ec^e<<~MpfJUYl+8eBI_1$i=#PjiG(YDn(y-C>a^wGBXrRMpi_B#q*8raa@e-Ud_ zpp!w#C%X7aiw1V_C4-&;W_E^Sm*GrGQ@D%~Yc!FnH<27vB;AXYElwj?A+j76EtkFk ztQnLH(%g1N;yL-HDxH7w4$Br&Nh+*DlvWH3532iRts=b9jQdK;qtFxR_ z@@dZ~1RpLn(}p95xKD~?P1jzJwB4QRae7Q&{PV@Tf{kf~d?t%)x^gqdwN&_q{v=o= zsZ-3v9nN{4>g2am^nAcD6$bq9Wx^n4>{7WWW$Mw-pAAxTX_=j|qz6(k;j!AMik51w zmJ48!Gh_f)4+wt(9yZ#3Etf03DPl@|INQOZ*`cuN@KfPku zSJ(A^Ab)F9&1+7!?)skHH6UD)YYr8vgA+6BxZgNNEgHDwNXgi~!b%w=*|S{jPUULK z*ZM>In*!Ax6@4r`NQ2_hUqlPxbzJD+o)jL0o)U&NyWKJLeroyQl%7%baS*^^d{o_k zOibnFlXUC>T~pB%2EGy{)%%EhN6d_ifT@22^mj$hv*8#40R%EJG9Z`EivcKqU64U< zgD?z*@B9iM!y#FM6GE<)Sfy&(VaiV14pgM28VV8#|G!YPN!!U!&-U{tOSpoBV$}fKcPOxi5VYDN_7*-^X zh%9fYh?*@a?AC*86LUx*Q}?{&JjJwLQ(}w#eF-RAiyF9bjc`U&y!|uM`r-}>%uuV7 z;TRK>5+0J1+W{q$;T{zOG&UfY&Wiykf8|$8Z`(!?zUx;k&>U6=t@r(CfdUCo7wE06 zZjKMM$w-7LDiP&6{r8;*B}<7MIcZQdhym}n!=2rk`DS(~YOxSn{5sJizM4-iE^QLV zE9avX^Ebknq_WK-X|IfnVqS|Y8KyI1Y>CB}dtG?#R!=~NtpKjNTf3LL( z)v%mi&wsnPG(i}xiY|ss&{WK3C zx^H-PGqqWc2UHA0^S0Vl+ff011eJBCrnBIKd^zrG`w9$$$6~hg(HK=iU>`U4eNSe+ zDYBg!+4FQ4DnB0>t6{ibH8l#Ee+=To8?xK5(6v3BaW}O|?)0if)%L@7JfW^P%`hIP z-)BvK;BwMh&X)~2s*hdVyW*UC43kA7%6Yk6Ha$PNAJ8z)s&Q>tu93WlQDOAAY=M$b{d}K(tAr~)elrrR=V8hTb+_L7DrS*{t7nM=I_~U%N z81IKU;K8dDfhJo2d4GQne|T~#=&;iOvsnD#p9>rbhXBwqptnF_&(a-a))uJ{H1cNx zs|4C-b&(eU#+>EKTKUs>SqfZaywFY+2xXVJ2o;3-L6b)S9Yf2|Gu$!!#b6+p#HIrd zom|ns1@jK{9R`}TIZAaPmbIlsX!aB&)XY|TRFRs-LSux5K&6lze{M~54vZ@%@kHGA zAnsfu1>hnD02{U}p);0!D)OF2Botx-vMm(f4VPle(0|pM@XC6((@e+A zVatGT2WLNiWfV(o(9-*!pku%_$PArAMQpP_qSGGGnO%OmW0Z6zvHz3mf(k+goqm$R zlnOVC{A9D>J_@N>Fh>?!rh6uhC;P-F>ycK!*LH9|VL6NyH|&^t_jxV))6_?%{`Aj9 zAH52Yh|l=Fs6Y60Ir@Y-{=TrqD-TwRQIKKgE|W96P2ki&{kGesld&TA12r`=m(Gg; zD1Y5o>u=jO5dZGKLcsQc24a>Ek(3H-K-1UKB`wyt+kmbg6iZ38*pe&RY4hLj9<*bp ziLovzHcTIQyyNS5y5HSVC1;6BUJg{G`{Ti*7bYY+l{WPz8J{Lv2bq~H2`ZJ^`ea-t z?}ZZWmQQ{4jpStF+9Wqg5&ynSWFU7pF@d7d)%`qVKEO&}wlqt(&vq$Ob3I zKfOEJ=kBBhszq5bTQ^K!KHKMWv`e&-xym(ZN8MzkbE%Z()Ap~1qf|NA;t#`)PIK^ z%SxiUpx8=5vJERZMpX=4YTmVHT`}vK>y}MJ7D1+Mm_B{;c9>Z)e*XLD$g-&DXt_si z=k>HISzN~z(U#cVPzG!OL%3B-im7dtCT-VMlf@KFXD!;O-!={k!GbgHEt|6HxC_SF zi^3j_g1w?)8c#2yv@E--?@^UB7k@8EmAFaW^oydIRC~9nR-fV|E3QzPc8N?XJ|P3= zK)YbcqUC9~s1AeY@Xup^vN8(KFBVMIXQTMr<9TqO$EeTX`FQYgpg}E_=rtU?a?*ki zPG*DmA5>DpAZQMvEcrxJXNh&0^l%H6Oq1imFAOel-(2S2c*a&HwNG4bWq)Slb-#~p zt~cfZl00lf<3Fxpu(1z76Pzs00DEh2(;7)eo(^2Wq~8)&OlB-RVQ#t}3n3ESdf)It5 zB&?@Jgsm0lRksU+4pLGc()(jDOGA8{i9%v? zxMZ%eG0=>H5)kC9QUo*05lWFz`+!FFXk>@DgB!yR5P1l$PKgGIrXzu?m~<>`wuB2@ z$9njbgxY}(i4;r_%6~c~U~3A;>#>yf1P+6RceD$fFvpu}8dKy6NJ=J4CKD!jy5@D- z3d4Ik<`i@J23ZTi2nNFcpBz@mK%S1x#dkvk&hugje?%Nm`U zNuZ<@DE&Y?r*=wh%uBc;&*{LFcLUEkVXkLx!DPll%ba2EmSAsaULbfwH`$izM0d`l>u1^|9RQ0)-%~wSo!Heab{h)K5 z+JKpGAxZ(zWFk)a3V@>eDti!o!gESGWB+&f%rtu@Cx3=(2ZdW3@BUT)M1+Riexpj$ zG? z)N%gDB~)MaqGIl(YcH_8sv7wF4wC%AX`CK6E4kvspDN-GO-o}LR&N20y}&vxpsPS} zaCLV*h=15B8C%EW!-Lm9Z{Uofh?V#*$UzA%y*CenIRlu}%KtYp_a#dFw?xUvt4ur{ zY9ro2@g!bjgQXT#TH@tx?;;0&Nf%`)-`oqxpT@P0S@dRE~_Zo>OJMx~%Q<=gkxxTI~b5drt2$cE@ z78PvQld&Qbv;8QO1GA7W5={{{H3~0GWo~D5Xfhx%G%`0hm*F)56a_IgH8L=l&x-*l zfB6MaoZHfX3*&CVoxy^;6C}91JA=Esy9Esn!6CT2ySuwBCUQf7S*d>1+jHVgWF*b2D*pGcp3085z0$V`%HZ z4G;#pm>U6P=mC5lFJtL{8PEd$eK-IndZzz|`?vRBfy{0Gb_N<6+FIKIZQRXmOaUh5 zR>lB1QE7T7Hz!&E(8lO5L!gzTf9;1q&;@921vL0D_`7r=0gv}j{4L{D^o#Ee?YiVQaYUBAIGBLL? zGWn|wBWF7X6&rJVXJZNBf7^VB;Qq)=jhz5&jEsyN>|6k2dw{W z2JTPv53#Yyzxd<+9n9STT8tm##{^*f>*v3(bUr4`$kxWn{g3(ISIi)(AucbgM)U8M z|Em-fv~>e`(y_4s=$P4t9WLoZf#LaryUTQ2u*ur~v<)LDu$To{a&Nf5u;%k&V&t;}_Ha=Oy^t<^SL8{}tu` zb^QNtMWW7DR)6a$|7Gz1qX$}>Te<(+;$xnjoj!I$#`a@FZ2qsQf12^X7Fy8O%IN>< zB%FXB8zNw1YW3e^G0?QajNSg8 zZ2$wkjjhv%3*e(Ue{X<^tpnU&H_FZqU=aLE^e^H7FbMr2P5^`Oe~E($z##UAm;nsp ze~1OZAn}LT01Q%p=p%#lANt53^M^h%$o?TN0E66riSr|a;vf3Rp!A1W0SwB2=p&!X zANt6r`d{Mu$OrsGANdUa&__PQ|I%Nl&tUWq{OH&CANWy@f60IGW5*aw%w7JW|4U%? zNB@_#t+T^F{67p#|A8MJnEeAkS}^|ye$;985Bw<9`VTUF6l(Ji{3z7+zsUMw`|&>X z5A{bWc7N0#r(^fAcDDcMlN=bm002nLpyW|Be4M_=e674j*p{e?OW& zw&Fkh_dAfWv750W-1360;g=wbnxMAFDgiuKy8Q{>S@M0g6e>E;Wrud>XC&xEs>&Y$ zn-2E^iNif8Yr7(pcVAbCUOi8m>!3qh;uTtdd%ftze<@Dyx56z=VGc~@p9s|U6Tsrr zDStiidbRgb^|u6X2JMt2&$f5wM3T=%dvxs+bF1wySse>m*jG5HWS4?}DVd>*Qi;^| zFPtOKG02$5CV_IIBY>esy>vsKyStx7&6<2Cl8mE)^FEDYDe%?wGZB#E`?S@bhTGUVG&69V0ZM!t4rpgn6fapy8m$>`+vDE2Qs zf1wiO-RY1RLxml3!Qo$4N?9G)sM)m~g)^^AdU%EC=YBW@@()-#oyjwY zruKffA`H5ts6@+nIy%jQTe8~*VpQsP1SzvpZk1NTNq>f* ze*r50SeXoHfNf9>M`aNZn4c7$OM%-IYIZqozgoy;<&XJxz+rf17LN`_(SoOC4G4UhmY7_O_ZVy-)$A>Wub< z?7;zkc6(0~%O@nrIRXA_D?Jp)?qZn``NoG5_>O3I6D9Ye?S)Q*txw~<`drQgcF_a( z@;gJZRkF?w3slm)&Su5Y^8qtM!V}9mE#2~S-*gMTu^XF+AiKKe;P&W>COlNAf5%q| zS;`K5?svrtT(JT@_7%9n=7*tMiI5hy$LSNMF$~>WN-*LAwt;Oc|a)J!L^_A4GOJ}fAt>@kkGackp&6yu}Muh-akXQ&&FZY#(6c7Mo4#n zSXzKcZ1b1vd-s7^Ssy=(PA~651_l2D8bmolv2sA1{urA>g>=jfcOLd$ZT`^nR(Z#`&(@n^HtM2`K5WreI2y4DmmZ(|aiuqmXnyg1 zIUnTGK?+)8Lkjdh3~PKF0jGyCm}8bm)3PG?R0oP|3`XZL!vA<_Av`8B8D!)rrNYxBYyYrRQTC{FBk+oICQG zpw>sRP^8wz!t%G%X+>e|EqHMWPh3A;c+Et*^wcQ_++#yzA5)+yxo`^)v5eRjcyc$? zSxX>W+0ck%E)mp)f6}3nhS;maV9p=Em^2HSp`{ z`0(w9Iqnmiq+5R14K8VB4hs3y4qDwk-IYb4wi=}}<&SeS_&)k@qhP9ULR4_qEB z7#ybNSAGO)63C-au~wNZ(8$@T>xDV_0N9eWViYyWc+9eeHe6HMiLQRL$_t<+xSAPs z`ieiXn2UG^1=MRH7g(QqJR~Y&JdzR2zJP0qWV3pr1^3x`C^D!${X(LHZS^k#>PbKz z)W=(!#g`bHe_T_vHTfNC*{3%a!q8_d2r)Y2tK>cqoVI^1*5FLWddTsMdVvHxraq}M|_M<7*k^re% zfJu9Hf0#S9(i13>_kFmzm@2y~un`n%o6Nc<#DxdNLsJ1yS9<=CQTABTKJA`(m6~JN zSz4}bg4e)z+~@p7Z(S1hRVYA$pNH+L01{pq!Nakz?#$a+T0co<$*-h?gd|Ikj8{SN%6F=jS{QAmV@#*<12@ zeI=XnsA#DU#l&y@$rggy4`Xju6Yoh zG4faW@6zuEFZ6+;21q}%G(!w$9=zZE_;q?e>j?GCK_E_tGHF*>pN;`(eV?HWNLTPbBmbpyez62jc@~ef*K7NzIpl(5| zl7%$CIF~lLF%g|(DCCFF0~t%OMVT1W1CA4CuOaRT9y{sWc?4*;W2HluZ6qi%f22CF z=ARs$V9GofC1K8kq%VrP`VL(fvr$CrT>I8(cFB(u+6{q5FD^Fxbg1MXl8*%j4I@uT z$5YUOuD48;Bwqw$uxLKP>jLe_C}Ci?d^vTp~uVBm^b zVEXiR zxgnFh#Cq)Z1HDzY!W^i@uqe4jR*`%i9MgHLhXM0&MYWpWh766hRAW%{f54y#Ey)@K zi%(u(<(J?0NgTNh9Np!-qqcO1isXI~2U|8t_>zJR_+M=fK;PK~7=QJcb)hSYa#dw1 zFCcivQs#b6xg^^Rj`igpy*2B^eR#i%k$Jc1I)pCDLRi8(C65&a!%_`;UkMZ28FFb1 zfa2Fz;@&#pmNd3g92jdDe@1@v-Qh|v1&PcaUFXqw(6SjyZYaMU+yIL{fkB_$>eyZg z@iiyk`g|9#@4yZ$rcf}K_=PJCLB$I6oTH(ok zEqV_lu~3I>Rd)n`m2tpbIu@y{JI$Dvejzy`KBYFnrb#CTRS^h}f14ZuL!jknLG9Xg z<4C$>VE#Lx@V5<_N?S3Y3 z`^02=PipJJKFf14C?8c7GxWNHhEs%%>q*Se@k+Y<$Xw65MvZu}JfIIBY$eX#<^y?+g4Zpr7LMq69+49?!)70X)4g!x*- zJ&v|-m<$4rRc9N*_HLA_CjB`7q>=gyxd zr#B1=*~XfT`og`FSZyG3n60W4#MCgOdii8P8%Po=Wh=^PWDpC)Z8^nxAIsV>VHMLI zE3^Dg>3P^Yf6l!I2a{U=wxL63EZMkZfSWjK=s(YoQJwWNW;XobNP{|&>l^VrpjYph zo;jdYgOzbaKnrv#ayJL9zM39$cxxuFyB1}^c`-#P$STz_S zN;}KJ*@$oR>dS+9vjCo6$9XsgoUN$dbgH4{ooxEtf44^>8~xm8mqm`&94Zx=8xrH4Be4cekEcPgi91n`}HR_Ac!Zjf50b#o|Z!4~X31*k&sa~NwR z-@ofxS_#!$xFff$k>kG+QB9HCG^ovs{*Yq;L6<>EbuafFMxQ(MxzV(5KPz4#GMC5= z_9y$9eXyhn3l!9eRWm(F6=Y7wdOzG>brvLUMecXJzhA{& z8#IXJ#MgJDCReR7!`;x+6Oa^3r?9_*2!ahSdSwv z?%lE4ZHqT+2ba5a`P*nxM85CYFa~~Z*R8vHe-EucN2Pn4`m*5NOG8TH1FLQ)*^s9d zzcP55oG1ugd6ycEbioWQ-uo==I@JCmt^{Xoea)JVy=#p$kN)ucF<5`{&G9~~@ zQXbQXlFx^0=W}nthD-O3?mG!gAY=zsd#F0wAs(+8xa>>-P!?sWrkFg6336w_1&V3S z)P?`hkCnZa!(aS94)cWg?WSJ#_O;t0e|JZYm7u5{eYwM6{e3^bISSM%NA%kL`k;3I z?&|Y}=Z&j^7L8_vA&Vg!{c5ao3mNR^yD zX^*nOSVej78B!<_+;}>D`GUkH{aCX6ev%jw7l#y!0`&KmU7kGhLp{m-`(z9Tf4RHl zhKhCmA=@@>#1PbhyVq$sTc4I^b z`Lz2ApL(b1=@}5!d%HnIAB2r?f5tgFNYS7PTh~3V2P8K&LiB0%jWyUkl2V&1JyFT_ z2)PEm&;2$cn-P+GPb&eKGCntlJp{AjYj`;<-!|OM3+aNSVXzX+p7ucp_XvKVJIIFb zkcIrAhJmJL*y<27h4w2r94nIFw?~!M$PZMT?90zGCwyhaE^>4k&TipTf8VAl=`2SL z&v4;7QdaoKKw(c{v9`sRMlzcM6r+(Wit%wN5riZPyZC(s;4I<&nx4=nEKsHeBP67k zkr$wd2+|rWN#{=fV`Z%7V54)Udz)I&c@24;x{%W#VFLRWADo-x5h)O)YNFB&^> z@D-g_U80^#CA1j#KMo4Gf8fw4X!!!IPVn0^dtqYHhjI;TZq$64{ZR>3){ z(PADf_Izv_+duHU)vLvi_!w@hj5e(<%Da>`k+R+3*dL$kq=@Mmoqkc36~v;LT;9#k z-EbsAMO#hVq{+DMtMmMT_Zmj*e9URO+;GKaCT$(z_8OgPW8cVGe`FPZsw$YXbhz@7 z2m%p_F0j6xyGnB@53e+!?a@keD+%!59zxLw{@R$b<$y1Z)!0SxOvEzEtzRI(Ar#}I zPNR2_(xFHywkM$4=cE%MykUgcQAZ5B!05L_?eDw^x$1Fiu!mI@kWz(rQtF^FefG0P zHlix4f&69~#}o$Se|iX4Mg6ncco=)^l3d5(&GXir+5~g8?h5u}EGUwPSmoIZz+5(a zW}@`<)!n3BPwAaxneR8fss25#AiLNh-0RSZU?SnmkdgX%Y(4s2bhEmMH%Rr5v*6$Z zV>Q%Py`wBED}`b-_E#u#+oB-<@1i`lvA8UAsV|z~Z|gg}O3Q)SP6WHs4-+DdM zKZ}${a_3s|0+7Rh;a#QS3l>#3N_Z6{!e#l)ucTL+NEMq~x)lIo&ON%V>ze@Zvnj{&591^`syMWDuOVQUiYkn02oXdR*X?*`BkuY^ z$Vk<~3p8qS-)G}=bR)*a*?OaoRfsC&Y;b>5io}d>f0Q>uoEG4|GNjrcP7j>E68FX&|}arUyUqnMi$v`CR@xWVv1$HUUH$ zPnN4z%!ii-IMEKwVR&8)X{D@#dxz@;ADMl3;3_d|njAVH*vYeLpCN~r^5IzHQ4oDQ|gm4GCA#>XtD&JUdb7NPXKdsSAgms(0mHUnd=RHQNBqpHpA*Tn*fA+Df$ZcNxBaD?{G)N zq;G5~5TM9Z(gs%kX)?N6Rv1lw&(Oy9^|P;T7JH z@RSJ+N-jo^aq7D0Mr~2WkJIIs# z^3+)mCj`Z=W*$O|00pkT4TCMuN1x?{iO+8H40uv*@!QB&d1CN5_4AU>Rws<4*3etk zy4I23*TK%uq@tYWyRf=k=?y&bf03X;uG7%QG&yvIR*mg~IYvLyUC=K0_5_QeW0~!? z3AISDFmJFe7J&nmDK#sT#*UVOZ>)?^XyyC?$hYPCi;K3Id8pHI(z^4;;i;cO;N=3R zmVuRnriWmXyU+?Z5{_C{w|8Og5&>aE9xsy{Zhg!0WpbLByRsr0Sk6zTf9OyGFHn(N zPRTm>^M{BK1R8uU7ndZw&1FBK+r9+-kQVTLs>EizGHQo530QCQ$2PI4NkqbXM8#*o z5g=EcInUNu$(OpC(OYcr=qebNN8~jGSZL6H7wh(hXmM!%A~w`=ATL-(S1ktOTH)q& zoOdX$c1YQF=5VlPdI+E8e`{b*6QO}LmZK9_Q2U_Vkfg(;Y#>mPF>@fiE`OKRMmk_R zpP#T1y7a)Syo=TIV?l&757QTO#qsGed;kjJ5W2&i!@sgtZ9jSclZ(5=9!-EuChbVY zZX;2A=l!5_ZIKi--e=mGux!h(gT`2OI~>-WP`v@la2qk2ouQyxe@F7;+%h2ua5DME zVCQHnN&Ai8X7O(0;&PU%NUw`9lP&>~=k_7V%h@s!ezRdTWYSs2Py){9inu_`@f}n$ zp5ff4021p9S^>@T010JB2vc-|YGcCH+DeC2Yq}q(3}PiGPDzuEK{-P=-*r1&m(6IwD zuDJVD-*VoM&M)iLxOFKx7ayn51F|=Zo#TZ_JJxlh9=A3$d@>`u*)HeXt@Ebf3;jxJ ztvEQ+pCiJmlgEPyVZ&!8Jz%OstAL9MSkQXJh6a*7T5LWde?z~|Vzd+Zoh1nRNA-9S z@~H52sUR$AuJMvjS-)}@f?0Puu}VJ=@4?FJ*IyV~p2htR)A_RBbFD3DdGzRDe=-j< zwSO<-z2zpZ6yRyb->1~XlkM3KL>NJuySo%`rxBEV9YljUG?2%x`Qped7+KH~OwkuD z*wVB8>yZwUf737S=du05XNZ!;seZ9Hu*~y2r0B2AOaXv;%#3Ih1Eb?%OMZ-*Np>DE zKK(%hc=9ayR4^1TxmJ>+xx(`@utX2}o3@&8XJ;s>dCedqwut6Z=+CH1%Du6ay)368 zS=Xr!c>AI{hexu*g1OA&P`PwfLtXT2I7{M}ktLJ1e=n;)6F;4!kwR3d+!s4_Z<)F# zO(CSTEfeX+V-E$Te%9YO%meyDUaOI;MbB}^@|IR*=L&HRRlkXQdA(8XQOU~k017U3UCZr$OrhK?lJ#8<$k z@vO@pf5@3WjC>ZePYIdE;DbChfbbZ)k$w{^`ML_&p>0w4GLnF{q!i@IJig}1)7?o_ zUTk=0LT-8hAG?QQ%pN`#O&JI%~QN4k(DfQM5xo0cNjLz zSlw_zg-CVTqp*k=I5d2?+Ki7It?Dd-5?>L4f3{)S^dg1V!Y1Ha>U|zjeCAPsR_4dW z%XJOV*PV#!NgqdZ`c9U=h6f@Vr8{n63%vjP&m;AaOH_**P3>H{2n5Pbal7GPA+^*< zlx-r&(BT8OvRSwj)_Kzg72y|O}T8nR3mSc~7w>+1Y)kdc$AN$8%SE4GC^OH~#Vovg{9?5?I+ zP^CU;!<_0~Sqa&c8eewhRHsq`wTan$_5%1L7To8OQF;xq!l*p!=PBw z?e3UbiTcQB0=jQNkOH|NBwZWjna7dpe@;l5ejDQ1i`^lP`UNnH*itS#;-RKUP>!$u zS}ka6Y*s{&Z6BG17AJt?C%)aB0-t&uRwM9S}-%rwQukkmvTCYT%z1EvmNsQ`y^9NZ>w%q85 z?e@A`BB<|sapE!Z^-o^I7bU!#NMr~{1^fmD0E^@1&y=p+8#C;3Iq7r(f1tdD=!Df! z{W!5qeHSP_Y9uNb>Z2~TR5)MS0>Xc&OX`NnITFb}-)}iRRKE7Yr8w|D3wA#Cl)Y(q z4U>;XVd)F>fiF)DgGFhP6W$y}TAO`G1w~~>NFBj{Ow6y-D20dZoH55Kf0M0ROkflZ)q4A3bT@)Jo|eZA6EWq;2TN7QctS$EA-40V z9Ra9-^P?YIkc-``%8~}qY*?z|#$hk1U*FK}u!??Af_Yh!J34p)FJ z??0FNh9f#Sa?W8uC#bmUI!i8iBv6R3HQM6G{S*ao9!$91{*^z5F)6rZwp&mo6WG+btDhjX(68=G zR0?2vthoei0wo*H26(-SaU{zo;hvw5s=7ha#ELuZXt}T>LG27MssqVJezVc3ZS7>4 z7*<<7O#e98Mt{InOZ0o@!1hgbgyhb@=j*1Ee8<^VP=P_hL)!8M-(rl-kv0tQ%x-Do zm+CbD$#a#X5ltEW=HC2r(_-2bZ6%iD z{cAns!A>MU2VBX;{!LQH&Tldm#6ts8DPKsfG=9w9-+#|zqYbEx5f*iEdB+`{=;w}F zXrBr!1;=KI_YUiN>17vVX?5c1S9A$S*-31QY47V*pOS!67&H z-l+;nUnM`Upq_~#fcprkR9z%&Y}T-&*pw=1-rLNs9!9yP`dTBWBY;2hg!zm$ycGU) z-CxC%A=e02#LzIVNMg`0qC7UVrDD)4R3Iyi8iZ^dmS1HQ==f3zJk+dMp+ZuHp55C# zDSzn<7sk_G+A%6@ABtah!Xa3nUjou9qCwXqAcos)XYV3oHR-ma;A49+Dbs`MMJ8I= z?9PJGl+j}&=@nY$AQ_;Ov0Kz z0$F7D9)D1}OX3*ucx+LmDJM$`gEObW%ArcP1A*g+EhFjzdl~*#^|<<<(b|DIipAhU zU%<@29vH4E75&O5Y%?3T3$xJqya;|VNSL=U>r+VF>+YwkQRF51>xT)W+B^-`g?~5f zjbn$}cTv*=Nx8K;M+NpRexxQjhxyZIzn-Fjt4%o&ns>55K?~C}A(RUEcjwV@e`(8u z`?rBB+ZXvQzvsq=TDoiRBSH@WvXNgV2tZVePKk=-tkk;cF3bxxj*a6;?TG zVx(n=jfk?fPQ~?5Y5~O`SI-AFvvvGLy9_$FneY;7hg*f2w*e#^L&PFR`|ND)$T&vfM6gLXdN zqtR1#CTOW5sDG%w(qSAQH6v)$}|0-KlQKZ$UN&RrxIX?2LMK}yqFMp9re2qJ2 z)x6PXl!R$Tmau?;`c52@xeO7=CcuxxQ+gZQVQVR^dO$bXL@R%q$xkvBaQ$8Oh-q!b zdf6KX=6FVdlBxo{j_CDpyIo7$o}8aIav6IG4c6xsW4E#6M6mz?{@r~lBjBOr7>*G+ z_mGWej;#ekil_Ar?1V70^M3~(S*G;s_2nHM%w0MI427e=jngUN9bx9LUwuD+zz zfDne*eQV^KkX0n_X&IL5nBFyioAR$$y=j|7?2#d?wVKA>VIh3pr-}kdEilMhF@Pqh z_Z{iE$2=c4oj~t8l-Kgo1|Vr`7nFYAz{s}cH2$YGS5ft#(qY^6dw<#aw~J7R?+}%D zxVVS9o1;4COwvTh5^fx2Na-Mx1Ghz#i|EDIpd~2&Tj)c67Zqy zn*0eic8^%4FRTzY0~EPr8#p?>(C+#(wO~fU_SmMsv%f>AdLNuPi21ug6Yf zBtL-vy4p&vPNK{A`hTjp07m21`D!MDS;f$ijc=9oD?l)2@4Hl1dHW&T#GDG+lgI8P z1Vo@SdTz7`JGu19I%aOdq{$*~JId79NvY5mIVo$ZZyadSESH9mTBbbH_VwzG&YV0W zW~)kHs4i7zaMOe83gpA4!q^>1R3=Nh6Mbuh=Euei{7Yrc)_+_XN=lP3$*`4ug5kf5 z$8;cuZl6gSi5*r;Y7?sD5RF@5+dyJ|j%!)XPAQ&F`ek zeNp~0GVlH5A$zC%5L(XomfEW+I{Ewka21T%+blGZ8H(k})LaT~Op88!P*o-wJZ`P4 z^O%S|PC0_{B@HZ0pRGj?7G;iuUuwhSzRSg}Q$JMCM}H-uRXNF-n;nGIum-s&Vbb_SXsCn6dwkIME9Ocl5Swl(N{VRRenZIHG@ zFLHm2aetHE%Dl+iB0QS>MWIZfBVhEEn;uimeHVw1!fkAn3C__9j^J8%#ttEh(K*38 zIgpS8$75r#Mp28$0AZHeLe_gm7fg#tY@ZJvb>|#CO?lBR<)sAXzI_d9(2b4yV9~`2 zKbXvTJEN2MRmB4<@28f7rY<#piEKo{xo5yke}C36BiNM6)U#dt7;M}2NO_Ijr*C~M z?)e+3YFx7hfx+ZSKZ&*K`J^GVI%;!O0xR<+q$5HGCsov=P~^G%2QCZ`GOg^GTo@CZ zuNqob&`AYt3mIUyalyD@qn9==H5M{vcO7d(u4P>#aVG|wIq4c98_&3k!hWbk{MI{J zgnx8V4KS#oO!rZ2K{)F;BC`wZv!MFY@t$vPd0h7K{YGTb?y#91-#K`WGCjNoOuwvp zMmj?#Zgj6z-?Tp~o3sf!o0!+jbr`CpJFBD{fQ(_k>9eu=T1Q_r!AYlWe#7GRm#ZrV$*CE%uf{ z8REn941QI{6PlDy(O{{O89T5(CKN0zQAeUs1Vzw!&{mhr;{MaF;!-1}!Tr4_OMiYR z!J`2TdYQIzZ(;e&eml^M7g=}Jf|!=IN>5s_mqk{-VycC6>!?unTaU6UNK676Z^HdT zGr}Og712 zs-pKML98$8b9r^aW+0*jN3o~*@f3;dUlL%43geb7jke{-F)s8nSk5i&G(-F>%+@L` zrq~sI@-(7T0}9@=!~I9!Ixs=$iW1YB^ZV}ITaV426p zmDg&{{fo9djn>*YL|jrr;dic+s=p%b)-yc*66b=#%F&JUxNzH}$c3_#tRy7!5UR&M zO7u(B1JVly)9zsjpxkI=L|ZkBe{OWgW_az@J-k8@KhJ65HSVY%Vi5<~gy*W|zkPxV zjm+1siv6UVo*lZ(&LI`t{&IcLS%*Mn&>d+Q|E3A*!!YSDxM4~ zgS|drCCGb-sfja~Wa9zlxA3I8I-KUS+!rpL%aaiE+d!#ADD~apZly6aC-nOmskkG8 zq|WBUdo<5;^;E1dYwddb5#91AWkzl^_J}Uy>Dnexsw-{vX#hg8$A2HYdwa?9Q}K{A zK~kbE0g30qNDy#U17u8ny6RO8)#57p;VIyEy}QBQ{rqNLOApki8j4XyZ^@1za`jI0 z38QWCd_lga7s}##%w1q(MeScZMTZ@0GE-zP zYT=OF3&w~^5)&qWRDZqBeVaR3+kY*te}aAi?4KvWXxU>_u>1GHl^XLzD6TeyZZ~>| z9Y`30nqQbx96D=D$+RwgFW~<9;!iYCCN#R1{ccugO9e%2xMH3|ZZC9xH0NZ`A?D?> z-(=!n8WI(3bmzrRO5RfM@?&}%ke-8m)8lEssg+3|G}6^EO@FSnqWUP6DY{Oxsod&< zQz$isA^b{$g0rr3KzuSN6zA8|rP51LCNAp>^tSc#10@=LCO-=t(c4`ZYhWYZPBKee zf(_ak2TjE6H7@T>v~L8sEW?&9?6j^Z<+G3!{seV~A#QwR3Mbd}Dfx$-7uO!ZEr#3n`RysYi%gtGPUAD8ZnaUYC6dms801-(SwKamRR#fflttGJ{~zB z1&x$dWq-!sMC4qI^N<>%v-!Tt!4($WMQ1Asbb|8@Sqy49<>k?^jl?mtF3_f3!2ZCh z;9R47qPMXB!L5ZKM&z#9O%!8>r1Ile*zML~zg4^{Q`X_iC~^@t4&j{oY`lT(3pOl4 zJ!4Oj07HD_YSj(4!9qSWDBo~%;e2rC*I zixlUglFbM_B2W3T!w!%B|U25_`+ z#(xW~Gr(u8)56LQJw2(0^WLIk;!!?-W9R7L_vovuDAhIJ$hfEu(!jW#z=Ic)QYk*% z6EBQ67{6)wjeXp|>bM$epE6dfVQEYS6%Aj_gTd_agWcQW|?imyL9U?x5o1b#;O6 z5Bx<{jB(hyk!a$ZS4Z8$qxBm5(|`N;d=Q=})6#VZh;^#t?}W^SW^}w9DiOP2$;UIy z98-j*eesV~p;&2I9{Yc%UU#z@OiO*Xh3x-QWzOl0oFN4GTdyTQg{Hi)U;*3vNvFn>3Uw^{S2ObZ=ew@!gyx zF)dJ}n}v!_-nT9v<*UNlM7_o+nNDY*a=^KKN!@Kg(kKhRu7 zyuA~GQx+dn6s#iq`}?#)wDCe=>^2p6DFXHJgaJ?7%uJk-fx1>AHh&|9otn1n9gYU& zV^;?Z57+4V{K=SqQ50KbP(C(8()=007W_mB$>s1W`e1Gfn-B#TrrLB6uRm;7N!)WW zh4!^tGgJVsVXhMfQ+1w0=vH3UwKcx{m@KEofOZpZaLNnc6ft@qAh@H-DF(6jJE%oo zPR36`hvqe?O1e~Iaev|TW5N4dOOT#&2`%`Y>|+Mfy9{USnliB~Upwf5q5kX&^LOk| z>1*`gsjCqJ^)yT-v8qk0?DPjBUWzA$D?;}ziofaJHz2j8rTBML znM=D#IMD7ts!7o%Iwt3HFu%T%IBd{3GRPmaR=mGZIjJ+TU4NhGvDIkWrXR$Gv~AuQ zlVNR!DyAs*>+d5f8M;;Xkc8f;ik~LG?1xfZ&&~@7<{cU_PFO=03{=S4 zGWwxAdAIv&5zb{w6E}35#Xc9w%kb(40Z7Es{cxHK#Kr8Ifk<}&gcLG;j@B(sxEEs! zsfj)99naM*t8kxn@Z{JXs63MM)eyI~<~-nt$0qh0lYiDPq0LRCye?c9S#{U~IIGAe zEz)!PNp5hsoP=royCO?o-A+&Bb0;+SB*Kx45M*WG>+*T5xNwZH+kQd%Iq>ucaO#?6f4HyhQ-BI2$ zzPxoU(tk|=UaIl&!4_`lG7pOr7@T=DQ2{x79Z_GAv;^D6&B?P~^i#3jF`s#bNG5_1 z1*BT@HEEb~@<8Ez0xeTL|EL$I7*->(r;Kn-cy`6miUbBkqyDN%_?eBizOe;rh!&z> z;8Izc#&34}wDrqXM9S5mr2qp9SWcy#S_yuU-hVkJ<**)g)*5=Sa3yC8f&6FD>ih^d zrlQAsHZ(ZX^Rj_7wy#5V6&$T;&iPOrM|;dHxy2jWk?UJsY>^V@3Q2D#wI(wX=2Q9t zQK1exK*f{VovfohVO(nBsa7Zsrf&0omY7Pux^ENYWZ9dVU>Ev%*I(7IW+& zw0|w|EF5de?ecsOtqy^jZ_h?>XcN{e==o1g;In79kk_ip=-s0y0-K+)>Kb&6s(z6M z>8=ntJ1~?P19LV%yXSU<793@tAe~ST=T7T`7m}K_0pzwZ9eRM>=m8xe;X?~4xQl8i;*YYGr*1ntr zLlRCHk{(l%;HH|=jIkj1dhOoO=q2qyK@V+E%yltMVX0~ZjmAsp)o{g?AP)v+Lvjs& zI^dMZiIUvI&Ern+2^i&e+Q|-V>=y~~=AYddOvd&tOXPie6_Wpd07X1wyq9r`0TYwr zw=E1=NKj5!D??2}STQn}4>SQ5lQFo90amlSxY`^LG72wDWo~D5Xfhx&GBq(Um*F)5 z6a_LfIX5|%&x-*ke~k78P@UP<1&Ts&cejlOcXxMp_l*U2ch}(VPLSXP2_D>nI|SDt z!R_vJpVR5{zgKl{Q3cj$Y2zmR7EyH2?hsP@B;JSa^82 z=>KvDh}Z$0t<6mA0SYFrRzN#YMl%yzfSQAuHPF@Te?n06Te-SA@-i`bcz7_H*tsw| zI9m$R&;vZIe_gErsz4W@vpdin@S89|(Zmk;H#0_fN`ShRwaedfH3th<4-;n~03@)r zHUrwbfIQsn&4JDUP;!8pj66We5orInvHaf#^nm~L2Ef9|@=v(`c>fM$ZU2|EiJ6&$ zoui4pm$khmz{1)V2vCxgXLR*+r3aYUoBuX6v2}3(fBBoZn^@bLn1T%cs@w!1DWU=} z0TKKUJr^@)Ye!cXMi*<_-xQgChXHk2!rolW!Ojk7@9F~oyFPJiXP_CV?OsfOpX>*F z2M>Fn{{RbXdvlB5B+T6$nKbOJo!o#j;{P!LiQxapEP<{74rXR%E*>@j&VxYy}7mTB|MGDE&sb3ZXJu#r|C>S40W`}%0QH~I*JtKnHUs@)`Tx8Cf4ThsoBQ8U z{@+Ib{}v?aW^4PGn))yO|Bu?l&f3=NKL(&tc5?--g@OZUIqd(hsTT0>RaO9+Tf5o) ze_ySPs|jd5MC>hX|7oMOi=?$D&|KNt)y(Se8T#)jfWq5a+XIyyT&#azHUI|Df&CvH zXyMF0fG!jl&{_SZ0)qDGe^W}>n>m>OUOZL~PJoHCvxyfx=;%R+1K`5~+E8<#=U<}@ zU}Cg)a0R&lK=k|o77otvzfY8t1HdHme_Ql7;sh{>{y|&-Cb2(=8^9#~2k`)yB>q8M z%m60IKZpguB=rZe0+^)#AT|J#%pb%KV3PfVK()yIL7-aX{~%B;3V#r&7R5gZREyF- zh#ORk@*f1suKEXova9_;pzP{@5GcFG9|X#-`3HfrYyCl>?Am`2D7(%-hzDe8fAR-` zEKUC)P+v@)P0T(3LGO=+>mNDWKk~n~4)-{uZ(|1Jn*e_;792qIwk9rC{|XE$Fx?11N^uzaXgd?*D?I$~^uxH6U-#e?d@quRqm*T)lzLf5-lx`_9bG8Pqe^zg{HJ zW%ytG*MA*ApeN7_etE&ce~d5GrXjTR{<8>y2gBZ^z%1pSRt61&&$4ru+aoeeDotHZ z@TT*vNa{!*>e`M3^^Ncf$&1g)mnN8q_GFcgC*NnIMAezS4)~>M>~B*gCnAl5L~w)* z>cacJFHXLiK_4K#fOpGM7C5BuNI=~owu637B=aGD?HyD z-vDz+I#wrvZM{BEO-}10qu&_r!qeODM_NaBdi}J@g$9KPEj?IhC9L$K*H(G6iPE8} zTqoZ3XaQv~QR!FQQ@Nj^Ov3nmf-glM@mYS9Ff;3NL-m7?e-oZ_6!>1o`_(jGD1P0V zLtC`w@!q)(7o(rjBy4b40W)!dV zB9Tw}!Lf8XL{Z8vBh|mRSUVD}AM9oGz*Ee4u34ke@sXogg>?5chGF8cIcQikBy51^ z*8K3t?Wa$oe}-5`4w?@aH6D?oBk|knT%mmdVFUAqKkSo$evb|~#iqDWq{cDa^!_tvYW{am zsX`U|f1ytVS@4#{*8;9n_tIc1C`f#qnP1xcoaNkDj@X{EG{nH5th2D2q+M$oW@i0v zf4y*t7he6%h$;0qoqh)Dx3}-JE3vzi>SY_<$+Q=J{@GafjP-5bEC!!>ljzfxg6xAr zz7BKsc!IkR=O%8-g8qF!;GJ{6(?}K>8=k-&L`tsucO5y#H96el5t?3l9H~(`ACpKi zT~VpLE_h-huT^T~Xu0>{{j5sNvzqC(f1EPP6cn~kM~~HQ49PfKdOf%&bHIs_nEN4o zSUkD$MJiTG%M{Z(?}$6ualA}=HwS-(YSsZ#d0awW;D2CQ+M0?7nb?1HB>^CJMmKkzn<)&)lWRSlJ`3)3d|Mt#oDqa}aH#6v1k@V62+3HDp|~9uirSq^LgVl@vmnDRrJ2K44tsIl1^29M z0Ei@!DnfDP?K#x0Jg6!ePGø|Me-&gP);|dJFPuis(f9aHYwo-g-TJYIbLI)sc zut3PWo6Xx{L0LDK^-v9yDV!eL4G6bt&4<_Emekm-nNl(@XF$^AJut`5n# zA&9Cj9ey|6Gf#Rnz43xx7{ z-gpM_Xctw^2+^fQRUz(*;$LGFq_}t}WaO=1sggyOED5&lZ8^QbBV^$cB$b-4_~qdC zPLwA~l;TB1a7W$4lLI!s+ZItBG~es&EjGPho&?icncfSbf9fe>4w3`B;$dYmS;JW` ze|Lj3&BN~#gXbO^@D`CSozG_jhxcN<(kt-%@?+hVMZ~S9Di_gFWQtLby;yCD)zl+} z&J5sMS#quj#K*NF6d!L`M;Ii_BqjFW{lrJd<)~lc;faT?^Fs>WaGgV!x`HZ6=q@fZW?3H@)1^{i+u! zmnb|j^LA;lg3(!&CyD~gzD-B0MvUcgz_rR;nEbASe;aK2gJQ&7jNE7Nf?2-ep5wV> z+aSqDYG{O|SjFq;GH|}F?NamC>b|El@T3~l=S|wqX#Q_yg{eD(7@-(d5H3AsJp9d4 z2}oiR#$lRAMOIr~BLkFJD#??Qr4Gtn13zZaLINnNK6a7Ku(5UCDf2Ayoa)B8@I-*W zH{Pise?~fWUeS8sRZJ;89d?<$8A@p-5r(!1LCi5E(pnFrVrBP0ue9|>*r%9d)%uCi z;ISU|?No`!^sRW0OsOm%V{}5RpH>pxV4bPV*sCg5r5-MFBt>5(wU0oOwrb5<9s4rw z&`=R@Yi?AmU>s5su12ZesMs#Yl~4yur<%ENf2!wPn*BVib2Er>rsD+k>#ScQL@bTD zThfV8e*6VLDG9D2QFMC!8hbG-7t%A2A|3m_p;-`IS4DUdMP_-+m9lvEEiI=dWfz_maE@D02ku&4oiYrm3(`qSpcfEUB0nNsJGU z87!k#fNsm_PvU)M9D9TkB-=&}qTaQm5&7Z2ScTl@I$@#T9bb3eEJpNegPRnSa^uaH z*ukf*M&Md{ER({(!`^f4Ny6y}d#M@tUxwws%dB~@br4-Rs!oO@Ny~L7Wqvqpe~p$* z2}WGsd_1p|*fi0L47Rve_GAx~4lBU&J%-VGZsJ>&B3{5m)xjWR6aB@peEqzCzb&m# zHv35r`kp0iGV{!gL-C%c%2AM&OSVJw<+|C03F17u#gh70r6-mOJ+iByUhNO=iDW64 z!L}e?5>*Nw15Qk;$VWS`S{mzSf4pe-kt3VFTdj&1`2kf?Ln2jC6Wi_+&qkwyMV(yU z1`dVtI>^oa^Ht2B(J&bC9W^M;1OXLKOg1H9TZ7Amq<$O5Dd#8RR9b|A!&SQrD%xKt zprtp<4^YNkWlCx~;R1%|8JBekFNK%vu|7Gcp&I=wpNIV|fiKRO`1ABxg`8-_#sw#Eprv<>q%N@yUNGg*wp+z9 zF&zI>QNS!sPk2l2Lv!gBQyd?R8s2+E!!I|yyRMM3^)|xCn4X^+LnNq~rAGNC+p$(v zoZiJ(4yAlhfB)qo50x*EfB&Nsf&J31Tac@*yckQe_5grm0zVzzDRFVY>3eCA&~D7M zH;b4WT@PWgGE2WdF>vIa8tViC+b7vHg_Y6JR9ouH*=7n@;&$MO${v%QqaueK7r537 zFxr=oQ7Zb;J`uuuL@{P4ZsZPSej1if9WyU1L+*N4D6iF zUd3!ao*d<&S*b)_+bQu=wt(pJxQqcopc*vG9f16LwjIq1d0bB=T;8fmhhZ<+U(NZ| z%Y*}+VK(mEn8Z4*(1 zy5oZ7j1}y;mIlAif7mCuGQCh&S2*<{y>`WRfR8Gzj-3BsCF}DQ@FR`I%&w$&wsGrF zt5DI7j2W1)nlx1!{~J_i(m5p1-5!h^BPdrgm{5O5v%ZRL@YUM6Y(TQ4=pi#hY<~vR{@DXWZT>eksE>x*2v*0 zmSL(;R^N+R2?cRv@`tM7z7TbsjeYLD6i%+e&4tS{scs5nz|0g0FpCa9vUSh`Z&IMX zN`Q6-Yb_^Ve>Gm5w%75oSv6+!wSDJKRBPP+UdFcIC19(bbg${T@Mc!IZ}ikBr3hN0 zF5{=bq@&59AwtlS)rryv2;r+zw)UN3*r zmvw{r+(&}@o>OEE`Wo=Bt_3vv*1XbJ1z(lI23DzSe~o}jK}STAnqOa?rlGL~tKAN_ z1{kDxBeyRHyhHNBvZZzPDHAl#+?RU5h>@nfcMNg2#zf=1C<7JMf3&r*3EH{e;?1pLoakvaQ!M z2`*PMe|8a~&dq{YW6hx5QL|x7os=7gkyJL!ee*I)*%OK@Q|uhV>sH+Oj|=!M_NaQ6 z8v972CvibPM`*fziz-VVD+;2=ia~G#;hzc*#!H6Zzevg5@^O5EF7X&T>44moad!GC zQo&{+61=H{X6;rT*tfphf7Lbf^YlBqjx*{Jf06jjEpI~Hia9ZiYAM7zAX&r}4e^Ab z>LWcS&5w4Is*;g*s~=N5dUNG&Z?I|yxIA)6c%f(m>T;DP+7!DUmLth6N+Ehb-g(9l zI1PmqdqK)jr@eLBpmNBUSIP94HT(Hm5%*9edW-+S(3tA`=+U7QN7waIt;;+4^I%}A ze`GL+rTePcHeeapLoftx>~=5w4&N8D`jiA~VJ-5oDeIfz3MauiQ=Zq%ld;J~A$r*` zQnX&(WHhSr_pjp;dBuGm_`Oi4Cd34Yh2HztSMnyIIOu*hqn{5(grAC|_xuI}JW=+4 zYPCSYWbWBVxWs2L+tVWZAlKOn=~jAQf5)VbqQ?lf9dMtKI5No3Pz@J9LHv|676ceK zRZ#XBrxl&AcaOMK3AMYAb$m0_e~zL}!diGy8Qrc>G_?q$TkZV15t`>f1{b$nt^wES zJ#%e&Y&l`F8~@R*NwQ!jlfNHB`_XH?t*UzZ-6L)1yJ5@QH+CUyR)fBe>=n{ke-lO7 zi&t5Oz0*$eK!=8$42`pEf5f}eq@-ys!Bd)VCD)nK_8;@!wO7=LaFHGPh=;54GqJk9 zC=3q$dT`k*3w-*(BcuH*$)dP2X9nWO+tkYw9maB*w!~?98tO3P@iuACbUzub?5Y|U za?gqmaUCq-A=FQsRU{&+@5>^Gf3k>lpY|iWzjVN&ub>Ouq$w8eQE<99sNt*Yphc0d z;?~Nizp+o2pC1TigH64^J-zFH2#~}v*OZc9pr<>)cEPHadM(*9WNNE)YU+m^xdpe1 z9Ym>qc+e%T_6`-VbQMNqy91(UW#=C%EC~zR(C}+n8Sg4|MhdalWYxzD#Gl&sAX?Hs$jqZ;K~kyCzW^ z=dH3aMLS!iY;%=OgkcgKe=SscJI^6<*4zl{!}B!w`~|vGkmkqF{N84RK-=602o8s@ zsCoy5(~^9s^omp!?=h?^qxI_*ReEKvq~|7nO_THpsq>x*FG>EyIZ%8b?8YKDP0%-+NAg&rYNe^;?h0&7|f{8!x_ zf(}BQDipBUyKnCHg01trK77lP>)Gq8&Nhc}0*<7=QMPAqTnL0lo^Q;1?WE?Rh)^kE z6paN`P8kG!lFZP9wOhew-Vsfsr*|WQ^JP4=GR%J1v(5TsK1*1zKiM=^yuV$Jxa~^j zSU`*~mxSFYZ&r-be@J|cc!Fa1)th81ZA<1~a& zn$zjxfW+`cI0;@3LW(P4hpfg|Wjf;Be%0e1K=;bq#WyV2uXsRyzDW%ux|BE2qH5l* zv%F7)?PtQmg&G3ufB;_Nf?lI}>r(QwY>xg~BQ|jj;T5*of9VQt;PV5DFZ7t}R~wd@ zZ`mRT&acr}wLLSnuXy9K?tS!fB);HqS50A4shS%fKjy$^JZGzfHtDTx@N4vH^AbV^ zudE80(cMyR)x(`BcC3l2aqxuShx9gr$5rK#^)C$MG+G|2A9b$p8k$yW4Z=dNQa8|2 z0Af9$tM3nKf3TuslXt=lF%?OjYx;G(OZiK~sc@Xr`9#cR#0ZR;B7^+k8EgRHoZk9l zwpS?QFVQ)2?D(`3L2?Xui|bmYYJ18t6SX2$Qtv|sum{#2aT=$;k4yYyU7D6w=IX_% zBRiFL;PBt1384+HL+GcO4qgVg|H4LsC_lMHmzPH zy*7+Oe*n@6;)h9TQF7B+W_S{RsRslJzW6HQ;Y>)y^zV|LSUtaX%^mI^tOmuGyuig; zrP);Mf9%1J2kz33BU|ZVi%}uLwG8HiS?Bw{zFq^5np`(SqR819V#sSFw~6Z_e^f1q z#u=UG$aW+Li5(K9#ZnMT+x#rLIB%XGpSeYue_iQ^P9um>-x0QHD`7CURf$#R*6JpL z78!DnZOwS6+nf=E$i?MgS7nL}hP!(!OI;}667;#BZnA*=N_d-WQ$MvOW{21d?2UNT z{Hr_`?+B*KC0W<}5XD#^IhXFwP!^SR!OE_~r+^SC=IuPmZ}{*xw+juYIJc!HI%gS8 zf69UOBdG8qk*$kA6zOmuk#v2k+89{VM<&+*4;EA(OkBZ{cdYHuXh;}^pgHmzHsM$N z8Axo?RS!7qj}zLqICuA*_9!E_aSXxI78Zi_lwoy95r>f;1btk67D^Gxlf?Q8IPI*m zB8}+$0u((&U-<7?J~VXjRm$+EENy9-fB!sa`}S6sYUt4VINdM#+%hJfkLz66r#7QW zr6G6pKtHO@L+zv_R2-@F{T_)K8hZTVi(Et{!9f9{r3e4SuJ{j%D=;y=a0`VL$#YIf zIDW1feDm)c=3lvmq&ng$lC?kCwFZB8<%yBJ{+iQBQi@_E{rc*oo)dM4o{I6#e_*Q* zus!y?4?zY0-ut+|pY0N|)?!lJiF{LEOh%Ki(+6u;(!{%WC2y6Nao#{?edE#Om;`*8 zJ|}i;OnSuvZR;#|%P*+2Mo0(%oq5bQvqZk%61t=Ylm3-%Xq2@{W2~0@3(NS@V5Q7c zvtE_a<<;;#5*T+HmoeWv7*fJIc&mPcPJ7 z%yJ7WTMJ`5YziR*%vQc|jKgQ)n2)QT zioF9`_$QlLX^JAT_04CUf8Xl0>$GS0ZDN3j756%}bo|Tu-(}pI( zGC$qFc`PWUWEwFwqk@I@OHl-44@`nDiiz+$Q*1yPOmWJ!;)|B81+DU=b=#%w)e3=Y zP*tD8n7eAT4ULZZN4{Su$^ksD!XJpGCF69+O1&$P8eAV{psT*Kiy6*mJh#^yn|uXCgJR%H?9n za#K9u?R+id0$#0$(H~{~r3yKun|4ga?s3GGtUTy zV%0L}Nr#yx+a*=D5T7)K!2?@$Q5%Wb5cYWW+P3zm_HDPDe+Ix?w!8C^VNw10P|-an z$vJ0u%)$II0BJ^9dHA&z(_av3Z|l*TQnVB=b4>cdrzS7^ycFLa-UX}EgCS`cl_#Cj zp>T$dGx9c(BW&y~N2ET%!wzFUtk4z(a&>i(&r~F#dfNKpetB-eFOlRof)*f=nxifz zMw3IUq0kpwe=(6}kiL%pHH0K^IUFMze!(bXA7k8vAw5~ujafRIyHozDU~Qxu5htOk z^|isXV&rYmTEsym2B}YzE^(CCcS{qBvSLMEoCD%P$y;1P4 z@Jwx#e?F|!ql0S#-x}(t&{)e+qH4M`Cx7WI)Pm+7Bae<2$Jgv#4BpaVS}D?s$xn{T zr@~B*zxtYBY3K_A zc%)mYj%L>!cnkAFdyG(WJ{9uY9hS-UkrZise>2BpjERF5Nc|AX`>kJ%J|xKtgSGR0 zXQ9JLj>$;cc=8?3xQbDrtzAe-iXE!q9!E-~Z0E9AR5T`4_HA0dP8|eMQJ3W|`Q970 zSZ;;YS?uTf8{Nr6aC|uZ4v2EjkS>)4cj*i5?oZ1r-xVx3W(R9-YLnU8x+{ySJn8+# ze`it~SR#6SYrIw<#f1%8in5;#3G9g>Qe?kE^O1_&gec}gjOmxqmNjV!rz8*Eg^ygT z61>23gg$Mtp2Sp4hB5NjN@_>x?spBOb`^!-^$fet=Rn-8qdt@oW+!MK<2)^FGdLTu z)TUrNYqY=UBW{hp+(FWI=G8$1#1Ykxe@wtn;X`C>E&`LW#d>nxNQBzO8$a21FBZ%T zZEBIZ1#qK2M(g7;4+1CvOt(}Z=OGF4v)a`!pv=nnd38|QSuw*hmAL<*ZqL(_zaTe@Py! zo+6|Kmo!Cwi!+B*A-$_KwMn%`E_s^G!pmCYVTEgU`lhsR@}j41?_J!)#ND+8j#Y$n zTTng_jsVU()#Yulcnr2e$7~ny^(5#-kcuCQvM!^lK;{!Fj{h1-9Ol%+0s>DNdbHSu zrekh^8}u?+Mgg^k|J< zATBr_jP}n%EVH35QQ6#aJYgb?naS&WDba=QuP9k@)thxQArY2Xf1JFe;1Z9)Um|&o4_^& zHkEv{ILN5(%q^VGGo>Ubu)rwrC(ETS_GuZ-Bm7z#dzZ00>!hbZdH+M!*Q2%2A))r> zx1nA3_r?~QTad z?#r{V&V-V&kRW{46C&zD^a>wAs%*zM9pB!f7K##cG?-b3|c+FRlgXj zj_!w~COB^XZ^6*rM1r|i)X~wbvQ(KKzjk*U&ea8kvSi6wz&Rt%I5VqViJ1~}(K%#a zXMMjXU`Lk`v=mNj6B!RLT1>hosFT+$_+n3Jk_u+vmomz?j7Q<$h!+uaGMg5W)C8QY zGRET8U7RY>e~pYy$39($ZmNS^dPCI6`I5lGk#=D`u2E8k?~`%P0>@IB08~J$zeBPtet7H1@{0^)Nm9JQ z1U41qMB){!fp7x-D35eD+M;BGrP#jAuD0^2UGr4w?4(Z$6<_gv(rfBvJ|AAgBa@_D zr)q(X&^K|+j(UuASJ zv%tH^^r`K+rQso)IB;oujYy;m3b<;&bf(WClu)DoUlGr1T7%yzX$}Q>)B82 zZ8C)VO8T}kiTy=EOVVc@3O44;yZai9$a*tW8q+UYkPS$DnYxQ<4M|RW2T$WtFpbH>0AN z_g0vSBIpgm8trGtC?Qep(4(CVN8dx7QynI>>x__vkRp{wY(fY}Rb+V*7)}Qd#7pC$ zpCI3;)ubG4A9`oz8`vj@M^Gl92<_hRj?{O*`hTfc^9DRH=>$t}O_qjde;0^m(ebM~Y z;C~0c>Yy1xt!31X4w-#!@icIj@uEYMCN(e>lj|@Of;dPZm~WLJ$*|RaxxW3Q=%ehi z8nUeFJM=8ospJI2kf>L9ZXuV%TTCvS+6L0QpN5u9i>^H?!ctMHmE8)j+;*bI%Wh5n^M3qtq5 z5#pH5g}tNk)HlPU^PLK`mKmeHhLTXLK#%0;Oo~0d+oJ$8Z&IlTD6h3gxGV3mrQeo zkHZgNe=^W#7GXn{_qzEY{KQG4;&HopgMrgC=vgv2Ry~FZMLUsAgSnIn?5i=k-KJ|2 z7(Zy&(3rF$p`0@ryxO@h2|@=pUVp_DialMUK!~G-a6?H|*m&zFP|lB@h)IPo-}gU? z?546R4w8E9C?GQzoi^cll;-ki;h4%cRxH}M*r`z^khnS<{R%bG_gBVEbEHqz&E7<@ z?qI|yI$EI$GofJ=ZE=&~*CAvbudd$Pp*$tkz=PMK1g6X%?_GT|BJN3N=6~SGCM8Zz z${7=gwa~x_)Sf+$e3f##(jJA$sC72LRB3c|RU)G6Ml)C^H%m$Y>K-O(y$M3zaBxvT z=hI@k5z$8L(4H7-hB81^c4OwDi$rAD!_x`S%%0d8A4$~SH5eAv^HTF3zg_#@dVL#v zo|$9IK;zrMue`VWUj0ddCx861r~M3vjdI5S;R6zB9wnZ^-X6+}*Z1rl=$8&5>m(-BA*Pd>}sfyGPvyI;;5)pv~{?^bLhGk>D1w_lKupmB26 z&z4E}j|jMWF!rM-@O4&i8g9^{c@KZb~uI_vEXz$YjkX zmr_vYI6W2K2Zw*XQEK$Nk78Z#c8#~3%OVJEbm4J=FUCAM?r`F0=Y_C;f05FLXcI^e z7u{UnF zQ7Hw4n_wZS&E?8w@r8KlsO%|z*dI>Yn*P*;k{4my z5q0S4lXGU?#Lpk0^_85~6z<*7fNSpT8^BAC^&1-892)OCR}npwFh^=nLE)$F)t~Ex zPI9|wF}^k$uYY3YB`{=RZcWSwAUS^=&*AH507!ll&V{{lwhpLp)lvrQq+DyKJ(Rh!LU$gX4$9bNhzknvC zz>BE*vHz)A+Nnc%Hw-EYHQXdn+|Y$4ONbxcefwr1yA!L@F)^L1{%K*1rPfQ0XSe6N zFkU? zrIr2uUaJhtO~yT%%(oy-Blja1n9Bmo1<@oNJc&5+R+nf{W{+V#^`d&YEafbd<$#$kW+k@K_ zFlVPytbON3PqwMq4wdz@6`k`O?XmG<;ETJfjStjlFdz~>T*uo7>G>z`^nz~`#K9$P{ zo3dTvk{>l>OYUcXx$B)EpL`JXrcCTEVt?SAPWV_k%k1|{G`e|IiFv~_YlC7RGs?wP zJjK$TfWYiPgwSA%-#*a7F|V&hJ7X)5^UQI)Tt+gfnUy}O?Zrij!(KVVt+$tUheiTF zNLT#VU`zd}rg{u`mvYXr*D%WE05=;#u5H}3AhkJa1EKl77KEGzJG3xXJP*H5Wq+g1 zE`3?+`LMTjOucUlTKtQ6IWQSLBHEiPV;mptCZD^wZ>Z6x? z3BnBTqwTg1q)ad)n50j*KX|M%!GGOKmZ44X(@*@;;{+6i$JYwx$C)PHR|d*Wvn@AW`0E`R#4DGX_^ z(`V(aH5bpksKpCe97P+}ah;{q!~yU&>+h(;yvPEizS0=aZfhz=1pIQ>?y|KCGztHrmbI6v%IgZwzCc8ws~DynpT@%j-#J7{FF2!=LW(^ z(i;ziDU;(x?HOoS67e8H_I7 zGldG+^>R@|Hh+8u4QCker(1UFIk9N8{2@;Cj*^dg?HV8J*Gx5O>lC&q5^vi-rnRe( z1>t@t+(`OZH>|fE7a>eSqT#R8K9Drh`SVUnnnL?cp zznZcg73IBKfg!Yq^hCY<&;`=ob1=lcN_P-GD#3B;B7Z}xjnKI)Z(i;f$Zv(FET3ku zl-3YFHc?Jj=Oe8=m(_gjbeg4UyX)#}jI!POQYO~=_6xIz)d%)4bXp3Vkal_;>L4=x z)WY0?njc*^GFs}Mr{}wo%cVsGM=3)@wRI!$M+ct(k0ep4T~lOcr%Keck00$wicaaD zkQ7YpcYm&<{BTdfnevV~Qa$!8))vN%{82sR#HV0|HJ$of&6|pntk{XiDTuF1*ttp- zcMn7@W56z>u&x9AeKF6sHe+Q!>o{apANq-_t^X1@3OwiA8_V$zh8h4K>X4QyC?OmxPL1)1^ut7L){0R`SNyymm71nA%6MwBUf^RkLd@r2{CxB8R7^PZ+y9mQTWQcY~U zh=c~>=PUqFNW14h-IxKeSfRmyPcy-rOQ96*oP>E2g9%XvVJY) zxPQR#bj`(=et%fyR-|x@%W2yKS%s=4pfr9X3me`zR>gYth3m98B#MapnSFa7Coj_j z?5qK=x?*Z}mgX1H5Ad|l5XYDsQC^ZR&R9b!NkLO=lLp%Xw#Nc@QKP`~G}YL-v@+G( zYFp6@0#OM`+BwoF49FE8TOYJD=l;Vv9PrSMDbT zQIwz#csDw7$C1rxT(Yr~I#ig?0e_q24t5pGJ5J(|7I8P9K0C+yVI!HDoh7Z6vb=GA z(pFj-=)4jLdC?vXUX|FZCzFeBwSI0<{wH)Hf8Ulo1?SId@;2ikNERE15j=O(nD=vu^q3<4NfDaF^5f z*&Ujq=aLK_xh^dhpew6ZJOG)-hk-xS_3|{@6WChw`+^?fqA8LINfC523HxkCU>Wgnt9!iY?%zVXg3g8jmd{R*rhDP z7%V6aXsJIdNN)#m;c|jQ&xf8M!-yFk5c|rDQ(8pA!759|46c%j!SW5KJs#yfJSrDk z+RP`3-(gOwcCvu^rKZArXMh_s-7$yv{`!GP3Le` z|EZdt(LJGNeNN#4+yrb+6c6`$yZMPl8Ah9X)6})I$fGOO)J8O3VDtdXDl&z8pUgs4 z)1$j29d?97R%D?Yw(D1(+ud9Xs!g~kD46pMi={!ViCLa;KC1ibvth(?rJr@) z$e%1Kru$xbG6e&re^S{{6eO1GX-RBSX@Tectje=lB?^%FUr`IPqRwbh4>L(Gw0((&5VKCJh_b{{j{3|4Xjf!=EAO@Y|tc z^N&oHT=B~ST7TziNHHc&8|cMzrhb{+_z3|6adFi}J2V~%vyYw!IF37iKpHhlg5ijrtPN_@8OYi6XN#79fkySFNuDDk(5QCewB#8)mz zA_k*IFBG-xVY^X8+*(=+5BiSkelAy%+#Wf9DD#=ZjDI4rnwnZhl~~7yOJs{y7gFq5 zi^yvhIB4oz@AHUufcvbXu1L|gksq-@>4PWj&W?>B38=4~xn|F|bqx&B$zFT3f z3Nl?u|U6!OAttX`{YEv%*vC&3gjL3zsJ6B z;kGB&ezEb5E>eX;;7e@7iXuyILRFVS-bG~;hqlnbjcY2Mg^!dNTg@1OTdS`n*x7@9 z8w;Z~>){^3_dhWaAm_uBK@I=FVBTjjW2xWcV1I_qLFLdlYKS$Q*>YOI8U5UsOOGRv z^VNaep6UgvOVVA+qZP@r$&B*XZA)CgI`v{=!sE^@#KDeSR-Y7Bi3?B64bFVyXElD^ zqmDNlgbhEJ9Hb$-qM0!xTXP&2Q*fU=Dj@>R3Dy8tO48lto zWJj9id5J^TrfWAjOysj(Q3!^pU^Y~xgm}okO9DJ1zuz);xoRN#&C-I0_J?q>ZhtKN z@Uk;}i!Q=&O7>OK-CS%Y8GLBUGbDaS#7?P|S|g15?D(1fxnUY%{z6tAF6k;e;e{_C z3_%vSZ7Bq~*}zLf)7FLubzlxfDIy1vzs?i8Ne)S)GL`UJu&%j_ zT`-ZX{Ey`6M>xAegSDLt)cAWRqJPnX>X)p8&%}8+3DB7(9xP)Tc*6`vg5n{`2G|_A z^aHT@yO&Cvt6yXENg#&3CC5|7#JFyq9#5b)ww)Ph>)aS#2X|UF--TGC0FVpv^E6u_ zLSpd7)t@qd36DoB>fZA)7Br`#`XSMqsX76M+HMtSV1xf0UI+pFA$QZ$Qt=fxDfT_qfg&D(}A!hkm;v z9Ak*PRh&||RQ8DYFeL2Fcz>`L-me(q(2;xp^?~jO9>lKB0i@1`+FU=v?DScY)z&r&Fm;)!~t10h?`*(JqGi=XD(PVm|a(W4Vq z`ZKFNx`T1be8OFxd(p}3*-L7Im}z?`~MT*8z1ClS!w^0sd`??RX1Iz20!pA zhkv-X$ANVO`C#Y=Nvd_*RfsiVY@8bk2U zGxJ2xeuSOFEmw@Rhp$u3!)IgB%m?&Q%X9DG}yGGRKppF6Z7** z70N0riwA`JV+}3J9gI0sFr!SO?0Kgy7JS)h*o($l z0c(6)7*7{RS0#w{MjL!X=SSNxO>*FmK6)MmTYv8u-%$uaqh@5<(t93ywQr3@MmidJ zyYGOrEl6t=Q?_>-rhA27lmNwIrNg&Eq}|X=X{1&&U5Wx;(B9UeMboB|bO57wQ0bfnf)MZnnN-OZ50 znI`dUww+#xx8ayBV!DDPKOGDYo|L-R25$>i#=-j%szF3ZWit||6x?JB@H@Ykrhi$f z2&3{3W-)PF()zF4DiHJMe`|Du&=;C1Dsy9Q6D9%*AZtDi^0F0f=7}nustW#Ra*Edr zy*df#v!sXj<)oZ}hIOtm+beVDSD^k8MFfVm4*#b<@$#?lO}n;-IcQH~%iRwjdH7)n z*IrCgE1=_VJdpQrDus>-nGrXDK!4BF^;ki$;q^!4vwI_v&c2!0?0etAx$up*N1_!; zz4Zr|LK6?76Ppz&m+1)CF3@cqLjJGjb1dvc;j7!fqKPl8#HYF_Xd=xf}e z8CN?#KwrVP|6tH!&!mbdUJoDAML5}*O%!QEI};BWr#dG_c9oBG|CvFP$$$EE-9vXO zQo*~4*~%#Pl~E;Nq35l&n)^1syJcR!eDuly| zq7vVBl<@Hqvpm5Nzu^>wz(+r_E)B#J$Oo>1xvITu>)aY#zY-&l{vHEyJocS6(_MXq zNz=g(UO=Y~sg8Rv>wcmC0hi}Pj>n1e2YbosUHYxD7#s%fDbjs>et#~(Nm4$KWY#+j zAM1c$)mAC(&xYsqA4Ga`FbXr{Va6G~VgiolZal`zxy>Y;8cAqouYpesGlR1DGJi5M zz3y+!`?I#mDUs)1ojREof80Q!;wUos5>hMD5sVuim-$B+*!J$D)ou)c^?zWfCn2E~ zzqxD9W`7|mc_0FGrGEnrQ#;Yg?8APvV4iKe2OJM#;g6kB5UeM5G#z(cmKtTpRg^49WPer&!P^bxV2C>@o0FE2 zL@1n+*k!)%ug6`wsMm=cYWtPQlVqP zwgBaO#no^PHKAkDH~ zvSv3M2U}VBNGfet7u<}g4%e0FBNhr`H@_A~VU6M%7+^VY>xw<+*=7bC`-0Zp??5VJt2zCt!~CVVF8AgGFFwTag&H?)9IKdgD4{ zo+FypefJQ>RB>>y08u7}BREzqkU9C_klu(b%MMS|6N?dh;Kw@y>}wt(vzfb~s#r|9 zR~gR%u7uEGbQxZ?eN((?U^GvB&+J@zKdB}z`hR)Vng}>7E3xzZZmwEUgY0ta)RUM| z3F~xeAwB9{P-lQ17aU=8_o#r4AzO*OH)ji$i6?zcSIb*iwE-UZ4nC~PR*|fg9|XP^ zAW?rhcaO(bgu`K3XWK+{tf!C}3+Q^VD)6~j2D#4viV&kaoGhP!x|syAwRWXO zUVlXCfyn|(cd*q{rD44?PAgS){zo0hmd**(5--PO{=%^7#5ZIj7HOR4tzNeq8 zph=<5Matq<2Yl0ow`1BC-qyEw2(c103Vfpq{2RM#7EX>}g1G^HgOg%RxsfTv6-kbiq7 zi3G?$5^_h7CuSix5!gAA>B&d<=RB16oO{A&Jl>HL_4F1c1R8&~2c#bq62{#~VYkY6 zEr2Xkn+~PUJHb8fH^UDTD5kuMgpZofK#7+q{D*d5q3lYn|1_-qtfv9qHSNti$k^5y zJA%cytBP`bX;$`K4bR|@gK#g$ihoMpp@P(%fUP+1VkQZ*LLynTo&RtuAtfI89M>8y*4rcZq}m=r_LYzNqgh?*u<8l06qb2?a=8SIQkFUAO|@~Lt2A% zW$+`|#^%vezj@T@AyG7do+_J`0d6JPDcg~YwU;OI32o7XNwD~KITDBVIpgnmS;!=x?Irf99bi$mLthHKq-$)X5ujka5^J&JBRnEHs zD+{b-){@>WnK?YZQ{?)9En!yxj;QO$g4TXC7Fo_0;DI7+f3M@*RApQj*lmk^jjVKdnIfd0={0+`f0wdg)AwcR%kVJzG#5efxU z^ibD!g9jwgBgq4e(MqO7_osjqYx-&3bkPD$0S!^}TwA(ww|^ub)SS4rq#m=ARlrc~ zJMth#iS&5}9B~DA6{H1@HjjJRNZ4DgqJ-;W1xp6G?+q#Yb|_vTLQ$Kw%fRi_qGY{g zT-*&3u=E(9Bnc9@0OF;&22BCoVh(@NE-p0|PjxG4^&iMfZQFQyn}MCKj(~@wqI)7C z>3cu(x}OyW&wnYXZiZ_+!91a!0L%C3!n^sV)nMQy3EC5!z`U2#ZC!ZWwk{2gC1jr zG3g1#UTg?pS+9Y{W|GjtFS(=|52Rw?u*I!WY2*5->3;?EkS2BoMD9xvsnTEMzC~gS z>VD~(C5m6j;)sqn*4A|T*_4AUa0r?8v}EQi0c(J-1>)>FkGY1w;ktT493p++{$CM7 z$OJ3Pk%bgqA_Flb4V6A|w-cnnQ==m({qy|23;&gqK~C6f8bSKqIpOtR8z;l3S9c?R z7Sgzs34j0j^FOkp1xOI-(K}5&5^Yx*`GEL$jDSaqXGp`zo7Ra3B5EA|(^lf*24?g4 zaR$_?jWc9Fa7pfvQ;yBGx2z3UAA(#0X3V#qXFtLDJnByMA+(3}?3{pV%@wBQpV)zF z-XFW@LNca8!_xHZ9lEAW9C-_o!7;~QHt^rTawtb~H+LX#VBveSt`5s;9yBrQ8#JCm*4vkv1ty~`&%GLF+R z8h^ec{GQ5p>by%}+vS5{@IP|2V-&K~XL@Za?Q=koy(m7q|HQnd1_;y#UjkZX>PRn& zy*Hxx+F=V`thp$1JjHoLo?c1Jt-liu5mED%M)dp!IlRFirP~Z@4QA|tZ-VW<#>w(9 zR={Q7U}LyXLKXNJluWk_FddSbMo=xCZ+|SH7_V3qoI6$VliLpUBmDVxFhrkA@a_>K zz%N}PtzAj$-#l+kM9R7!d3F(N27vjN!c&NAmqwl( zF!<>cS#*^<7ObM~dt1vw%=cQ9z{Bb*8&34!%T%vZSz_)q_g7c#kfU1D!n8h+(cOc*jL(-)-dx8^FX!p ziY(T9@aYZ67~W(ffYtrxG55|j4q;f2a?+1u_9>v)0BE{pD7E~MRVxIazz8j7HJm|X zOCahl@&7ir;b^RUERA*TGCR_~Vv`4eUN;@b2(tC>3u?H4tsdr}&rKlZY;tzM0;+>a!gW`EW1 zyVNUORprdVC#q`9jrWVz>wpQNHtj3JqwZ@ej8+G*kV1E`k6@cy; zwd3oIfrN(A)Du<$SL}X-CgeUBI&{+7MUtAQOTVxM^1>;>f`_DQkLzB>6p3xYWuJL8 za&BWLWbC>VE0&|+q5Fu8p(6FVP|PehDCiK1yQ+}x<;b|19nTK_ySRa-{-hD32kkqD zz&F3^KJ|LYrxK}#nVQsx<$opR#}4>lofv>TS3ei$e!~T3y!P@$FX#Aznwv^^aj?X) z1s(!>tFsIx%`V4tb>j%7w@-8W6a>~wa4o$w2Yu44CU|PAxwjOGXyKfm_9?u0tWc}KYwhWhMvUzON*(; zy*;vDHT6}v;dQEsx#FJKM6mBwXAVu2xC_->uGKqPp1Sg6@KWZ)dU22*g-&v^O0!U# zQz+_ry6`mkpD6t$A(6EL`7QNlmX1=1Q(7e*L{iUY*_&1_T-K_DUAA-eA(*jSVF$eW zpA3kUiIs_O@X3}Mqkk8QwbZ7}O96|-J8a8ZN4{y-n4_P~`^$)|q6|SVVrNnGZF7y! zg3(q-dpPS$e$@Y1Un)RNEmrv%R#=h{i3}Hb(km9K+o70Z;5BecI^uJ-?LFoxgFAr! zo3?X8J9k<(N5e9|-S?w%7Z;{BN^WrNZ!0z{x6d9b$*moEF}vcUC6jM)JkMoa61hZB7aw|wQZ zSg$4vZp*XW4K&zsn*#`thvYhaYs8DQ#BE%cjpts7J`6?6PBHbUuGS5qmhp}X3)zOqwB_F`&|VMMHf}fEALNWK{jRf zV2?CC2bERU?*U#QhC8U|l^y4gF#S#{v+B^QZoGqxGk@exmK9S!}voh&^zN;8i6<0)@-~o{m zH&1ShR$kM{WCEd-IO-yvCfRvQ@XiE8sA`D>QOu7SJf;5<`;2j5|R6n9)`ef?B|#frqxD>15OCrFUfiFysmHo->@oovuV`mJ zh6G>1)O#BL^B9`lhvZp#(k(z0&_-RTsU?osvee^y6i^SY2(Db`U2yBL~A1`AhozKn4 zFWW=?oLPt65cz<*TcR&>=;Q;hm3vH_wB1`dlKhKqZ(wM8VY|yUvQCiPvXAsPJ``#sQ@al_-5B+pg{iV!qo)p%*Yk_F2?x z+y7W7jJ7l@v0y%SqV8hX#*0~GMSrz%QcxF(>T^ZBtdTOE8x($x%f8tA__YC7)tY;c zPfGS-8-Y#BJ)>u^V1vvj}+6SQ!v^AAHDkyMvk zXkmq5ix4!VoqWb!~kPL(g?Piq{LOtBByVI++SM4Po&O{R` z_qtm2F;ZQRQ&zuYbA(prU@QL+0-1 zqaZILY;IE5&jcCkIXzTu(2mI7ZzxfZ0RBhhHiSQJ7_jO3zk7wkJ8;KAMb^WD}9Q1Z( znqi$0uwzb}(`lb9Ie*m7EERp=t9it5drY`S80a-{vX@elIrn>xOc^!_ivLcas(SQm zJ1gUsj0A8!Bk~+o4pR@O`Fier;G3EILxq3~J*Cc!t1Yd?<7+}eCU)1RmpOJ0U%89v z=P@xM@;t7?JT#KhK;POAUH-I@y}iYfK?*MRN3#s4*FhF}q<^LPj-08H5oQ-~-8nPI zo2DTf9OS@?CB_VECKO#f`}Gs@4Z}~vR%l)CO3PU{sLUouY9quTlhpz%ahd#6DWXS# z)h`t_UpV^(&yoZ0FZm|#cHDzF_O{&+Bhr1jytjd?pF4wQFDhY_89&sB}fZrhTr zTVS&82L^%gxA?%0C5=ApWx3_F4yA4G0St;wfdDj_`hQB@&Rok>%-Yq@5hh|3@BtR; zkx-aXm3Li44vFqp;OrvRdNx92%-@IRgNXvejL6J{Vj@H?+I9)YjM2nO7-4j z)S^_{+hr1POXdRo75SK)`#4})v{pU6J+Nn=1^&^Ic&BM5#dlwgjA!bw?VbY{xp9k4 zeO4gBfy*XK?<2qf=_8-9@`hBGH_=#6!$lBhiLrCahy&hE9Jv$dhY*LYTvj+vsHr7< z+Qc)Laf$&Gm)A1^ECy6VSyEa`mkBfhycl9~VPk7$bZlj2bT49ZVPk7$baH8DXmppv zGyx`;@iYNpw`4T|LRJkjFbXeBWo~D5Xfhx+ldyXi1UE1?GMCPa0V{u0Q|r<;0sk#|r3(m%pkMTO?!D*!|61R- zvewRiXP%jPpLw6z$=Ynp`bK;TjtB>cDgut;1MveT0ZKYX79b!12o&N60tNBe*o>hl z802p|KAS1T3kgNQCI5c|q2vXzN1<)X_9!$^2LT6Ydcy!9Apl5J5+o)G1OfzsK#9MB z2ro&1vb_(~5un2l&_uu?NPIRWgonQu)Y%1vuJiXTfD_CG07*!Q@%|16D7ZtspkRAA zK*t{C0&z!I1lz*^MhGwzg7W`I3QlPk6v{(VK)~16m*3tU$&Y{Va+c-d1^7ZyE&xLa z65{0paRmIL4A8ZAhy0<&kIx1$c7Y=Qau^|;P`>tF5CGZ$gMuM&Bs#scDu!s9Y;m!ajC=3G7Q`P22 z`Js3L_Hf5vKzn}}5`m7l_pyh<>>bd6-&?l_s45r$?9mMW@I!*VpdKhBKN1T2#Zll_ z8g!dg;EqZNcXtRJg~b20KV_&F1dQ&xzrdfvb%P^(;emgzoS<+=r(ZN2y*&g>;80I* zh=%eX4BCYMZ<{j&1rPyBh>D7U01!_A#1HHu@T-8azXyNhxAV6d%^^6@1K|O1Leqc* zL!BV#FZ@8Hy$=L{^74iR2mYtypDTP22;c|>qW}&NXDA&1-`UY-h|^zd^!a;1{Q#Cg zwERE-;IGfW?yS)Yb40*l{{M#mK4Jk43l(ie9iBgw|K(IvMEC&$`2-~Zd=jES00;yU z1&E1>0D^!2nde^}_?!K2tG+$-&+h&sqXygw0g(8M1iE{F6Y=?@49-7e!v*+f1ziMM z&kz9TzvXWQ6aj+K7tsHC2!4nB|Fr)r%l|6>|K5?RHw^aM&-oYN|MAg$2Fe~iBMN_TXSB}wK*Ib$;lJ!qq$<=8;;0Wr zfnEO6(%*-Ht^tF>A^Hd;^w)C-9R&pbmk&L9U^n!$1&Kbg-!2Gxvi@0D1rA0y{u)6+ z5mA7>mzTXiK3W0jl?WgZgq~GLh~ICC0|fZt2oyR5faVwsa6)+D|2kNZ2tdFA-6OQ@ z(e{7eCLln-9SZkG{xx;3&Pg2 z)QeCUDuY{!$9%;j-%fj-A&ia)TIWfz?6`j|(xX%Z24Xu)Y)g)Gv-#^Nu|A=l=O0UN zx{*5%B=!LAfbw$^<}5l?qC#Q!9_AwpX4VbVsD%|t5}B7}j<>Of$>a^@BWTivVrK%) zH~%fmq}gV{nSC0hM;qP5ZFG!y}v%!OlV!!(qs1)49B80?B7=So$XDJ*|9 zW$w}JYgl$-Yu{%}hB{J*g}j@cb(O;I>OFkZ;@yZ4nU^W-TRWk*-Oe}uCO~+vH7(AC zw?3Oyk*&@V<9syds7?r0)Q?TY2*7FVUiqmri>Ro)u+YX_Zb`s>7$Icyaq8ZsU1DA; zNYFY{1|~lI{;8suCIZm%j~-0J$9d$|LfC1XpK2jI{fTY z>+8mdW>OjwF}SKi*hZt6=7k@L5trrau`s0OVCM2{_3a$)jph+$D7wth#q zn$!b%iNz_FWK$vHVq?+;W9=P`9Njw>l2Hnwvm`|1ZiiJ2&zGNxzIh@O-YS2SDIN-Z zxH5HoOW9yQnWSOsu0h|o+cqfLLzD@>ijxuAPc?@N&cpdJT%20) zw_$Qx%Ty(MmaLCj<4GH@)I5&Q`{`H7+Z*TwG=~Gg7g%NCs^Z^$^o4)ky%#Xo6MgNk zfaqyBe7Lt`ZRSa*9In%b6Kf&7UU3@TN?Kx(Jol!=Twmo_`$llfR=i^{YhmNqD_iv z=mL7qs9NaorMz}Bm?wV*MyPaY4Ja>L>EpzUr1x=}Lqza6P2MZe**jor48DNL(Sy0y zVp$GrZ9)v6eYCE2kKQJE3$2LMs@5BsNn+NxoA6@x#rK_iUkyor*rI05q;h-Se90O1 zmgl@*jpBY&K|Xue0Q$Glm+D9oOOc9OQD?aUo`)P80jTuZ*83he8WA9{nBZsysYPzjhYQD8(=21@@ z9^CdZRLWc|!!9sTcEP71nw7WZEgYsAD>mpf{V zs0X-lf-i(3{JwvuFvgFB?Hi4n=xa1O1!_%HjU#EJ2oA?B>N<-L1onM;lP4{U+rBR{ zwraEK70d7Csz*eplS!}Xb0ld#9a{zVr^n^F{#jzJ8RsN+er7|o{tpsAzGl8 zS^YKhCfbMcs*1 zBPhK}GYoi2etPQkIWT6*hE&<*-I?@uNnmd7refyU?tJjotD&Vrq@WXr(y9O2X1(q3 z^V#R})?h~Q^aePsm?uXB&Bt3>vDd5lgXD@~6yeZyOAwID7?>lUz|n8Pb&!ANWeH@fKcf zZgRt9Cri}yMHRWV0M0mHNN`~6^w5ZW(QFpaBl>?lDABE(DzN>82Yh5@t7-QATwpb! zZdEwOkqaC0TlMGTLI6hF!iH`sRrvOYXQs>B6T=Zb_EmY-XP@NecnL5MP8?9hu=E@k z64BJ3da*uzwiP&rpWie}q!H9pAt)HAg0v&bmn zM&N%>nncyCp62f%MXNlrumwnWr8xi-ad1m%Jv(Jx{oHY-- zY!cEi;m<0!hBzttZ2KiaQp+_?8+=#Cjpvs?RDEZdGq`4iC-FjcQqf8>tKmxSrnR`sT8 zVuH)Ni}9&nXGUBzShZkUnZ`NM!m1h(TuVkAgj>~pNC6T4TuQMSkHIui3$9`@4V)e= zhH$k0v1v5+HO8l-SsLyn(DYt~?43bV`;>R=I<7-4h4+;9vRkYip?$83xe#taz zbp0$v`lgKUR9M7%__DQz6BAJ`R0E7y*@zM>hh*loT@3o{PFX55Zo~4iUh*$-th!~% zN^R`s7y76)N1*&6>I>;B_8d=eu}P5RlA!{n&d42^Wv}#=8T`IaeZK>+`mv~xBslU3 z6j#MRO`iJWfk+VNL>KzQH_0b%Ls@>mQ|UgaLI7kxuA3#3+1DNOC{fmT-ZaGF21z34ZU`v6mOuMw=4cq&agEnPdUMglT>@*)|fjNQt4#pb2Mswo)&PpJI)KzhgD&>rDA%+Ks*AZ1Wuq=}BO02UV(vhxIV{QC+*^nFYZ_RIt}H zapKU5nRru7OoC4TUG}^*|Fx(<`xE3OK6X#Ar<>~P(sB%MMJ{t=S{i)2vWyQZ=;QI& z>VjweXZKLL8^cZbKEI!a_LSLEWc&_4oZ21DAmRn0D_0bp4#=rmvUkwKbFny%I;}UB z{fs&OmP?O((!x|Tg}t?xCPV8vvjxQ4OnWaiT|L3vTA@u&P@?eWnr&}hoZRG^`Z6S~ zzPSy3L@7krR_YIofOs84jBjy=%JtJ*5x6Q#>_Q;Rr&!U=S)h9bioiO?7W1Tls>p@q zYI5^t2g9(?57^K(Z~M5P%Z0ddN1gI3PMchr{tddJMsp^~JevFkJa3#?*U_g6)%MKp ztckHNJb9MW!<`nh#_H5hDvJV5wz~JV;t0dR(tBsAD5f^v-+>uA@1-NeS)K9yhYLus>mmO!0W_8o@|># zdl~kb2s$+V9>7N-RtJ$$I?B=Eo!;H#779xPh2J`i1oJ!~2<=ZEd^jiQaRLuhjM)mhHlRU#S|U85p0i z;CcOvB6E;#{z}O(R^dc!+yuw=K{}(e)e`Ib=g-J6}3Bi41+Ty2gL|7w|h$M}A`BvW_X}_1$ z;`WZ-Svmbwh7%zhIC+_=;n{)*S+qdiM~+b*+ln~)Ujg|Zm3_;=OAPkY7y`|+p{1&6 z&ZU;a2imF}jqbJ)K&solmd*FzFFJKX2zJmY^2Ovt1_jcHmpqIovg6VfS(#PtYu;sh>@7+Udn|2Q$%C_cN?i7tZrnb`G??GR<3gD|J`~*DM4~PksONEt zuHhCr8kB1P)=$=OYN;kFLTe%d-OUay0=XSBO=1xxf8#!NW5KAh%pr^$Dc*^+U4*4QMgIa41` zHbtJFzl_DvxOUCxG>GKbxZEg7`$>}(_+_E6WgEf(ZNDfhuRb;?*px}V&}Vq5W$ZC) zjJ9NE{REdS=3(;vqxt2T(pt0`eR-ikiPa{=N`&!3jlksZ&qEnrEY3bzgT6A7dZw~9 zO4{O5Yfc}8u1njs*#z(@${(ZrbL23Sx)#&~WgAhPfp)rbos_Cxdv|`kwSl-z7GEGN|c)@N1!~a!IoHP}gc8 zQT1Ne1h99?E6MVszp-i&*PCWg{D}Meu(krso`TcwXK`XGQ9sFT^Qx-by{&{%(?N-ed;_Dv=0Zsg|qK9F<}Y2mY3bnCc2L~xfb7T_|^@=8do z<)~B=zg84NX{kX**gTw6y!9H{pBYP|@3R`OJ)Hf}q!^5NGMWyT8V@5k3lIpUdn8i0 z>lp5{o&BoRsC`h+*g_IikhF{F+|M4u7;?4Ms>2K+JjRLHxqnqyxQxb%B*IXRc`dC36_#U!@AMHwd8|ch*6BpT7 zwS-hy?3wGY8`}9RhW^FI#q=5V<<%GO4G#E@Q8+wNTBLJ!)AAzoyBpx{-I(HMc)ht<+mugvjZ<`Qe?(Hg zez2wQWH~_(YW7zM+ODPT;0*hXygVIe6qgxfv~?UmX(lw+|KZ|_t5RptdJdfYEAt6_ zmz7J3z77>>mBpCE&5eA@^kT=vE9G6PZ+iPW%go_=Oz3J%{(T-{H0WaQdnFe#oV3!S zaPcC>^k=&YNfm-HxZYn;o?m*|ozNO1@U@#y5orhj*=5(McSl{EWp#ZNoVP~f7Ni#b zmr644FBI1XzTAl=%(qaWfFd^1qUn;k6N*NTG086CAlvsv}bEt2YooPh$A$8N%A; zvHBTsMN8vD53gyJu=#g0hQ_bvIX%=aK2&UL1D?eR5ugLis=xl zUG=-ysc91fMx26!+4@C)(#Nh3jl<_{{+jZh>Zyql_eN|syYDum8+*KP#&@wtZqm-- zROz-n%JatNE=bc6M$J6alROQb_C#$VLjnH{Fkfk_?*}R&e(X?WgLa3tbIX}huR)R< z%gr74r@h+5XD?HO%k_;OPiS7~8()$eNM#f*EcoW&SMBWS;frI`R37WCeVgcelKX{8 zv)^>X2hUIV>#{_@N~LlzE)!sal*jI2e6dkSD zNa>y?Qi-v8PjiRgnT_gtylkHC1^Np1lS|eLhUWOj677C>7i%s3l(L*m4MjN8OG)_WN>O1I5G@E5e3pFINQKz$sqQF-P!Rt zDt8UEpS9Vx_g;IzRILC-gRpX2WM*X8Lx?Rj$6}a^~L1w#{@$aH*?$3Ti zk7;~%5G*RGFbG7pd(U~}!Ad0!l}q#XLjLcWn=9hQq`0}p`R&5ArPUU8GdJR$nuk8^ zT#$}M2e8n0Mmy*Z;9xnP+V`tEBlcotRSpjZ)v;37^YwgXw;Bt4tk>ViTl^jmawswu z|BPiaTK<)#IR494bNnQPSv|IfEstAF+a+2bRaDzrRj=Rdv}uyPgn9qAjUsNfaX1?G zjz$4Byh-b_x^zq!|IkQ1x5L-L&~#)q)8YlCynnCYaT6{JhZ~R}&4HJA6vN6vhHdx? z6N=w(EPmzEi@Ykxlfv&lJ+IZUjPNr1DO``~wLB#*48szh-)^0+VmX>92<;3q?HxUh zq_;5y+IziO{7IbNF$B59N^Bo+MpYZPv^IKI0FQb=vNemr_aFQ4#8B!=3{+AFP{9QC zetDznQ~k1Bak0)~c=4?Q3pca2xsxQ`2x~jbE7kLBI(|M{)s)YC9NHs?^h?q+;VN*h zkVBEn6R-Tkh`Sd`8bUeg&XBj0LZ;i$uU)wKZTYi!-*@i57YL)dDkixU@zzx46i3P~6kGopc_LuN7mU+ba+HYEM$rGNtoXdI6eO}U+uO@f z7hroF+4iY>bFdw|Ep~jHDVgnqzTc^GJPL4KBl^G&SMyjTNbH4Vy!yeY&hUu#y!CL* zWSZPe^v+w*+Sl$rWV%t{(_$gl^^h_#1&4Gu7N3P?x<_TI`K}BW8!R(+g_ED=)iK!Z z`-V8@Gv~Sq;hQH*v~*8pwCsb#JK#!=!mgeZEtj41W3rnlPcyfoRDV1=F%`*1r0CP) z4K@8k@>inZl-~r~!lPTG7@ur$j_F4Vj{1y^eYc>}jdbZ#hkuo_C$v%3cYn!m>gh%4 zda_%1yvY5cYaOab)D07BX5+AYVT_R;VgTVVZ%@jE^>392PygVd5Y`U97SLDNXVa8M zFwS57B<`F2WU7Qi3g}1g)2aCQrG_Ynfv{8xW4x=wn{1j+!s(t7KB3(#=jCIHzOL0z zaT)w=E<=~o26!{;Fp1!Vna1N|@5Tbx?3<=xKhbo)7D*|g996AZG;{pN9+ur2E4F)T zHRGdmclm{xeH)J^+&}lPa~X4CQ|nNtD+`T;nh1eMx%=e|0NW~}#19n#WG}0mDr+fdlhmyBP4RRPz*Ri37~q1>D+a7w z{72`y@kI%M8Sp> z?VU=%x*P%ygz^IaUc4Ayn!m3gAOZ@5{b7Sh!2hrz5nw#F3ZTsng8T^p0-^Z1DnPgh z0s(>i8wvzMB*5noBpXOV0w4bh@D~mtfjE~82!z2Q=Qc{R!N8zDB7-4+*x(Y-KjOhb z5Q+0x7y=3;*>L}20|`VR&pRR@us;GKz|cPe!od>f%LD?BDrGi`0g{ zcSBnL+nT?7gFMdy2na{~=?5X9&SQ}X#CaPj^M54%2LJ-$K%hT%2qJNK9xMU=gI16P z5)MA^2bTDg1uzVLJ~0>wLHv`0RR8}~3Q}ce-@w+ zAozT7a0KXIr|}>D;Ru+-`G5!n^q&LrpDjTk;K*}51_6QK^K6l9P~dm2)BC=^N~D5$KXLi1m*JU^oV diff --git a/doc/tutorial/tutorial.tex b/doc/tutorial/tutorial.tex index 9f8694d..4aafa20 100644 --- a/doc/tutorial/tutorial.tex +++ b/doc/tutorial/tutorial.tex @@ -24,7 +24,7 @@ \section{Overview} \paragraph{} This guide details the use of STMicroelectronics STM32 discovery kits in -an opensource environment. +an open source environment. \newpage @@ -48,18 +48,18 @@ This documentation assumes the toolchains is installed in a \$TOOLCHAIN\_PATH. \section{Installing STLINK} \paragraph{} -STLINK is an opensource software to program and debug the discovery kits. Those +STLINK is open source software to program and debug ST's STM32 Discovery kits. Those kits have an onboard chip that translates USB commands sent by the host PC into -JTAG commands. This chip is called STLINK, which is confusing since the software -has the same name. It comes into 2 versions (STLINK v1 and v2). From a software +JTAG/SWD commands. This chip is called STLINK, (yes, isn't that confusing? suggest a better +name!) and comes in 2 versions (STLINK v1 and v2). From a software point of view, those versions differ only in the transport layer used to communicate -(v1 uses SCSI passthru commands, while v2 uses raw USB). +(v1 uses SCSI passthru commands, while v2 uses raw USB). From a user point of view, they +are identical. \paragraph{} Before continuing, the following dependencies must be met: \begin{itemize} \item libusb-1.0 -\item libsgutils2 (optionnal) \end{itemize} \paragraph{} @@ -78,7 +78,7 @@ Everything can be built from the top directory:\\ \begin{small} \begin{lstlisting}[frame=tb] $> cd stlink.git -$> make CONFIG_USE_LIBSG=0 +$> make \end{lstlisting} \end{small} It includes: @@ -95,13 +95,20 @@ It includes: A simple LED blinking example is provided in the example directory. It is built using:\\ \begin{small} \begin{lstlisting}[frame=tb] -# update the make option accordingly to your architecture cd stlink.git/example/blink ; PATH=$TOOLCHAIN_PATH/bin:$PATH make \end{lstlisting} \end{small} This builds three files, one for each of the Discovery boards currently -available. +available, linked to run from SRAM. (So no risk of overwriting anything you didn't mean to) +These blink examples can safely be used to verify that: + +\begin{itemize} +\item Your installed toolchain is capable of compiling for cortex M3/M4 targets +\item stlink is functional +\item Your arm-none-eabi-gdb is functional +\item Your board is functional +\end{itemize} \paragraph{} A GDB server must be started to interact with the STM32. Depending on the discovery kit you @@ -109,10 +116,10 @@ are using, you must run one of the 2 commands:\\ \begin{small} \begin{lstlisting}[frame=tb] # STM32VL discovery kit (onboard ST-link) -$> sudo ./st-util --stlinkv1 [-d /dev/sg2] +$> ./st-util --stlinkv1 # STM32L or STM32F4 discovery kit (onboard ST-link/V2) -$> sudo ./st-util +$> ./st-util # Full help for other options (listen port, version) $> ./st-util --help @@ -140,7 +147,8 @@ By default, the program was linked such that the base address is 0x20000000. Fro memory map, GDB knows this address belongs to SRAM. To load the program in SRAM, simply use:\\ \begin{small} \begin{lstlisting}[frame=tb] -$> load blink.elf +$> # Choose one as appropriate for your Discovery kit +$> load blink_32L.elf | load blink_32VL.elf | load blink_F4.elf \end{lstlisting} \end{small} @@ -154,8 +162,7 @@ $> continue \end{small} \paragraph{} -The board BLUE and GREEN leds should be blinking (those leds are near the user and reset buttons). - +All the LEDs on the board should now be blinking in time (those leds are near the user and reset buttons). \newpage \section{Reading and writing to flash} @@ -168,13 +175,13 @@ be linked against address 0x8000000. The flash tool is then used as shown below: $> cd stlink.git/flash ; # stlinkv1 command to read 4096 from flash into out.bin -$> ./flash read /dev/sg2 out.bin 0x8000000 4096 +$> ./flash read v1 out.bin 0x8000000 4096 # stlinkv2 command $> ./flash read out.bin 0x8000000 4096 # stlinkv1 command to write the file in.bin into flash -$> ./flash write /dev/sg2 in.bin 0x8000000 +$> ./flash write v1 in.bin 0x8000000 # stlinkv2 command $> ./flash write in.bin 0x8000000 @@ -225,16 +232,6 @@ $> make \end{lstlisting} \end{small} -\subsection{STM32VL support} -\paragraph{} -It seems support for STM32VL is quite broken. If it does not work, try build STLINK using libsg: -\begin{small} -\begin{lstlisting}[frame=tb] -$> cd stlink.git -$> make CONFIG_USE_LIBSG=1 -\end{lstlisting} -\end{small} - \newpage \section{References} diff --git a/flash/main.c b/flash/main.c index 849b5d6..4415781 100644 --- a/flash/main.c +++ b/flash/main.c @@ -88,8 +88,7 @@ int main(int ac, char** av) if (o.devname != NULL) /* stlinkv1 */ { - static const int scsi_verbose = 2; - sl = stlink_v1_open(o.devname, scsi_verbose); + sl = stlink_v1_open(100); if (sl == NULL) goto on_error; } else /* stlinkv2 */ From e2245196082f8cac03b0a57a12198d9396c3ca85 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Fri, 4 Nov 2011 02:30:13 +0000 Subject: [PATCH 36/63] Include a udev rules file for v1 boards too, for permissions --- 49-stlinkv1.rules | 11 +++++++++++ README | 6 +++--- 2 files changed, 14 insertions(+), 3 deletions(-) create mode 100644 49-stlinkv1.rules diff --git a/49-stlinkv1.rules b/49-stlinkv1.rules new file mode 100644 index 0000000..d474d6a --- /dev/null +++ b/49-stlinkv1.rules @@ -0,0 +1,11 @@ +# stm32 discovery boards, with onboard st/linkv1 +# ie, STM32VL + +SUBSYSTEMS=="usb", ATTRS{idVendor}=="0483", ATTRS{idProduct}=="3744", \ + MODE:="0666", \ + SYMLINK+="stlinkv1_%n" + +# If you share your linux system with other users, or just don't like the +# idea of write permission for everybody, you can replace MODE:="0666" with +# OWNER:="yourusername" to create the device owned by you, or with +# GROUP:="somegroupname" and mange access using standard unix groups. diff --git a/README b/README index 109aa25..470c52a 100644 --- a/README +++ b/README @@ -75,13 +75,13 @@ for GDB. Setting up udev rules ===================== -For convenience, you may install udev rules file, 49-stlinkv2.rules, located +For convenience, you may install udev rules file, 49-stlinkv*.rules, located in the root of repository. You will need to copy it to /etc/udev/rules.d, and then either reboot or execute $ udevadm control --reload-rules -Udev will now create a /dev/stlinkv2_XX file, with the appropriate permissions. -This is currently all the device is for, (only one stlinkv2 is supported at +Udev will now create a /dev/stlinkv2_XX or /dev/stlinkv1_XX file, with the appropriate permissions. +This is currently all the device is for, (only one stlink of each version is supported at any time presently) Running programs from SRAM From 52b626bd16ae76df6c40d93c1d10efd334f01cec Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Fri, 4 Nov 2011 02:31:17 +0000 Subject: [PATCH 37/63] netbeans project update for flash utility --- nbproject/configurations.xml | 365 +++++++++++++++++++++++++++++++++++ nbproject/project.xml | 4 + 2 files changed, 369 insertions(+) diff --git a/nbproject/configurations.xml b/nbproject/configurations.xml index 47cfb04..e129c44 100644 --- a/nbproject/configurations.xml +++ b/nbproject/configurations.xml @@ -839,5 +839,370 @@ + + + LOCAL_SOURCES + default + + + + flash + ${MAKE} -f Makefile + ${MAKE} -f Makefile clean + + + + DEBUG + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + src + + + CONFIG_USE_LIBSG=1 + CONFIG_USE_LIBUSB=1 + + + + + + + src + + + CONFIG_USE_LIBSG=1 + CONFIG_USE_LIBUSB=1 + + + + + + + . + + + DEBUG=1 + + + + + + + + + + diff --git a/nbproject/project.xml b/nbproject/project.xml index 580df10..946c06f 100644 --- a/nbproject/project.xml +++ b/nbproject/project.xml @@ -21,6 +21,10 @@ gdbserver 0 + + flash + 0 + From fb9d6399a71ddd962d466692fc9d026e1b057c46 Mon Sep 17 00:00:00 2001 From: Petteri Aimonen Date: Thu, 10 Nov 2011 21:38:16 +0200 Subject: [PATCH 38/63] Fixed a bug that caused gdb to display wrong registers when using stlink ver 1. --- src/stlink-sg.c | 27 ++++++++++++--------------- 1 file changed, 12 insertions(+), 15 deletions(-) diff --git a/src/stlink-sg.c b/src/stlink-sg.c index 2bbbaf9..1868eba 100644 --- a/src/stlink-sg.c +++ b/src/stlink-sg.c @@ -707,9 +707,6 @@ void _stlink_sg_force_debug(stlink_t *sl) { void _stlink_sg_read_all_regs(stlink_t *sl, reg *regp) { struct stlink_libsg *sg = sl->backend_data; - /* unused */ - regp = regp; - clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_READALLREGS; sl->q_len = 84; @@ -722,23 +719,23 @@ void _stlink_sg_read_all_regs(stlink_t *sl, reg *regp) { // 0-3 | 4-7 | ... | 60-63 | 64-67 | 68-71 | 72-75 | 76-79 | 80-83 // r0 | r1 | ... | r15 | xpsr | main_sp | process_sp | rw | rw2 for (int i = 0; i < 16; i++) { - sg->reg.r[i] = read_uint32(sl->q_buf, 4 * i); + regp->r[i] = read_uint32(sl->q_buf, 4 * i); if (sl->verbose > 1) - DLOG("r%2d = 0x%08x\n", i, sg->reg.r[i]); + DLOG("r%2d = 0x%08x\n", i, regp->r[i]); } - sg->reg.xpsr = read_uint32(sl->q_buf, 64); - sg->reg.main_sp = read_uint32(sl->q_buf, 68); - sg->reg.process_sp = read_uint32(sl->q_buf, 72); - sg->reg.rw = read_uint32(sl->q_buf, 76); - sg->reg.rw2 = read_uint32(sl->q_buf, 80); + regp->xpsr = read_uint32(sl->q_buf, 64); + regp->main_sp = read_uint32(sl->q_buf, 68); + regp->process_sp = read_uint32(sl->q_buf, 72); + regp->rw = read_uint32(sl->q_buf, 76); + regp->rw2 = read_uint32(sl->q_buf, 80); if (sl->verbose < 2) return; - DLOG("xpsr = 0x%08x\n", sg->reg.xpsr); - DLOG("main_sp = 0x%08x\n", sg->reg.main_sp); - DLOG("process_sp = 0x%08x\n", sg->reg.process_sp); - DLOG("rw = 0x%08x\n", sg->reg.rw); - DLOG("rw2 = 0x%08x\n", sg->reg.rw2); + DLOG("xpsr = 0x%08x\n", regp->xpsr); + DLOG("main_sp = 0x%08x\n", regp->main_sp); + DLOG("process_sp = 0x%08x\n", regp->process_sp); + DLOG("rw = 0x%08x\n", regp->rw); + DLOG("rw2 = 0x%08x\n", regp->rw2); } // Read an arm-core register, the index must be in the range 0..20. From e9a205ff98bea6a3a902352711a3980ccd4518be Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Fri, 11 Nov 2011 15:38:09 +0000 Subject: [PATCH 39/63] Finish removing sg-utils dependencies. The code deps were removed, but the flags stayed in some makefiles. --- flash/Makefile | 16 ---------------- gdbserver/Makefile | 15 --------------- 2 files changed, 31 deletions(-) diff --git a/flash/Makefile b/flash/Makefile index 8a30b41..6e16754 100644 --- a/flash/Makefile +++ b/flash/Makefile @@ -1,10 +1,3 @@ -# make ... for both libusb and libsg -# -# make CONFIG_USE_LIBSG=0 ... -# for just libusb -# -CC=gcc - CFLAGS+=-g CFLAGS+=-DCONFIG_USE_LIBUSB=1 CFLAGS+=-DDEBUG @@ -14,15 +7,6 @@ CFLAGS+=-I../src LDFLAGS=-lusb-1.0 -L.. -lstlink -ifeq ($(CONFIG_USE_LIBSG),) -CONFIG_USE_LIBSG=1 -endif - -ifneq ($(CONFIG_USE_LIBSG),0) -CFLAGS+=-DCONFIG_USE_LIBSG=1 -LDFLAGS+=-lsgutils2 -endif - SRCS=main.c OBJS=$(SRCS:.c=.o) diff --git a/gdbserver/Makefile b/gdbserver/Makefile index a8d1b90..e73103d 100644 --- a/gdbserver/Makefile +++ b/gdbserver/Makefile @@ -1,9 +1,3 @@ -# make ... for both libusb and libsg -# -# make CONFIG_USE_LIBSG=0 ... -# for just libusb -# - PRG := st-util OBJS = gdb-remote.o gdb-server.o @@ -11,15 +5,6 @@ CFLAGS+=-g -Wall -Werror -std=gnu99 -I../src CFLAGS+=-DCONFIG_USE_LIBUSB=1 LDFLAGS=-lusb-1.0 -L.. -lstlink -ifeq ($(CONFIG_USE_LIBSG),) -CONFIG_USE_LIBSG=1 -endif - -ifneq ($(CONFIG_USE_LIBSG),0) -CFLAGS+=-DCONFIG_USE_LIBSG=1 -LDFLAGS+=-lsgutils2 -endif - all: $(PRG) $(PRG): $(OBJS) From 5a5d36fdc3f1732d595fe923e45433d9e32077af Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Sat, 12 Nov 2011 20:36:43 +0000 Subject: [PATCH 40/63] Move all the flash size mapping from gdb server into core. All the device params like flash size and page size should all be in the core open routines, not _only_ in the gdbserver. (This should stop it from ending up duplicated in the core, and get rid of some of the hacks that were turning up. All of this is chip specific!) --- gdbserver/gdb-server.c | 76 +++------------------- src/stlink-common.c | 44 +++++++++++++ src/stlink-common.h | 141 +++++++++++++++++++++++++++++++++++++---- src/stlink-sg.c | 16 +---- src/stlink-usb.c | 40 +----------- 5 files changed, 185 insertions(+), 132 deletions(-) diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index bcb3c97..ce0549e 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -45,39 +45,6 @@ static const char* current_memory_map = NULL; #define CORE_M3_R2 0x4BA00477 #define CORE_M4_R0 0x2BA01477 -struct chip_params { - uint32_t chip_id; - char* description; - uint32_t flash_size_reg; - uint32_t max_flash_size, flash_pagesize; - uint32_t sram_size; - uint32_t bootrom_base, bootrom_size; -} const devices[] = { - { 0x410, "F1 Medium-density device", 0x1ffff7e0, - 0x20000, 0x400, 0x5000, 0x1ffff000, 0x800 }, // table 2, pm0063 - { 0x411, "F2 device", 0, /* No flash size register found in the docs*/ - 0x100000, 0x20000, 0x20000, 0x1fff0000, 0x7800 }, // table 1, pm0059 - { 0x412, "F1 Low-density device", 0x1ffff7e0, - 0x8000, 0x400, 0x2800, 0x1ffff000, 0x800 }, // table 1, pm0063 - { 0x413, "F4 device", 0x1FFF7A10, - 0x100000, 0x20000, 0x30000, 0x1fff0000, 0x7800 }, // table 1, pm0081 - { 0x414, "F1 High-density device", 0x1ffff7e0, - 0x80000, 0x800, 0x10000, 0x1ffff000, 0x800 }, // table 3 pm0063 - // This ignores the EEPROM! (and uses the page erase size, - // not the sector write protection...) - { 0x416, "L1 Med-density device", 0x1FF8004C, // table 1, pm0062 - 0x20000, 0x100, 0x4000, 0x1ff00000, 0x1000 }, - { 0x418, "F1 Connectivity line device", 0x1ffff7e0, - 0x40000, 0x800, 0x10000, 0x1fffb000, 0x4800 }, - { 0x420, "F1 Medium-density value line device", 0x1ffff7e0, - 0x20000, 0x400, 0x2000, 0x1ffff000, 0x800 }, - { 0x428, "F1 High-density value line device", 0x1ffff7e0, - 0x80000, 0x800, 0x8000, 0x1ffff000, 0x800 }, - { 0x430, "F1 XL-density device", 0x1ffff7e0, // pm0068 - 0x100000, 0x800, 0x18000, 0x1fffe000, 0x1800 }, - { 0 } -}; - typedef struct _st_state_t { // things from command line, bleh int stlink_version; @@ -89,7 +56,7 @@ typedef struct _st_state_t { int serve(stlink_t *sl, int port); -char* make_memory_map(const struct chip_params *params, uint32_t flash_size); +char* make_memory_map(stlink_t *sl); int parse_options(int argc, char** argv, st_state_t *st) { @@ -201,6 +168,8 @@ int main(int argc, char** argv) { if(sl == NULL) return 1; break; } + + // ALLLL of this should move into "stlink_open_xxx" if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) { if (stlink_current_mode(sl) == STLINK_DEV_DFU_MODE) { @@ -220,34 +189,7 @@ int main(int argc, char** argv) { printf("Chip ID is %08x, Core ID is %08x.\n", chip_id, core_id); - const struct chip_params* params = NULL; - - for(int i = 0; i < sizeof(devices) / sizeof(devices[0]); i++) { - if(devices[i].chip_id == (chip_id & 0xFFF)) { - params = &devices[i]; - break; - } - } - - if(params == NULL) { - fprintf(stderr, "Cannot recognize the connected device!\n"); - return 0; - } - - printf("Device connected: %s\n", params->description); - printf("Device parameters: SRAM: 0x%x bytes, Flash: up to 0x%x bytes in pages of 0x%x bytes\n", - params->sram_size, params->max_flash_size, params->flash_pagesize); - - FLASH_PAGE = params->flash_pagesize; - - uint32_t flash_size; - - stlink_read_mem32(sl, params->flash_size_reg, 4); - flash_size = sl->q_buf[0] | (sl->q_buf[1] << 8); - - printf("Flash size is %d KiB.\n", flash_size); - // memory map is in 1k blocks. - current_memory_map = make_memory_map(params, flash_size * 0x400); + current_memory_map = make_memory_map(sl); while(serve(sl, state.listen_port) == 0); @@ -275,16 +217,16 @@ static const char* const memory_map_template = " " // option byte area ""; -char* make_memory_map(const struct chip_params *params, uint32_t flash_size) { +char* make_memory_map(stlink_t *sl) { /* This will be freed in serve() */ char* map = malloc(4096); map[0] = '\0'; snprintf(map, 4096, memory_map_template, - flash_size, - params->sram_size, - flash_size, params->flash_pagesize, - params->bootrom_base, params->bootrom_size); + sl->flash_size, + sl->sram_size, + sl->flash_size, sl->flash_pgsz, + sl->sys_base, sl->sys_size); return map; } diff --git a/src/stlink-common.c b/src/stlink-common.c index f58c344..89c2630 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -305,6 +305,50 @@ void stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid) { return; } +/** + * reads and decodes the flash parameters, as dynamically as possible + * @param sl + * @return 0 for success, or -1 for unsupported core type. + */ +int stlink_load_device_params(stlink_t *sl) { + ILOG("Loading device parameters....\n"); + chip_params_t *params = NULL; + uint32_t chip_id = stlink_chip_id(sl); + for(size_t i = 0; i < sizeof(devices) / sizeof(devices[0]); i++) { + if(devices[i].chip_id == (chip_id & 0xFFF)) { + params = &devices[i]; + break; + } + } + if (params == NULL) { + WLOG("unknown chip id! %#x\n", chip_id); + return -1; + } + + // These are fixed... + sl->flash_base = STM32_FLASH_BASE; + sl->sram_base = STM32_SRAM_BASE; + + // read flash size from hardware, if possible... + if ((chip_id & 0xFFF) == STM32_CHIPID_F2) { + sl->flash_size = 0; // FIXME - need to work this out some other way, just set to max possible? + } else { + stlink_read_mem32(sl, params->flash_size_reg, 4); + uint32_t flash_size = sl->q_buf[0] | (sl->q_buf[1] << 8); + sl->flash_size = flash_size * 1024; + } + sl->flash_pgsz = params->flash_pagesize; + sl->sram_size = params->sram_size; + sl->sys_base = params->bootrom_base; + sl->sys_size = params->bootrom_size; + + ILOG("Device connected is: %s\n", params->description); + ILOG("SRAM size: %#x bytes (%d KiB), Flash: %#x bytes (%d KiB) in pages of %zd bytes\n", + sl->sram_size, sl->sram_size / 1024, sl->flash_size, sl->flash_size / 1024, + sl->flash_pgsz); + return 0; +} + void stlink_reset(stlink_t *sl) { DLOG("*** stlink_reset ***\n"); sl->backend->reset(sl); diff --git a/src/stlink-common.h b/src/stlink-common.h index bcd60aa..5534b6f 100644 --- a/src/stlink-common.h +++ b/src/stlink-common.h @@ -80,10 +80,134 @@ extern "C" { #define STM32VL_CORE_ID 0x1ba01477 #define STM32L_CORE_ID 0x2ba01477 #define STM32F4_CORE_ID 0x2ba01477 + +// stm32 chipids, only lower 12 bits.. +#define STM32_CHIPID_F1_MEDIUM 0x410 +#define STM32_CHIPID_F2 0x411 +#define STM32_CHIPID_F1_LOW 0x412 +#define STM32_CHIPID_F4 0x413 +#define STM32_CHIPID_F1_HIGH 0x414 +#define STM32_CHIPID_L1_MEDIUM 0x416 +#define STM32_CHIPID_F1_CONN 0x418 +#define STM32_CHIPID_F1_VL_MEDIUM 0x420 +#define STM32_CHIPID_F1_VL_HIGH 0x428 +#define STM32_CHIPID_F1_XL 0x430 + +// Constant STM32 memory map figures +#define STM32_FLASH_BASE 0x08000000 +#define STM32_SRAM_BASE 0x20000000 /* Enough space to hold both a V2 command or a V1 command packaged as generic scsi*/ #define C_BUF_LEN 32 + typedef struct chip_params_ { + uint32_t chip_id; + char* description; + uint32_t flash_size_reg; + uint32_t flash_pagesize; + uint32_t sram_size; + uint32_t bootrom_base, bootrom_size; + } chip_params_t; + + + // These maps are from a combination of the Programming Manuals, and + // also the Reference manuals. (flash size reg is normally in ref man) + static const chip_params_t devices[] = { + { // table 2, PM0063 + .chip_id = 0x410, + .description = "F1 Medium-density device", + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x400, + .sram_size = 0x5000, + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800 + }, + { // table 1, PM0059 + .chip_id = 0x411, + .description = "F2 device", + .flash_size_reg = 0, /* no flash size reg found in the docs! */ + .flash_pagesize = 0x20000, + .sram_size = 0x20000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800 + }, + { // PM0063 + .chip_id = 0x412, + .description = "F1 Low-density device", + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x400, + .sram_size = 0x2800, + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800 + }, + { + .chip_id = 0x413, + .description = "F4 device", + .flash_size_reg = 0x1FFF7A10, + .flash_pagesize = 0x20000, + .sram_size = 0x30000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800 + }, + { + .chip_id = 0x414, + .description = "F1 High-density device", + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x800, + .sram_size = 0x10000, + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800 + }, + { + // This ignores the EEPROM! (and uses the page erase size, + // not the sector write protection...) + .chip_id = 0x416, + .description = "L1 Med-density device", + .flash_size_reg = 0x1ff8004c, + .flash_pagesize = 0x100, + .sram_size = 0x4000, + .bootrom_base = 0x1ff00000, + .bootrom_size = 0x1000 + }, + { + .chip_id = 0x418, + .description = "F1 Connectivity line device", + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x800, + .sram_size = 0x10000, + .bootrom_base = 0x1fffb000, + .bootrom_size = 0x4800 + }, + { + .chip_id = 0x420, + .description = "F1 Medium-density Value Line device", + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x400, + .sram_size = 0x2000, + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800 + }, + { + .chip_id = 0x428, + .description = "F1 High-density value line device", + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x800, + .sram_size = 0x8000, + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800 + }, + { + .chip_id = 0x430, + .description = "F1 XL-density device", + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x800, + .sram_size = 0x18000, + .bootrom_base = 0x1fffe000, + .bootrom_size = 0x1800 + } + }; + + typedef struct { uint32_t r[16]; uint32_t xpsr; @@ -161,29 +285,21 @@ extern "C" { uint32_t core_id; int core_stat; - - - /* medium density stm32 flash settings */ -#define STM32_FLASH_BASE 0x08000000 -#define STM32_FLASH_SIZE (128 * 1024) #define STM32_FLASH_PGSZ 1024 #define STM32L_FLASH_PGSZ 256 stm32_addr_t flash_base; size_t flash_size; size_t flash_pgsz; - /* in flash system memory */ -#define STM32_SYSTEM_BASE 0x1ffff000 -#define STM32_SYSTEM_SIZE (2 * 1024) - stm32_addr_t sys_base; - size_t sys_size; - /* sram settings */ -#define STM32_SRAM_BASE 0x20000000 #define STM32_SRAM_SIZE (8 * 1024) #define STM32L_SRAM_SIZE (16 * 1024) stm32_addr_t sram_base; size_t sram_size; + + // bootloader + stm32_addr_t sys_base; + size_t sys_size; struct stlink_version_ version; }; @@ -236,6 +352,7 @@ extern "C" { int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size); int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size); int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size); + int stlink_load_device_params(stlink_t *sl); diff --git a/src/stlink-sg.c b/src/stlink-sg.c index 1868eba..fd10c16 100644 --- a/src/stlink-sg.c +++ b/src/stlink-sg.c @@ -1100,19 +1100,6 @@ static stlink_t* stlink_open(const int verbose) { sl->core_stat = STLINK_CORE_STAT_UNKNOWN; slsg->q_addr = 0; - /* flash memory settings */ - sl->flash_base = STM32_FLASH_BASE; - sl->flash_size = STM32_FLASH_SIZE; - sl->flash_pgsz = STM32_FLASH_PGSZ; - - /* system memory */ - sl->sys_base = STM32_SYSTEM_BASE; - sl->sys_size = STM32_SYSTEM_SIZE; - - /* sram memory settings */ - sl->sram_base = STM32_SRAM_BASE; - sl->sram_size = STM32_SRAM_SIZE; - return sl; } @@ -1127,7 +1114,7 @@ stlink_t* stlink_v1_open(const int verbose) { } stlink_version(sl); - + stlink_load_device_params(sl); if ((sl->version.st_vid != USB_ST_VID) || (sl->version.stlink_pid != USB_STLINK_PID)) { ugly_log(UERROR, LOG_TAG, "WTF? successfully opened, but unable to read version details. BROKEN!\n"); @@ -1160,5 +1147,6 @@ stlink_t* stlink_v1_open(const int verbose) { } // re-query device info stlink_version(sl); + stlink_load_device_params(sl); return sl; } diff --git a/src/stlink-usb.c b/src/stlink-usb.c index 785f7be..b4df70e 100644 --- a/src/stlink-usb.c +++ b/src/stlink-usb.c @@ -673,45 +673,7 @@ stlink_t* stlink_open_usb(const int verbose) { } stlink_version(sl); - - /* per device family initialization */ - stlink_core_id(sl); - if (sl->core_id == STM32L_CORE_ID) { - - /* flash memory settings */ - sl->flash_base = STM32_FLASH_BASE; - sl->flash_size = STM32_FLASH_SIZE; - sl->flash_pgsz = STM32L_FLASH_PGSZ; - - /* system memory */ - sl->sys_base = STM32_SYSTEM_BASE; - sl->sys_size = STM32_SYSTEM_SIZE; - - /* sram memory settings */ - sl->sram_base = STM32_SRAM_BASE; - sl->sram_size = STM32L_SRAM_SIZE; - - } else if (sl->core_id == STM32VL_CORE_ID) { - - /* flash memory settings */ - sl->flash_base = STM32_FLASH_BASE; - sl->flash_size = STM32_FLASH_SIZE; - sl->flash_pgsz = STM32_FLASH_PGSZ; - - /* system memory */ - sl->sys_base = STM32_SYSTEM_BASE; - sl->sys_size = STM32_SYSTEM_SIZE; - - /* sram memory settings */ - sl->sram_base = STM32_SRAM_BASE; - sl->sram_size = STM32_SRAM_SIZE; - - } else { - - fprintf(stderr, "unknown coreid: %x\n", sl->core_id); - goto on_libusb_error; - - } + stlink_load_device_params(sl); error = 0; From 0c587eedfd33396cc6da94850e0dfcac15a953f2 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Sat, 12 Nov 2011 20:45:41 +0000 Subject: [PATCH 41/63] Read chip and core id in device param loading. Instead of expecting everyone to read it every time they need to check it. Just assume it's always there. --- src/stlink-common.c | 5 +++-- src/stlink-common.h | 1 + 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index 89c2630..3391f4f 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -314,6 +314,7 @@ int stlink_load_device_params(stlink_t *sl) { ILOG("Loading device parameters....\n"); chip_params_t *params = NULL; uint32_t chip_id = stlink_chip_id(sl); + sl->chip_id = chip_id; for(size_t i = 0; i < sizeof(devices) / sizeof(devices[0]); i++) { if(devices[i].chip_id == (chip_id & 0xFFF)) { params = &devices[i]; @@ -342,6 +343,8 @@ int stlink_load_device_params(stlink_t *sl) { sl->sys_base = params->bootrom_base; sl->sys_size = params->bootrom_size; + sl->core_id = stlink_core_id(sl); + ILOG("Device connected is: %s\n", params->description); ILOG("SRAM size: %#x bytes (%d KiB), Flash: %#x bytes (%d KiB) in pages of %zd bytes\n", sl->sram_size, sl->sram_size / 1024, sl->flash_size, sl->flash_size / 1024, @@ -742,7 +745,6 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t page) { /* page an addr in the page to erase */ - stlink_core_id(sl); if (sl->core_id == STM32L_CORE_ID) { #define STM32L_FLASH_REGS_ADDR ((uint32_t)0x40023c00) @@ -1020,7 +1022,6 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned } } - stlink_core_id(sl); if (sl->core_id == STM32L_CORE_ID) { /* use fast word write. todo: half page. */ diff --git a/src/stlink-common.h b/src/stlink-common.h index 5534b6f..9279c37 100644 --- a/src/stlink-common.h +++ b/src/stlink-common.h @@ -283,6 +283,7 @@ extern "C" { // transport layer verboseness: 0 for no debug info, 10 for lots int verbose; uint32_t core_id; + uint32_t chip_id; int core_stat; #define STM32_FLASH_PGSZ 1024 From 3c6f2f5231a11bc73e3bce0003318d0f87614ad1 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Mon, 14 Nov 2011 01:25:56 +0000 Subject: [PATCH 42/63] Fix flash writing for VL cores. The change from run->step breaks the VL cores. Need to double check that this still works for L cores. The whole flash writing needs to be better abstracted. Lots more informational debug. --- src/stlink-common.c | 114 ++++++++++++++++++++++++-------------------- 1 file changed, 62 insertions(+), 52 deletions(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index 3391f4f..4286cf0 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -24,7 +24,7 @@ /* todo: stm32l15xxx flash memory, pm0062 manual */ /* stm32f FPEC flash controller interface, pm0063 manual */ - +// TODO - all of this needs to be abstracted out.... #define FLASH_REGS_ADDR 0x40022000 #define FLASH_REGS_SIZE 0x28 @@ -412,7 +412,7 @@ void stlink_version(stlink_t *sl) { } void stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { - DLOG("*** stlink_write_mem32 ***\n"); + DLOG("*** stlink_write_mem32 %u bytes to %#x\n", len, addr); if (len % 4 != 0) { fprintf(stderr, "Error: Data length doesn't have a 32 bit alignment: +%d byte.\n", len % 4); return; @@ -744,7 +744,7 @@ int write_buffer_to_sram(stlink_t *sl, flash_loader_t* fl, const uint8_t* buf, s int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t page) { /* page an addr in the page to erase */ - + ILOG("Erasing flash page at addr: %#x\n", page); if (sl->core_id == STM32L_CORE_ID) { #define STM32L_FLASH_REGS_ADDR ((uint32_t)0x40023c00) @@ -853,7 +853,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t page) lock_flash(sl); } else { - fprintf(stderr, "unknown coreid: %x\n", sl->core_id); + WLOG("unknown coreid: %x\n", sl->core_id); return -1; } @@ -891,13 +891,13 @@ int init_flash_loader(stlink_t *sl, flash_loader_t* fl) { /* allocate the loader in sram */ if (write_loader_to_sram(sl, &fl->loader_addr, &size) == -1) { - fprintf(stderr, "write_loader_to_sram() == -1\n"); + WLOG("Failed to write flash loader to sram!\n"); return -1; } /* allocate a one page buffer in sram right after loader */ fl->buf_addr = fl->loader_addr + size; - + ILOG("Successfully loaded flash loader in sram\n"); return 0; } @@ -960,7 +960,7 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { } else { - fprintf(stderr, "unknown coreid: %x\n", sl->core_id); + WLOG("unknown coreid, not sure what flash loader to use, aborting!: %x\n", sl->core_id); return -1; } @@ -994,33 +994,38 @@ int stlink_fcheck_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned len) { size_t off; flash_loader_t fl; - + ILOG("Attempting to write %d (%#x) bytes to stm32 address: %u (%#x)\n", + len, len, addr, addr); /* check addr range is inside the flash */ if (addr < sl->flash_base) { - fprintf(stderr, "addr too low\n"); + WLOG("addr too low\n"); return -1; } else if ((addr + len) < addr) { - fprintf(stderr, "addr overruns\n"); + WLOG("addr overruns\n"); return -1; } else if ((addr + len) > (sl->flash_base + sl->flash_size)) { - fprintf(stderr, "addr too high\n"); + WLOG("addr too high\n"); return -1; } else if ((addr & 1) || (len & 1)) { - fprintf(stderr, "unaligned addr or size\n"); + WLOG("unaligned addr or size\n"); return -1; } else if (addr & (sl->flash_pgsz - 1)) { - fprintf(stderr, "addr not a multiple of pagesize, not supported\n"); + WLOG("addr not a multiple of pagesize, not supported\n"); return -1; } /* erase each page */ + int page_count = 0; for (off = 0; off < len; off += sl->flash_pgsz) { /* addr must be an addr inside the page */ if (stlink_erase_flash_page(sl, addr + off) == -1) { - fprintf(stderr, "erase_flash_page(0x%zx) == -1\n", addr + off); - return -1; + WLOG("Failed to erase_flash_page(%#zx) == -1\n", addr + off); + return -1; } + page_count++; } + ILOG("Finished erasing %d pages of %d (%#x) bytes\n", + page_count, sl->flash_pgsz, sl->flash_pgsz); if (sl->core_id == STM32L_CORE_ID) { @@ -1139,39 +1144,41 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned val = read_uint32(sl->q_buf, 0) | (1 << 0) | (1 << 1) | (1 << 2); write_uint32(sl->q_buf, val); stlink_write_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t)); - } - else if (sl->core_id == STM32VL_CORE_ID) - { - /* flash loader initialization */ - if (init_flash_loader(sl, &fl) == -1) { - fprintf(stderr, "init_flash_loader() == -1\n"); - return -1; - } - - /* write each page. above WRITE_BLOCK_SIZE fails? */ -#define WRITE_BLOCK_SIZE 0x40 - for (off = 0; off < len; off += WRITE_BLOCK_SIZE) - { - /* adjust last write size */ - size_t size = WRITE_BLOCK_SIZE; - if ((off + WRITE_BLOCK_SIZE) > len) size = len - off; - - /* unlock and set programming mode */ - unlock_flash_if(sl); - set_flash_cr_pg(sl); - - if (run_flash_loader(sl, &fl, addr + off, base + off, size) == -1) { - fprintf(stderr, "run_flash_loader(0x%zx) == -1\n", addr + off); - return -1; + } else if (sl->core_id == STM32VL_CORE_ID) { + ILOG("Starting Flash write for VL core id\n"); + /* flash loader initialization */ + if (init_flash_loader(sl, &fl) == -1) { + WLOG("init_flash_loader() == -1\n"); + return -1; } - lock_flash(sl); - } + /* write each page. above WRITE_BLOCK_SIZE fails? */ +#define WRITE_BLOCK_SIZE 0x40 + int write_block_count = 0; + for (off = 0; off < len; off += WRITE_BLOCK_SIZE) { + ILOG("Writing flash block %d of size %d (%#x)\n", write_block_count, + WRITE_BLOCK_SIZE, WRITE_BLOCK_SIZE); + /* adjust last write size */ + size_t size = WRITE_BLOCK_SIZE; + if ((off + WRITE_BLOCK_SIZE) > len) size = len - off; + + /* unlock and set programming mode */ + unlock_flash_if(sl); + set_flash_cr_pg(sl); + //DLOG("Finished setting flash cr pg, running loader!\n"); + if (run_flash_loader(sl, &fl, addr + off, base + off, size) == -1) { + WLOG("run_flash_loader(%#zx) failed! == -1\n", addr + off); + return -1; + } + lock_flash(sl); + DLOG("Finished writing block %d\n", write_block_count++); + } } else { - fprintf(stderr, "unknown coreid: %x\n", sl->core_id); - return -1; + WLOG("unknown coreid, not sure how to write: %x\n", sl->core_id); + return -1; } + ILOG("Starting verification of write complete\n"); for (off = 0; off < len; off += sl->flash_pgsz) { size_t aligned_size; @@ -1189,32 +1196,35 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned if (memcmp(sl->q_buf, base + off, cmp_size)) return -1; } - + ILOG("Flash written and verified! jolly good!\n"); return 0; } +/** + * Write the given binary file into flash at address "addr" + * @param sl + * @param path readable file path, should be binary image + * @param addr where to start writing + * @return 0 on success, -ve on failure. + */ int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { /* write the file in flash at addr */ - int err; mapped_file_t mf = MAPPED_FILE_INITIALIZER; - if (map_file(&mf, path) == -1) { - fprintf(stderr, "map_file() == -1\n"); + WLOG("map_file() == -1\n"); return -1; } - err = stlink_write_flash(sl, addr, mf.base, mf.len); - unmap_file(&mf); - return err; } int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size) { reg rr; - + DLOG("Running flash loader, write address:%#x, size: %zd\n", target, size); + // FIXME This can never return -1 if (write_buffer_to_sram(sl, fl, buf, size) == -1) { fprintf(stderr, "write_buffer_to_sram() == -1\n"); return -1; @@ -1250,7 +1260,7 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons } /* run loader */ - stlink_step(sl); + stlink_run(sl); /* wait until done (reaches breakpoint) */ while (is_core_halted(sl) == 0) ; From 77f2d8b76c218e9edceaba71c6cc4f8724da49a1 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Mon, 14 Nov 2011 02:25:31 +0000 Subject: [PATCH 43/63] Don't try reading device params in bad USB modes. You cannot read device params when we're not in debug mode and trying to will fill the USB buffer with garbage, and you will have to unplug and replug and start again. (which will fail, because, you're in the wrong mode... :) --- src/stlink-sg.c | 36 +++++++++++++++++++++++++++--------- 1 file changed, 27 insertions(+), 9 deletions(-) diff --git a/src/stlink-sg.c b/src/stlink-sg.c index fd10c16..c4392db 100644 --- a/src/stlink-sg.c +++ b/src/stlink-sg.c @@ -1104,8 +1104,7 @@ static stlink_t* stlink_open(const int verbose) { } - -stlink_t* stlink_v1_open(const int verbose) { +stlink_t* stlink_v1_open_inner(const int verbose) { ugly_init(verbose); stlink_t *sl = stlink_open(verbose); if (sl == NULL) { @@ -1114,7 +1113,6 @@ stlink_t* stlink_v1_open(const int verbose) { } stlink_version(sl); - stlink_load_device_params(sl); if ((sl->version.st_vid != USB_ST_VID) || (sl->version.stlink_pid != USB_STLINK_PID)) { ugly_log(UERROR, LOG_TAG, "WTF? successfully opened, but unable to read version details. BROKEN!\n"); @@ -1123,11 +1121,14 @@ stlink_t* stlink_v1_open(const int verbose) { DLOG("Reading current mode...\n"); switch (stlink_current_mode(sl)) { - case STLINK_DEV_MASS_MODE: - return sl; - case STLINK_DEV_DEBUG_MODE: - // TODO go to mass? + case STLINK_DEV_MASS_MODE: return sl; + case STLINK_DEV_DEBUG_MODE: + // TODO go to mass? + return sl; + default: + ILOG("Current mode unusable, trying to get back to a useful state...\n"); + break; } DLOG("Attempting to exit DFU mode\n"); @@ -1145,8 +1146,25 @@ stlink_t* stlink_v1_open(const int verbose) { fputs("Error: could not open stlink device\n", stderr); return NULL; } - // re-query device info + // re-query device info (and retest) stlink_version(sl); - stlink_load_device_params(sl); + if ((sl->version.st_vid != USB_ST_VID) || (sl->version.stlink_pid != USB_STLINK_PID)) { + ugly_log(UERROR, LOG_TAG, + "WTF? successfully opened, but unable to read version details. BROKEN!\n"); + return NULL; + } + return sl; +} + +stlink_t* stlink_v1_open(const int verbose) { + stlink_t *sl = stlink_v1_open_inner(verbose); + if (sl == NULL) { + fputs("Error: could not open stlink device\n", stderr); + return NULL; + } + // by now, it _must_ be fully open and in a useful mode.... + stlink_enter_swd_mode(sl); + stlink_load_device_params(sl); + ILOG("Successfully opened a stlink v1 debugger\n"); return sl; } From 29cf5d590c76ef157d9697a5871b12b8af770f00 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Mon, 7 Nov 2011 22:00:13 +0000 Subject: [PATCH 44/63] Restructure libs source to support multi platform The "libstm32l_discovery" was actually the ST std periph library, plus the CMSIS core files. Renamed it as such, and restructured the directories and naming to make this easier to contain the std periph drivers for more than just one board. Verified with the LCD demo makefile, and loading it in sram again. --- example/lcd/Makefile | 21 +++++--- example/libs_stm/build/Makefile | 37 ++++++++++++++ .../inc/base/stdint.h | 0 .../inc/core_support/core_cm3.c | 0 .../inc/core_support/core_cm3.h | 0 .../inc/device_support/stm32l1xx.h | 0 .../inc/device_support/system_stm32l1xx.h | 0 .../inc => libs_stm/inc/stm32l1xx}/misc.h | 0 .../inc/stm32l1xx}/stm32l1xx_adc.h | 0 .../inc/stm32l1xx}/stm32l1xx_comp.h | 0 .../inc/stm32l1xx}/stm32l1xx_crc.h | 0 .../inc/stm32l1xx}/stm32l1xx_dac.h | 0 .../inc/stm32l1xx}/stm32l1xx_dbgmcu.h | 0 .../inc/stm32l1xx}/stm32l1xx_dma.h | 0 .../inc/stm32l1xx}/stm32l1xx_exti.h | 0 .../inc/stm32l1xx}/stm32l1xx_flash.h | 0 .../inc/stm32l1xx}/stm32l1xx_gpio.h | 0 .../inc/stm32l1xx}/stm32l1xx_i2c.h | 0 .../inc/stm32l1xx}/stm32l1xx_iwdg.h | 0 .../inc/stm32l1xx}/stm32l1xx_lcd.h | 0 .../inc/stm32l1xx}/stm32l1xx_pwr.h | 0 .../inc/stm32l1xx}/stm32l1xx_rcc.h | 0 .../inc/stm32l1xx}/stm32l1xx_rtc.h | 0 .../inc/stm32l1xx}/stm32l1xx_spi.h | 0 .../inc/stm32l1xx}/stm32l1xx_syscfg.h | 0 .../inc/stm32l1xx}/stm32l1xx_tim.h | 0 .../inc/stm32l1xx}/stm32l1xx_usart.h | 0 .../inc/stm32l1xx}/stm32l1xx_wwdg.h | 0 .../src => libs_stm/src/stm32l1xx}/misc.c | 0 .../src/stm32l1xx}/stm32l1xx_adc.c | 0 .../src/stm32l1xx}/stm32l1xx_comp.c | 0 .../src/stm32l1xx}/stm32l1xx_crc.c | 0 .../src/stm32l1xx}/stm32l1xx_dac.c | 0 .../src/stm32l1xx}/stm32l1xx_dbgmcu.c | 0 .../src/stm32l1xx}/stm32l1xx_dma.c | 0 .../src/stm32l1xx}/stm32l1xx_exti.c | 0 .../src/stm32l1xx}/stm32l1xx_flash.c | 0 .../src/stm32l1xx}/stm32l1xx_flash_ramfunc.c | 0 .../src/stm32l1xx}/stm32l1xx_gpio.c | 0 .../src/stm32l1xx}/stm32l1xx_i2c.c | 0 .../src/stm32l1xx}/stm32l1xx_iwdg.c | 0 .../src/stm32l1xx}/stm32l1xx_lcd.c | 0 .../src/stm32l1xx}/stm32l1xx_pwr.c | 0 .../src/stm32l1xx}/stm32l1xx_rcc.c | 0 .../src/stm32l1xx}/stm32l1xx_rtc.c | 0 .../src/stm32l1xx}/stm32l1xx_spi.c | 0 .../src/stm32l1xx}/stm32l1xx_syscfg.c | 0 .../src/stm32l1xx}/stm32l1xx_tim.c | 0 .../src/stm32l1xx}/stm32l1xx_usart.c | 0 .../src/stm32l1xx}/stm32l1xx_wwdg.c | 0 example/libstm32l_discovery/build/Makefile | 51 ------------------- 51 files changed, 52 insertions(+), 57 deletions(-) create mode 100644 example/libs_stm/build/Makefile rename example/{libstm32l_discovery => libs_stm}/inc/base/stdint.h (100%) rename example/{libstm32l_discovery => libs_stm}/inc/core_support/core_cm3.c (100%) rename example/{libstm32l_discovery => libs_stm}/inc/core_support/core_cm3.h (100%) rename example/{libstm32l_discovery => libs_stm}/inc/device_support/stm32l1xx.h (100%) rename example/{libstm32l_discovery => libs_stm}/inc/device_support/system_stm32l1xx.h (100%) rename example/{libstm32l_discovery/inc => libs_stm/inc/stm32l1xx}/misc.h (100%) rename example/{libstm32l_discovery/inc => libs_stm/inc/stm32l1xx}/stm32l1xx_adc.h (100%) rename example/{libstm32l_discovery/inc => libs_stm/inc/stm32l1xx}/stm32l1xx_comp.h (100%) rename example/{libstm32l_discovery/inc => libs_stm/inc/stm32l1xx}/stm32l1xx_crc.h (100%) rename example/{libstm32l_discovery/inc => libs_stm/inc/stm32l1xx}/stm32l1xx_dac.h (100%) rename example/{libstm32l_discovery/inc => libs_stm/inc/stm32l1xx}/stm32l1xx_dbgmcu.h (100%) rename example/{libstm32l_discovery/inc => libs_stm/inc/stm32l1xx}/stm32l1xx_dma.h (100%) rename example/{libstm32l_discovery/inc => libs_stm/inc/stm32l1xx}/stm32l1xx_exti.h (100%) rename example/{libstm32l_discovery/inc => libs_stm/inc/stm32l1xx}/stm32l1xx_flash.h (100%) rename example/{libstm32l_discovery/inc => libs_stm/inc/stm32l1xx}/stm32l1xx_gpio.h (100%) rename example/{libstm32l_discovery/inc => libs_stm/inc/stm32l1xx}/stm32l1xx_i2c.h (100%) rename example/{libstm32l_discovery/inc => libs_stm/inc/stm32l1xx}/stm32l1xx_iwdg.h (100%) rename example/{libstm32l_discovery/inc => libs_stm/inc/stm32l1xx}/stm32l1xx_lcd.h (100%) rename example/{libstm32l_discovery/inc => libs_stm/inc/stm32l1xx}/stm32l1xx_pwr.h (100%) rename example/{libstm32l_discovery/inc => libs_stm/inc/stm32l1xx}/stm32l1xx_rcc.h (100%) rename example/{libstm32l_discovery/inc => libs_stm/inc/stm32l1xx}/stm32l1xx_rtc.h (100%) rename example/{libstm32l_discovery/inc => libs_stm/inc/stm32l1xx}/stm32l1xx_spi.h (100%) rename example/{libstm32l_discovery/inc => libs_stm/inc/stm32l1xx}/stm32l1xx_syscfg.h (100%) rename example/{libstm32l_discovery/inc => libs_stm/inc/stm32l1xx}/stm32l1xx_tim.h (100%) rename example/{libstm32l_discovery/inc => libs_stm/inc/stm32l1xx}/stm32l1xx_usart.h (100%) rename example/{libstm32l_discovery/inc => libs_stm/inc/stm32l1xx}/stm32l1xx_wwdg.h (100%) rename example/{libstm32l_discovery/src => libs_stm/src/stm32l1xx}/misc.c (100%) rename example/{libstm32l_discovery/src => libs_stm/src/stm32l1xx}/stm32l1xx_adc.c (100%) rename example/{libstm32l_discovery/src => libs_stm/src/stm32l1xx}/stm32l1xx_comp.c (100%) rename example/{libstm32l_discovery/src => libs_stm/src/stm32l1xx}/stm32l1xx_crc.c (100%) rename example/{libstm32l_discovery/src => libs_stm/src/stm32l1xx}/stm32l1xx_dac.c (100%) rename example/{libstm32l_discovery/src => libs_stm/src/stm32l1xx}/stm32l1xx_dbgmcu.c (100%) rename example/{libstm32l_discovery/src => libs_stm/src/stm32l1xx}/stm32l1xx_dma.c (100%) rename example/{libstm32l_discovery/src => libs_stm/src/stm32l1xx}/stm32l1xx_exti.c (100%) rename example/{libstm32l_discovery/src => libs_stm/src/stm32l1xx}/stm32l1xx_flash.c (100%) rename example/{libstm32l_discovery/src => libs_stm/src/stm32l1xx}/stm32l1xx_flash_ramfunc.c (100%) rename example/{libstm32l_discovery/src => libs_stm/src/stm32l1xx}/stm32l1xx_gpio.c (100%) rename example/{libstm32l_discovery/src => libs_stm/src/stm32l1xx}/stm32l1xx_i2c.c (100%) rename example/{libstm32l_discovery/src => libs_stm/src/stm32l1xx}/stm32l1xx_iwdg.c (100%) rename example/{libstm32l_discovery/src => libs_stm/src/stm32l1xx}/stm32l1xx_lcd.c (100%) rename example/{libstm32l_discovery/src => libs_stm/src/stm32l1xx}/stm32l1xx_pwr.c (100%) rename example/{libstm32l_discovery/src => libs_stm/src/stm32l1xx}/stm32l1xx_rcc.c (100%) rename example/{libstm32l_discovery/src => libs_stm/src/stm32l1xx}/stm32l1xx_rtc.c (100%) rename example/{libstm32l_discovery/src => libs_stm/src/stm32l1xx}/stm32l1xx_spi.c (100%) rename example/{libstm32l_discovery/src => libs_stm/src/stm32l1xx}/stm32l1xx_syscfg.c (100%) rename example/{libstm32l_discovery/src => libs_stm/src/stm32l1xx}/stm32l1xx_tim.c (100%) rename example/{libstm32l_discovery/src => libs_stm/src/stm32l1xx}/stm32l1xx_usart.c (100%) rename example/{libstm32l_discovery/src => libs_stm/src/stm32l1xx}/stm32l1xx_wwdg.c (100%) delete mode 100644 example/libstm32l_discovery/build/Makefile diff --git a/example/lcd/Makefile b/example/lcd/Makefile index 0f31ae6..8bfdbbb 100644 --- a/example/lcd/Makefile +++ b/example/lcd/Makefile @@ -7,11 +7,20 @@ CFLAGS+=-mcpu=cortex-m3 -ffreestanding -nostdlib -nostdinc CFLAGS+=-I. -# stm32l_discovery lib -CFLAGS+=-I../libstm32l_discovery/inc -CFLAGS+=-I../libstm32l_discovery/inc/base -CFLAGS+=-I../libstm32l_discovery/inc/core_support -CFLAGS+=-I../libstm32l_discovery/inc/device_support + +PLATFORM=stm32l1xx +LIBS_STM_PATH=../libs_stm + +INC_CORE_SUPPORT=$(LIBS_STM_PATH)/inc/core_support +SRC_CORE_SUPPORT=$(LIBS_STM_PATH)/inc/core_support +INC_DEVICE_SUPPORT=$(LIBS_STM_PATH)/inc/device_support +INC_PLATFORM=$(LIBS_STM_PATH)/inc/$(PLATFORM) + +CFLAGS+=-I$(INC_CORE_SUPPORT) +CFLAGS+=-I$(INC_DEVICE_SUPPORT) +CFLAGS+=-I$(INC_PLATFORM) +CFLAGS+=-I$(LIBS_STM_PATH)/inc/base + # to run from SRAM CFLAGS+=-Wl,-T,linker_stm32l.lds @@ -25,7 +34,7 @@ OBJS=$(SRCS:.c=.o) all: $(ELF) $(ELF): $(OBJS) - $(CC) $(CFLAGS) -o $@ $(OBJS) -L../libstm32l_discovery/build -lstm32l_discovery + $(CC) $(CFLAGS) -o $@ $(OBJS) -L$(LIBS_STM_PATH)/build -lstm32l_discovery %.o: %.c $(CC) $(CFLAGS) -c -o $@ $^ diff --git a/example/libs_stm/build/Makefile b/example/libs_stm/build/Makefile new file mode 100644 index 0000000..d96e48c --- /dev/null +++ b/example/libs_stm/build/Makefile @@ -0,0 +1,37 @@ +LIB = libstm32l_discovery.a + +CC = arm-none-eabi-gcc +AR = arm-none-eabi-ar +RANLIB = arm-none-eabi-ranlib + +PLATFORM=stm32l1xx + +INC_CORE_SUPPORT=../inc/core_support +SRC_CORE_SUPPORT=../inc/core_support +INC_DEVICE_SUPPORT=../inc/device_support +INC_PLATFORM=../inc/$(PLATFORM) +SRC_PLATFORM=../src/$(PLATFORM) + +CFLAGS = -Wall -O2 -mlittle-endian -mthumb +CFLAGS += -mcpu=cortex-m3 -ffreestanding -nostdlib -nostdinc +CFLAGS += -I$(INC_PLATFORM) -I$(INC_DEVICE_SUPPORT) -I$(INC_CORE_SUPPORT) -I../inc/base + +SRCS=$(wildcard $(SRC_PLATFORM)/*.c) +SRCS+=$(SRC_CORE_SUPPORT)/core_cm3.c + +OBJS = $(SRCS:.c=.o) + +all: $(LIB) + +$(LIB): $(OBJS) + $(AR) -r $(LIB) $(OBJS) + $(RANLIB) $(LIB) + +%.o : %.c + $(CC) $(CFLAGS) -c -o $@ $^ + +clean: + -rm -f $(OBJS) + -rm -f $(LIB) + +.PHONY: all clean diff --git a/example/libstm32l_discovery/inc/base/stdint.h b/example/libs_stm/inc/base/stdint.h similarity index 100% rename from example/libstm32l_discovery/inc/base/stdint.h rename to example/libs_stm/inc/base/stdint.h diff --git a/example/libstm32l_discovery/inc/core_support/core_cm3.c b/example/libs_stm/inc/core_support/core_cm3.c similarity index 100% rename from example/libstm32l_discovery/inc/core_support/core_cm3.c rename to example/libs_stm/inc/core_support/core_cm3.c diff --git a/example/libstm32l_discovery/inc/core_support/core_cm3.h b/example/libs_stm/inc/core_support/core_cm3.h similarity index 100% rename from example/libstm32l_discovery/inc/core_support/core_cm3.h rename to example/libs_stm/inc/core_support/core_cm3.h diff --git a/example/libstm32l_discovery/inc/device_support/stm32l1xx.h b/example/libs_stm/inc/device_support/stm32l1xx.h similarity index 100% rename from example/libstm32l_discovery/inc/device_support/stm32l1xx.h rename to example/libs_stm/inc/device_support/stm32l1xx.h diff --git a/example/libstm32l_discovery/inc/device_support/system_stm32l1xx.h b/example/libs_stm/inc/device_support/system_stm32l1xx.h similarity index 100% rename from example/libstm32l_discovery/inc/device_support/system_stm32l1xx.h rename to example/libs_stm/inc/device_support/system_stm32l1xx.h diff --git a/example/libstm32l_discovery/inc/misc.h b/example/libs_stm/inc/stm32l1xx/misc.h similarity index 100% rename from example/libstm32l_discovery/inc/misc.h rename to example/libs_stm/inc/stm32l1xx/misc.h diff --git a/example/libstm32l_discovery/inc/stm32l1xx_adc.h b/example/libs_stm/inc/stm32l1xx/stm32l1xx_adc.h similarity index 100% rename from example/libstm32l_discovery/inc/stm32l1xx_adc.h rename to example/libs_stm/inc/stm32l1xx/stm32l1xx_adc.h diff --git a/example/libstm32l_discovery/inc/stm32l1xx_comp.h b/example/libs_stm/inc/stm32l1xx/stm32l1xx_comp.h similarity index 100% rename from example/libstm32l_discovery/inc/stm32l1xx_comp.h rename to example/libs_stm/inc/stm32l1xx/stm32l1xx_comp.h diff --git a/example/libstm32l_discovery/inc/stm32l1xx_crc.h b/example/libs_stm/inc/stm32l1xx/stm32l1xx_crc.h similarity index 100% rename from example/libstm32l_discovery/inc/stm32l1xx_crc.h rename to example/libs_stm/inc/stm32l1xx/stm32l1xx_crc.h diff --git a/example/libstm32l_discovery/inc/stm32l1xx_dac.h b/example/libs_stm/inc/stm32l1xx/stm32l1xx_dac.h similarity index 100% rename from example/libstm32l_discovery/inc/stm32l1xx_dac.h rename to example/libs_stm/inc/stm32l1xx/stm32l1xx_dac.h diff --git a/example/libstm32l_discovery/inc/stm32l1xx_dbgmcu.h b/example/libs_stm/inc/stm32l1xx/stm32l1xx_dbgmcu.h similarity index 100% rename from example/libstm32l_discovery/inc/stm32l1xx_dbgmcu.h rename to example/libs_stm/inc/stm32l1xx/stm32l1xx_dbgmcu.h diff --git a/example/libstm32l_discovery/inc/stm32l1xx_dma.h b/example/libs_stm/inc/stm32l1xx/stm32l1xx_dma.h similarity index 100% rename from example/libstm32l_discovery/inc/stm32l1xx_dma.h rename to example/libs_stm/inc/stm32l1xx/stm32l1xx_dma.h diff --git a/example/libstm32l_discovery/inc/stm32l1xx_exti.h b/example/libs_stm/inc/stm32l1xx/stm32l1xx_exti.h similarity index 100% rename from example/libstm32l_discovery/inc/stm32l1xx_exti.h rename to example/libs_stm/inc/stm32l1xx/stm32l1xx_exti.h diff --git a/example/libstm32l_discovery/inc/stm32l1xx_flash.h b/example/libs_stm/inc/stm32l1xx/stm32l1xx_flash.h similarity index 100% rename from example/libstm32l_discovery/inc/stm32l1xx_flash.h rename to example/libs_stm/inc/stm32l1xx/stm32l1xx_flash.h diff --git a/example/libstm32l_discovery/inc/stm32l1xx_gpio.h b/example/libs_stm/inc/stm32l1xx/stm32l1xx_gpio.h similarity index 100% rename from example/libstm32l_discovery/inc/stm32l1xx_gpio.h rename to example/libs_stm/inc/stm32l1xx/stm32l1xx_gpio.h diff --git a/example/libstm32l_discovery/inc/stm32l1xx_i2c.h b/example/libs_stm/inc/stm32l1xx/stm32l1xx_i2c.h similarity index 100% rename from example/libstm32l_discovery/inc/stm32l1xx_i2c.h rename to example/libs_stm/inc/stm32l1xx/stm32l1xx_i2c.h diff --git a/example/libstm32l_discovery/inc/stm32l1xx_iwdg.h b/example/libs_stm/inc/stm32l1xx/stm32l1xx_iwdg.h similarity index 100% rename from example/libstm32l_discovery/inc/stm32l1xx_iwdg.h rename to example/libs_stm/inc/stm32l1xx/stm32l1xx_iwdg.h diff --git a/example/libstm32l_discovery/inc/stm32l1xx_lcd.h b/example/libs_stm/inc/stm32l1xx/stm32l1xx_lcd.h similarity index 100% rename from example/libstm32l_discovery/inc/stm32l1xx_lcd.h rename to example/libs_stm/inc/stm32l1xx/stm32l1xx_lcd.h diff --git a/example/libstm32l_discovery/inc/stm32l1xx_pwr.h b/example/libs_stm/inc/stm32l1xx/stm32l1xx_pwr.h similarity index 100% rename from example/libstm32l_discovery/inc/stm32l1xx_pwr.h rename to example/libs_stm/inc/stm32l1xx/stm32l1xx_pwr.h diff --git a/example/libstm32l_discovery/inc/stm32l1xx_rcc.h b/example/libs_stm/inc/stm32l1xx/stm32l1xx_rcc.h similarity index 100% rename from example/libstm32l_discovery/inc/stm32l1xx_rcc.h rename to example/libs_stm/inc/stm32l1xx/stm32l1xx_rcc.h diff --git a/example/libstm32l_discovery/inc/stm32l1xx_rtc.h b/example/libs_stm/inc/stm32l1xx/stm32l1xx_rtc.h similarity index 100% rename from example/libstm32l_discovery/inc/stm32l1xx_rtc.h rename to example/libs_stm/inc/stm32l1xx/stm32l1xx_rtc.h diff --git a/example/libstm32l_discovery/inc/stm32l1xx_spi.h b/example/libs_stm/inc/stm32l1xx/stm32l1xx_spi.h similarity index 100% rename from example/libstm32l_discovery/inc/stm32l1xx_spi.h rename to example/libs_stm/inc/stm32l1xx/stm32l1xx_spi.h diff --git a/example/libstm32l_discovery/inc/stm32l1xx_syscfg.h b/example/libs_stm/inc/stm32l1xx/stm32l1xx_syscfg.h similarity index 100% rename from example/libstm32l_discovery/inc/stm32l1xx_syscfg.h rename to example/libs_stm/inc/stm32l1xx/stm32l1xx_syscfg.h diff --git a/example/libstm32l_discovery/inc/stm32l1xx_tim.h b/example/libs_stm/inc/stm32l1xx/stm32l1xx_tim.h similarity index 100% rename from example/libstm32l_discovery/inc/stm32l1xx_tim.h rename to example/libs_stm/inc/stm32l1xx/stm32l1xx_tim.h diff --git a/example/libstm32l_discovery/inc/stm32l1xx_usart.h b/example/libs_stm/inc/stm32l1xx/stm32l1xx_usart.h similarity index 100% rename from example/libstm32l_discovery/inc/stm32l1xx_usart.h rename to example/libs_stm/inc/stm32l1xx/stm32l1xx_usart.h diff --git a/example/libstm32l_discovery/inc/stm32l1xx_wwdg.h b/example/libs_stm/inc/stm32l1xx/stm32l1xx_wwdg.h similarity index 100% rename from example/libstm32l_discovery/inc/stm32l1xx_wwdg.h rename to example/libs_stm/inc/stm32l1xx/stm32l1xx_wwdg.h diff --git a/example/libstm32l_discovery/src/misc.c b/example/libs_stm/src/stm32l1xx/misc.c similarity index 100% rename from example/libstm32l_discovery/src/misc.c rename to example/libs_stm/src/stm32l1xx/misc.c diff --git a/example/libstm32l_discovery/src/stm32l1xx_adc.c b/example/libs_stm/src/stm32l1xx/stm32l1xx_adc.c similarity index 100% rename from example/libstm32l_discovery/src/stm32l1xx_adc.c rename to example/libs_stm/src/stm32l1xx/stm32l1xx_adc.c diff --git a/example/libstm32l_discovery/src/stm32l1xx_comp.c b/example/libs_stm/src/stm32l1xx/stm32l1xx_comp.c similarity index 100% rename from example/libstm32l_discovery/src/stm32l1xx_comp.c rename to example/libs_stm/src/stm32l1xx/stm32l1xx_comp.c diff --git a/example/libstm32l_discovery/src/stm32l1xx_crc.c b/example/libs_stm/src/stm32l1xx/stm32l1xx_crc.c similarity index 100% rename from example/libstm32l_discovery/src/stm32l1xx_crc.c rename to example/libs_stm/src/stm32l1xx/stm32l1xx_crc.c diff --git a/example/libstm32l_discovery/src/stm32l1xx_dac.c b/example/libs_stm/src/stm32l1xx/stm32l1xx_dac.c similarity index 100% rename from example/libstm32l_discovery/src/stm32l1xx_dac.c rename to example/libs_stm/src/stm32l1xx/stm32l1xx_dac.c diff --git a/example/libstm32l_discovery/src/stm32l1xx_dbgmcu.c b/example/libs_stm/src/stm32l1xx/stm32l1xx_dbgmcu.c similarity index 100% rename from example/libstm32l_discovery/src/stm32l1xx_dbgmcu.c rename to example/libs_stm/src/stm32l1xx/stm32l1xx_dbgmcu.c diff --git a/example/libstm32l_discovery/src/stm32l1xx_dma.c b/example/libs_stm/src/stm32l1xx/stm32l1xx_dma.c similarity index 100% rename from example/libstm32l_discovery/src/stm32l1xx_dma.c rename to example/libs_stm/src/stm32l1xx/stm32l1xx_dma.c diff --git a/example/libstm32l_discovery/src/stm32l1xx_exti.c b/example/libs_stm/src/stm32l1xx/stm32l1xx_exti.c similarity index 100% rename from example/libstm32l_discovery/src/stm32l1xx_exti.c rename to example/libs_stm/src/stm32l1xx/stm32l1xx_exti.c diff --git a/example/libstm32l_discovery/src/stm32l1xx_flash.c b/example/libs_stm/src/stm32l1xx/stm32l1xx_flash.c similarity index 100% rename from example/libstm32l_discovery/src/stm32l1xx_flash.c rename to example/libs_stm/src/stm32l1xx/stm32l1xx_flash.c diff --git a/example/libstm32l_discovery/src/stm32l1xx_flash_ramfunc.c b/example/libs_stm/src/stm32l1xx/stm32l1xx_flash_ramfunc.c similarity index 100% rename from example/libstm32l_discovery/src/stm32l1xx_flash_ramfunc.c rename to example/libs_stm/src/stm32l1xx/stm32l1xx_flash_ramfunc.c diff --git a/example/libstm32l_discovery/src/stm32l1xx_gpio.c b/example/libs_stm/src/stm32l1xx/stm32l1xx_gpio.c similarity index 100% rename from example/libstm32l_discovery/src/stm32l1xx_gpio.c rename to example/libs_stm/src/stm32l1xx/stm32l1xx_gpio.c diff --git a/example/libstm32l_discovery/src/stm32l1xx_i2c.c b/example/libs_stm/src/stm32l1xx/stm32l1xx_i2c.c similarity index 100% rename from example/libstm32l_discovery/src/stm32l1xx_i2c.c rename to example/libs_stm/src/stm32l1xx/stm32l1xx_i2c.c diff --git a/example/libstm32l_discovery/src/stm32l1xx_iwdg.c b/example/libs_stm/src/stm32l1xx/stm32l1xx_iwdg.c similarity index 100% rename from example/libstm32l_discovery/src/stm32l1xx_iwdg.c rename to example/libs_stm/src/stm32l1xx/stm32l1xx_iwdg.c diff --git a/example/libstm32l_discovery/src/stm32l1xx_lcd.c b/example/libs_stm/src/stm32l1xx/stm32l1xx_lcd.c similarity index 100% rename from example/libstm32l_discovery/src/stm32l1xx_lcd.c rename to example/libs_stm/src/stm32l1xx/stm32l1xx_lcd.c diff --git a/example/libstm32l_discovery/src/stm32l1xx_pwr.c b/example/libs_stm/src/stm32l1xx/stm32l1xx_pwr.c similarity index 100% rename from example/libstm32l_discovery/src/stm32l1xx_pwr.c rename to example/libs_stm/src/stm32l1xx/stm32l1xx_pwr.c diff --git a/example/libstm32l_discovery/src/stm32l1xx_rcc.c b/example/libs_stm/src/stm32l1xx/stm32l1xx_rcc.c similarity index 100% rename from example/libstm32l_discovery/src/stm32l1xx_rcc.c rename to example/libs_stm/src/stm32l1xx/stm32l1xx_rcc.c diff --git a/example/libstm32l_discovery/src/stm32l1xx_rtc.c b/example/libs_stm/src/stm32l1xx/stm32l1xx_rtc.c similarity index 100% rename from example/libstm32l_discovery/src/stm32l1xx_rtc.c rename to example/libs_stm/src/stm32l1xx/stm32l1xx_rtc.c diff --git a/example/libstm32l_discovery/src/stm32l1xx_spi.c b/example/libs_stm/src/stm32l1xx/stm32l1xx_spi.c similarity index 100% rename from example/libstm32l_discovery/src/stm32l1xx_spi.c rename to example/libs_stm/src/stm32l1xx/stm32l1xx_spi.c diff --git a/example/libstm32l_discovery/src/stm32l1xx_syscfg.c b/example/libs_stm/src/stm32l1xx/stm32l1xx_syscfg.c similarity index 100% rename from example/libstm32l_discovery/src/stm32l1xx_syscfg.c rename to example/libs_stm/src/stm32l1xx/stm32l1xx_syscfg.c diff --git a/example/libstm32l_discovery/src/stm32l1xx_tim.c b/example/libs_stm/src/stm32l1xx/stm32l1xx_tim.c similarity index 100% rename from example/libstm32l_discovery/src/stm32l1xx_tim.c rename to example/libs_stm/src/stm32l1xx/stm32l1xx_tim.c diff --git a/example/libstm32l_discovery/src/stm32l1xx_usart.c b/example/libs_stm/src/stm32l1xx/stm32l1xx_usart.c similarity index 100% rename from example/libstm32l_discovery/src/stm32l1xx_usart.c rename to example/libs_stm/src/stm32l1xx/stm32l1xx_usart.c diff --git a/example/libstm32l_discovery/src/stm32l1xx_wwdg.c b/example/libs_stm/src/stm32l1xx/stm32l1xx_wwdg.c similarity index 100% rename from example/libstm32l_discovery/src/stm32l1xx_wwdg.c rename to example/libs_stm/src/stm32l1xx/stm32l1xx_wwdg.c diff --git a/example/libstm32l_discovery/build/Makefile b/example/libstm32l_discovery/build/Makefile deleted file mode 100644 index 09d3b71..0000000 --- a/example/libstm32l_discovery/build/Makefile +++ /dev/null @@ -1,51 +0,0 @@ -LIB = libstm32l_discovery.a - -CC = arm-none-eabi-gcc -AR = arm-none-eabi-ar -RANLIB = arm-none-eabi-ranlib - -CFLAGS = -Wall -O2 -mlittle-endian -mthumb -CFLAGS += -mcpu=cortex-m3 -ffreestanding -nostdlib -nostdinc -CFLAGS += -I../inc -I../inc/device_support -I../inc/core_support -I../inc/base - -SRCS = \ -../src/misc.c \ -../src/stm32l1xx_adc.c \ -../src/stm32l1xx_comp.c \ -../src/stm32l1xx_crc.c \ -../src/stm32l1xx_dac.c \ -../src/stm32l1xx_dbgmcu.c \ -../src/stm32l1xx_dma.c \ -../src/stm32l1xx_exti.c \ -../src/stm32l1xx_flash.c \ -../src/stm32l1xx_flash_ramfunc.c \ -../src/stm32l1xx_gpio.c \ -../src/stm32l1xx_i2c.c \ -../src/stm32l1xx_iwdg.c \ -../src/stm32l1xx_lcd.c \ -../src/stm32l1xx_pwr.c \ -../src/stm32l1xx_rcc.c \ -../src/stm32l1xx_rtc.c \ -../src/stm32l1xx_spi.c \ -../src/stm32l1xx_syscfg.c \ -../src/stm32l1xx_tim.c \ -../src/stm32l1xx_usart.c \ -../src/stm32l1xx_wwdg.c \ -../inc/core_support/core_cm3.c - -OBJS = $(SRCS:.c=.o) - -all: $(LIB) - -$(LIB): $(OBJS) - $(AR) -r $(LIB) $(OBJS) - $(RANLIB) $(LIB) - -%.o : %.c - $(CC) $(CFLAGS) -c -o $@ $^ - -clean: - -rm -f $(OBJS) - -rm -f $(LIB) - -.PHONY: all clean From 3ec53a0d34016839cf6583117dd549da88aa63c7 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Mon, 7 Nov 2011 22:55:20 +0000 Subject: [PATCH 45/63] Rename 32L specific examples --- example/{lcd => 32l_lcd}/Makefile | 16 ++++++---------- example/{lcd => 32l_lcd}/discover_board.h | 0 example/{lcd => 32l_lcd}/linker_stm32l.lds | 0 example/{lcd => 32l_lcd}/main.c | 0 example/{lcd => 32l_lcd}/stm32l_discovery_lcd.c | 0 example/{lcd => 32l_lcd}/stm32l_discovery_lcd.h | 0 6 files changed, 6 insertions(+), 10 deletions(-) rename example/{lcd => 32l_lcd}/Makefile (56%) rename example/{lcd => 32l_lcd}/discover_board.h (100%) rename example/{lcd => 32l_lcd}/linker_stm32l.lds (100%) rename example/{lcd => 32l_lcd}/main.c (100%) rename example/{lcd => 32l_lcd}/stm32l_discovery_lcd.c (100%) rename example/{lcd => 32l_lcd}/stm32l_discovery_lcd.h (100%) diff --git a/example/lcd/Makefile b/example/32l_lcd/Makefile similarity index 56% rename from example/lcd/Makefile rename to example/32l_lcd/Makefile index 8bfdbbb..fce2194 100644 --- a/example/lcd/Makefile +++ b/example/32l_lcd/Makefile @@ -11,20 +11,16 @@ CFLAGS+=-I. PLATFORM=stm32l1xx LIBS_STM_PATH=../libs_stm -INC_CORE_SUPPORT=$(LIBS_STM_PATH)/inc/core_support -SRC_CORE_SUPPORT=$(LIBS_STM_PATH)/inc/core_support -INC_DEVICE_SUPPORT=$(LIBS_STM_PATH)/inc/device_support -INC_PLATFORM=$(LIBS_STM_PATH)/inc/$(PLATFORM) - -CFLAGS+=-I$(INC_CORE_SUPPORT) -CFLAGS+=-I$(INC_DEVICE_SUPPORT) -CFLAGS+=-I$(INC_PLATFORM) CFLAGS+=-I$(LIBS_STM_PATH)/inc/base - +CFLAGS+=-I$(LIBS_STM_PATH)/inc/core_support +CFLAGS+=-I$(LIBS_STM_PATH)/inc/device_support +CFLAGS+=-I$(LIBS_STM_PATH)/inc/$(PLATFORM) # to run from SRAM CFLAGS+=-Wl,-T,linker_stm32l.lds +LDFLAGS+=-L$(LIBS_STM_PATH)/build -lstm32l_discovery + SRCS=\ main.c\ stm32l_discovery_lcd.c @@ -34,7 +30,7 @@ OBJS=$(SRCS:.c=.o) all: $(ELF) $(ELF): $(OBJS) - $(CC) $(CFLAGS) -o $@ $(OBJS) -L$(LIBS_STM_PATH)/build -lstm32l_discovery + $(CC) $(CFLAGS) -o $@ $(OBJS) $(LDFLAGS) %.o: %.c $(CC) $(CFLAGS) -c -o $@ $^ diff --git a/example/lcd/discover_board.h b/example/32l_lcd/discover_board.h similarity index 100% rename from example/lcd/discover_board.h rename to example/32l_lcd/discover_board.h diff --git a/example/lcd/linker_stm32l.lds b/example/32l_lcd/linker_stm32l.lds similarity index 100% rename from example/lcd/linker_stm32l.lds rename to example/32l_lcd/linker_stm32l.lds diff --git a/example/lcd/main.c b/example/32l_lcd/main.c similarity index 100% rename from example/lcd/main.c rename to example/32l_lcd/main.c diff --git a/example/lcd/stm32l_discovery_lcd.c b/example/32l_lcd/stm32l_discovery_lcd.c similarity index 100% rename from example/lcd/stm32l_discovery_lcd.c rename to example/32l_lcd/stm32l_discovery_lcd.c diff --git a/example/lcd/stm32l_discovery_lcd.h b/example/32l_lcd/stm32l_discovery_lcd.h similarity index 100% rename from example/lcd/stm32l_discovery_lcd.h rename to example/32l_lcd/stm32l_discovery_lcd.h From d69cad884996b01fb993b3df16c1050adaca5daa Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Mon, 7 Nov 2011 22:56:15 +0000 Subject: [PATCH 46/63] Rename board specific demos as appropriate --- example/{dac => 32l_dac}/Makefile | 0 example/{dac => 32l_dac}/discover_board.h | 0 example/{dac => 32l_dac}/main.c | 0 example/{dac => 32l_dac}/startup_stm32l1xx_md.s | 0 example/{dac => 32l_dac}/stm32_flash.ld | 0 example/{dac => 32l_dac}/system_stm32l1xx.c | 0 6 files changed, 0 insertions(+), 0 deletions(-) rename example/{dac => 32l_dac}/Makefile (100%) rename example/{dac => 32l_dac}/discover_board.h (100%) rename example/{dac => 32l_dac}/main.c (100%) rename example/{dac => 32l_dac}/startup_stm32l1xx_md.s (100%) rename example/{dac => 32l_dac}/stm32_flash.ld (100%) rename example/{dac => 32l_dac}/system_stm32l1xx.c (100%) diff --git a/example/dac/Makefile b/example/32l_dac/Makefile similarity index 100% rename from example/dac/Makefile rename to example/32l_dac/Makefile diff --git a/example/dac/discover_board.h b/example/32l_dac/discover_board.h similarity index 100% rename from example/dac/discover_board.h rename to example/32l_dac/discover_board.h diff --git a/example/dac/main.c b/example/32l_dac/main.c similarity index 100% rename from example/dac/main.c rename to example/32l_dac/main.c diff --git a/example/dac/startup_stm32l1xx_md.s b/example/32l_dac/startup_stm32l1xx_md.s similarity index 100% rename from example/dac/startup_stm32l1xx_md.s rename to example/32l_dac/startup_stm32l1xx_md.s diff --git a/example/dac/stm32_flash.ld b/example/32l_dac/stm32_flash.ld similarity index 100% rename from example/dac/stm32_flash.ld rename to example/32l_dac/stm32_flash.ld diff --git a/example/dac/system_stm32l1xx.c b/example/32l_dac/system_stm32l1xx.c similarity index 100% rename from example/dac/system_stm32l1xx.c rename to example/32l_dac/system_stm32l1xx.c From 518fe1b0d0b45ab6a9ec217f8b1ce51850077e97 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Mon, 7 Nov 2011 22:56:34 +0000 Subject: [PATCH 47/63] Fix compile error with new libraries --- example/32l_dac/Makefile | 25 +++++++++++-------------- 1 file changed, 11 insertions(+), 14 deletions(-) diff --git a/example/32l_dac/Makefile b/example/32l_dac/Makefile index 84db69e..4bd6eb4 100644 --- a/example/32l_dac/Makefile +++ b/example/32l_dac/Makefile @@ -5,25 +5,22 @@ CC=arm-none-eabi-gcc OBJCOPY=arm-none-eabi-objcopy CFLAGS=-O3 -mlittle-endian -mthumb -ifeq ($(CONFIG_STM32L_DISCOVERY), 1) - CFLAGS+=-mcpu=cortex-m3 -DCONFIG_STM32L_DISCOVERY=1 -else ifeq ($(CONFIG_STM32VL_DISCOVERY), 1) - CFLAGS+=-mcpu=cortex-m3 -DCONFIG_STM32VL_DISCOVERY=1 -else ifeq ($(CONFIG_STM32F4_DISCOVERY), 1) - CFLAGS+=-mcpu=cortex-m4 -DCONFIG_STM32F4_DISCOVERY=1 -else -$(error "must specify CONFIG_ for board!") -endif +CFLAGS+=-mcpu=cortex-m3 -DCONFIG_STM32L_DISCOVERY=1 CFLAGS+=-ffreestanding -nostdlib -nostdinc # to run from FLASH CFLAGS+=-Wl,-T,stm32_flash.ld +PLATFORM=stm32l1xx +LIBS_STM_PATH=../libs_stm + # stm32l_discovery lib -CFLAGS+=-I../libstm32l_discovery/inc -CFLAGS+=-I../libstm32l_discovery/inc/base -CFLAGS+=-I../libstm32l_discovery/inc/core_support -CFLAGS+=-I../libstm32l_discovery/inc/device_support +CFLAGS+=-I$(LIBS_STM_PATH)/inc/base +CFLAGS+=-I$(LIBS_STM_PATH)/inc/core_support +CFLAGS+=-I$(LIBS_STM_PATH)/inc/device_support +CFLAGS+=-I$(LIBS_STM_PATH)/inc/$(PLATFORM) + +LDFLAGS+=-L$(LIBS_STM_PATH)/build -lstm32l_discovery all: $(BIN_IMAGE) @@ -31,7 +28,7 @@ $(BIN_IMAGE): $(EXECUTABLE) $(OBJCOPY) -O binary $^ $@ $(EXECUTABLE): main.c system_stm32l1xx.c startup_stm32l1xx_md.s - $(CC) $(CFLAGS) $^ -o $@ -L../libstm32l_discovery/build -lstm32l_discovery + $(CC) $(CFLAGS) $^ -o $@ $(LDFLAGS) clean: rm -rf $(EXECUTABLE) From fd1e3f5f2eba9e3a0b0d3e665737dd1c232b4a73 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Tue, 8 Nov 2011 00:57:54 +0000 Subject: [PATCH 48/63] Build libraries for stm32l1xx and stm32f10x These libraries IGNORE assert_param. Maybe later. --- example/32l_lcd/Makefile | 2 +- example/libs_stm/README | 9 + example/libs_stm/build/Makefile | 37 +- example/libs_stm/build/Makefile.common | 34 + example/libs_stm/build/Makefile.f10x | 5 + example/libs_stm/build/Makefile.l1xx | 5 + .../libs_stm/inc/device_support/stm32f10x.h | 8227 +++++++++++++++++ .../inc/device_support/system_stm32f10x.h | 97 + example/libs_stm/inc/stm32f10x/misc.h | 219 + .../libs_stm/inc/stm32f10x/stm32f10x_adc.h | 482 + .../libs_stm/inc/stm32f10x/stm32f10x_bkp.h | 194 + .../libs_stm/inc/stm32f10x/stm32f10x_can.h | 535 ++ .../libs_stm/inc/stm32f10x/stm32f10x_cec.h | 209 + .../libs_stm/inc/stm32f10x/stm32f10x_crc.h | 93 + .../libs_stm/inc/stm32f10x/stm32f10x_dac.h | 316 + .../libs_stm/inc/stm32f10x/stm32f10x_dbgmcu.h | 118 + .../libs_stm/inc/stm32f10x/stm32f10x_dma.h | 437 + .../libs_stm/inc/stm32f10x/stm32f10x_exti.h | 183 + .../libs_stm/inc/stm32f10x/stm32f10x_flash.h | 425 + .../libs_stm/inc/stm32f10x/stm32f10x_fsmc.h | 716 ++ .../libs_stm/inc/stm32f10x/stm32f10x_gpio.h | 379 + .../libs_stm/inc/stm32f10x/stm32f10x_i2c.h | 670 ++ .../libs_stm/inc/stm32f10x/stm32f10x_iwdg.h | 139 + .../libs_stm/inc/stm32f10x/stm32f10x_pwr.h | 155 + .../libs_stm/inc/stm32f10x/stm32f10x_rcc.h | 726 ++ .../libs_stm/inc/stm32f10x/stm32f10x_rtc.h | 134 + .../libs_stm/inc/stm32f10x/stm32f10x_sdio.h | 530 ++ .../libs_stm/inc/stm32f10x/stm32f10x_spi.h | 490 + .../libs_stm/inc/stm32f10x/stm32f10x_tim.h | 1133 +++ .../libs_stm/inc/stm32f10x/stm32f10x_usart.h | 411 + .../libs_stm/inc/stm32f10x/stm32f10x_wwdg.h | 114 + ..._Notes_for_STM32F10x_StdPeriph_Driver.html | 203 + example/libs_stm/src/stm32f10x/misc.c | 223 + .../libs_stm/src/stm32f10x/stm32f10x_adc.c | 1306 +++ .../libs_stm/src/stm32f10x/stm32f10x_bkp.c | 311 + .../libs_stm/src/stm32f10x/stm32f10x_can.c | 990 ++ .../libs_stm/src/stm32f10x/stm32f10x_cec.c | 432 + .../libs_stm/src/stm32f10x/stm32f10x_crc.c | 163 + .../libs_stm/src/stm32f10x/stm32f10x_dac.c | 579 ++ .../libs_stm/src/stm32f10x/stm32f10x_dbgmcu.c | 161 + .../libs_stm/src/stm32f10x/stm32f10x_dma.c | 693 ++ .../libs_stm/src/stm32f10x/stm32f10x_exti.c | 268 + .../libs_stm/src/stm32f10x/stm32f10x_flash.c | 1735 ++++ .../libs_stm/src/stm32f10x/stm32f10x_fsmc.c | 858 ++ .../libs_stm/src/stm32f10x/stm32f10x_gpio.c | 642 ++ .../libs_stm/src/stm32f10x/stm32f10x_i2c.c | 1285 +++ .../libs_stm/src/stm32f10x/stm32f10x_iwdg.c | 189 + .../libs_stm/src/stm32f10x/stm32f10x_pwr.c | 316 + .../libs_stm/src/stm32f10x/stm32f10x_rcc.c | 1477 +++ .../libs_stm/src/stm32f10x/stm32f10x_rtc.c | 341 + .../libs_stm/src/stm32f10x/stm32f10x_sdio.c | 798 ++ .../libs_stm/src/stm32f10x/stm32f10x_spi.c | 907 ++ .../libs_stm/src/stm32f10x/stm32f10x_tim.c | 2834 ++++++ .../libs_stm/src/stm32f10x/stm32f10x_usart.c | 1054 +++ .../libs_stm/src/stm32f10x/stm32f10x_wwdg.c | 223 + 55 files changed, 35179 insertions(+), 33 deletions(-) create mode 100644 example/libs_stm/README create mode 100644 example/libs_stm/build/Makefile.common create mode 100644 example/libs_stm/build/Makefile.f10x create mode 100644 example/libs_stm/build/Makefile.l1xx create mode 100644 example/libs_stm/inc/device_support/stm32f10x.h create mode 100644 example/libs_stm/inc/device_support/system_stm32f10x.h create mode 100644 example/libs_stm/inc/stm32f10x/misc.h create mode 100644 example/libs_stm/inc/stm32f10x/stm32f10x_adc.h create mode 100644 example/libs_stm/inc/stm32f10x/stm32f10x_bkp.h create mode 100644 example/libs_stm/inc/stm32f10x/stm32f10x_can.h create mode 100644 example/libs_stm/inc/stm32f10x/stm32f10x_cec.h create mode 100644 example/libs_stm/inc/stm32f10x/stm32f10x_crc.h create mode 100644 example/libs_stm/inc/stm32f10x/stm32f10x_dac.h create mode 100644 example/libs_stm/inc/stm32f10x/stm32f10x_dbgmcu.h create mode 100644 example/libs_stm/inc/stm32f10x/stm32f10x_dma.h create mode 100644 example/libs_stm/inc/stm32f10x/stm32f10x_exti.h create mode 100644 example/libs_stm/inc/stm32f10x/stm32f10x_flash.h create mode 100644 example/libs_stm/inc/stm32f10x/stm32f10x_fsmc.h create mode 100644 example/libs_stm/inc/stm32f10x/stm32f10x_gpio.h create mode 100644 example/libs_stm/inc/stm32f10x/stm32f10x_i2c.h create mode 100644 example/libs_stm/inc/stm32f10x/stm32f10x_iwdg.h create mode 100644 example/libs_stm/inc/stm32f10x/stm32f10x_pwr.h create mode 100644 example/libs_stm/inc/stm32f10x/stm32f10x_rcc.h create mode 100644 example/libs_stm/inc/stm32f10x/stm32f10x_rtc.h create mode 100644 example/libs_stm/inc/stm32f10x/stm32f10x_sdio.h create mode 100644 example/libs_stm/inc/stm32f10x/stm32f10x_spi.h create mode 100644 example/libs_stm/inc/stm32f10x/stm32f10x_tim.h create mode 100644 example/libs_stm/inc/stm32f10x/stm32f10x_usart.h create mode 100644 example/libs_stm/inc/stm32f10x/stm32f10x_wwdg.h create mode 100644 example/libs_stm/src/stm32f10x/Release_Notes_for_STM32F10x_StdPeriph_Driver.html create mode 100644 example/libs_stm/src/stm32f10x/misc.c create mode 100644 example/libs_stm/src/stm32f10x/stm32f10x_adc.c create mode 100644 example/libs_stm/src/stm32f10x/stm32f10x_bkp.c create mode 100644 example/libs_stm/src/stm32f10x/stm32f10x_can.c create mode 100644 example/libs_stm/src/stm32f10x/stm32f10x_cec.c create mode 100644 example/libs_stm/src/stm32f10x/stm32f10x_crc.c create mode 100644 example/libs_stm/src/stm32f10x/stm32f10x_dac.c create mode 100644 example/libs_stm/src/stm32f10x/stm32f10x_dbgmcu.c create mode 100644 example/libs_stm/src/stm32f10x/stm32f10x_dma.c create mode 100644 example/libs_stm/src/stm32f10x/stm32f10x_exti.c create mode 100644 example/libs_stm/src/stm32f10x/stm32f10x_flash.c create mode 100644 example/libs_stm/src/stm32f10x/stm32f10x_fsmc.c create mode 100644 example/libs_stm/src/stm32f10x/stm32f10x_gpio.c create mode 100644 example/libs_stm/src/stm32f10x/stm32f10x_i2c.c create mode 100644 example/libs_stm/src/stm32f10x/stm32f10x_iwdg.c create mode 100644 example/libs_stm/src/stm32f10x/stm32f10x_pwr.c create mode 100644 example/libs_stm/src/stm32f10x/stm32f10x_rcc.c create mode 100644 example/libs_stm/src/stm32f10x/stm32f10x_rtc.c create mode 100644 example/libs_stm/src/stm32f10x/stm32f10x_sdio.c create mode 100644 example/libs_stm/src/stm32f10x/stm32f10x_spi.c create mode 100644 example/libs_stm/src/stm32f10x/stm32f10x_tim.c create mode 100644 example/libs_stm/src/stm32f10x/stm32f10x_usart.c create mode 100644 example/libs_stm/src/stm32f10x/stm32f10x_wwdg.c diff --git a/example/32l_lcd/Makefile b/example/32l_lcd/Makefile index fce2194..fdb79c3 100644 --- a/example/32l_lcd/Makefile +++ b/example/32l_lcd/Makefile @@ -19,7 +19,7 @@ CFLAGS+=-I$(LIBS_STM_PATH)/inc/$(PLATFORM) # to run from SRAM CFLAGS+=-Wl,-T,linker_stm32l.lds -LDFLAGS+=-L$(LIBS_STM_PATH)/build -lstm32l_discovery +LDFLAGS+=-L$(LIBS_STM_PATH)/build -lstm32_stdperiph_l1xx SRCS=\ main.c\ diff --git a/example/libs_stm/README b/example/libs_stm/README new file mode 100644 index 0000000..c3dcc4e --- /dev/null +++ b/example/libs_stm/README @@ -0,0 +1,9 @@ +This directory contains the StdPeriph libraries from ST, and the CMSIS core and device +support, all from ST. + +Issues: +* No tracking of which version of which library (yet) +* Both of these define assert_param() as empty. That may not be what you + want! + + diff --git a/example/libs_stm/build/Makefile b/example/libs_stm/build/Makefile index d96e48c..d35e3d6 100644 --- a/example/libs_stm/build/Makefile +++ b/example/libs_stm/build/Makefile @@ -1,37 +1,10 @@ -LIB = libstm32l_discovery.a -CC = arm-none-eabi-gcc -AR = arm-none-eabi-ar -RANLIB = arm-none-eabi-ranlib - -PLATFORM=stm32l1xx - -INC_CORE_SUPPORT=../inc/core_support -SRC_CORE_SUPPORT=../inc/core_support -INC_DEVICE_SUPPORT=../inc/device_support -INC_PLATFORM=../inc/$(PLATFORM) -SRC_PLATFORM=../src/$(PLATFORM) - -CFLAGS = -Wall -O2 -mlittle-endian -mthumb -CFLAGS += -mcpu=cortex-m3 -ffreestanding -nostdlib -nostdinc -CFLAGS += -I$(INC_PLATFORM) -I$(INC_DEVICE_SUPPORT) -I$(INC_CORE_SUPPORT) -I../inc/base - -SRCS=$(wildcard $(SRC_PLATFORM)/*.c) -SRCS+=$(SRC_CORE_SUPPORT)/core_cm3.c - -OBJS = $(SRCS:.c=.o) - -all: $(LIB) - -$(LIB): $(OBJS) - $(AR) -r $(LIB) $(OBJS) - $(RANLIB) $(LIB) - -%.o : %.c - $(CC) $(CFLAGS) -c -o $@ $^ +all: + make -f Makefile.f10x + make -f Makefile.l1xx clean: - -rm -f $(OBJS) - -rm -f $(LIB) + make -f Makefile.f10x clean + make -f Makefile.l1xx clean .PHONY: all clean diff --git a/example/libs_stm/build/Makefile.common b/example/libs_stm/build/Makefile.common new file mode 100644 index 0000000..954413e --- /dev/null +++ b/example/libs_stm/build/Makefile.common @@ -0,0 +1,34 @@ +CC = arm-none-eabi-gcc +AR = arm-none-eabi-ar +RANLIB = arm-none-eabi-ranlib + + +INC_CORE_SUPPORT=../inc/core_support +SRC_CORE_SUPPORT=../inc/core_support +INC_DEVICE_SUPPORT=../inc/device_support +INC_PLATFORM=../inc/$(PLATFORM) +SRC_PLATFORM=../src/$(PLATFORM) + +CFLAGS += -Wall -O2 -mlittle-endian -mthumb +CFLAGS += -mcpu=cortex-m3 -ffreestanding -nostdlib -nostdinc +CFLAGS += -I$(INC_PLATFORM) -I$(INC_DEVICE_SUPPORT) -I$(INC_CORE_SUPPORT) -I../inc/base + +SRCS=$(wildcard $(SRC_PLATFORM)/*.c) +SRCS+=$(SRC_CORE_SUPPORT)/core_cm3.c + +OBJS = $(SRCS:.c=.o) + +all: $(LIB) + +$(LIB): $(OBJS) + $(AR) -r $(LIB) $(OBJS) + $(RANLIB) $(LIB) + +%.o : %.c + $(CC) $(CFLAGS) -c -o $@ $^ + +clean: + -rm -f $(OBJS) + -rm -f $(LIB) + +.PHONY: all clean diff --git a/example/libs_stm/build/Makefile.f10x b/example/libs_stm/build/Makefile.f10x new file mode 100644 index 0000000..dfe0376 --- /dev/null +++ b/example/libs_stm/build/Makefile.f10x @@ -0,0 +1,5 @@ +LIB = libstm32_stdperiph_f10x.a +PLATFORM=stm32f10x +CFLAGS+= -mcpu=cortex-m3 + +include Makefile.common diff --git a/example/libs_stm/build/Makefile.l1xx b/example/libs_stm/build/Makefile.l1xx new file mode 100644 index 0000000..7469ff5 --- /dev/null +++ b/example/libs_stm/build/Makefile.l1xx @@ -0,0 +1,5 @@ +LIB = libstm32_stdperiph_l1xx.a +PLATFORM=stm32l1xx +CFLAGS+=-mcpu=cortex-m3 + +include Makefile.common diff --git a/example/libs_stm/inc/device_support/stm32f10x.h b/example/libs_stm/inc/device_support/stm32f10x.h new file mode 100644 index 0000000..9d12400 --- /dev/null +++ b/example/libs_stm/inc/device_support/stm32f10x.h @@ -0,0 +1,8227 @@ +/** + ****************************************************************************** + * @file stm32f10x.h + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. + * This file contains all the peripheral register's definitions, bits + * definitions and memory mapping for STM32F10x Connectivity line, High + * density, Medium density, Medium density Value line, Low density + * and Low density Value line and XL-density devices. + ****************************************************************************** + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *