diff --git a/config/chips/F1xx_CL.chip b/config/chips/F1xx_CL.chip
index d774412..45f06d3 100644
--- a/config/chips/F1xx_CL.chip
+++ b/config/chips/F1xx_CL.chip
@@ -1,4 +1,4 @@
-# Chip-ID file for STM32F1xx Connectivity Line device
+# Chip-ID file for STM32F1xx Connectivity Line device (F105 / F107)
 #
 dev_type STM32F1xx_CL
 ref_manual_id 0008
diff --git a/inc/stlink.h b/inc/stlink.h
index e3fd632..7dfd8a7 100644
--- a/inc/stlink.h
+++ b/inc/stlink.h
@@ -1,3 +1,4 @@
+
 /*
  * File: stlink.h
  * This should contain all the common top level stlink interfaces,
diff --git a/src/common.c b/src/common.c
index 97f41a5..c498301 100644
--- a/src/common.c
+++ b/src/common.c
@@ -4,16 +4,21 @@
 #include <sys/types.h>
 #include <unistd.h>
 #include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
 #include <md5.h>
 #include <stlink.h>
 #include <stm32.h>
-#include <string.h>
-#include <stdlib.h>
+
 #include "common_flash.h"
 #include "calculate.h"
 #include "map_file.h"
 #include "common.h"
 
+#ifndef O_BINARY
+#define O_BINARY 0
+#endif
+
 #ifdef _MSC_VER
 #define __attribute__(x)
 #endif
@@ -110,7 +115,7 @@ int stlink_core_id(stlink_t *sl) {
   DLOG("core_id = 0x%08x\n", sl->core_id);
   return (ret);
 }
-
+// 287
 // stlink_chip_id() is called by stlink_load_device_params()
 // do not call this procedure directly.
 int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) {
@@ -120,8 +125,7 @@ int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) {
   // Read the CPU ID to determine where to read the core id
   if (stlink_cpu_id(sl, &cpu_id) ||
       cpu_id.implementer_id != STLINK_REG_CMx_CPUID_IMPL_ARM) {
-    ELOG("Can not connect to target. Please use \'connect under reset\' and "
-         "try again\n");
+    ELOG("Can not connect to target. Please use \'connect under reset\' and try again\n");
     return -1;
   }
 
@@ -174,7 +178,7 @@ int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) {
 
   return (ret);
 }
-
+// 288
 /**
  * Cortex M tech ref manual, CPUID register description
  * @param sl stlink context
@@ -203,102 +207,100 @@ int stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid) {
  * @param sl
  * @return 0 for success, or -1 for unsupported core type.
  */
- int stlink_load_device_params(stlink_t *sl) {
-   // This seems to normally work so is unnecessary info for a normal user.
-   // Demoted to debug. -- REW
-   DLOG("Loading device parameters....\n");
-   const struct stlink_chipid_params *params = NULL;
-   stlink_core_id(sl);
-   uint32_t flash_size;
+int stlink_load_device_params(stlink_t *sl) {
+  // This seems to normally work so is unnecessary info for a normal user.
+  // Demoted to debug. -- REW
+  DLOG("Loading device parameters....\n");
+  const struct stlink_chipid_params *params = NULL;
+  stlink_core_id(sl);
+  uint32_t flash_size;
 
-   if (stlink_chip_id(sl, &sl->chip_id)) {
-     return (-1);
-   }
+  if (stlink_chip_id(sl, &sl->chip_id)) {
+    return (-1);
+  }
 
-   params = stlink_chipid_get_params(sl->chip_id);
+  params = stlink_chipid_get_params(sl->chip_id);
 
-   if (params == NULL) {
-     WLOG("unknown chip id! %#x\n", sl->chip_id);
-     return (-1);
-   }
+  if (params == NULL) {
+    WLOG("unknown chip id! %#x\n", sl->chip_id);
+    return (-1);
+  }
 
-   if (params->flash_type == STM32_FLASH_TYPE_UNKNOWN) {
-     WLOG("Invalid flash type, please check device declaration\n");
-     sl->flash_size = 0;
-     return (0);
-   }
+  if (params->flash_type == STM32_FLASH_TYPE_UNKNOWN) {
+    WLOG("Invalid flash type, please check device declaration\n");
+    sl->flash_size = 0;
+    return (0);
+  }
 
-   // These are fixed...
-   sl->flash_base = STM32_FLASH_BASE;
-   sl->sram_base = STM32_SRAM_BASE;
-   stlink_read_debug32(sl, (params->flash_size_reg) & ~3, &flash_size);
+  // These are fixed...
+  sl->flash_base = STM32_FLASH_BASE;
+  sl->sram_base = STM32_SRAM_BASE;
+  stlink_read_debug32(sl, (params->flash_size_reg) & ~3, &flash_size);
 
-   if (params->flash_size_reg & 2) {
-     flash_size = flash_size >> 16;
-   }
+  if (params->flash_size_reg & 2) {
+    flash_size = flash_size >> 16;
+  }
 
-   flash_size = flash_size & 0xffff;
+  flash_size = flash_size & 0xffff;
 
-   if ((sl->chip_id == STM32_CHIPID_L1_MD ||
+  if ((sl->chip_id == STM32_CHIPID_L1_MD ||
         sl->chip_id == STM32_CHIPID_F1_VL_MD_LD ||
         sl->chip_id == STM32_CHIPID_L1_MD_PLUS) &&
-       (flash_size == 0)) {
-     sl->flash_size = 128 * 1024;
-   } else if (sl->chip_id == STM32_CHIPID_L1_CAT2) {
-     sl->flash_size = (flash_size & 0xff) * 1024;
-   } else if ((sl->chip_id & 0xFFF) == STM32_CHIPID_L1_MD_PLUS_HD) {
-     // 0 is 384k and 1 is 256k
-     if (flash_size == 0) {
-       sl->flash_size = 384 * 1024;
-     } else {
-       sl->flash_size = 256 * 1024;
-     }
-   } else {
-     sl->flash_size = flash_size * 1024;
-   }
+      (flash_size == 0)) {
+    sl->flash_size = 128 * 1024;
+  } else if (sl->chip_id == STM32_CHIPID_L1_CAT2) {
+    sl->flash_size = (flash_size & 0xff) * 1024;
+  } else if ((sl->chip_id & 0xFFF) == STM32_CHIPID_L1_MD_PLUS_HD) {
+    // 0 is 384k and 1 is 256k
+    if (flash_size == 0) {
+      sl->flash_size = 384 * 1024;
+    } else {
+      sl->flash_size = 256 * 1024;
+    }
+  } else {
+    sl->flash_size = flash_size * 1024;
+  }
 
-   sl->flash_type = params->flash_type;
-   sl->flash_pgsz = params->flash_pagesize;
-   sl->sram_size = params->sram_size;
-   sl->sys_base = params->bootrom_base;
-   sl->sys_size = params->bootrom_size;
-   sl->option_base = params->option_base;
-   sl->option_size = params->option_size;
-   sl->chip_flags = params->flags;
+  sl->flash_type = params->flash_type;
+  sl->flash_pgsz = params->flash_pagesize;
+  sl->sram_size = params->sram_size;
+  sl->sys_base = params->bootrom_base;
+  sl->sys_size = params->bootrom_size;
+  sl->option_base = params->option_base;
+  sl->option_size = params->option_size;
+  sl->chip_flags = params->flags;
 
-   // medium and low devices have the same chipid. ram size depends on flash
-   // size. STM32F100xx datasheet Doc ID 16455 Table 2
-   if (sl->chip_id == STM32_CHIPID_F1_VL_MD_LD &&
-       sl->flash_size < 64 * 1024) {
-     sl->sram_size = 0x1000;
-   }
+  // medium and low devices have the same chipid. ram size depends on flash
+  // size. STM32F100xx datasheet Doc ID 16455 Table 2
+  if (sl->chip_id == STM32_CHIPID_F1_VL_MD_LD &&
+      sl->flash_size < 64 * 1024) {
+    sl->sram_size = 0x1000;
+  }
 
-   if (sl->chip_id == STM32_CHIPID_G4_CAT3) {
-     uint32_t flash_optr;
-     stlink_read_debug32(sl, STM32Gx_FLASH_OPTR, &flash_optr);
+  if (sl->chip_id == STM32_CHIPID_G4_CAT3) {
+    uint32_t flash_optr;
+    stlink_read_debug32(sl, STM32Gx_FLASH_OPTR, &flash_optr);
 
-     if (!(flash_optr & (1 << STM32G4_FLASH_OPTR_DBANK))) {
-       sl->flash_pgsz <<= 1;
-     }
-   }
+    if (!(flash_optr & (1 << STM32G4_FLASH_OPTR_DBANK))) {
+      sl->flash_pgsz <<= 1;
+    }
+  }
 
-   // H7 devices with small flash has one bank
-   if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK &&
-       sl->flash_type == STM32_FLASH_TYPE_H7) {
-     if ((sl->flash_size / sl->flash_pgsz) <= 1)
-       sl->chip_flags &= ~CHIP_F_HAS_DUAL_BANK;
-   }
+  // H7 devices with small flash has one bank
+  if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK &&
+      sl->flash_type == STM32_FLASH_TYPE_H7) {
+    if ((sl->flash_size / sl->flash_pgsz) <= 1)
+      sl->chip_flags &= ~CHIP_F_HAS_DUAL_BANK;
+  }
 
-   ILOG("%s: %u KiB SRAM, %u KiB flash in at least %u %s pages.\n",
-        params->dev_type, (unsigned)(sl->sram_size / 1024),
-        (unsigned)(sl->flash_size / 1024),
-        (sl->flash_pgsz < 1024) ? (unsigned)(sl->flash_pgsz)
-                                : (unsigned)(sl->flash_pgsz / 1024),
-        (sl->flash_pgsz < 1024) ? "byte" : "KiB");
-
-   return (0);
- }
+  ILOG("%s: %u KiB SRAM, %u KiB flash in at least %u %s pages.\n",
+      params->dev_type, (unsigned)(sl->sram_size / 1024), (unsigned)(sl->flash_size / 1024),
+      (sl->flash_pgsz < 1024) ? (unsigned)(sl->flash_pgsz) : (unsigned)(sl->flash_pgsz / 1024),
+      (sl->flash_pgsz < 1024) ? "byte" : "KiB");
 
+  return (0);
+}
+// 254
 int stlink_reset(stlink_t *sl, enum reset_type type) {
   uint32_t dhcsr;
   unsigned timeout;
@@ -908,7 +910,7 @@ int stlink_parse_ihex(const char *path, uint8_t erased_pattern, uint8_t **mem,
 
   return (res);
 }
-
+// 280
 uint8_t stlink_get_erased_pattern(stlink_t *sl) {
   if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) {
     return (0x00);
@@ -917,6 +919,7 @@ uint8_t stlink_get_erased_pattern(stlink_t *sl) {
   }
 }
 
+// 322
 int stlink_target_connect(stlink_t *sl, enum connect_type connect) {
   if (connect == CONNECT_UNDER_RESET) {
     stlink_enter_swd_mode(sl);
diff --git a/src/flashloader.c b/src/flashloader.c
index ce230d7..e4c7d72 100644
--- a/src/flashloader.c
+++ b/src/flashloader.c
@@ -1,6 +1,6 @@
 #include <stdio.h>
-#include <stlink.h>
 #include <string.h>
+#include <stlink.h>
 #include "common_flash.h"
 
 #define L1_WRITE_BLOCK_SIZE 0x80
diff --git a/src/map_file.c b/src/map_file.c
index 17697c1..3bb7555 100644
--- a/src/map_file.c
+++ b/src/map_file.c
@@ -1,19 +1,20 @@
 #include <fcntl.h>
 #include <sys/stat.h>
 #include <md5.h>
-#include <stlink.h>
 #include <unistd.h>
+#include <stlink.h>
+#include <logging.h>
 
 #include "map_file.h"
 
-#ifndef MAX_FILE_SIZE
-#define MAX_FILE_SIZE (1<<20) // 1 GB max file size
-#endif
-
 #ifndef O_BINARY
 #define O_BINARY 0
 #endif
 
+#ifndef MAX_FILE_SIZE
+#define MAX_FILE_SIZE (1<<20) // 1 GB max file size
+#endif
+
 int map_file(mapped_file_t *mf, const char *path) {
   int error = -1;
   struct stat st;
diff --git a/src/option_bytes.c b/src/option_bytes.c
index bd792b4..f5d8c00 100644
--- a/src/option_bytes.c
+++ b/src/option_bytes.c
@@ -1,6 +1,6 @@
 #include <stdio.h>
-#include <stlink.h>
 #include <string.h>
+#include <stlink.h>
 #include "common_flash.h"
 #include "map_file.h"
 #include "common.h"
diff --git a/src/read_write.c b/src/read_write.c
index f20d76a..efaa5a2 100644
--- a/src/read_write.c
+++ b/src/read_write.c
@@ -1,6 +1,6 @@
 #include <stdio.h>
-#include <stlink.h>
 #include <string.h>
+#include <stlink.h>
 
 // Endianness
 // https://commandcenter.blogspot.com/2012/04/byte-order-fallacy.html