kopia lustrzana https://github.com/stlink-org/stlink
Add F3 small devices (F301, F302) with ID 0x439
- Add F3 small devices (F301, F302) with MCU device ID code 0x439 - Sort supported devices by MCU device ID codepull/246/head
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@ -98,33 +98,46 @@ extern "C" {
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* DBGMCU_IDCODE register (0xE0042000)
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* DBGMCU_IDCODE register (0xE0042000)
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*/
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*/
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// stm32 chipids, only lower 12 bits..
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// stm32 chipids, only lower 12 bits..
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#define STM32_CHIPID_F1_MEDIUM 0x410
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#define STM32_CHIPID_F1_MEDIUM 0x410
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#define STM32_CHIPID_F2 0x411
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#define STM32_CHIPID_F2 0x411
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#define STM32_CHIPID_F1_LOW 0x412
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#define STM32_CHIPID_F1_LOW 0x412
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#define STM32_CHIPID_F3 0x422
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#define STM32_CHIPID_F4 0x413
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#define STM32_CHIPID_F37x 0x432
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#define STM32_CHIPID_F1_HIGH 0x414
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#define STM32_CHIPID_F4 0x413
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#define STM32_CHIPID_F4_HD 0x419
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#define STM32_CHIPID_L1_MEDIUM 0x416
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#define STM32_CHIPID_F4_LP 0x423
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#define STM32_CHIPID_F4_DE 0x433
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#define STM32_CHIPID_F1_CONN 0x418
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#define STM32_CHIPID_F1_HIGH 0x414
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#define STM32_CHIPID_F4_HD 0x419
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#define STM32_CHIPID_L1_MEDIUM 0x416
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#define STM32_CHIPID_F1_VL_MEDIUM 0x420
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#define STM32_CHIPID_F3 0x422
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#define STM32_CHIPID_F4_LP 0x423
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#define STM32_CHIPID_L1_MEDIUM_PLUS 0x427
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#define STM32_CHIPID_L1_MEDIUM_PLUS 0x427
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#define STM32_CHIPID_F1_VL_HIGH 0x428
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#define STM32_CHIPID_F1_XL 0x430
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#define STM32_CHIPID_F37x 0x432
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#define STM32_CHIPID_F4_DE 0x433
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#define STM32_CHIPID_L1_HIGH 0x436
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#define STM32_CHIPID_L152_RE 0x437
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#define STM32_CHIPID_F3_SMALL 0x439
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#define STM32_CHIPID_F0 0x440
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#define STM32_CHIPID_F0_SMALL 0x444
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#define STM32_CHIPID_F0_CAN 0x448
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/*
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/*
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* 0x436 is actually assigned to some L1 chips that are called "Medium-Plus"
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* 0x436 is actually assigned to some L1 chips that are called "Medium-Plus"
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* and some that are called "High". 0x427 is assigned to the other "Medium-
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* and some that are called "High". 0x427 is assigned to the other "Medium-
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* plus" chips. To make it a bit simpler we just call 427 MEDIUM_PLUS and
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* plus" chips. To make it a bit simpler we just call 427 MEDIUM_PLUS and
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* 0x436 HIGH.
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* 0x436 HIGH.
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*/
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*/
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#define STM32_CHIPID_L1_HIGH 0x436
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#define STM32_CHIPID_L152_RE 0x437
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#define STM32_CHIPID_F1_CONN 0x418
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#define STM32_CHIPID_F1_VL_MEDIUM 0x420
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#define STM32_CHIPID_F1_VL_HIGH 0x428
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#define STM32_CHIPID_F1_XL 0x430
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#define STM32_CHIPID_F0 0x440
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#define STM32_CHIPID_F0_SMALL 0x444
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#define STM32_CHIPID_F0_CAN 0x448
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// Constant STM32 memory map figures
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// Constant STM32 memory map figures
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#define STM32_FLASH_BASE 0x08000000
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#define STM32_FLASH_BASE 0x08000000
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@ -354,6 +367,16 @@ static const chip_params_t devices[] = {
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.bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2
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.bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2
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.bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2
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.bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2
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},
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},
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{
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// STM32F30x
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.chip_id = STM32_CHIPID_F3_SMALL,
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.description = "F3 small device",
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.flash_size_reg = 0x1ffff7cc,
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.flash_pagesize = 0x800,
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.sram_size = 0xa000,
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.bootrom_base = 0x1fffd800,
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.bootrom_size = 0x2000
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},
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};
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};
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