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Kod Zgłoszenia Packages Projekty Wydania Wiki Aktywność

Updated device parametres 

- Human-readable  FLASH_TYPE in .chip files
- Added enum for STM32_CORE_IDs
pull/1216/head
nightwalker-87 2022-01-20 23:19:10 +01:00
rodzic 80b05c547e
commit 8d96e769f3
64 zmienionych plików z 123 dodań i 113 usunięć
Pokaż statystyki Ściągnij plik aktualizacji Ściągnij plik porównania Expand all files Collapse all files

2
config/chips/F03x.chip
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@ -3,7 +3,7 @@
dev_type STM32F03x
ref_manual_id 0091
chip_id 0x444 // STM32_CHIPID_F0xx_SMALL
flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3
flash_type F0_F1_F3
flash_size_reg 0x1ffff7cc
flash_pagesize 0x400 // 1 KB
sram_size 0x1000 // 4 KB

2
config/chips/F04x.chip
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@ -3,7 +3,7 @@
dev_type STM32F04x
ref_manual_id 0091
chip_id 0x445 // STM32_CHIPID_F04
flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3
flash_type F0_F1_F3
flash_size_reg 0x1ffff7cc
flash_pagesize 0x400 // 1 KB
sram_size 0x1800 // 6 KB

2
config/chips/F05x.chip
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@ -3,7 +3,7 @@
dev_type STM32F05x
ref_manual_id 0091
chip_id 0x440 // STM32_CHIPID_F0
flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3
flash_type F0_F1_F3
flash_size_reg 0x1ffff7cc
flash_pagesize 0x400 // 1 KB
sram_size 0x2000 // 8 KB

2
config/chips/F07x.chip
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@ -3,7 +3,7 @@
dev_type STM32F07x
ref_manual_id 0091
chip_id 0x448 // STM32_CHIPID_F0_CAN
flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3
flash_type F0_F1_F3
flash_size_reg 0x1ffff7cc
flash_pagesize 0x800 // 2 KB
sram_size 0x4000 // 16 KB

2
config/chips/F09x.chip
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@ -3,7 +3,7 @@
dev_type STM32F09x
ref_manual_id 0091
chip_id 0x442 // STM32_CHIPID_F09x
flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3
flash_type F0_F1_F3
flash_size_reg 0x1ffff7cc
flash_pagesize 0x800 // 2 KB
sram_size 0x8000 // 32 KB

2
config/chips/F1xx_CL.chip
Wyświetl plik

@ -3,7 +3,7 @@
dev_type STM32F1xx_CL
ref_manual_id 0008
chip_id 0x418 // STM32_CHIPID_F1_CONN
flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3
flash_type F0_F1_F3
flash_size_reg 0x1ffff7e0
flash_pagesize 0x800 // 2 KB
sram_size 0x10000 // 64 KB

2
config/chips/F1xx_HD.chip
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@ -3,7 +3,7 @@
dev_type F1xx_HD
ref_manual_id 0008
chip_id 0x414 // STM32_CHIPID_F1_HD
flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3
flash_type F0_F1_F3
flash_size_reg 0x1ffff7e0
flash_pagesize 0x800 // 2 KB
sram_size 0x10000 // 64 KB

2
config/chips/F1xx_LD.chip
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@ -3,7 +3,7 @@
dev_type STM32F1xx_LD
ref_manual_id 0008
chip_id 0x412 // STM32_CHIPID_F1_LD
flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3
flash_type F0_F1_F3
flash_size_reg 0x1ffff7e0
flash_pagesize 0x400 // 1 KB
sram_size 0x2800 // 10 KB

2
config/chips/F1xx_MD.chip
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@ -3,7 +3,7 @@
dev_type STM32F1xx_MD
ref_manual_id 0008
chip_id 0x410 // STM32_CHIPID_F1_MD
flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3
flash_type F0_F1_F3
flash_size_reg 0x1ffff7e0
flash_pagesize 0x400 // 1 KB
sram_size 0x5000 // 20 KB

2
config/chips/F1xx_VL_HD.chip
Wyświetl plik

@ -3,7 +3,7 @@
dev_type STM32F1xx_VL_HD
ref_manual_id 0041
chip_id 0x428 // STM32_CHIPID_F1_VL_HD
flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3
flash_type F0_F1_F3
flash_size_reg 0x1ffff7e0
flash_pagesize 0x800 // 2 KB
sram_size 0x8000 // 32 KB

2
config/chips/F1xx_VL_MD_LD.chip
Wyświetl plik

@ -3,7 +3,7 @@
dev_type STM32F1xx_VL_MD_LD
ref_manual_id 0041
chip_id 0x420 // STM32_CHIPID_F1_VL_MD_LD
flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3
flash_type F0_F1_F3
flash_size_reg 0x1ffff7e0
flash_pagesize 0x400 // 1 KB
sram_size 0x2000 // 8 KB /* 0x1000 for low density devices */

2
config/chips/F1xx_XLD.chip
Wyświetl plik

@ -3,7 +3,7 @@
dev_type STM32F1xx_XLD
ref_manual_id 0008
chip_id 0x430 // STM32_CHIPID_F1_XLD
flash_type 2 // STM32_FLASH_TYPE_F1_XL
flash_type F1_XL
flash_size_reg 0x1ffff7e0
flash_pagesize 0x800 // 2 KB
sram_size 0x18000 // 96 KB

2
config/chips/F2xx.chip
Wyświetl plik

@ -3,7 +3,7 @@
dev_type STM32F2xx
ref_manual_id 0033
chip_id 0x411 // STM32_CHIPID_F2
flash_type 3 // STM32_FLASH_TYPE_F2_F4
flash_type F2_F4
flash_size_reg 0x1fff7a22
flash_pagesize 0x20000 // 128 KB
sram_size 0x20000 // 128 KB

2
config/chips/F301_F302_F318.chip
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@ -3,7 +3,7 @@
dev_type STM32F301_F302_F318
ref_manual_id 0365 // also RM0366
chip_id 0x439 // STM32_CHIPID_F3xx_SMALL
flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3
flash_type F0_F1_F3
flash_size_reg 0x1ffff7cc
flash_pagesize 0x800 // 2 KB
sram_size 0xa000 // 40 KB

2
config/chips/F302_F303_F358.chip
Wyświetl plik

@ -3,7 +3,7 @@
dev_type STM32F302_F303_358
ref_manual_id 0365 // also RM0316
chip_id 0x422 // STM32_CHIPID_F3
flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3
flash_type F0_F1_F3
flash_size_reg 0x1ffff7cc
flash_pagesize 0x800 // 2 KB
sram_size 0xa000 // 40 KB

2
config/chips/F302_F303_F398_HD.chip
Wyświetl plik

@ -3,7 +3,7 @@
dev_type STM32F302_F303_F398_HD
ref_manual_id 0365 // also RM0316 (Rev 5)
chip_id 0x446 // STM32_CHIPID_F303_HD
flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3
flash_type F0_F1_F3
flash_size_reg 0x1ffff7cc
flash_pagesize 0x800 // 2 KB
sram_size 0x10000 // 64 KB

2
config/chips/F303_F328_F334.chip
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@ -3,7 +3,7 @@
dev_type STM32F303_F328_F334
ref_manual_id 0364 // also RM0316
chip_id 0x438 // STM32_CHIPID_F334
flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3
flash_type F0_F1_F3
flash_size_reg 0x1ffff7cc
flash_pagesize 0x800 // 2 KB
sram_size 0x3000 // 12 KB

2
config/chips/F37x.chip
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@ -3,7 +3,7 @@
dev_type STM32F37x
ref_manual_id 0313
chip_id 0x432 // STM32_CHIPID_F37x
flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3
flash_type F0_F1_F3
flash_size_reg 0x1ffff7cc
flash_pagesize 0x800 // 2 KB
sram_size 0xa000 // 40 KB

2
config/chips/F401xB_xC.chip
Wyświetl plik

@ -3,7 +3,7 @@
dev_type STM32F401xB_xC
ref_manual_id 0368
chip_id 0x423 // STM32_CHIPID_F4_LP
flash_type 3 // STM32_FLASH_TYPE_F2_F4
flash_type F2_F4
flash_size_reg 0x1fff7a22
flash_pagesize 0x4000 // 16 KB
sram_size 0x10000 // 64 KB

2
config/chips/F401xD_xE.chip
Wyświetl plik

@ -3,7 +3,7 @@
dev_type STM32F401xD_xE
ref_manual_id 0368
chip_id 0x433 // STM32_CHIPID_F4_DE
flash_type 3 // STM32_FLASH_TYPE_F2_F4
flash_type F2_F4
flash_size_reg 0x1fff7a22
flash_pagesize 0x4000 // 16 KB
sram_size 0x18000 // 96 KB

2
config/chips/F410.chip
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@ -3,7 +3,7 @@
dev_type STM32F410
ref_manual_id 0401
chip_id 0x458 // STM32_CHIPID_F410
flash_type 3 // STM32_FLASH_TYPE_F2_F4
flash_type F2_F4
flash_size_reg 0x1fff7a22
flash_pagesize 0x4000 // 16 KB
sram_size 0x8000 // 32 KB

2
config/chips/F411xC_xE.chip
Wyświetl plik

@ -3,7 +3,7 @@
dev_type STM32F411xC_xE
ref_manual_id 0383
chip_id 0x431 // STM32_CHIPID_F411xx
flash_type 3 // STM32_FLASH_TYPE_F2_F4
flash_type F2_F4
flash_size_reg 0x1fff7a22
flash_pagesize 0x4000 // 16 KB
sram_size 0x20000 // 128 KB

2
config/chips/F412.chip
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@ -3,7 +3,7 @@
dev_type STM32F412
ref_manual_id 0402
chip_id 0x441 // STM32_CHIPID_F412
flash_type 3 // STM32_FLASH_TYPE_F2_F4
flash_type F2_F4
flash_size_reg 0x1fff7a22
flash_pagesize 0x4000 // 16 KB
sram_size 0x40000 // 256 KB

2
config/chips/F413_F423.chip
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@ -3,7 +3,7 @@
dev_type STM32F413_F423
ref_manual_id 0430 // RM0430 (Rev 2)
chip_id 0x463 // STM32_CHIPID_F413
flash_type 3 // STM32_FLASH_TYPE_F2_F4
flash_type F2_F4
flash_size_reg 0x1fff7a22
flash_pagesize 0x4000 // 16 KB
sram_size 0x50000 // 320 KB

2
config/chips/F42x_F43x.chip
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@ -3,7 +3,7 @@
dev_type STM32F42x_F43x
ref_manual_id 0090 // RM0090 (Rev. 2)
chip_id 0x463 // STM32_CHIPID_F4_HD
flash_type 3 // STM32_FLASH_TYPE_F2_F4
flash_type F2_F4
flash_size_reg 0x1fff7a22
flash_pagesize 0x4000 // 16 KB
sram_size 0x40000 // 256 KB

2
config/chips/F446.chip
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@ -3,7 +3,7 @@
dev_type STM32F446
ref_manual_id 0390
chip_id 0x421 // STM32_CHIPID_F446
flash_type 3 // STM32_FLASH_TYPE_F2_F4
flash_type F2_F4
flash_size_reg 0x1fff7a22
flash_pagesize 0x20000 // 128 KB
sram_size 0x20000 // 128 KB

2
config/chips/F46x_F47x.chip
Wyświetl plik

@ -3,7 +3,7 @@
dev_type STM32F46x_F47x
ref_manual_id 0090 // RM0090 (Rev. 2)
chip_id 0x434 // STM32_CHIPID_F4_DSI
flash_type 3 // STM32_FLASH_TYPE_F2_F4
flash_type F2_F4
flash_size_reg 0x1fff7a22
flash_pagesize 0x4000 // 16 KB
sram_size 0x40000 // 256 KB

2
config/chips/F4x5_F4x7.chip
Wyświetl plik

@ -3,7 +3,7 @@
dev_type STM32F4x5_F4x7
ref_manual_id 0090 // RM0090 (Rev. 2)
chip_id 0x413 // STM32_CHIPID_F4
flash_type 3 // STM32_FLASH_TYPE_F2_F4
flash_type F2_F4
flash_size_reg 0x1fff7a22
flash_pagesize 0x4000 // 16 KB
sram_size 0x30000 // 192 KB

2
config/chips/F72x_F73x.chip
Wyświetl plik

@ -3,7 +3,7 @@
dev_type STM32F72x_F73x
ref_manual_id 0431
chip_id 0x452 // STM32_CHIPID_F72xxx
flash_type 4 // STM32_FLASH_TYPE_F7
flash_type F7
flash_size_reg 0x1ff07a22
flash_pagesize 0x800 // 2 KB
sram_size 0x40000 // 256 KB

2
config/chips/F74x_F75x.chip
Wyświetl plik

@ -3,7 +3,7 @@
dev_type STM32F74x_F75x
ref_manual_id 0385
chip_id 0x449 // STM32_CHIPID_F7
flash_type 4 // STM32_FLASH_TYPE_F7
flash_type F7
flash_size_reg 0x1ff0f442
flash_pagesize 0x800 // 2 KB
sram_size 0x50000 // 320 KB

2
config/chips/F76x_F77x.chip
Wyświetl plik

@ -3,7 +3,7 @@
dev_type STM32F76x_F77x
ref_manual_id 0410
chip_id 0x451 // STM32_CHIPID_F76xxx
flash_type 4 // STM32_FLASH_TYPE_F7
flash_type F7
flash_size_reg 0x1ff0f442
flash_pagesize 0x800 // 2 KB
sram_size 0x80000 // 512 KB

2
config/chips/G03x_G04x.chip
Wyświetl plik

@ -3,7 +3,7 @@
dev_type STM32G03x_G04x
ref_manual_id 0444 // also RM454
chip_id 0x466 // STM32_CHIPID_G0_CAT1
flash_type 5 // STM32_FLASH_TYPE_G0
flash_type G0
flash_size_reg 0x1fff75e0
flash_pagesize 0x800 // 2 KB
sram_size 0x2000 // 8 KB

2
config/chips/G05x_G06x.chip
Wyświetl plik

@ -3,7 +3,7 @@
dev_type STM32G05x_G06x
ref_manual_id 0444
chip_id 0x456 // STM32_CHIPID_G0_CAT4
flash_type 5 // STM32_FLASH_TYPE_G0
flash_type G0
flash_size_reg 0x1fff75e0
flash_pagesize 0x800 // 2 KB
sram_size 0x9000 // 36 KB

2
config/chips/G07x_G08x.chip
Wyświetl plik

@ -3,7 +3,7 @@
dev_type STM32G07x_G08x
ref_manual_id 0444
chip_id 0x460 // STM32_CHIPID_G0_CAT2
flash_type 5 // STM32_FLASH_TYPE_G0
flash_type G0
flash_size_reg 0x1fff75e0
flash_pagesize 0x800 // 2 KB
sram_size 0x9000 // 36 KB

2
config/chips/G0Bx_G0Cx.chip
Wyświetl plik

@ -3,7 +3,7 @@
dev_type STM32G0Bx_G0Cx
ref_manual_id 0444
chip_id 0x467 // STM32_CHIPID_G0_CAT3
flash_type 5 // STM32_FLASH_TYPE_G0
flash_type G0
flash_size_reg 0x1fff75e0
flash_pagesize 0x800 // 2 KB
sram_size 0x9000 // 36 KB

2
config/chips/G43x_G44x.chip
Wyświetl plik

@ -3,7 +3,7 @@
dev_type STM32G43x_G44x
ref_manual_id 0440
chip_id 0x468 // STM32_CHIPID_G4_CAT2
flash_type 6 // STM32_FLASH_TYPE_G4
flash_type G4
flash_size_reg 0x1fff75e0
flash_pagesize 0x800 // 2 KB
sram_size 0x8000 // 32 KB

2
config/chips/G47x_G48x.chip
Wyświetl plik

@ -3,7 +3,7 @@
dev_type STM32G47x_G48x
ref_manual_id 0440
chip_id 0x469 // STM32_CHIPID_G4_CAT3
flash_type 6 // STM32_FLASH_TYPE_G4
flash_type G4
flash_size_reg 0x1fff75e0
flash_pagesize 0x800 // 2 KB
sram_size 0x20000 // 128 KB

2
config/chips/G49x_G4Ax.chip
Wyświetl plik

@ -3,7 +3,7 @@
dev_type STM32G49x_G4Ax
ref_manual_id 0440
chip_id 0x479 // STM32_CHIPID_G4_CAT4
flash_type 6 // STM32_FLASH_TYPE_G4
flash_type G4
flash_size_reg 0x1fff75e0
flash_pagesize 0x800 // 2 KB
sram_size 0x1c000 // 112 KB

2
config/chips/H72x_H73x.chip
Wyświetl plik

@ -3,7 +3,7 @@
dev_type STM32H72x_H73x
ref_manual_id 0468
chip_id 0x483 // STM32_CHIPID_H72x
flash_type 7 // STM32_FLASH_TYPE_H7
flash_type H7
flash_size_reg 0x1ff1e880
flash_pagesize 0x20000 // 128 KB
sram_size 0x20000 // 128 KB "DTCM"

2
config/chips/H74x_H75x.chip
Wyświetl plik

@ -3,7 +3,7 @@
dev_type STM32H74x_H75x
ref_manual_id 0433
chip_id 0x450 // STM32_CHIPID_H74xxx
flash_type 7 // STM32_FLASH_TYPE_H7
flash_type H7
flash_size_reg 0x1ff1e880
flash_pagesize 0x20000 // 128 KB
sram_size 0x20000 // 128 KB "DTCM"

2
config/chips/H7Ax_H7Bx.chip
Wyświetl plik

@ -3,7 +3,7 @@
dev_type STM32H7Ax_H7Bx
ref_manual_id 0455
chip_id 0x480 // STM32_CHIPID_H7Ax
flash_type 7 // STM32_FLASH_TYPE_H7
flash_type H7
flash_size_reg 0x08fff80c
flash_pagesize 0x2000 // 8 KB
sram_size 0x20000 // 128 KB "DTCM"

2
config/chips/L0xxx_Cat_1.chip
Wyświetl plik

@ -3,7 +3,7 @@
dev_type STM32L0xxx_Cat_1
ref_manual_id 0451 // also RM0377
chip_id 0x457 // STM32_CHIPID_L011
flash_type 8 // STM32_FLASH_TYPE_L0_L1
flash_type L0_L1
flash_size_reg 0x1ff8007c
flash_pagesize 0x80 // 128 B
sram_size 0x2000 // 8 KB

2
config/chips/L0xxx_Cat_2.chip
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@ -3,7 +3,7 @@
dev_type STM32L0xxx_Cat_2
ref_manual_id 0451 // also RM0377
chip_id 0x425 // STM32_CHIPID_L0_CAT2
flash_type 8 // STM32_FLASH_TYPE_L0_L1
flash_type L0_L1
flash_size_reg 0x1ff8007c
flash_pagesize 0x80 // 128 B
sram_size 0x2000 // 8 KB

2
config/chips/L0xxx_Cat_3.chip
Wyświetl plik

@ -3,7 +3,7 @@
dev_type STM32L0xxx_Cat_3
ref_manual_id 0451 // also RM0367 & RM0377
chip_id 0x417 // STM32_CHIPID_L0
flash_type 8 // STM32_FLASH_TYPE_L0_L1
flash_type L0_L1
flash_size_reg 0x1ff8007c
flash_pagesize 0x80 // 128 B
sram_size 0x2000 // 8 KB

2
config/chips/L0xxx_Cat_5.chip
Wyświetl plik

@ -3,7 +3,7 @@
dev_type STM32L0xxx_Cat_5
ref_manual_id 0451 // also RM0367 & RM0377
chip_id 0x447 // STM32_CHIPID_L0_CAT5
flash_type 8 // STM32_FLASH_TYPE_L0_L1
flash_type L0_L1
flash_size_reg 0x1ff8007c
flash_pagesize 0x80 // 128 B
sram_size 0x5000 // 20 KB

2
config/chips/L1xx_Cat_1.chip
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@ -3,7 +3,7 @@
dev_type STM32L1xx_Cat_1
ref_manual_id 0038
chip_id 0x416 // STM32_CHIPID_L1_MD
flash_type 8 // STM32_FLASH_TYPE_L0_L1
flash_type L0_L1
flash_size_reg 0x1ff8004c
flash_pagesize 0x100 // 128 B
sram_size 0x4000 // 16 KB

2
config/chips/L1xx_Cat_2.chip
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@ -3,7 +3,7 @@
dev_type STM32L1xx_Cat_2
ref_manual_id 0038
chip_id 0x429 // STM32_CHIPID_L1_CAT2
flash_type 8 // STM32_FLASH_TYPE_L0_L1
flash_type L0_L1
flash_size_reg 0x1ff8004c
flash_pagesize 0x100 // 128 B
sram_size 0x8000 // 32 KB

2
config/chips/L1xx_Cat_3.chip
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@ -3,7 +3,7 @@
dev_type STM32L1xx_Cat_3
ref_manual_id 0038
chip_id 0x427 // STM32_CHIPID_L1_MD_PLUS
flash_type 8 // STM32_FLASH_TYPE_L0_L1
flash_type L0_L1
flash_size_reg 0x1ff800cc
flash_pagesize 0x100 // 128 B
sram_size 0x8000 // 32 KB

2
config/chips/L1xx_Cat_4.chip
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@ -3,7 +3,7 @@
dev_type STM32L1xx_Cat_4
ref_manual_id 0038
chip_id 0x436 // STM32_CHIPID_L1_MD_PLUS_HD
flash_type 8 // STM32_FLASH_TYPE_L0_L1
flash_type L0_L1
flash_size_reg 0x1ff800cc
flash_pagesize 0x100 // 128 B
sram_size 0xc000 // 48 KB

2
config/chips/L1xx_Cat_5.chip
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@ -3,7 +3,7 @@
dev_type STM32L1xx_Cat_5
ref_manual_id 0038
chip_id 0x437 // STM32_CHIPID_L152_RE
flash_type 8 // STM32_FLASH_TYPE_L0_L1
flash_type L0_L1
flash_size_reg 0x1ff800cc
flash_pagesize 0x100 // 128 B
sram_size 0x14000 // 80 KB

2
config/chips/L41x_L42x.chip
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@ -3,7 +3,7 @@
dev_type STM32L41x_L42x
ref_manual_id 0394
chip_id 0x464 // STM32_CHIPID_L41x_L42x
flash_type 9 // STM32_FLASH_TYPE_L4_L4P
flash_type L4_L4P
flash_size_reg 0x1fff75e0
flash_pagesize 0x800 // 2 KB
sram_size 0xa000 // 40 KB

2
config/chips/L43x_L44x.chip
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@ -3,7 +3,7 @@
dev_type STM32L41x_L42x
ref_manual_id 0392
chip_id 0x435 // STM32_CHIPID_L43x_L44x
flash_type 9 // STM32_FLASH_TYPE_L4_L4P
flash_type L4_L4P
flash_size_reg 0x1fff75e0
flash_pagesize 0x800 // 2 KB
sram_size 0xc000 // 48 KB

2
config/chips/L45x_L46x.chip
Wyświetl plik

@ -3,7 +3,7 @@
dev_type STM32L45x_L46x
ref_manual_id 0394
chip_id 0x462 // STM32_CHIPID_L45x_L46x
flash_type 9 // STM32_FLASH_TYPE_L4_L4P
flash_type L4_L4P
flash_size_reg 0x1fff75e0
flash_pagesize 0x800 // 2 KB
sram_size 0x20000 // 128 KB

2
config/chips/L47x_L48x.chip
Wyświetl plik

@ -3,7 +3,7 @@
dev_type STM32L47x_L48x
ref_manual_id 0351
chip_id 0x415 // STM32_CHIPID_L4
flash_type 9 // STM32_FLASH_TYPE_L4_L4P
flash_type L4_L4P
flash_size_reg 0x1fff75e0
flash_pagesize 0x800 // 2 KB
sram_size 0x18000 // 96 KB

2
config/chips/L496x_L4A6x.chip
Wyświetl plik

@ -3,7 +3,7 @@
dev_type STM32L496x_L4A6x
ref_manual_id 0351
chip_id 0x461 // STM32_CHIPID_L496x_L4A6x
flash_type 9 // STM32_FLASH_TYPE_L4_L4P
flash_type L4_L4P
flash_size_reg 0x1fff75e0
flash_pagesize 0x800 // 2 KB
sram_size 0x40000 // 256 KB

2
config/chips/L4Px.chip
Wyświetl plik

@ -3,7 +3,7 @@
dev_type STM32L4Px
ref_manual_id 0432
chip_id 0x471 // STM32_CHIPID_L4PX
flash_type 9 // STM32_FLASH_TYPE_L4_L4P
flash_type L4_L4P
flash_size_reg 0x1fff75e0
flash_pagesize 0x1000 // 4 KB
sram_size 0xa0000 // 640 KB

2
config/chips/L4Rx.chip
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@ -3,7 +3,7 @@
dev_type STM32L4Rx
ref_manual_id 0432
chip_id 0x470 // STM32_CHIPID_L4RX
flash_type 9 // STM32_FLASH_TYPE_L4_L4P
flash_type L4_L4P
flash_size_reg 0x1fff75e0
flash_pagesize 0x1000 // 4 KB
sram_size 0xa0000 // 640 KB

2
config/chips/L5x5.chip → config/chips/L5x5.chip.txt
Wyświetl plik

@ -3,7 +3,7 @@
dev_type STM32L5x2
ref_manual_id 0438
chip_id 0x0 // (temporary setting only!)
flash_type 10 // (temporary setting only!)
flash_type 0 // (temporary setting only!)
flash_size_reg 0x0bfa07a0
flash_pagesize 0x2000 // 8 KB
sram_size 0x40000 // 256 KB

2
config/chips/U5x5.chip → config/chips/U5x5.chip.txt
Wyświetl plik

@ -3,7 +3,7 @@
dev_type STM32U5x5
ref_manual_id 0456
chip_id 0x0 // (temporary setting only!)
flash_type 10 // (temporary setting only!)
flash_type 0 // (temporary setting only!)
flash_size_reg 0x0bfa07a0
flash_pagesize 0x2000 // 8 KB
sram_size 0xc4800 // 786 KB

2
config/chips/WBx0_WBx5.chip
Wyświetl plik

@ -3,7 +3,7 @@
dev_type STM32WBx0_WBx5
ref_manual_id 0434 // also RM0471
chip_id 0x495 // STM32_CHIPID_WB55
flash_type 11 // STM32_FLASH_TYPE_WB_WL
flash_type WB_WL
flash_size_reg 0x1fff75e0
flash_pagesize 0x1000 // 4 KB
sram_size 0x40000 // 256 KB

2
config/chips/WLx5.chip
Wyświetl plik

@ -3,7 +3,7 @@
dev_type STM32WLEx
ref_manual_id 0033
chip_id 0x497 // STM32_CHIPID_WLE
flash_type 11 // STM32_FLASH_TYPE_WB_WL
flash_type WB_WL
flash_size_reg 0x1fff75e0
flash_pagesize 0x800 // 2 KB
sram_size 0x10000 // 64 KB

2
config/chips/unknown_device.chip
Wyświetl plik

@ -3,7 +3,7 @@
dev_type unknown
ref_manual_id 0000
chip_id 0x0 // STM32_CHIPID_UNKNOWN
flash_type 0 // STM32_FLASH_TYPE_UNKNOWN
flash_type UNKNOWN
flash_size_reg 0x0
flash_pagesize 0x0
sram_size 0x0

49
inc/stm32.h
Wyświetl plik

@ -8,47 +8,39 @@
#define STM32_H
/* STM32 Cortex-M core ids (CPUTAPID) */
#define STM32_CORE_ID_M0_SWD 0x0bb11477 // (RM0091 Section 32.5.3) F0 SW-DP
enum stm32_core_id {
STM32_CORE_ID_M0_SWD = 0x0bb11477, // (RM0091 Section 32.5.3) F0 SW-DP
// (RM0444 Section 40.5.3) G0 SW-DP
#define STM32_CORE_ID_M0P_SWD 0x0bc11477 // (RM0385 Section 27.5.3) L0 SW-DP
#define STM32_CORE_ID_M3_r1p1_SWD 0x1ba01477 // (RM0008 Section 31.8.3) F1 SW-DP
#define STM32_CORE_ID_M3_r1p1_JTAG 0x3ba00477 // (RM0008 Section 31.6.3) F1 JTAG
#define STM32_CORE_ID_M3_r2p0_SWD 0x2ba01477 // (RM0033 Section 32.8.3) F2 SW-DP
STM32_CORE_ID_M0P_SWD = 0x0bc11477, // (RM0385 Section 27.5.3) L0 SW-DP
STM32_CORE_ID_M3_r1p1_SWD = 0x1ba01477, // (RM0008 Section 31.8.3) F1 SW-DP
STM32_CORE_ID_M3_r1p1_JTAG = 0x3ba00477, // (RM0008 Section 31.6.3) F1 JTAG
STM32_CORE_ID_M3_r2p0_SWD = 0x2ba01477, // (RM0033 Section 32.8.3) F2 SW-DP
// (RM0038 Section 30.8.3) L1 SW-DP
#define STM32_CORE_ID_M3_r2p0_JTAG 0x0ba00477 // (RM0033 Section 32.6.3) F2 JTAG
STM32_CORE_ID_M3_r2p0_JTAG = 0x0ba00477, // (RM0033 Section 32.6.3) F2 JTAG
// (RM0038 Section 30.6.2) L1 JTAG
#define STM32_CORE_ID_M4_r0p1_SWD 0x1ba01477 // (RM0316 Section 33.8.3) F3 SW-DP
STM32_CORE_ID_M4_r0p1_SWD = 0x1ba01477, // (RM0316 Section 33.8.3) F3 SW-DP
// (RM0351 Section 48.8.3) L4 SW-DP
// (RM0432 Section 57.8.3) L4+ SW-DP
#define STM32_CORE_ID_M4_r0p1_JTAG 0x4ba00477 // (RM0316 Section 33.6.3) F3 JTAG
STM32_CORE_ID_M4_r0p1_JTAG = 0x4ba00477, // (RM0316 Section 33.6.3) F3 JTAG
// (RM0351 Section 48.6.3) L4 JTAG
// (RM0432 Section 57.6.3) L4+ JTAG
#define STM32_CORE_ID_M4F_r0p1_SWD 0x2ba01477 // (RM0090 Section 38.8.3) F4 SW-DP
STM32_CORE_ID_M4F_r0p1_SWD = 0x2ba01477, // (RM0090 Section 38.8.3) F4 SW-DP
// (RM0090 Section 47.8.3) G4 SW-DP
#define STM32_CORE_ID_M4F_r0p1_JTAG 0x4ba00477 // (RM0090 Section 38.6.3) F4 JTAG
STM32_CORE_ID_M4F_r0p1_JTAG = 0x4ba00477, // (RM0090 Section 38.6.3) F4 JTAG
// (RM0090 Section 47.6.3) G4 JTAG
#define STM32_CORE_ID_M7F_SWD 0x5ba02477 // (RM0385 Section 40.8.3) F7 SW-DP
#define STM32_CORE_ID_M7F_JTAG 0x5ba00477 // (RM0385 Section 40.6.3) F7 JTAG
#define STM32_CORE_ID_M7F_H7_SWD 0x6ba02477 // (RM0433 Section 60.4.1) H7 SW-DP
#define STM32_CORE_ID_M7F_H7_JTAG 0x6ba00477 // (RM0433 Section 60.4.1) H7 JTAG
#define STM32_CORE_ID_M33_SWD 0x0be02477 // (RM0438 Section 52.2.10) L5 SW-DP
STM32_CORE_ID_M7F_SWD = 0x5ba02477, // (RM0385 Section 40.8.3) F7 SW-DP
STM32_CORE_ID_M7F_JTAG = 0x5ba00477, // (RM0385 Section 40.6.3) F7 JTAG
STM32_CORE_ID_M7F_H7_SWD = 0x6ba02477, // (RM0433 Section 60.4.1) H7 SW-DP
STM32_CORE_ID_M7F_H7_JTAG = 0x6ba00477, // (RM0433 Section 60.4.1) H7 JTAG
STM32_CORE_ID_M33_SWD = 0x0be02477, // (RM0438 Section 52.2.10) L5 SW-DP
// (RM0456 Section 65.3.3) U5 SW-DP
#define STM32_CORE_ID_M33_JTAGD 0x0be01477 // (RM0438 Section 52.2.10) L5 JTAG-DP
STM32_CORE_ID_M33_JTAGD = 0x0be01477, // (RM0438 Section 52.2.10) L5 JTAG-DP
// (RM0456 Section 65.3.3) U5 JTAG-DP
#define STM32_CORE_ID_M33_JTAG 0x0ba04477 // (RM0438 Section 52.2.8) L5 JTAG
STM32_CORE_ID_M33_JTAG = 0x0ba04477, // (RM0438 Section 52.2.8) L5 JTAG
// (RM0456 Section 56.3.1) U5 JTAG
};
/* STM32 flash types */
// New flash type definitions must go before STM32_FLASH_TYPE_UNDEFINED
// with the latter updated to the highest enum value.
enum stm32_flash_type {
STM32_FLASH_TYPE_UNKNOWN = 0,
STM32_FLASH_TYPE_F0_F1_F3 = 1,
@ -62,7 +54,6 @@ enum stm32_flash_type {
STM32_FLASH_TYPE_L4_L4P = 9,
STM32_FLASH_TYPE_L5_U5 = 10,
STM32_FLASH_TYPE_WB_WL = 11,
STM32_FLASH_TYPE_UNDEFINED = 12, // max. value exceeded
};
/* STM32 chip-ids */
@ -70,7 +61,7 @@ enum stm32_flash_type {
// stm32 chipids, only lower 12 bits...
enum stm32_chipids {
STM32_CHIPID_UNKNOWN = 0x000,
STM32_CHIPID_UNKNOWN = 0x000,
STM32_CHIPID_F1_MD = 0x410, /* medium density */
STM32_CHIPID_F2 = 0x411,

63
src/stlink-lib/chipid.c
Wyświetl plik

@ -1,3 +1,4 @@
#include <stm32.h>
#include <stlink.h>
#include "chipid.h"
@ -7,7 +8,6 @@
#include <ctype.h>
#include <stdlib.h>
static struct stlink_chipid_params *devicelist;
void dump_a_chip (FILE *fp, struct stlink_chipid_params *dev) {
@ -28,7 +28,6 @@ void dump_a_chip (FILE *fp, struct stlink_chipid_params *dev) {
struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chip_id) {
struct stlink_chipid_params *params = NULL;
// struct stlink_chipid_params *p2;
for (params = devicelist; params != NULL; params = params->next)
if (params->chip_id == chip_id) {
fprintf(stderr, "\ndetected chip_id parametres\n\n");
@ -74,7 +73,7 @@ void process_chipfile(char *fname) {
buf[strlen(p) - 1] = 0; // chomp newline
sscanf(p, "%*s %n", &nc);
ts->dev_type = strdup(p + nc);
} else if (strcmp (word, "ref_manual_id") == 0) {
} else if (strcmp(word, "ref_manual_id") == 0) {
// ts->ref_manual_id = strdup (value);
buf[strlen(p) - 1] = 0; // chomp newline
sscanf(p, "%*s %n", &nc);
@ -83,59 +82,80 @@ void process_chipfile(char *fname) {
if (sscanf(value, "%i", &ts->chip_id) < 1) {
fprintf(stderr, "Failed to parse chip-id\n");
}
} else if (strcmp (word, "flash_type") == 0) {
if (sscanf(value, "%i", (int *)&ts->flash_type) < 1) {
fprintf(stderr, "Failed to parse flash type\n");
} else if ((ts->flash_type < STM32_FLASH_TYPE_UNKNOWN) || (ts->flash_type >= STM32_FLASH_TYPE_UNDEFINED)) {
fprintf(stderr, "Unrecognized flash type\n");
} else if (strcmp(word, "flash_type") == 0) {
if (strcmp(value, "F0_F1_F3") == 0) {
ts->flash_type = STM32_FLASH_TYPE_F0_F1_F3;
} else if (strcmp(value, "F1_XL") == 0) {
ts->flash_type = STM32_FLASH_TYPE_F1_XL;
} else if (strcmp(value, "F2_F4") == 0) {
ts->flash_type = STM32_FLASH_TYPE_F2_F4;
} else if (strcmp(value, "F7") == 0) {
ts->flash_type = STM32_FLASH_TYPE_F7;
} else if (strcmp(value, "G0") == 0) {
ts->flash_type = STM32_FLASH_TYPE_G0;
} else if (strcmp(value, "G4") == 0) {
ts->flash_type = STM32_FLASH_TYPE_G4;
} else if (strcmp(value, "H7") == 0) {
ts->flash_type = STM32_FLASH_TYPE_H7;
} else if (strcmp(value, "L0_L1") == 0) {
ts->flash_type = STM32_FLASH_TYPE_L0_L1;
} else if (strcmp(value, "L4_L4P") == 0) {
ts->flash_type = STM32_FLASH_TYPE_L4_L4P;
} else if (strcmp(value, "L5_U5") == 0) {
ts->flash_type = STM32_FLASH_TYPE_L5_U5;
} else if (strcmp(value, "WB_WL") == 0) {
ts->flash_type = STM32_FLASH_TYPE_WB_WL;
} else {
ts->flash_type = STM32_FLASH_TYPE_UNKNOWN;
fprintf(stderr, "Failed to parse flash type or unrecognized flash type\n");
}
} else if (strcmp (word, "flash_size_reg") == 0) {
} else if (strcmp(word, "flash_size_reg") == 0) {
if (sscanf(value, "%i", &ts->flash_size_reg) < 1) {
fprintf(stderr, "Failed to parse flash size reg\n");
}
} else if (strcmp (word, "flash_pagesize") == 0) {
} else if (strcmp(word, "flash_pagesize") == 0) {
if (sscanf(value, "%i", &ts->flash_pagesize) < 1) {
fprintf(stderr, "Failed to parse flash page size\n");
}
} else if (strcmp (word, "sram_size") == 0) {
} else if (strcmp(word, "sram_size") == 0) {
if (sscanf(value, "%i", &ts->sram_size) < 1) {
fprintf(stderr, "Failed to parse SRAM size\n");
}
} else if (strcmp (word, "bootrom_base") == 0) {
} else if (strcmp(word, "bootrom_base") == 0) {
if (sscanf(value, "%i", &ts->bootrom_base) < 1) {
fprintf(stderr, "Failed to parse BootROM base\n");
}
} else if (strcmp (word, "bootrom_size") == 0) {
} else if (strcmp(word, "bootrom_size") == 0) {
if (sscanf(value, "%i", &ts->bootrom_size) < 1) {
fprintf(stderr, "Failed to parse BootROM size\n");
}
} else if (strcmp (word, "option_base") == 0) {
} else if (strcmp(word, "option_base") == 0) {
if (sscanf(value, "%i", &ts->option_base) < 1) {
fprintf(stderr, "Failed to parse option base\n");
}
} else if (strcmp (word, "option_size") == 0) {
} else if (strcmp(word, "option_size") == 0) {
if (sscanf(value, "%i", &ts->option_size) < 1) {
fprintf(stderr, "Failed to parse option size\n");
}
} else if (strcmp (word, "flags") == 0) {
} else if (strcmp(word, "flags") == 0) {
pp = strtok (p, " \t\n");
while ((pp = strtok (NULL, " \t\n"))) {
if (strcmp (pp, "none") == 0) {
if (strcmp(pp, "none") == 0) {
// NOP
} else if (strcmp (pp, "dualbank") == 0) {
} else if (strcmp(pp, "dualbank") == 0) {
ts->flags |= CHIP_F_HAS_DUAL_BANK;
} else if (strcmp (pp, "swo") == 0) {
} else if (strcmp(pp, "swo") == 0) {
ts->flags |= CHIP_F_HAS_SWO_TRACING;
} else {
fprintf (stderr, "Unknown flags word in %s: '%s'\n",
fprintf(stderr, "Unknown flags word in %s: '%s'\n",
fname, pp);
}
}
sscanf(value, "%x", &ts->flags);
} else {
fprintf (stderr, "Unknown keyword in %s: %s\n",
fprintf(stderr, "Unknown keyword in %s: %s\n",
fname, word);
}
}
@ -156,7 +176,6 @@ void init_chipids(char *dir_to_scan) {
}
devicelist = NULL;
// dump_chips ();
d = opendir(dir_to_scan);
if (d) {