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rewrite flashloaders as clean room doc

pull/932/head
xp 2020-04-24 16:59:47 +08:00
rodzic b53a207da4
commit 8aaf95abf6
8 zmienionych plików z 245 dodań i 277 usunięć
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87
flashloaders/stm32f0.s
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@ -1,32 +1,63 @@
/* Adopted from STM AN4065 stm32f0xx_flash.c:FLASH_ProgramWord */
.syntax unified
.text
write:
ldr r4, STM32_FLASH_BASE
mov r5, #1 /* FLASH_CR_PG, FLASH_SR_BUSY */
mov r6, #4 /* PGERR */
write_half_word:
ldr r3, [r4, #16] /* FLASH->CR */
orr r3, r5
str r3, [r4, #16] /* FLASH->CR |= FLASH_CR_PG */
ldrh r3, [r0] /* r3 = *sram */
strh r3, [r1] /* *flash = r3 */
busy:
ldr r3, [r4, #12] /* FLASH->SR */
tst r3, r5 /* FLASH_SR_BUSY */
beq busy
.global mycopy
mycopy:
ldr r7, =flash_base
ldr r4, [r7]
ldr r7, =flash_off_cr
ldr r6, [r7]
adds r6, r6, r4
ldr r7, =flash_off_sr
ldr r5, [r7]
adds r5, r5, r4
tst r3, r6 /* PGERR */
bne exit
myloop:
# FLASH_CR ^= 1
ldr r7, =0x1
ldr r3, [r6]
orrs r3, r3, r7
str r3, [r6]
add r0, r0, #2 /* sram += 2 */
add r1, r1, #2 /* flash += 2 */
sub r2, r2, #0x01 /* count-- */
cmp r2, #0
bne write_half_word
exit:
ldr r3, [r4, #16] /* FLASH->CR */
bic r3, r5
str r3, [r4, #16] /* FLASH->CR &= ~FLASH_CR_PG */
bkpt #0x00
# copy 2 bytes
ldrh r3, [r0]
strh r3, [r1]
STM32_FLASH_BASE: .word 0x40022000
ldr r7, =2
adds r0, r0, r7
adds r1, r1, r7
# wait if FLASH_SR == 1
mywait:
ldr r7, =0x1
ldr r3, [r5]
tst r3, r7
beq mywait
# exit if FLASH_SR == 4
ldr r7, =0x4
tst r3, r7
beq myexit
# loop if r2 != 0
ldr r7, =0x1
subs r2, r2, r7
cmp r2, #0
bne myloop
myexit:
# FLASH_CR &= ~1
ldr r7, =0x1
ldr r3, [r6]
bics r3, r3, r7
str r3, [r6]
bkpt
flash_base:
.align 2
.word 0x40022000
flash_off_cr:
.word 0x10
flash_off_sr:
.word 0x0c

54
flashloaders/stm32f4.s
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@ -1,32 +1,36 @@
.global start
.syntax unified
.syntax unified
.text
@ r0 = source
@ r1 = target
@ r2 = wordcount
@ r3 = flash_base
@ r4 = temp
.global mycopy
mycopy:
ldr r12, flash_base
ldr r10, flash_off_sr
add r10, r10, r12
start:
ldr r3, flash_base
next:
cbz r2, done
ldr r4, [r0]
str r4, [r1]
myloop:
# copy 4 bytes
ldr r3, [r0]
str r3, [r1]
wait:
ldrh r4, [r3, #0x0e]
tst.w r4, #1
bne wait
add r0, r0, #4
add r1, r1, #4
add r0, #4
add r1, #4
sub r2, #1
b next
done:
# wait if FLASH_SR == 1
mywait:
ldrh r3, [r10]
tst r3, #0x1
beq mywait
# loop if r2 != 0
sub r2, r2, #1
cmp r2, #0
bne myloop
myexit:
bkpt
.align 2
flash_base:
.word 0x40023c00
.align 2
.word 0x40023c00
flash_off_sr:
.word 0x0e

55
flashloaders/stm32f4lv.s
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@ -1,33 +1,36 @@
.global start
.syntax unified
.syntax unified
.text
@ r0 = source
@ r1 = target
@ r2 = wordcount
@ r3 = flash_base
@ r4 = temp
.global mycopy
mycopy:
ldr r12, flash_base
ldr r10, flash_off_sr
add r10, r10, r12
start:
lsls r2, r2, #2
ldr r3, flash_base
next:
cbz r2, done
ldrb r4, [r0]
strb r4, [r1]
myloop:
# copy 1 bytes
ldrb r3, [r0]
strb r3, [r1]
wait:
ldrh r4, [r3, #0x0e]
tst.w r4, #1
bne wait
add r0, r0, #1
add r1, r1, #1
add r0, #1
add r1, #1
sub r2, #1
b next
done:
# wait if FLASH_SR == 1
mywait:
ldrh r3, [r10]
tst r3, #0x1
beq mywait
# loop if r2 != 0
sub r2, r2, #1
cmp r2, #0
bne myloop
myexit:
bkpt
.align 2
flash_base:
.word 0x40023c00
.align 2
.word 0x40023c00
flash_off_sr:
.word 0x0e

58
flashloaders/stm32f7.s
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@ -1,33 +1,39 @@
.global start
.syntax unified
.syntax unified
.text
@ r0 = source
@ r1 = target
@ r2 = wordcount
@ r3 = flash_base
@ r4 = temp
.global mycopy
mycopy:
ldr r12, flash_base
ldr r10, flash_off_sr
add r10, r10, r12
start:
ldr r3, flash_base
next:
cbz r2, done
ldr r4, [r0]
str r4, [r1]
dsb sy
myloop:
# copy 4 bytes
ldr r3, [r0]
str r3, [r1]
wait:
ldrh r4, [r3, #0x0e]
tst.w r4, #1
bne wait
add r0, r0, #4
add r1, r1, #4
add r0, #4
add r1, #4
sub r2, #1
b next
done:
# memory barrier
dsb sy
# wait if FLASH_SR == 1
mywait:
ldrh r3, [r10]
tst r3, #0x1
beq mywait
# loop if r2 != 0
sub r2, r2, #1
cmp r2, #0
bne myloop
myexit:
bkpt
.align 2
flash_base:
.word 0x40023c00
.align 2
.word 0x40023c00
flash_off_sr:
.word 0x0e

59
flashloaders/stm32f7lv.s
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@ -1,34 +1,39 @@
.global start
.syntax unified
.syntax unified
.text
@ r0 = source
@ r1 = target
@ r2 = wordcount
@ r3 = flash_base
@ r4 = temp
.global mycopy
mycopy:
ldr r12, flash_base
ldr r10, flash_off_sr
add r10, r10, r12
start:
lsls r2, r2, #2
ldr r3, flash_base
next:
cbz r2, done
ldrb r4, [r0]
strb r4, [r1]
dsb sy
myloop:
# copy 1 byte
ldrb r3, [r0]
strb r3, [r1]
wait:
ldrh r4, [r3, #0x0e]
tst.w r4, #1
bne wait
add r0, r0, #1
add r1, r1, #1
add r0, #1
add r1, #1
sub r2, #1
b next
done:
# memory barrier
dsb sy
# wait if FLASH_SR == 1
mywait:
ldrh r3, [r10]
tst r3, #0x1
beq mywait
# loop if r2 != 0
sub r2, r2, #1
cmp r2, #0
bne myloop
myexit:
bkpt
.align 2
flash_base:
.word 0x40023c00
.algin 2
.word 0x40023c00
flash_off_sr:
.word 0x0e

76
flashloaders/stm32l0x.s
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@ -1,64 +1,22 @@
/***************************************************************************
* Copyright (C) 2010 by Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* Copyright (C) 2011 Øyvind Harboe *
* oyvind.harboe@zylin.com *
* *
* Copyright (C) 2011 Clement Burin des Roziers *
* clement.burin-des-roziers@hikob.com *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
// Build : arm-eabi-gcc -c stm32lx.S
.text
.syntax unified
.cpu cortex-m0plus
.thumb
.thumb_func
.global write
.text
/*
r0 - source address
r1 - destination address
r2 - count
*/
.global mycopy
mycopy:
myloop:
# copy 4 bytes
ldr r3, [r0]
str r3, [r1]
// Go to compare
b test_done
ldr r7, =4
add r0, r0, r7
add r1, r1, r7
write_word:
// Load one word from address in r0, increment by 4
ldr r4, [r0]
// Store the word to address in r1, increment by 4
str r4, [r1]
// Decrement r2
subs r2, #1
adds r1, #4
// does not matter, only first addr is important
// next 15 bytes are in sequnce RM0367 page 66
adds r0, #4
# loop if r2 != 0
ldr r7, =1
subs r2, r2, r7
cmp r2, #0
bne myloop
test_done:
// Test r2
cmp r2, #0
// Loop if not zero
bcc.n write_word
// Set breakpoint to exit
bkpt #0x00
myexit:
bkpt

61
flashloaders/stm32l4.s
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@ -1,39 +1,38 @@
.global start
.syntax unified
.syntax unified
.text
@ Adapted from stm32f4.s
@ STM32L4's flash controller expects double-word writes, has the flash
@ controller mapped in a different location with the registers we care about
@ moved down from the base address, and has BSY moved to bit 16 of SR.
@ r0 = source
@ r1 = target
@ r2 = wordcount
@ r3 = flash_base
@ r4 = temp
@ r5 = temp
.global mycopy
mycopy:
ldr r12, flash_base
ldr r10, flash_off_bsy
add r10, r10, r12
start:
ldr r3, flash_base
next:
cbz r2, done
ldr r4, [r0] /* copy doubleword from source to target */
ldr r5, [r0, #4]
str r4, [r1]
str r5, [r1, #4]
myloop:
# copy 8 bytes
ldr r3, [r0]
ldr r4, [r0, #4]
str r3, [r1]
str r4, [r1, #4]
wait:
ldrh r4, [r3, #0x12] /* high half of status register */
tst r4, #1 /* BSY = bit 16 */
bne wait
add r0, r0, #8
add r1, r1, #8
add r0, #8
add r1, #8
sub r2, #1
b next
done:
# wait if FLASH_BSY[0b] == 1
mywait:
ldrh r3, [r10]
tst r3, #0x1
beq mywait
# loop if r2 != 0
sub r2, r2, #1
cmp r2, #0
bne myloop
myexit:
bkpt
.align 2
flash_base:
.align 2
.word 0x40022000
flash_off_bsy:
.word 0x12

72
flashloaders/stm32lx.s
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@ -1,60 +1,22 @@
/***************************************************************************
* Copyright (C) 2010 by Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* Copyright (C) 2011 Øyvind Harboe *
* oyvind.harboe@zylin.com *
* *
* Copyright (C) 2011 Clement Burin des Roziers *
* clement.burin-des-roziers@hikob.com *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
// Build : arm-eabi-gcc -c stm32lx.s
.text
.syntax unified
.cpu cortex-m3
.thumb
.thumb_func
.global write
.text
/*
r0 - source address
r1 - destination address
r2 - output, remaining word count
*/
.global mycopy
mycopy:
myloop:
# copy 4 bytes
ldr r3, [r0]
str r3, [r1]
// Go to compare
b test_done
ldr r7, =4
add r0, r0, r7
add r1, r1, r7
write_word:
// Load one word from address in r0, increment by 4
ldr.w ip, [r0], #4
// Store the word to address in r1, increment by 4
str.w ip, [r1], #4
// Decrement r2
subs r2, #1
# loop if r2 != 0
ldr r7, =1
subs r2, r2, r7
cmp r2, #0
bne myloop
test_done:
// Test r2
cmp r2, #0
// Loop if not zero
bhi write_word
// Set breakpoint to exit
bkpt #0x00
myexit:
bkpt