kopia lustrzana https://github.com/stlink-org/stlink
Added flash loader stub for F2/F4.
rodzic
10924baac1
commit
8151bf5c4a
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@ -0,0 +1,32 @@
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.global start
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.syntax unified
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@ r0 = source
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@ r1 = target
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@ r2 = wordcount
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@ r3 = flash_base
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@ r4 = temp
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start:
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ldr r3, flash_base
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next:
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cbz r2, done
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ldr r4, [r0]
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str r4, [r1]
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wait:
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ldrh r4, [r3, #0x0e]
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tst.w r4, #1
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bne wait
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add r0, #4
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add r1, #4
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sub r2, #1
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b next
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done:
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bkpt
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.align 2
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flash_base:
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.word 0x40023c00
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@ -1182,6 +1182,28 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) {
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0x00, 0xbe
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0x00, 0xbe
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};
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};
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static const uint8_t loader_code_stm32f4[] = {
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// flashloaders/stm32f4.s
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0x07, 0x4b,
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0x62, 0xb1,
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0x04, 0x68,
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0x0c, 0x60,
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0xdc, 0x89,
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0x14, 0xf0, 0x01, 0x0f,
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0xfb, 0xd1,
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0x00, 0xf1, 0x04, 0x00,
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0x01, 0xf1, 0x04, 0x01,
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0xa2, 0xf1, 0x01, 0x02,
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0xf1, 0xe7,
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0x00, 0xbe,
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0x00, 0x3c, 0x02, 0x40,
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};
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const uint8_t* loader_code;
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const uint8_t* loader_code;
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size_t loader_size;
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size_t loader_size;
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@ -1195,6 +1217,11 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) {
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loader_code = loader_code_stm32vl;
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loader_code = loader_code_stm32vl;
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loader_size = sizeof(loader_code_stm32vl);
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loader_size = sizeof(loader_code_stm32vl);
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}
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}
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else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4)
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{
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loader_code = loader_code_stm32f4;
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loader_size = sizeof(loader_code_stm32f4);
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}
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else
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else
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{
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{
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WLOG("unknown coreid, not sure what flash loader to use, aborting!: %x\n", sl->core_id);
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WLOG("unknown coreid, not sure what flash loader to use, aborting!: %x\n", sl->core_id);
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@ -1358,6 +1385,13 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned
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if ((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4)) {
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if ((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4)) {
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/* todo: check write operation */
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/* todo: check write operation */
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ILOG("Starting Flash write for F2/F4\n");
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/* flash loader initialization */
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if (init_flash_loader(sl, &fl) == -1) {
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WLOG("init_flash_loader() == -1\n");
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return -1;
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}
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/* First unlock the cr */
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/* First unlock the cr */
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unlock_flash_if(sl);
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unlock_flash_if(sl);
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@ -1368,6 +1402,20 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned
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/* set programming mode */
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/* set programming mode */
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set_flash_cr_pg(sl);
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set_flash_cr_pg(sl);
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for(off = 0; off < len;) {
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size_t size = len - off > 0x8000 ? 0x8000 : len - off;
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printf("size: %u\n", size);
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if (run_flash_loader(sl, &fl, addr + off, base + off, size) == -1) {
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WLOG("run_flash_loader(%#zx) failed! == -1\n", addr + off);
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return -1;
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}
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off += size;
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}
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#if 0
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#define PROGRESS_CHUNK_SIZE 0x1000
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#define PROGRESS_CHUNK_SIZE 0x1000
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/* write a word in program memory */
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/* write a word in program memory */
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for (off = 0; off < len; off += sizeof(uint32_t)) {
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for (off = 0; off < len; off += sizeof(uint32_t)) {
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@ -1389,6 +1437,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned
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wait_flash_busy(sl);
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wait_flash_busy(sl);
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}
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}
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#endif
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/* Relock flash */
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/* Relock flash */
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lock_flash(sl);
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lock_flash(sl);
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@ -1618,6 +1667,17 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons
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stlink_write_reg(sl, 0, 3); /* flash bank 0 (input) */
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stlink_write_reg(sl, 0, 3); /* flash bank 0 (input) */
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stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */
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stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */
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} else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4) {
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size_t count = size / sizeof(uint32_t);
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if (size % sizeof(uint32_t)) ++count;
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/* setup core */
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stlink_write_reg(sl, fl->buf_addr, 0); /* source */
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stlink_write_reg(sl, target, 1); /* target */
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stlink_write_reg(sl, count, 2); /* count (32 bits words) */
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stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */
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} else {
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} else {
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fprintf(stderr, "unknown coreid: 0x%x\n", sl->core_id);
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fprintf(stderr, "unknown coreid: 0x%x\n", sl->core_id);
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return -1;
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return -1;
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@ -1657,6 +1717,14 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons
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return -1;
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return -1;
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}
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}
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} else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4) {
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stlink_read_reg(sl, 2, &rr);
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if (rr.r[2] != 0) {
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fprintf(stderr, "write error, count == %u\n", rr.r[2]);
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return -1;
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}
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} else {
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} else {
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fprintf(stderr, "unknown coreid: 0x%x\n", sl->core_id);
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fprintf(stderr, "unknown coreid: 0x%x\n", sl->core_id);
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