kopia lustrzana https://github.com/stlink-org/stlink
[ merge ] STM32_CHIPIP_F3 patch from Geoffrey Brown
rodzic
c4183b6772
commit
7942914971
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@ -1085,7 +1085,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr)
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val = stlink_read_debug32(sl, STM32L_FLASH_PECR)
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| (1 << 0) | (1 << 1) | (1 << 2);
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stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
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} else if (sl->core_id == STM32VL_CORE_ID || sl->core_id == STM32F0_CORE_ID) {
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} else if (sl->core_id == STM32VL_CORE_ID || sl->core_id == STM32F0_CORE_ID || sl->chip_id == STM32_CHIPID_F3) {
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/* wait for ongoing op to finish */
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wait_flash_busy(sl);
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@ -1290,7 +1290,7 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) {
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if (sl->chip_id == STM32_CHIPID_L1_MEDIUM) { /* stm32l */
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loader_code = loader_code_stm32l;
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loader_size = sizeof(loader_code_stm32l);
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} else if (sl->core_id == STM32VL_CORE_ID) {
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} else if (sl->core_id == STM32VL_CORE_ID || sl->chip_id == STM32_CHIPID_F3) {
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loader_code = loader_code_stm32vl;
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loader_size = sizeof(loader_code_stm32vl);
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} else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4) {
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@ -1633,7 +1633,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned
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val = stlink_read_debug32(sl, STM32L_FLASH_PECR)
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| (1 << 0) | (1 << 1) | (1 << 2);
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stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
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} else if (sl->core_id == STM32VL_CORE_ID || sl->core_id == STM32F0_CORE_ID) {
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} else if (sl->core_id == STM32VL_CORE_ID || sl->core_id == STM32F0_CORE_ID || sl->chip_id == STM32_CHIPID_F3) {
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ILOG("Starting Flash write for VL/F0 core id\n");
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/* flash loader initialization */
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if (init_flash_loader(sl, &fl) == -1) {
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@ -1732,7 +1732,7 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons
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stlink_write_reg(sl, count, 2); /* count (32 bits words) */
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stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */
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} else if (sl->core_id == STM32VL_CORE_ID || sl->core_id == STM32F0_CORE_ID) {
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} else if (sl->core_id == STM32VL_CORE_ID || sl->core_id == STM32F0_CORE_ID || sl->chip_id == STM32_CHIPID_F3) {
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size_t count = size / sizeof(uint16_t);
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if (size % sizeof(uint16_t)) ++count;
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@ -1787,7 +1787,7 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons
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return -1;
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}
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} else if (sl->core_id == STM32VL_CORE_ID || sl->core_id == STM32F0_CORE_ID) {
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} else if (sl->core_id == STM32VL_CORE_ID || sl->core_id == STM32F0_CORE_ID || sl->chip_id == STM32_CHIPID_F3) {
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stlink_read_reg(sl, 2, &rr);
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if (rr.r[2] != 0) {
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@ -84,6 +84,7 @@ extern "C" {
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// TODO clean this up...
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#define STM32VL_CORE_ID 0x1ba01477
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#define STM32L_CORE_ID 0x2ba01477
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#define STM32F3_CORE_ID 0x2ba01477
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#define STM32F4_CORE_ID 0x2ba01477
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#define STM32F0_CORE_ID 0xbb11477
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#define CORE_M3_R1 0x1BA00477
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@ -98,6 +99,7 @@ extern "C" {
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#define STM32_CHIPID_F1_MEDIUM 0x410
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#define STM32_CHIPID_F2 0x411
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#define STM32_CHIPID_F1_LOW 0x412
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#define STM32_CHIPID_F3 0x422
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#define STM32_CHIPID_F4 0x413
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#define STM32_CHIPID_F1_HIGH 0x414
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#define STM32_CHIPID_L1_MEDIUM 0x416
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